; --------------------------------------------------------------------------------
; @Title: S32R41 On-Chip Peripherals
; @Props: Released
; @Author: KWI, JON, NEJ
; @Changelog: 2020-10-16 KWI
;             2021-07-29 KWI
;             2022-01-20 JON
;             2022-07-20 NEJ
;             2022-10-27 NEJ
;             2022-11-25 NEJ
; @Manufacturer: NXP - NXP Semiconductors
; @Doc: SVD generated (SVD2PER 1.8.6), based on: S32R41_M7.svd (Ver. 1.8),
;                                                S32R41_A53.svd (Ver. 1.8)
; @Core: Cortex-A53, Cortex-M7F
; @Chip: S32R41-A53, S32R41-M7-0, S32R41-M7-1, S32R41-M7-HSE
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: pers32r41.per 16102 2023-05-11 15:23:25Z skrausse $

sif (CORENAME()=="CORTEXA53")
tree "Core Registers (Cortex-A53)"
AUTOINDENT.PUSH
AUTOINDENT.ON center tree
tree.open "AArch64"
tree "ID Registers"
rgroup.quad spr:0x30000++0x0
line.long 0x0 "MIDR_EL1,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code"
bitfld.long 0x0 20.--23.  "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19.  "ARCH,Architecture" "Reserved,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme"
newline
hexmask.long.word 0x0 4.--15. 0x1 "PART,Primary Part Number"
bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x30005++0x00
line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register"
bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
newline
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
bitfld.quad 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4"
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30005++0x00
line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity level 3. Third highest level affinity field"
newline
bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
newline
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
endif
rgroup.quad SPR:0x30006++0x0
line.long 0x0 "REVIDR_EL1,Revision ID Register"
rgroup.quad SPR:0x30014++0x00
line.long 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30015++0x00
line.long 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..."
bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.quad SPR:0x30016++0x00
line.long 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.quad SPR:0x30017++0x00
line.long 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,Reserved,?..."
newline
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30026++0x00
line.long 0x00 "ID_MMFR4_EL1,Memory Model Feature Register 4"
bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
newline
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
newline
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..."
endif
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30071++0x00
line.quad 0x00 "ID_AA64MMFR1_EL1,AArch64 Memory Model Feature Register 1"
endif
rgroup.quad SPR:0x30020++0x00
line.long 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0"
bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.quad SPR:0x30021++0x00
line.long 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1"
bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30022++0x00
line.long 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2"
bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30023++0x00
line.long 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3"
bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..."
bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30024++0x00
line.long 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4"
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30025++0x00
line.long 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5"
bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
newline
bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30060++0x00
line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0"
bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..."
bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions are implemented" "Not implemented,Implemented,?..."
bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions are implemented" "Not implemented,Implemented,?..."
newline
bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..."
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30061++0x00
line.quad 0x00 "ID_AA64ISAR1_EL1,AArch64 Instruction Set Attribute Register 1"
endif
rgroup.quad SPR:0x30010++0x00
line.long 0x00 "ID_PFR0_EL1,Processor Feature Register 0"
bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30011++0x00
line.long 0x00 "ID_PFR1_EL1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0"
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,?..."
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,?..."
newline
bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
newline
bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0"
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
newline
bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
newline
bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
endif
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30041++0x00
line.quad 0x00 "ID_AA64PFR1_EL1,AArch64 Processor Feature Register 1"
endif
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x30012++0x00
line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x30012++0x00
line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
endif
rgroup.quad spr:0x30050++0x00
line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0"
bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..."
bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..."
bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
newline
bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,Implemented,?..."
bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..."
bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented,?..."
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30051++0x00
line.quad 0x00 "ID_AA64DFR1_EL1,AArch64 Debug Feature Register 1"
rgroup.quad spr:0x30054++0x00
line.quad 0x00 "ID_AA64AFR0_EL1,AArch64 Auxiliary Feature Register 0"
rgroup.quad spr:0x30055++0x00
line.quad 0x00 "ID_AA64AFR1_EL1,AArch64 Auxiliary Feature Register 1"
endif
rgroup.quad SPR:0x30013++0x00
line.long 0x00 "ID_AFR0_EL1,Auxiliary Feature Register 0"
rgroup.quad SPR:0x31007++0x00
line.long 0x00 "AIDR_EL1,Auxiliary ID Register"
rgroup.quad SPR:0x33007++0x00
line.long 0x00 "DCZID_EL0,Data Cache Zero ID"
bitfld.long 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited"
bitfld.long 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
tree.end
tree "System Control and Configuration"
group.quad spr:0x36111++0x00
line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register"
bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled"
group.quad SPR:0x30100++0x0
line.long 0x00 "SCTLR_EL1,System Control Register (EL1)"
bitfld.long 0x0 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
bitfld.long 0x0 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 9. "UMA,User Mask Access" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT instruction disable" "No,Yes"
newline
bitfld.long 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad SPR:0x34100++0x0
line.long 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad SPR:0x36100++0x0
line.long 0x00 "SCTLR_EL3,System Control Register (EL3)"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
rgroup.quad SPR:0x30101++0x0
line.long 0x00 "ACTLR_EL1,Auxiliary Control Register (EL1)"
group.quad SPR:0x34101++0x0
line.long 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
group.quad SPR:0x36101++0x0
line.long 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
group.quad SPR:0x30102++0x00
line.long 0x00 "CPACR_EL1,Architectural Feature Access Control Register"
bitfld.long 0x00 28. "TTA,Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1" "Disabled,?..."
bitfld.long 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap all,Trap El0,Trap all,Not trapped"
group.quad SPR:0x36110++0x0
line.long 0x0 "SCR_EL3,Secure Configuration Register"
bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
newline
bitfld.long 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled"
bitfld.long 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64"
newline
bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes"
newline
bitfld.long 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes"
bitfld.long 0x00 3. "EA,External Abort  exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
newline
bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
newline
bitfld.long 0x00 0. "NS,Secure mode" "Secure,Non-secure"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
newline
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
newline
bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
group.quad spr:0x30510++0x00
line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)"
group.quad spr:0x30511++0x00
line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)"
group.quad spr:0x34510++0x00
line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)"
group.quad spr:0x34511++0x00
line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)"
group.quad spr:0x36510++0x00
line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)"
group.quad spr:0x36511++0x00
line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)"
tree.open "Exception Syndrome Registers"
if (CORENAME()=="CORTEXA57")
if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..."
elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..."
elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
elif (CORENAME()=="CORTEXA53")
if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SES,System Error Source" "Processor,System,External,"
newline
hexmask.long.tbyte 0x00 0.--21. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
endif
tree.end
newline
if (CORENAME()=="CORTEXA57")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif (CORENAME()=="CORTEXA53")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
group.quad spr:0x30600++0x00
line.quad 0x00 "FAR_EL1,Fault Address Register"
group.quad spr:0x34600++0x00
line.quad 0x00 "FAR_EL2,Fault Address Register"
group.quad spr:0x36600++0x00
line.quad 0x00 "FAR_EL3,Fault Address Register"
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
group.quad spr:0x30C00++0x00
line.quad 0x00 "VBAR_EL1,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
group.quad spr:0x34C00++0x00
line.quad 0x00 "VBAR_EL2,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
group.quad spr:0x36C00++0x00
line.quad 0x00 "VBAR_EL3,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
rgroup.quad spr:0x36C01++0x00
line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register"
hexmask.quad 0x00 2.--43. 0x4 "RVBA,Reset Vector Base Address"
rgroup.quad SPR:0x30C10++0x00
line.long 0x00 "ISR_EL1,Interrupt Status Register"
bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending"
bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
newline
bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
group.quad SPR:0x36C02++0x00
line.long 0x00 "RMR_EL3,Reset Management Register"
bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x31F30++0x00
line.quad 0x00 "CBAR_EL1,Configuration Base Address Register"
hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]"
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x31F30++0x00
line.quad 0x00 "CBAR_EL1,Configuration Base Address Register"
hexmask.quad.tbyte 0x00 18.--39. 1. "PERIPHBASE[39:18],Periphbase[39:18]"
endif
group.quad spr:0x30D01++0x00
line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register"
group.quad spr:0x33D02++0x00
line.quad 0x00 "TPIDR_EL0,Software Thread ID Register"
group.quad spr:0x33D03++0x00
line.quad 0x00 "TPIDRRO_EL0,Software Thread ID Register"
group.quad spr:0x30D04++0x00
line.quad 0x00 "TPIDR_EL1,Software Thread ID Register"
group.quad spr:0x34D02++0x00
line.quad 0x00 "TPIDR_EL2,Software Thread ID Register"
group.quad spr:0x36D02++0x00
line.quad 0x00 "TPIDR_EL3,Software Thread ID Register"
tree.end
tree "Memory Management Unit"
group.quad spr:0x30100++0x0
line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)"
bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled"
newline
bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes"
newline
bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x36100++0x0
line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x30200++0x00
line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad spr:0x30201++0x00
line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)"
bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit"
bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KByte,64 KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled"
bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB"
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)"
bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit"
bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,Reserved,4 KB,64 KB"
bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled"
bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 7. "EPD0,Translation table walk disable for translations using TTBR0" "Enabled,Disabled"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x34200++0x00
line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 14. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB"
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x36200++0x00
line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 14. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB"
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad SPR:0x34300++0x00
line.long 0x00 "DACR32_EL2,Domain Access Control Register"
bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if (CORENAME()=="CORTEXA57")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif (CORENAME()=="CORTEXA53")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
rgroup.quad SPR:0x30510++0x00
line.long 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)"
rgroup.quad SPR:0x34510++0x00
line.long 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)"
rgroup.quad SPR:0x36510++0x00
line.long 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)"
rgroup.quad SPR:0x30511++0x00
line.long 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)"
rgroup.quad SPR:0x34511++0x00
line.long 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)"
rgroup.quad SPR:0x36511++0x00
line.long 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)"
if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-not nGnRnE,?..."
newline
hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif (((per.q(spr:0x30740))&0x01)==0x00)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
newline
hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
newline
bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Reserved,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,?..."
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
tree.open "Memory Attribute Indirection Registers"
group.quad spr:0x30A20++0x00
line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
group.quad spr:0x34A20++0x00
line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
group.quad spr:0x36A20++0x00
line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
rgroup.quad spr:0x30A30++0x00
line.quad 0x00 "AMAIR_EL1,Memory Attribute Indirection Register (EL1)"
rgroup.quad spr:0x34A30++0x00
line.quad 0x00 "AMAIR_EL2,Memory Attribute Indirection Register (EL2)"
rgroup.quad spr:0x36A30++0x00
line.quad 0x00 "AMAIR_EL3,Memory Attribute Indirection Register (EL3)"
tree.end
newline
group.quad SPR:0x30D01++0x00
line.long 0x0 "CONTEXTIDR_EL1,Context ID Register"
tree.end
tree "Virtualization Extensions"
group.quad SPR:0x34000++0x0
line.long 0x0 "VPIDR_EL2,Virtualization Processor ID Register"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x34005++0x00
line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register"
hexmask.quad.long 0x00 0.--31. 1. "VMPIDR_EL2,MPIDR value returned by Non-secure EL1 reads of the MPIDR_EL1"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x34005++0x00
line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register"
endif
group.quad spr:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
newline
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
newline
bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x34111++0x00
line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
newline
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x34111++0x00
line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
newline
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6"
endif
group.quad SPR:0x34112++0x00
line.long 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
group.quad SPR:0x36131++0x00
line.long 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)"
bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes"
bitfld.long 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
newline
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
group.quad SPR:0x36112++0x00
line.long 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
group.quad SPR:0x34113++0x00
line.long 0x00 "HSTR_EL2,Hypervisor System Trap Register"
bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Not supported,?..."
bitfld.long 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped"
bitfld.long 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped"
newline
bitfld.long 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped"
bitfld.long 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped"
bitfld.long 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped"
newline
bitfld.long 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped"
bitfld.long 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped"
bitfld.long 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped"
newline
bitfld.long 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped"
bitfld.long 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped"
bitfld.long 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped"
newline
bitfld.long 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped"
bitfld.long 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped"
bitfld.long 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped"
rgroup.quad SPR:0x34117++0x00
line.long 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register"
group.quad spr:0x34210++0x00
line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x34212++0x00
line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..."
bitfld.long 0x00 14. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x34212++0x00
line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,?..."
bitfld.long 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,?..."
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting IPA bits"
tree.end
tree "Cache Control and Configuration"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
group.quad SPR:0x32000++0x0
line.long 0x0 "CSSELR_EL1,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x31001++0x0
line.long 0x0 "CLIDR_EL1,Cache Level ID Register"
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..."
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
newline
bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..."
bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..."
bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..."
newline
bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
rgroup.quad SPR:0x31000++0x0
line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..."
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
bitfld.long 0x00 29. "RA,Read-Allocate" "Reserved,Supported"
newline
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x31001++0x0
line.long 0x0 "CLIDR_EL1,Cache Level ID Register"
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..."
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
rgroup.quad SPR:0x31000++0x0
line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..."
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
newline
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "1Reserved,Reserved,64 bytes,?..."
endif
tree "Level 1 memory system"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x30F10++0x00
line.long 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register"
group.quad SPR:0x30F11++0x00
line.long 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register"
group.quad SPR:0x30F12++0x00
line.long 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register"
group.quad SPR:0x30F13++0x00
line.long 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register"
group.quad SPR:0x30F00++0x00
line.long 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register"
group.quad SPR:0x30F01++0x00
line.long 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register"
group.quad SPR:0x30F02++0x00
line.long 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register"
group.quad SPR:0x30F03++0x00
line.long 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register"
group.quad spr:0x31F20++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes"
bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes"
newline
bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled"
bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes"
bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes"
newline
bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled"
bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled"
bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes"
newline
bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes"
bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes"
bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes"
newline
bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes"
bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes"
bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
newline
bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes"
bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced"
bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes"
newline
bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced"
bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes"
bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes"
bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled"
bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced"
newline
bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
newline
bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled"
bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced"
bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced"
newline
bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes"
bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes"
bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes"
newline
bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes"
bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes"
bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced"
bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced"
bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled"
bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled"
bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced"
newline
bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes"
bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled"
bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled"
bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes"
bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes"
bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled"
group.quad spr:0x31F21++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes"
bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines"
bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines"
newline
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..."
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..."
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x31F20++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
bitfld.quad 0x00 44. "ENDCCASCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes"
bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes"
newline
bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes"
newline
bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes"
bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes"
bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes"
newline
bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams"
bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled"
bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled"
newline
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8"
bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes"
bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache data RAM error injection enable" "Disabled,Enabled"
group.quad spr:0x31F21++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
endif
if (CORENAME()=="CORTEXA57")
group.quad spr:0x31F22++0x00
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x31F22++0x00
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address"
endif
tree.end
tree "Level 2 memory system"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x31B02++0x0
line.long 0x00 "L2CTLR_EL1,L2 Control Register"
bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes"
bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
bitfld.long 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled"
rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not presented,Presented"
newline
rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not presented,Presented"
rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not presented,1,2,?..."
bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle"
newline
bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
group.quad SPR:0x31B03++0x0
line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad SPR:0x31F00++0x00
line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register"
bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled"
bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled"
bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced"
newline
bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled"
bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes"
bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
newline
bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled"
bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit"
bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes"
newline
bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled"
bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes"
bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes"
bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes"
newline
bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes"
bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled"
bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes"
newline
bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled"
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited"
newline
bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled"
bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes"
group.quad spr:0x31F23++0x00
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x31B02++0x0
line.long 0x00 "L2CTLR_EL1,L2 Control Register"
bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
newline
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles"
group.quad SPR:0x31B03++0x0
line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad SPR:0x31F00++0x00
line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register"
bitfld.long 0x00 30.--31. "L2VC,L2 Victim Control" "0,1,2,3"
bitfld.long 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled"
bitfld.long 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable." "Disabled,Enabled"
newline
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
group.quad spr:0x31F23++0x00
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address"
endif
tree.end
tree.end
tree "System Performance Monitor"
group.quad SPR:0x339C0++0x00
line.long 0x0 "PMCR_EL0,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
group.quad SPR:0x339C1++0x00
line.long 0x00 "PMCNTENSET_EL0,Count Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00  30. "P30,Event Counter 30 enable bit" "Disabled,Enabled"
bitfld.long 0x00  29. "P29,Event Counter 29 enable bit" "Disabled,Enabled"
bitfld.long 0x00  28. "P28,Event Counter 28 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  27. "P27,Event Counter 27 enable bit" "Disabled,Enabled"
bitfld.long 0x00  26. "P26,Event Counter 26 enable bit" "Disabled,Enabled"
bitfld.long 0x00  25. "P25,Event Counter 25 enable bit" "Disabled,Enabled"
bitfld.long 0x00  24. "P24,Event Counter 24 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  23. "P23,Event Counter 23 enable bit" "Disabled,Enabled"
bitfld.long 0x00  22. "P22,Event Counter 22 enable bit" "Disabled,Enabled"
bitfld.long 0x00  21. "P21,Event Counter 21 enable bit" "Disabled,Enabled"
bitfld.long 0x00  20. "P20,Event Counter 20 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  19. "P19,Event Counter 19 enable bit" "Disabled,Enabled"
bitfld.long 0x00  18. "P18,Event Counter 18 enable bit" "Disabled,Enabled"
bitfld.long 0x00  17. "P17,Event Counter 17 enable bit" "Disabled,Enabled"
bitfld.long 0x00  16. "P16,Event Counter 16 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  15. "P15,Event Counter 15 enable bit" "Disabled,Enabled"
bitfld.long 0x00  14. "P14,Event Counter 14 enable bit" "Disabled,Enabled"
bitfld.long 0x00  13. "P13,Event Counter 13 enable bit" "Disabled,Enabled"
bitfld.long 0x00  12. "P12,Event Counter 12 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  11. "P11,Event Counter 11 enable bit" "Disabled,Enabled"
bitfld.long 0x00  10. "P10,Event Counter 10 enable bit" "Disabled,Enabled"
bitfld.long 0x00  9. "P9,Event Counter 9 enable bit" "Disabled,Enabled"
bitfld.long 0x00  8. "P8,Event Counter 8 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  7. "P7,Event Counter 7 enable bit" "Disabled,Enabled"
bitfld.long 0x00  6. "P6,Event Counter 6 enable bit" "Disabled,Enabled"
bitfld.long 0x00  5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00  4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00  2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
bitfld.long 0x00  1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
bitfld.long 0x00  0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
group.quad SPR:0x339C2++0x00
line.long 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00  30. "P30,Event Counter 30 clear bit" "Disabled,Enabled"
eventfld.long 0x00  29. "P29,Event Counter 29 clear bit" "Disabled,Enabled"
eventfld.long 0x00  28. "P28,Event Counter 28 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  27. "P27,Event Counter 27 clear bit" "Disabled,Enabled"
eventfld.long 0x00  26. "P26,Event Counter 26 clear bit" "Disabled,Enabled"
eventfld.long 0x00  25. "P25,Event Counter 25 clear bit" "Disabled,Enabled"
eventfld.long 0x00  24. "P24,Event Counter 24 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  23. "P23,Event Counter 23 clear bit" "Disabled,Enabled"
eventfld.long 0x00  22. "P22,Event Counter 22 clear bit" "Disabled,Enabled"
eventfld.long 0x00  21. "P21,Event Counter 21 clear bit" "Disabled,Enabled"
eventfld.long 0x00  20. "P20,Event Counter 20 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  19. "P19,Event Counter 19 clear bit" "Disabled,Enabled"
eventfld.long 0x00  18. "P18,Event Counter 18 clear bit" "Disabled,Enabled"
eventfld.long 0x00  17. "P17,Event Counter 17 clear bit" "Disabled,Enabled"
eventfld.long 0x00  16. "P16,Event Counter 16 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  15. "P15,Event Counter 15 clear bit" "Disabled,Enabled"
eventfld.long 0x00  14. "P14,Event Counter 14 clear bit" "Disabled,Enabled"
eventfld.long 0x00  13. "P13,Event Counter 13 clear bit" "Disabled,Enabled"
eventfld.long 0x00  12. "P12,Event Counter 12 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  11. "P11,Event Counter 11 clear bit" "Disabled,Enabled"
eventfld.long 0x00  10. "P10,Event Counter 10 clear bit" "Disabled,Enabled"
eventfld.long 0x00  9. "P9,Event Counter 9 clear bit" "Disabled,Enabled"
eventfld.long 0x00  8. "P8,Event Counter 8 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  7. "P7,Event Counter 7 clear bit" "Disabled,Enabled"
eventfld.long 0x00  6. "P6,Event Counter 6 clear bit" "Disabled,Enabled"
eventfld.long 0x00  5. "P5,Event Counter 5 clear bit" "Disabled,Enabled"
eventfld.long 0x00  4. "P4,Event Counter 4 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  3. "P3,Event Counter 3 clear bit" "Disabled,Enabled"
eventfld.long 0x00  2. "P2,Event Counter 2 clear bit" "Disabled,Enabled"
eventfld.long 0x00  1. "P1,Event Counter 1 clear bit" "Disabled,Enabled"
eventfld.long 0x00  0. "P0,Event Counter 0 clear bit" "Disabled,Enabled"
group.quad SPR:0x339C3++0x00
line.long 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
eventfld.long 0x00  30. "P30,Event Counter 30 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  29. "P29,Event Counter 29 clear bit" "Disabled,Enabled"
eventfld.long 0x00  28. "P28,Event Counter 28 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  27. "P27,Event Counter 27 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  26. "P26,Event Counter 26 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  25. "P25,Event Counter 25 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  24. "P24,Event Counter 24 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  23. "P23,Event Counter 23 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  22. "P22,Event Counter 22 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  21. "P21,Event Counter 21 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  20. "P20,Event Counter 20 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  19. "P19,Event Counter 19 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  18. "P18,Event Counter 18 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  17. "P17,Event Counter 17 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  16. "P16,Event Counter 16 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  15. "P15,Event Counter 15 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  14. "P14,Event Counter 14 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  13. "P13,Event Counter 13 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  12. "P12,Event Counter 12 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  11. "P11,Event Counter 11 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  10. "P10,Event Counter 10 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  9. "P9,Event Counter 9 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  8. "P8,Event Counter 8 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  7. "P7,Event Counter 7 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  6. "P6,Event Counter 6 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  5. "P5,Event Counter 5 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  4. "P4,Event Counter 4 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  3. "P3,Event Counter 3 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  2. "P2,Event Counter 2 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  1. "P1,Event Counter 1 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  0. "P0,Event Counter 0 overflow clear bit" "Disabled,Enabled"
wgroup.quad SPR:0x339C4++0x00
line.long 0x00 "PMSWINC_EL0,Performance Monitor Software Increment"
bitfld.long 0x00  30. "P30,Increment PMN30" "No action,Increment"
bitfld.long 0x00  29. "P29,Increment PMN29" "No action,Increment"
bitfld.long 0x00  28. "P28,Increment PMN28" "No action,Increment"
bitfld.long 0x00  27. "P27,Increment PMN27" "No action,Increment"
newline
bitfld.long 0x00  26. "P26,Increment PMN26" "No action,Increment"
bitfld.long 0x00  25. "P25,Increment PMN25" "No action,Increment"
bitfld.long 0x00  24. "P24,Increment PMN24" "No action,Increment"
bitfld.long 0x00  23. "P23,Increment PMN23" "No action,Increment"
newline
bitfld.long 0x00  22. "P22,Increment PMN22" "No action,Increment"
bitfld.long 0x00  21. "P21,Increment PMN21" "No action,Increment"
bitfld.long 0x00  20. "P20,Increment PMN20" "No action,Increment"
bitfld.long 0x00  19. "P19,Increment PMN19" "No action,Increment"
newline
bitfld.long 0x00  18. "P18,Increment PMN18" "No action,Increment"
bitfld.long 0x00  17. "P17,Increment PMN17" "No action,Increment"
bitfld.long 0x00  16. "P16,Increment PMN16" "No action,Increment"
bitfld.long 0x00  15. "P15,Increment PMN15" "No action,Increment"
newline
bitfld.long 0x00  14. "P14,Increment PMN14" "No action,Increment"
bitfld.long 0x00  13. "P13,Increment PMN13" "No action,Increment"
bitfld.long 0x00  12. "P12,Increment PMN12" "No action,Increment"
bitfld.long 0x00  11. "P11,Increment PMN11" "No action,Increment"
newline
bitfld.long 0x00  10. "P10,Increment PMN10" "No action,Increment"
bitfld.long 0x00  9. "P9,Increment PMN9" "No action,Increment"
bitfld.long 0x00  8. "P8,Increment PMN8" "No action,Increment"
bitfld.long 0x00  7. "P7,Increment PMN7" "No action,Increment"
newline
bitfld.long 0x00  6. "P6,Increment PMN6" "No action,Increment"
bitfld.long 0x00  5. "P5,Increment PMN5" "No action,Increment"
bitfld.long 0x00  4. "P4,Increment PMN4" "No action,Increment"
bitfld.long 0x00  3. "P3,Increment PMN3" "No action,Increment"
newline
bitfld.long 0x00  2. "P2,Increment PMN2" "No action,Increment"
bitfld.long 0x00  1. "P1,Increment PMN1" "No action,Increment"
bitfld.long 0x00  0. "P0,Increment PMN0" "No action,Increment"
group.quad SPR:0x339C5++0x00
line.long 0x00 "PMSELR_EL0,Performance Monitor Select Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.open "Common Event Identification Registers"
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x339C6++0x0
line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
newline
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
newline
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
newline
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
newline
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
newline
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
newline
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x339C6++0x0
line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0"
bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
newline
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
newline
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
newline
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
newline
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
newline
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
endif
rgroup.quad SPR:0x339C7++0x0
line.long 0x00 "PMCEID1_EL0,Common Event Identification Register 1"
bitfld.long 0x00 0. "EVENT32,Level 2 cache allocate" "Not implemented,Implemented"
tree.end
newline
group.quad spr:0x339D0++0x00
line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register"
group.quad SPR:0x339D1++0x00
line.long 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
group.quad SPR:0x339D2++0x00
line.long 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register"
group.quad SPR:0x339E0++0x00
line.long 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register"
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.long 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled"
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
group.quad SPR:0x309E1++0x00
line.long 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set"
bitfld.long 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled"
bitfld.long 0x00  30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.quad SPR:0x309E2++0x00
line.long 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00  30. "P30,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  29. "P29,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  28. "P28,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  27. "P27,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  26. "P26,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  25. "P25,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  24. "P24,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  23. "P23,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  22. "P22,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  21. "P21,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  20. "P20,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  19. "P19,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  18. "P18,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  17. "P17,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  16. "P16,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  15. "P15,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  14. "P14,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  13. "P13,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  12. "P12,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  11. "P11,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  10. "P10,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  9. "P9,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  8. "P8,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  7. "P7,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  6. "P6,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  5. "P5,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  4. "P4,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  3. "P3,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  2. "P2,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  1. "P1,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  0. "P0,Overflow Interrupt Clear" "Disabled,Enabled"
group.quad SPR:0x339E3++0x00
line.long 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register"
group.quad SPR:(0x33E80+0x0)++0x00
line.long 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0"
group.quad SPR:(0x33EC0+0x0)++0x00
line.long 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x1)++0x00
line.long 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1"
group.quad SPR:(0x33EC0+0x1)++0x00
line.long 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x2)++0x00
line.long 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2"
group.quad SPR:(0x33EC0+0x2)++0x00
line.long 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x3)++0x00
line.long 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3"
group.quad SPR:(0x33EC0+0x3)++0x00
line.long 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x4)++0x00
line.long 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4"
group.quad SPR:(0x33EC0+0x4)++0x00
line.long 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x5)++0x00
line.long 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5"
group.quad SPR:(0x33EC0+0x5)++0x00
line.long 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:0x33EF7++0x00
line.long 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.quad SPR:0x33E00++0x00
line.long 0x00 "CNTFRQ_EL0,Counter Frequency Register"
rgroup.quad spr:0x33E01++0x00
line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register"
group.quad SPR:0x30E10++0x00
line.long 0x00 "CNTKCTL_EL1,Timer PL1 Control Register"
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.quad SPR:0x33E20++0x00
line.long 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue register"
group.quad SPR:0x33E21++0x00
line.long 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register"
bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad SPR:0x33E30++0x00
line.long 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register"
group.quad SPR:0x33E31++0x00
line.long 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register"
bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x33E02++0x00
line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register"
group.quad spr:0x33E22++0x00
line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register"
group.quad spr:0x33E32++0x00
line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register"
group.quad spr:0x34E03++0x00
line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register"
group.quad SPR:0x34E10++0x00
line.long 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.quad SPR:0x34E20++0x00
line.long 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register"
group.quad SPR:0x34E21++0x00
line.long 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x34E22++0x00
line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register"
group.quad SPR:0x37E20++0x00
line.long 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register"
group.quad SPR:0x37E21++0x00
line.long 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x37E22++0x00
line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch64 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.quad spr:0x30C84++0x00
line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.quad spr:0x30C90++0x00
line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
if (((per.q(spr:0x30CB6))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
else
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad spr:0x30C83++0x00
line.quad 0x00 "ICC_BPR0_EL1,Interrupt Controller Binary Point Register 0"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.quad spr:0x30CC3++0x00
line.quad 0x00 "ICC_BPR1_EL1,Interrupt Controller Binary Point Register 1"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
group.quad spr:0x30CC4++0x00
line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)"
rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported"
rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Zero,Non-zero"
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6. "PMHE,Controls whether the priority mask Register is used as a hint for interrupt distribution" "Disabled,Enabled"
bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "CBPR,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 interrupts" "Separate registers,Same Register"
group.quad spr:0x36CC4++0x00
line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)"
rbitfld.quad 0x00 19. "ExtRange,Extended INTID range" "Not supported,Supported"
rbitfld.quad 0x00 18. "RSS,Range Selector Support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported"
newline
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop"
bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Priority drop/Deactivation,Priority drop"
bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled"
newline
bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same Register"
bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same Register"
if (((per.q(spr:0x30CC4))&0x3800)==0x00)
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
elif (((per.q(spr:0x30CC4))&0x3800)==0x800)
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
endif
hgroup.quad spr:0x30C80++0x00
hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0"
in
hgroup.quad spr:0x30CC0++0x00
hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1"
in
newline
group.quad SPR:0x30CC6++0x00
line.long 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0"
bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad SPR:0x30CC7++0x00
line.long 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)"
bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad SPR:0x36CC7++0x00
line.long 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)"
bitfld.long 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
group.quad SPR:0x30460++0x00
line.long 0x00 "ICC_PMR_EL1,Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.quad SPR:0x30CB3++0x00
line.long 0x00 "ICC_RPR_EL1,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
if (((per.q(spr:0x30CB7))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated."
else
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
if (((per.q(spr:0x30CB5))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
else
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad SPR:0x30CC5++0x00
line.long 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.quad SPR:0x34C95++0x00
line.long 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.quad SPR:0x36CC5++0x00
line.long 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
tree.end
tree "AArch64 Virtual Interface Control System Registers"
tree.open "Hypervisor Active Priorities Registers"
group.quad SPR:0x34C80++0x00
line.long 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
if (CORENAME()=="CORTEXA53")
group.quad SPR:0x34C90++0x00
line.long 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
endif
tree.end
newline
rgroup.quad SPR:0x34CB3++0x00
line.long 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register"
bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
newline
bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
rgroup.quad SPR:0x34CB5++0x00
line.long 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register"
bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
newline
bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
group.quad SPR:0x34CB0++0x00
line.long 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register"
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
newline
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
newline
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
if (((d.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x0)++0x00
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x0)++0x00
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x1)++0x00
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x1)++0x00
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x2)++0x00
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x2)++0x00
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x3)++0x00
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x3)++0x00
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
rgroup.quad SPR:0x34CB2++0x00
line.long 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register"
bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.quad SPR:0x34CB7++0x00
line.long 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
newline
bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
newline
bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
group.quad SPR:0x34C94++0x00
line.long 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register"
rgroup.quad SPR:0x34CB1++0x00
line.long 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register"
bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
newline
bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "Debug Registers"
rgroup.quad SPR:0x23010++0x00
line.long 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
group.quad SPR:0x20020++0x00
line.long 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register"
bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled"
bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled"
group.quad spr:0x23040++0x00
line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register"
rgroup.quad SPR:0x23050++0x00
line.long 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register"
wgroup.quad SPR:0x23050++0x00
line.long 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register"
group.quad SPR:0x24070++0x00
line.long 0x00 "DBGVCR32_EL2,Vector Catch Register"
bitfld.long 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Low,High"
newline
bitfld.long 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 7. "SF,FIQ vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 6. "SI,IRQ vector catch enable in Secure state" "Low,High"
newline
bitfld.long 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Low,High"
group.quad SPR:0x20002++0x00
line.long 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register"
group.quad SPR:0x20022++0x00
line.long 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 27. "RXO,Save/restore bit" "Low,High"
bitfld.long 0x00 26. "TXU,Save/restore bit" "Low,High"
newline
bitfld.long 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3"
bitfld.long 0x00 21. "TDA,Save/restore bit" "Low,High"
bitfld.long 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
bitfld.long 0x00 14. "HDE,Save/restore bit" "Low,High"
newline
bitfld.long 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
bitfld.long 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled"
bitfld.long 0x00 6. "ERR,Save/restore bit" "Low,High"
bitfld.long 0x00 0. "SS,Software step control" "Disabled,Enabled"
group.quad SPR:0x20032++0x00
line.long 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register"
group.quad SPR:0x20062++0x00
line.long 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register"
rgroup.quad spr:0x20100++0x00
line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register"
hexmask.quad 0x00 12.--47. 0x1000 "ROMADDR,ROM base physical address"
bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid"
wgroup.quad SPR:0x20104++0x00
line.long 0x00 "OSLAR_EL1,OS Lock Access Register"
bitfld.long 0x00 0. "OSLK,OS lock" "Unlock,Lock"
rgroup.quad SPR:0x20114++0x00
line.long 0x00 "OSLSR_EL1,OS Lock Status Register"
bitfld.long 0x00 2. "NTT,Not 32-bit access" "Low,High"
bitfld.long 0x00 1. "OSLK,OS lock status" "Not locked,Locked"
bitfld.long 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Impelemented,?..."
group.quad SPR:0x20134++0x00
line.long 0x00 "OSDLR_EL1,OS Double-lock Register"
bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked"
group.quad SPR:0x20144++0x00
line.long 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register"
bitfld.long 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes"
group.quad SPR:0x20786++0x00
line.long 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set"
bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set"
newline
bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set"
bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.quad SPR:0x20796++0x00
line.long 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.quad SPR:0x207E6++0x00
line.long 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
group.quad SPR:0x33450++0x00
line.long 0x00 "DSPSR_EL0,Debug Saved Processor Status Register"
group.quad spr:0x33451++0x00
line.quad 0x00 "DLR_EL0,Debug Link Register"
tree.end
tree "Breakpoint Registers"
if (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x0)++0x0
line.long 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x10)++0x0
line.long 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x20)++0x0
line.long 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x30)++0x0
line.long 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x40)++0x0
line.long 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x50)++0x0
line.long 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Watchpoint Control Registers"
group.quad spr:(0x20006+0x0)++0x00 "Watchpoint 0"
line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x10)++0x00 "Watchpoint 1"
line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x20)++0x00 "Watchpoint 2"
line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x30)++0x00 "Watchpoint 3"
line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree.end
tree.open "AArch32"
tree "ID Registers"
rgroup.long c15:0x0000++0x0
line.long 0x0 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code"
bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8"
newline
hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number"
bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA57")
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
if corename()=="CORTEXA57"
rgroup.long c15:0x0300++0x0
line.long 0x0 "TLBTR,TLB Type Register"
endif
if corename()=="CORTEXA57"
rgroup.long c15:0x0500++0x0
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
newline
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented"
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
newline
bitfld.long 0x00 0.--1. "CPUID,Indicates the core number in the device" "1,2,3,4"
elif corename()=="CORTEXA53"
rgroup.long c15:0x0500++0x0
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
newline
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,?..."
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
newline
hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
endif
rgroup.long c15:0x0600++0x0
line.long 0x0 "REVIDR,Revision ID Register"
rgroup.long c15:0x0410++0x00
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..."
bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
rgroup.long c15:0x0620++0x00
line.long 0x00 "ID_MMFR4,ID_MMFR4"
bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
rgroup.long c15:0x0020++0x00
line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.long c15:0x0120++0x00
line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1"
bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0220++0x00
line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2"
bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0320++0x00
line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3"
bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..."
bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0420++0x00
line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4"
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5"
bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
newline
bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x0110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
newline
bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
if corename()=="CORTEXA57"
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
elif corename()=="CORTEXA53"
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
endif
group.long c15:0x0310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
if corename()=="CORTEXA57"
rgroup.long c15:0x6C9++0x0
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
newline
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
newline
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
newline
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
newline
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
newline
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
rgroup.long c15:0x7C9++0x0
line.long 0x00 "PMCEID1,Common Event Identification Register 1"
elif corename()=="CORTEXA53"
rgroup.long c15:0x6C9++0x0
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
newline
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
newline
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
newline
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
newline
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
newline
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
rgroup.long c15:0x7C9++0x0
line.long 0x00 "PMCEID1,Common Event Identification Register 1"
bitfld.long 0x00 0. "EVENT32,L2D Cache Allocate" "Not implemented,Implemented"
endif
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
tree.end
tree "System Control and Configuration"
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,System Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
else
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
endif
group.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes"
newline
bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes"
bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled"
newline
bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes"
bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes"
newline
bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled"
bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled"
newline
bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes"
bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes"
newline
bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes"
bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes"
newline
bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes"
bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes"
newline
bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes"
newline
bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced"
bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes"
newline
bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced"
bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes"
newline
bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes"
bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes"
newline
bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled"
bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced"
newline
bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
newline
bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced"
bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced"
newline
bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes"
bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes"
newline
bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes"
bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes"
newline
bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes"
bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced"
bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced"
newline
bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled"
bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled"
newline
bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled"
bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced"
newline
bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes"
bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled"
bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes"
bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes"
bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled"
group.quad c15:0x110F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes"
bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines"
newline
bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
newline
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad c15:0x120F0++0x01
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address"
group.long c15:0x0101++0x0
line.long 0x0 "ACTLR,Auxiliary Control Register"
elif corename()=="CORTEXA53"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes"
bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes"
newline
bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
newline
bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes"
bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes"
newline
bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes"
bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes"
newline
bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams"
bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled"
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes"
group.quad c15:0x110F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
newline
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad c15:0x120F0++0x01
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address"
group.long c15:0x0101++0x0
line.long 0x0 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
endif
if corename()=="CORTEXA57"
group.long c15:0x0201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 28. "TRCDIS,Disable CP14 access to trace registers" "No,Yes"
newline
bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full"
bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full"
elif corename()=="CORTEXA53"
group.long c15:0x201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 only,Reserved,Full"
newline
bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 only,Reserved,Full"
endif
group.long c15:0x0011++0x0
line.long 0x00 "SCR,Secure Configuration Register"
bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
newline
bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes"
newline
bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes"
bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
newline
bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
bitfld.long 0x00 3. "EA,External Abort  exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
newline
bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
newline
bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure"
group.long c15:0x0111++0x00
line.long 0x00 "SDER,Secure Debug Enable Register"
bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted"
group.long c15:0x0131++0x00
line.long 0x00 "SDCR,Secure Debug Control Register"
bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
newline
bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
group.long c15:0x0211++0x00
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
newline
bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
if corename()=="CORTEXA57"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
group.long c15:0x010C++0x00
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
elif corename()=="CORTEXA53"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
group.long c15:0x010C++0x00
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
endif
rgroup.long c15:0x001C++0x00
line.long 0x00 "ISR,Interrupt Status Register"
bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending"
bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
newline
bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
group.long c15:0x020C++0x00
line.long 0x00 "RMR,Reset Management Register"
bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64"
group.long c15:0x0015++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
group.long c15:0x0115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable"
bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable"
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Async. external,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Async. parity/on memory access,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable"
bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable"
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/1st level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/1st level,Permission/1nd level,Sync. external/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..."
endif
elif corename()=="CORTEXA53"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX/STREX,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/section,Instruction cache maintenance,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/1st level,Permission/section,Sync. external/2nd level,Permission/2nd level,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..."
endif
endif
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif corename()=="CORTEXA53"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
group.long c15:0x0006++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
group.long c15:0x0206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
if corename()=="CORTEXA57"
rgroup.long c15:0x103F++0x00
line.long 0x00 "CBAR,Configuration Base Address Register"
hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]"
hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[42:32],Periphbase[42:32]"
elif corename()=="CORTEXA53"
rgroup.long c15:0x103F++0x00
line.long 0x00 "CBAR,Configuration Base Address Register"
hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]"
hexmask.long.byte 0x00 0.--7. 1. "PERIPHBASE[39:32],Periphbase[39:32]"
endif
group.long c15:0x000D++0x00
line.long 0x00 "FCSEIDR,FCSE Process ID register"
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register"
tree.end
tree "Memory Management Unit"
if corename()=="CORTEXA57"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
// MPIDR[31]==1 case is missing here for TTBR0 and TTBR1
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Registers"
hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base address"
bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner"
newline
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 2. "IMP,Implementation" "Low,High"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Registers"
hexmask.long 0x00 6.--31. 0x40 "TTBA,Translation table base address"
bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner"
newline
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 2. "IMP,Implementation" "Low,High"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
else
group.quad c15:0x10020++0x01
line.quad 0x00 "TTBR0,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad c15:0x11020++0x01
line.quad 0x00 "TTBR1,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
endif
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
newline
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
else
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable"
newline
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
newline
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected"
newline
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
endif
elif corename()=="CORTEXA53"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.quad c15:0x10020++0x01
line.quad 0x00 "TTBR0,Translation Table Base Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad c15:0x11020++0x01
line.quad 0x00 "TTBR1,Translation Table Base Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
newline
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected"
newline
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
else
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Register 0"
hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base 0 address"
bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Register 1"
hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base 1 address"
bitfld.long 0x00 0. 6. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
newline
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
endif
endif
if corename()=="CORTEXA57"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
elif corename()=="CORTEXA53"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
endif
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
group.long c15:0x0003++0x00
line.long 0x00 "DACR,Domain Access Control Register"
bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
else
group.long c15:0x0047++0x00
line.long 0x00 "PAR,Physical Address Register"
endif
tree.open "Memory Attribute Indirection Registers"
group.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x003A++0x00
line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x013A++0x00
line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x002A++0x0
line.long 0x00 "PRRR,Primary Region Remap Register"
bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 19. "NS1,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
bitfld.long 0x00 18. "NS0,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
newline
bitfld.long 0x00 17. "DS1,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
bitfld.long 0x00 16. "DS0,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
newline
bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
group.long c15:0x012A++0x0
line.long 0x00 "NMRR,Normal Memory Remap Register"
bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
endif
tree.end
newline
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x10d++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
else
group.long c15:0x10d++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier"
hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier"
endif
tree.end
tree "Virtualization Extensions"
group.long c15:0x4000++0x0
line.long 0x00 "VPIDR,Virtualization Processor ID Register"
group.long c15:0x4500++0x00
line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
group.long c15:0x4101++0x00
line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
if corename()=="CORTEXA57"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hypervisor Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
newline
bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
newline
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3"
newline
bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted"
newline
bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed"
bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed"
newline
bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed"
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
elif corename()=="CORTEXA53"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hypervisor Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
bitfld.long 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
newline
bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
newline
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
newline
bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
newline
bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3"
bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "No aborted,Aborted"
bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 5. "AMO,A-bit Mask Override" "No override,Override"
newline
bitfld.long 0x00 4. "IMO,I-bit Mask Override" "No override,Override"
bitfld.long 0x00 3. "FMO,F-bit Mask Override" "No override,Override"
newline
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
newline
bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
endif
group.long c15:0x4411++0x00
line.long 0x00 "HCR2,Hypervisor Configuration Register 2"
bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes"
group.long c15:0x4111++0x00
line.long 0x00 "HDCR,Hypervisor Debug Control Register"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
newline
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
newline
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long c15:0x4211++0x00
line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x0 20. "TTA,Trap Trace Access" "Not trapped,?..."
newline
bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped"
bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped"
newline
bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped"
group.long c15:0x4311++0x00
line.long 0x00 "HSTR,Hypervisor System Trap Register"
bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Disabled,Enabled"
bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "Reserved,?..."
newline
hexmask.long.word 0x00 5.--13. 1. "T4_15,Trap to Hypervisor mode Non-secure priv 5 - 13"
bitfld.long 0x00 0.--3. "T0_13,Trap to Hypervisor mode Non-secure priv 0 - 3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x4711++0x00
line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register"
if corename()=="CORTEXA57"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
elif corename()=="CORTEXA53"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
endif
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
group.long c15:0x4212++0x00
line.long 0x00 "VTCR,Virtualization Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High"
bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x4015++0x00
line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register"
group.long c15:0x4115++0x00
line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Syndrome Register"
group.long c15:0x4006++0x00
line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register"
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to c15,Trapped MCRR/MRRC to c15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,Reserved,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome"
group.long c15:0x4206++0x00
line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register"
group.long c15:0x4406++0x00
line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register"
hexmask.long 0x00 4.--31. 1. "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address"
tree.open "Hypervisor Memory Attribute Indirection Registers"
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
tree.end
newline
group.long c15:0x400C++0x00
line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address"
tree.end
tree "Cache Control and Configuration"
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,PIPT"
newline
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
if corename()=="CORTEXA57"
rgroup.long c15:0x1100++0x0
line.long 0x0 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..."
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
newline
bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..."
bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..."
bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..."
newline
bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
elif corename()=="CORTEXA53"
rgroup.long c15:0x1100++0x0
line.long 0x0 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..."
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
endif
rgroup.long c15:0x1700++0x0
line.long 0x00 "AIDR,Auxiliary ID Register"
rgroup.long c15:0x1000++0x0
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,Supported"
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
newline
bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
newline
hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "16 bytes,32 bytes,64 bytes,128 bytes,?..."
group.long c15:0x2000++0x0
line.long 0x0 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
tree "Level 1 memory system"
if corename()=="CORTEXA57"
group.long c15:0x001F++0x00
line.long 0x00 "DL1DATA0,Data L1 Data 0 Register"
group.long c15:0x011F++0x00
line.long 0x00 "DL1DATA1,Data L1 Data 1 Register"
group.long c15:0x021F++0x00
line.long 0x00 "DL1DATA2,Data L1 Data 2 Register"
group.long c15:0x031F++0x00
line.long 0x00 "DL1DATA3,Data L1 Data 3 Register"
group.long c15:0x000F++0x00
line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register"
group.long c15:0x010F++0x00
line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register"
group.long c15:0x020F++0x00
line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register"
group.long c15:0x030F++0x00
line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register"
wgroup.long c15:0x04F++0x00
line.long 0x00 "RAMINDEX,RAM Index Operation Register"
elif corename()=="CORTEXA53"
rgroup.long c15:0x300F++0x00
line.long 0x00 "CDBGDR0,Cache Debug Data Register 0"
rgroup.long c15:0x310F++0x00
line.long 0x00 "CDBGDR1,Cache Debug Data Register 1"
rgroup.long c15:0x320F++0x00
line.long 0x00 "CDBGDR2,Cache Debug Data Register 2"
rgroup.long c15:0x330F++0x00
line.long 0x00 "CDBGDR3,Cache Debug Data Register 3"
wgroup.long c15:0x302F++0x00
line.long 0x00 "CDBGDCT,Cache Debug Data Cache Tag Read Operation Register"
wgroup.long c15:0x312F++0x00
line.long 0x00 "CDBGICT,Cache Debug Instruction Cache Tag Read Operation Register"
wgroup.long c15:0x304F++0x00
line.long 0x00 "CDBGDCD,Cache Debug Cache Debug Data Cache Data Read Operation Register"
wgroup.long c15:0x314F++0x00
line.long 0x00 "CDBGICD,Cache Debug Instruction Cache Data Read Operation Register"
wgroup.long c15:0x324F++0x00
line.long 0x00 "CDBGTD,Cache Debug TLB Data Read Operation Register"
endif
tree.end
tree "Level 2 memory system"
if corename()=="CORTEXA57"
group.long c15:0x1209++0x0
line.long 0x00 "L2CTLR,L2 Control Register"
bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes"
bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4"
newline
rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Not supported,Supported"
bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "DIECCE,Data in-line ECC enable" "Disabled,Enabled"
rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present"
newline
rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present"
rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1,2,Present"
newline
bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle"
bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
newline
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle"
bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
group.long c15:0x1309++0x0
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
newline
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.long c15:0x100F++0x00
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled"
bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced"
bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled"
newline
bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes"
bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
newline
bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled"
bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit"
newline
bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes"
bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes"
bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes"
newline
bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes"
bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes"
newline
bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled"
bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes"
newline
bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled"
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
newline
bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited"
bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes"
group.quad c15:0x130F0++0x01
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index"
elif corename()=="CORTEXA53"
group.long c15:0x1209++0x0
line.long 0x00 "L2CTLR,L2 Control Register"
bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4"
bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
newline
rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
newline
rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles"
group.long c15:0x1309++0x0
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
newline
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.long c15:0x100F++0x00
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
bitfld.long 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
group.quad c15:0x110F0++0x01
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address"
endif
tree.end
tree.end
tree "System Performance Monitor"
group.long c15:0xc9++0x00
line.long 0x0 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
newline
group.long c15:0x1c9++0x00
line.long 0x00 "PMNCNTENSET,Count Enable Set Register "
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled"
bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled"
bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled"
bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled"
bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled"
bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled"
bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled"
bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled"
bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled"
bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled"
bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled"
bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled"
bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled"
bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled"
bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled"
bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled"
bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled"
bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled"
bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled"
bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
group.long c15:0x2c9++0x00
line.long 0x00 "PMCNTENCLR,Count Enable Clear Register"
eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled"
eventfld.long 0x00 29. "P29,Event Counter 29 clear bit " "Disabled,Enabled"
eventfld.long 0x00 28. "P28,Event Counter 28 clear bit " "Disabled,Enabled"
eventfld.long 0x00 27. "P27,Event Counter 27 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 26. "P26,Event Counter 26 clear bit " "Disabled,Enabled"
eventfld.long 0x00 25. "P25,Event Counter 25 clear bit " "Disabled,Enabled"
eventfld.long 0x00 24. "P24,Event Counter 24 clear bit " "Disabled,Enabled"
eventfld.long 0x00 23. "P23,Event Counter 23 clear bit " "Disabled,Enabled"
eventfld.long 0x00 22. "P22,Event Counter 22 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 21. "P21,Event Counter 21 clear bit " "Disabled,Enabled"
eventfld.long 0x00 20. "P20,Event Counter 20 clear bit " "Disabled,Enabled"
eventfld.long 0x00 19. "P19,Event Counter 19 clear bit " "Disabled,Enabled"
eventfld.long 0x00 18. "P18,Event Counter 18 clear bit " "Disabled,Enabled"
eventfld.long 0x00 17. "P17,Event Counter 17 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 16. "P16,Event Counter 16 clear bit " "Disabled,Enabled"
eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled"
eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled"
eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled"
eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled"
eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled"
eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled"
eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled"
eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled"
eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled"
eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled"
eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled"
eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled"
eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled"
group.long c15:0x3c9++0x00
line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register"
eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
eventfld.long 0x00 30. "P30,PMN30 overflow" "No overflow,Overflow"
eventfld.long 0x00 29. "P29,PMN29 overflow" "No overflow,Overflow"
eventfld.long 0x00 28. "P28,PMN28 overflow" "No overflow,Overflow"
eventfld.long 0x00 27. "P27,PMN27 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 26. "P26,PMN26 overflow" "No overflow,Overflow"
eventfld.long 0x00 25. "P25,PMN25 overflow" "No overflow,Overflow"
eventfld.long 0x00 24. "P24,PMN24 overflow" "No overflow,Overflow"
eventfld.long 0x00 23. "P23,PMN23 overflow" "No overflow,Overflow"
eventfld.long 0x00 22. "P22,PMN22 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 21. "P21,PMN21 overflow" "No overflow,Overflow"
eventfld.long 0x00 20. "P20,PMN20 overflow" "No overflow,Overflow"
eventfld.long 0x00 19. "P19,PMN19 overflow" "No overflow,Overflow"
eventfld.long 0x00 18. "P18,PMN18 overflow" "No overflow,Overflow"
eventfld.long 0x00 17. "P17,PMN17 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 16. "P16,PMN16 overflow" "No overflow,Overflow"
eventfld.long 0x00 15. "P15,PMN15 overflow" "No overflow,Overflow"
eventfld.long 0x00 14. "P14,PMN14 overflow" "No overflow,Overflow"
eventfld.long 0x00 13. "P13,PMN13 overflow" "No overflow,Overflow"
eventfld.long 0x00 12. "P12,PMN12 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 11. "P11,PMN11 overflow" "No overflow,Overflow"
eventfld.long 0x00 10. "P10,PMN10 overflow" "No overflow,Overflow"
eventfld.long 0x00 9. "P9,PMN9 overflow" "No overflow,Overflow"
eventfld.long 0x00 8. "P8,PMN8 overflow" "No overflow,Overflow"
eventfld.long 0x00 7. "P7,PMN7 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 6. "P6,PMN6 overflow" "No overflow,Overflow"
eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
group.long c15:0x4c9++0x00
line.long 0x00 "PMSWINC,Performance Monitor Software Increment"
bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment"
bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment"
bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment"
bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment"
bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment"
newline
bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment"
bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment"
bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment"
bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment"
bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment"
newline
bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment"
bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment"
bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment"
bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment"
bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment"
newline
bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment"
bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment"
bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment"
bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment"
bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment"
newline
bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment"
bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment"
bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment"
bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment"
bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment"
newline
bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment"
bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment"
bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment"
bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment"
bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment"
newline
bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment"
group.long c15:0x5c9++0x00
line.long 0x00 "PMSELR,Performance Monitor Select Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
group.long c15:0xd9++0x00
line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register"
group.long c15:0x1d9++0x00
line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register"
group.long c15:0x2d9++0x00
line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register"
group.long c15:0xe9++0x00
line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register"
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled"
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
group.long c15:0x1e9++0x00
line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.long c15:0x2e9++0x00
line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear"
eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled"
group.long c15:0x3e9++0x00
line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register"
group.long c15:0x8E++0x00
line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0"
group.long c15:(0x8E+0x40)++0x00
line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x18E++0x00
line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1"
group.long c15:(0x18E+0x40)++0x00
line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x28E++0x00
line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2"
group.long c15:(0x28E+0x40)++0x00
line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x38E++0x00
line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3"
group.long c15:(0x38E+0x40)++0x00
line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x48E++0x00
line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4"
group.long c15:(0x48E+0x40)++0x00
line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x58E++0x00
line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5"
group.long c15:(0x58E+0x40)++0x00
line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x07FE++0x00
line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.long c15:0x000E++0x00
line.long 0x00 "CNTFRQ,Counter Frequency Register"
rgroup.quad c15:0x100E0++0x01
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
group.long c15:0x001E++0x00
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.long c15:0x002E++0x00
line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register"
group.long c15:0x012E++0x00
line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.long c15:0x003E++0x00
line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register"
group.long c15:0x013E++0x00
line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x110E0++0x01
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
group.quad c15:0x120E0++0x01
line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register"
group.quad c15:0x130E0++0x01
line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register"
group.quad c15:0x140E0++0x01
line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register"
group.long c15:0x401E++0x00
line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register"
bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
group.long c15:0x402E++0x00
line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register"
group.long c15:0x412E++0x00
line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x160E0++0x01
line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch32 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.long c15:0x048C++0x00
line.long 0x00 "ICC_AP0R0,Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x009C++0x00
line.long 0x00 "ICC_AP1R0,Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
wgroup.quad c15:0x110C0++0x01
line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "SGIID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.long c15:0x038C++0x00
line.long 0x00 "ICC_BPR0,Binary Point Register 0"
bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.long c15:0x03CC++0x00
line.long 0x00 "ICC_BPR1,Binary Point Register 1"
bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.long c15:0x04CC++0x00
line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported"
rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1"
newline
bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1"
group.long c15:0x64CC++0x00
line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3"
rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported"
newline
rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled"
bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled"
bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled"
newline
bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register"
bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register"
if (((per.l(c15:0x4CC))&0x3800)==0x00)
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
elif (((per.l(c15:0x4CC))&0x3800)==0x800)
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
endif
hgroup.long c15:0x008C++0x00
hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0"
in
hgroup.long c15:0x00CC++0x00
hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1"
in
group.long c15:0x06CC++0x00
line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x07CC++0x00
line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x0064++0x00
line.long 0x00 "ICC_PMR,Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.long c15:0x03BC++0x00
line.long 0x00 "ICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
wgroup.quad c15:0x120C0++0x01
line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
wgroup.quad c15:0x100C0++0x01
line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.long c15:0x05CC++0x00
line.long 0x00 "ICC_SRE,System Register Enable Register for EL1"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
if corename()=="CORTEXA53"
group.long c15:0x459C++0x00
line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
endif
group.long c15:0x65CC++0x00
line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.long c15:0x67CC++0x00
line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable"
bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
tree.end
tree "AArch32 Virtual Interface Control System Registers"
tree.open "Hypervisor Active Priorities Registers"
group.long c15:0x408C++0x00
line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x409C++0x00
line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
rgroup.long c15:0x43BC++0x00
line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register"
bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
newline
bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
rgroup.long c15:0x45BC++0x00
line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register"
bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
newline
bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
group.long c15:0x40BC++0x00
line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register"
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
newline
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
newline
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
group.long c15:(0x40CC+0x0)++0x00
line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x100)++0x00
line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x200)++0x00
line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x300)++0x00
line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40EC+0x0)++0x00
line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x100)++0x00
line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x200)++0x00
line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x300)++0x00
line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
rgroup.long c15:0x42BC++0x00
line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register"
bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.long c15:0x459C++0x00
line.long 0x00 "ICH_SRE,Hypervisor System Register"
group.long c15:0x47BC++0x00
line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
newline
bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
newline
bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
group.long c15:0x449C++0x00
line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register"
rgroup.long c15:0x41BC++0x00
line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register"
bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
newline
bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "Debug Registers"
tree "Coresight Management Registers"
if corename()=="CORTEXA57"
rgroup.long c14:0x0000++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
newline
hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version"
bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported"
bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented"
elif corename()=="CORTEXA53"
rgroup.long c14:0x0000++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
newline
hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version"
bitfld.long 0x0 15. "DEVID,Debug Device ID" "Low,High"
bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported"
newline
bitfld.long 0x0 13. "PCSR,PC Sample register implemented" "Not implemented,Implemented"
bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented"
hexmask.long.byte 0x0 4.--7. 1. "VARIANT,Implementation-defined Variant Number"
newline
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Implementation-defined Revision Number"
endif
rgroup.long c14:0x0060++0x0
line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register"
group.long c14:0x0070++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled"
bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
group.long c14:0x0020++0x00
line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register"
bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled"
bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled"
group.long c14:0x0200++0x0
line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)"
group.long c14:0x0220++0x0
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled"
bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled"
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled"
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled"
newline
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
rgroup.long c14:0x0010++0x0
line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
wgroup.long c14:0x0230++0x0
line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)"
group.long c14:0x0050++0x0
line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)"
group.long c14:0x0687++0x0
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.long c14:0x0697++0x0
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.long c14:0x06E7++0x0
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. "SNDFI,Secure non-invasive debug features implementation" "No effect,Implemented"
bitfld.long 0x00 6. "SNDE,Secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 5. "SIDFI,Secure invasive debug features implementation" "No effect,Implemented"
newline
bitfld.long 0x00 4. "SIDE,Secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NSNDFI,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNDE,Non-secure non-invasive debug enable" "0,1"
newline
bitfld.long 0x00 1. "NSIDFI,Non-secure invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSIDE,Non-secure invasive debug enable" "0,1"
rgroup.long c14:0x0707++0x0
line.long 0x0 "DBGDEVID2,Debug Device ID Register 2"
rgroup.long c14:0x0717++0x0
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" "0,1,No offset,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c14:0x0727++0x00
line.long 0x00 "DBGDEVID,Debug Device ID Register 0"
bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..."
bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" "Not implemented,?..."
bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..."
bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented"
newline
bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..."
tree.end
newline
rgroup.quad c14:0x10010++0x1
line.quad 0x0 "DBGDRAR,Debug ROM Address Register"
hexmask.quad.word 0x0 32.--47. 0x1 "ROMADDR,ROM physical address"
hexmask.quad.tbyte 0x0 12.--31. 0x10 "ROMADDR,ROM physical address"
bitfld.quad 0x0 1. "VALID1,ROM table address valid" "Not valid,Valid"
newline
bitfld.quad 0x0 0. "VALID0,ROM table address valid" "Not valid,Valid"
rgroup.quad c14:0x10020++0x1
line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
wgroup.long c14:0x0401++0x00
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
rgroup.long c14:0x0411++0x00
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required"
bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked"
bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..."
if (((per.l(c14:0x0411))&0x2)==0x2)
group.long c14:0x0260++0x00
line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
else
hgroup.long c14:0x0260++0x00
hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
endif
group.long c14:0x0431++0x00
line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register"
bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked"
group.long c14:0x0441++0x00
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Low,High"
tree.end
tree "Breakpoint Registers"
if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
line.long 0x00 "DBGBVR0,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
hide.long 0x00 "DBGBVR0,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
line.long 0x00 "DBGBVR0,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x0)++0x0
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
line.long 0x00 "DBGBVR1,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
hide.long 0x00 "DBGBVR1,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
line.long 0x00 "DBGBVR1,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x10)++0x0
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
line.long 0x00 "DBGBVR2,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
hide.long 0x00 "DBGBVR2,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
line.long 0x00 "DBGBVR2,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x20)++0x0
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
line.long 0x00 "DBGBVR3,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
hide.long 0x00 "DBGBVR3,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
line.long 0x00 "DBGBVR3,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x30)++0x0
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
line.long 0x00 "DBGBVR4,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
hide.long 0x00 "DBGBVR4,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
line.long 0x00 "DBGBVR4,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x40)++0x0
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
line.long 0x00 "DBGBVR5,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
hide.long 0x00 "DBGBVR5,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
line.long 0x00 "DBGBVR5,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x50)++0x0
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
group.long c14:0x0141++0x0
line.long 0x00 "DBGBXVR4,Debug Breakpoint Extended Value Register 4"
hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value"
group.long c14:0x0151++0x0
line.long 0x00 "DBGBXVR5,Debug Breakpoint Extended Value Register 5"
hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value"
tree.end
tree "Watchpoint Control Registers"
group.long c14:(0x0600+0x0)++0x00 "Breakpoint 0"
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x10)++0x00 "Breakpoint 1"
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x20)++0x00 "Breakpoint 2"
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x30)++0x00 "Breakpoint 3"
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
tree.end
tree.end
AUTOINDENT.OFF
AUTOINDENT.POP
tree.open "Interrupt Controller (GIC-500)"
base COMP.BASE("GICD",-1.)
width 17.
tree "Distributor Interface"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)))
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
bitfld.long 0x00 6. "       DS            ,Disable Security" "No,Yes"
textline "                          "
bitfld.long 0x00 5. " ARE_NS       ,Affinity Routing Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "       ARE_S      ,Affinity Routing Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "       ENABLEGRP1S   ,Enable Secure Group 1 interrupts" "Disabled,Enabled"
textline "                          "
bitfld.long 0x00 1. " ENABLEGRP1NS ,Enable Secure Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
bitfld.long 0x00 4. "       ARE_NS        ,Affinity Routing Enable" "Reserved,Enabled"
textline "                          "
bitfld.long 0x00 1. " ENABLEGRP1A  ,Enable Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled"
else
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
rbitfld.long 0x00 6. "       DS            ,Disable Security" "Reserved,Yes"
textline "                          "
bitfld.long 0x00 4. " ARE          ,Affinity Routing Enable" "Reserved,Enabled"
bitfld.long 0x00 1. "       ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP0    ,Enable Group 0 interrupts" "Disabled,Enabled"
endif
rgroup.long 0x0004++0x03
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
bitfld.long 0x00 25. " NO1N         ,Indicates whether 1 of N SPI interrupts are supported" "Supported,Not supported"
bitfld.long 0x00 24. "  A3V        ,Indicates whether the Distributor supports nonzero values of Affinity level 3" "Not supported,Supported"
bitfld.long 0x00 19.--23. "  IDBITS        ,The number of interrupt identifier bits supported" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
textline "                          "
bitfld.long 0x00 17. " LPIS         ,Indicates whether the implementation supports LPIs" "Not supported,Supported"
bitfld.long 0x00 16. "  MBIS       ,Indicates whether the implementation supports message-based interrupts by writing to Distributor registers" "Not supported,Supported"
bitfld.long 0x00 10. "  SECURITYEXTN  ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented"
textline "                          "
bitfld.long 0x00 5.--7. " CPUNUMBER    ,Reports the number of PEs that can be used when affinity routing is not enabled" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 0.--4. "              ITLN       ,Indicates the maximum SPI INTID that the GIC implementation supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved"
rgroup.long 0x0008++0x03
line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register"
bitfld.long 0x00 24.--31. " PRODID       ,Indicates the product ID" "GIC-500,?..."
bitfld.long 0x00 16.--19. "        VAR        ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                          "
bitfld.long 0x00 12.--15. " REV          ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "             IMP        ,Implementer"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x10000)==0x10000)
wgroup.long 0x40++0x03
line.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
wgroup.long 0x48++0x03
line.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50))
wgroup.long 0x50++0x03
line.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Secure access)"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
else
hgroup.long 0x50++0x03
hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Non-secure access)"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58))
wgroup.long 0x58++0x03
line.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Secure access)"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
else
hgroup.long 0x58++0x03
hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)"
endif
else
hgroup.long 0x40++0x03
hide.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register"
hgroup.long 0x48++0x03
hide.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register"
hgroup.long 0x50++0x03
hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register"
hgroup.long 0x58++0x03
hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register"
endif
width 17.
tree "Group Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0080))
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)"
bitfld.long 0x00 31. " GSB31  ,Group Status Bit 31" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB30  ,Group Status Bit 30" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB29  ,Group Status Bit 29" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB28  ,Group Status Bit 28" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB27  ,Group Status Bit 27" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB26  ,Group Status Bit 26" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB25  ,Group Status Bit 25" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB24  ,Group Status Bit 24" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB23  ,Group Status Bit 23" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB22  ,Group Status Bit 22" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB21  ,Group Status Bit 21" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB20  ,Group Status Bit 20" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB19  ,Group Status Bit 19" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB18  ,Group Status Bit 18" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB17  ,Group Status Bit 17" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB16  ,Group Status Bit 16" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB15  ,Group Status Bit 15" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB14  ,Group Status Bit 14" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB13  ,Group Status Bit 13" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB12  ,Group Status Bit 12" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB11  ,Group Status Bit 11" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB10  ,Group Status Bit 10" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB9   ,Group Status Bit 9" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB8   ,Group Status Bit 8" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB7   ,Group Status Bit 7" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB6   ,Group Status Bit 6" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB5   ,Group Status Bit 5" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB4   ,Group Status Bit 4" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB3   ,Group Status Bit 3" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB2   ,Group Status Bit 2" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB1   ,Group Status Bit 1" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB0   ,Group Status Bit 0" "Secure,Non-secure Group 1"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. " GSB31  ,Group Status Bit 31" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB30  ,Group Status Bit 30" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB29  ,Group Status Bit 29" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB28  ,Group Status Bit 28" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB27  ,Group Status Bit 27" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB26  ,Group Status Bit 26" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB25  ,Group Status Bit 25" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB24  ,Group Status Bit 24" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB23  ,Group Status Bit 23" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB22  ,Group Status Bit 22" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB21  ,Group Status Bit 21" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB20  ,Group Status Bit 20" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB19  ,Group Status Bit 19" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB18  ,Group Status Bit 18" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB17  ,Group Status Bit 17" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB16  ,Group Status Bit 16" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB15  ,Group Status Bit 15" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB14  ,Group Status Bit 14" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB13  ,Group Status Bit 13" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB12  ,Group Status Bit 12" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB11  ,Group Status Bit 11" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB10  ,Group Status Bit 10" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB9   ,Group Status Bit 9" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB8   ,Group Status Bit 8" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB7   ,Group Status Bit 7" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB6   ,Group Status Bit 6" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB5   ,Group Status Bit 5" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB4   ,Group Status Bit 4" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB3   ,Group Status Bit 3" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB2   ,Group Status Bit 2" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB1   ,Group Status Bit 1" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB0   ,Group Status Bit 0" "Group 0,Group 1"
else
hgroup.long 0x0080++0x03
hide.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1))
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)"
bitfld.long 0x00 31. " GSB63  ,Group Status Bit 63" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB62  ,Group Status Bit 62" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB61  ,Group Status Bit 61" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB60  ,Group Status Bit 60" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB59  ,Group Status Bit 59" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB58  ,Group Status Bit 58" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB57  ,Group Status Bit 57" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB56  ,Group Status Bit 56" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB55  ,Group Status Bit 55" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB54  ,Group Status Bit 54" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB53  ,Group Status Bit 53" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB52  ,Group Status Bit 52" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB51  ,Group Status Bit 51" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB50  ,Group Status Bit 50" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB49  ,Group Status Bit 49" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB48  ,Group Status Bit 48" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB47  ,Group Status Bit 47" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB46  ,Group Status Bit 46" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB45  ,Group Status Bit 45" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB44  ,Group Status Bit 44" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB43  ,Group Status Bit 43" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB42  ,Group Status Bit 42" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB41  ,Group Status Bit 41" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB40  ,Group Status Bit 40" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB39  ,Group Status Bit 39" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB38  ,Group Status Bit 38" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB37  ,Group Status Bit 37" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB36  ,Group Status Bit 36" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB35  ,Group Status Bit 35" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB34  ,Group Status Bit 34" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB33  ,Group Status Bit 33" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB32  ,Group Status Bit 32" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1))
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 "
bitfld.long 0x00 31. " GSB63  ,Group Status Bit 63" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB62  ,Group Status Bit 62" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB61  ,Group Status Bit 61" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB60  ,Group Status Bit 60" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB59  ,Group Status Bit 59" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB58  ,Group Status Bit 58" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB57  ,Group Status Bit 57" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB56  ,Group Status Bit 56" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB55  ,Group Status Bit 55" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB54  ,Group Status Bit 54" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB53  ,Group Status Bit 53" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB52  ,Group Status Bit 52" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB51  ,Group Status Bit 51" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB50  ,Group Status Bit 50" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB49  ,Group Status Bit 49" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB48  ,Group Status Bit 48" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB47  ,Group Status Bit 47" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB46  ,Group Status Bit 46" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB45  ,Group Status Bit 45" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB44  ,Group Status Bit 44" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB43  ,Group Status Bit 43" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB42  ,Group Status Bit 42" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB41  ,Group Status Bit 41" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB40  ,Group Status Bit 40" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB39  ,Group Status Bit 39" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB38  ,Group Status Bit 38" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB37  ,Group Status Bit 37" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB36  ,Group Status Bit 36" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB35  ,Group Status Bit 35" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB34  ,Group Status Bit 34" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB33  ,Group Status Bit 33" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB32  ,Group Status Bit 32" "Group 0,Group 1"
else
hgroup.long 0x0084++0x03
hide.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2))
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)"
bitfld.long 0x00 31. " GSB95  ,Group Status Bit 95" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB94  ,Group Status Bit 94" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB93  ,Group Status Bit 93" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB92  ,Group Status Bit 92" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB91  ,Group Status Bit 91" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB90  ,Group Status Bit 90" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB89  ,Group Status Bit 89" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB88  ,Group Status Bit 88" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB87  ,Group Status Bit 87" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB86  ,Group Status Bit 86" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB85  ,Group Status Bit 85" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB84  ,Group Status Bit 84" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB83  ,Group Status Bit 83" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB82  ,Group Status Bit 82" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB81  ,Group Status Bit 81" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB80  ,Group Status Bit 80" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB79  ,Group Status Bit 79" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB78  ,Group Status Bit 78" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB77  ,Group Status Bit 77" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB76  ,Group Status Bit 76" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB75  ,Group Status Bit 75" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB74  ,Group Status Bit 74" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB73  ,Group Status Bit 73" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB72  ,Group Status Bit 72" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB71  ,Group Status Bit 71" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB70  ,Group Status Bit 70" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB69  ,Group Status Bit 69" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB68  ,Group Status Bit 68" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB67  ,Group Status Bit 67" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB66  ,Group Status Bit 66" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB65  ,Group Status Bit 65" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB64  ,Group Status Bit 64" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2))
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 "
bitfld.long 0x00 31. " GSB95  ,Group Status Bit 95" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB94  ,Group Status Bit 94" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB93  ,Group Status Bit 93" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB92  ,Group Status Bit 92" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB91  ,Group Status Bit 91" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB90  ,Group Status Bit 90" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB89  ,Group Status Bit 89" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB88  ,Group Status Bit 88" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB87  ,Group Status Bit 87" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB86  ,Group Status Bit 86" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB85  ,Group Status Bit 85" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB84  ,Group Status Bit 84" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB83  ,Group Status Bit 83" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB82  ,Group Status Bit 82" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB81  ,Group Status Bit 81" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB80  ,Group Status Bit 80" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB79  ,Group Status Bit 79" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB78  ,Group Status Bit 78" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB77  ,Group Status Bit 77" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB76  ,Group Status Bit 76" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB75  ,Group Status Bit 75" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB74  ,Group Status Bit 74" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB73  ,Group Status Bit 73" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB72  ,Group Status Bit 72" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB71  ,Group Status Bit 71" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB70  ,Group Status Bit 70" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB69  ,Group Status Bit 69" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB68  ,Group Status Bit 68" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB67  ,Group Status Bit 67" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB66  ,Group Status Bit 66" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB65  ,Group Status Bit 65" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB64  ,Group Status Bit 64" "Group 0,Group 1"
else
hgroup.long 0x0088++0x03
hide.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3))
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)"
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB99  ,Group Status Bit 99" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB98  ,Group Status Bit 98" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB97  ,Group Status Bit 97" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB96  ,Group Status Bit 96" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3))
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 "
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB126 ,Group Status Bit 126" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB125 ,Group Status Bit 125" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB123 ,Group Status Bit 123" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB122 ,Group Status Bit 122" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB120 ,Group Status Bit 120" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB119 ,Group Status Bit 119" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB117 ,Group Status Bit 117" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB116 ,Group Status Bit 116" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB114 ,Group Status Bit 114" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB113 ,Group Status Bit 113" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB111 ,Group Status Bit 111" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB110 ,Group Status Bit 110" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB108 ,Group Status Bit 108" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB107 ,Group Status Bit 107" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB105 ,Group Status Bit 105" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB104 ,Group Status Bit 104" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB102 ,Group Status Bit 102" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB101 ,Group Status Bit 101" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB99  ,Group Status Bit 99" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB98  ,Group Status Bit 98" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB97  ,Group Status Bit 97" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB96  ,Group Status Bit 96" "Group 0,Group 1"
else
hgroup.long 0x008C++0x03
hide.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4))
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)"
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4))
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 "
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB158 ,Group Status Bit 158" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB157 ,Group Status Bit 157" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB155 ,Group Status Bit 155" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB154 ,Group Status Bit 154" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB152 ,Group Status Bit 152" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB151 ,Group Status Bit 151" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB149 ,Group Status Bit 149" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB148 ,Group Status Bit 148" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB146 ,Group Status Bit 146" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB145 ,Group Status Bit 145" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB143 ,Group Status Bit 143" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB142 ,Group Status Bit 142" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB140 ,Group Status Bit 140" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB139 ,Group Status Bit 139" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB137 ,Group Status Bit 137" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB136 ,Group Status Bit 136" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB134 ,Group Status Bit 134" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB133 ,Group Status Bit 133" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB131 ,Group Status Bit 131" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB130 ,Group Status Bit 130" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB128 ,Group Status Bit 128" "Group 0,Group 1"
else
hgroup.long 0x0090++0x03
hide.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5))
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)"
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5))
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 "
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB190 ,Group Status Bit 190" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB189 ,Group Status Bit 189" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB187 ,Group Status Bit 187" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB186 ,Group Status Bit 186" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB184 ,Group Status Bit 184" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB183 ,Group Status Bit 183" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB181 ,Group Status Bit 181" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB180 ,Group Status Bit 180" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB178 ,Group Status Bit 178" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB177 ,Group Status Bit 177" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB175 ,Group Status Bit 175" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB174 ,Group Status Bit 174" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB172 ,Group Status Bit 172" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB171 ,Group Status Bit 171" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB169 ,Group Status Bit 169" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB168 ,Group Status Bit 168" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB166 ,Group Status Bit 166" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB165 ,Group Status Bit 165" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB163 ,Group Status Bit 163" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB162 ,Group Status Bit 162" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB160 ,Group Status Bit 160" "Group 0,Group 1"
else
hgroup.long 0x0094++0x03
hide.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6))
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)"
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6))
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 "
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB222 ,Group Status Bit 222" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB221 ,Group Status Bit 221" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB219 ,Group Status Bit 219" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB218 ,Group Status Bit 218" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB216 ,Group Status Bit 216" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB215 ,Group Status Bit 215" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB213 ,Group Status Bit 213" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB212 ,Group Status Bit 212" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB210 ,Group Status Bit 210" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB209 ,Group Status Bit 209" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB207 ,Group Status Bit 207" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB206 ,Group Status Bit 206" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB204 ,Group Status Bit 204" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB203 ,Group Status Bit 203" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB201 ,Group Status Bit 201" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB200 ,Group Status Bit 200" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB198 ,Group Status Bit 198" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB197 ,Group Status Bit 197" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB195 ,Group Status Bit 195" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB194 ,Group Status Bit 194" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB192 ,Group Status Bit 192" "Group 0,Group 1"
else
hgroup.long 0x0098++0x03
hide.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7))
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)"
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7))
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 "
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB254 ,Group Status Bit 254" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB253 ,Group Status Bit 253" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB251 ,Group Status Bit 251" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB250 ,Group Status Bit 250" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB248 ,Group Status Bit 248" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB247 ,Group Status Bit 247" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB245 ,Group Status Bit 245" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB244 ,Group Status Bit 244" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB242 ,Group Status Bit 242" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB241 ,Group Status Bit 241" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB239 ,Group Status Bit 239" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB238 ,Group Status Bit 238" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB236 ,Group Status Bit 236" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB235 ,Group Status Bit 235" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB233 ,Group Status Bit 233" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB232 ,Group Status Bit 232" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB230 ,Group Status Bit 230" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB229 ,Group Status Bit 229" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB227 ,Group Status Bit 227" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB226 ,Group Status Bit 226" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB224 ,Group Status Bit 224" "Group 0,Group 1"
else
hgroup.long 0x009C++0x03
hide.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8))
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)"
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8))
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 "
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB286 ,Group Status Bit 286" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB285 ,Group Status Bit 285" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB283 ,Group Status Bit 283" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB282 ,Group Status Bit 282" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB280 ,Group Status Bit 280" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB279 ,Group Status Bit 279" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB277 ,Group Status Bit 277" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB276 ,Group Status Bit 276" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB274 ,Group Status Bit 274" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB273 ,Group Status Bit 273" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB271 ,Group Status Bit 271" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB270 ,Group Status Bit 270" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB268 ,Group Status Bit 268" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB267 ,Group Status Bit 267" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB265 ,Group Status Bit 265" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB264 ,Group Status Bit 264" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB262 ,Group Status Bit 262" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB261 ,Group Status Bit 261" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB259 ,Group Status Bit 259" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB258 ,Group Status Bit 258" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB256 ,Group Status Bit 256" "Group 0,Group 1"
else
hgroup.long 0x00A0++0x03
hide.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9))
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)"
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9))
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 "
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB318 ,Group Status Bit 318" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB317 ,Group Status Bit 317" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB315 ,Group Status Bit 315" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB314 ,Group Status Bit 314" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB312 ,Group Status Bit 312" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB311 ,Group Status Bit 311" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB309 ,Group Status Bit 309" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB308 ,Group Status Bit 308" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB306 ,Group Status Bit 306" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB305 ,Group Status Bit 305" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB303 ,Group Status Bit 303" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB302 ,Group Status Bit 302" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB300 ,Group Status Bit 300" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB299 ,Group Status Bit 299" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB297 ,Group Status Bit 297" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB296 ,Group Status Bit 296" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB294 ,Group Status Bit 294" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB293 ,Group Status Bit 293" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB291 ,Group Status Bit 291" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB290 ,Group Status Bit 290" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB288 ,Group Status Bit 288" "Group 0,Group 1"
else
hgroup.long 0x00A4++0x03
hide.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA))
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)"
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA))
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB350 ,Group Status Bit 350" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB349 ,Group Status Bit 349" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB347 ,Group Status Bit 347" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB346 ,Group Status Bit 346" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB344 ,Group Status Bit 344" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB343 ,Group Status Bit 343" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB341 ,Group Status Bit 341" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB340 ,Group Status Bit 340" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB338 ,Group Status Bit 338" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB337 ,Group Status Bit 337" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB335 ,Group Status Bit 335" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB334 ,Group Status Bit 334" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB332 ,Group Status Bit 332" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB331 ,Group Status Bit 331" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB329 ,Group Status Bit 329" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB328 ,Group Status Bit 328" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB326 ,Group Status Bit 326" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB325 ,Group Status Bit 325" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB323 ,Group Status Bit 323" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB322 ,Group Status Bit 322" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB320 ,Group Status Bit 320" "Group 0,Group 1"
else
hgroup.long 0x00A8++0x03
hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB))
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)"
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB))
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB382 ,Group Status Bit 382" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB381 ,Group Status Bit 381" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB379 ,Group Status Bit 379" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB378 ,Group Status Bit 378" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB376 ,Group Status Bit 376" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB375 ,Group Status Bit 375" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB373 ,Group Status Bit 373" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB372 ,Group Status Bit 372" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB370 ,Group Status Bit 370" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB369 ,Group Status Bit 369" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB367 ,Group Status Bit 367" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB366 ,Group Status Bit 366" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB364 ,Group Status Bit 364" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB363 ,Group Status Bit 363" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB361 ,Group Status Bit 361" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB360 ,Group Status Bit 360" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB358 ,Group Status Bit 358" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB357 ,Group Status Bit 357" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB355 ,Group Status Bit 355" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB354 ,Group Status Bit 354" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB352 ,Group Status Bit 352" "Group 0,Group 1"
else
hgroup.long 0x00AC++0x03
hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC))
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)"
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC))
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB414 ,Group Status Bit 414" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB413 ,Group Status Bit 413" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB411 ,Group Status Bit 411" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB410 ,Group Status Bit 410" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB408 ,Group Status Bit 408" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB407 ,Group Status Bit 407" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB405 ,Group Status Bit 405" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB404 ,Group Status Bit 404" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB402 ,Group Status Bit 402" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB401 ,Group Status Bit 401" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB399 ,Group Status Bit 399" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB398 ,Group Status Bit 398" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB396 ,Group Status Bit 396" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB395 ,Group Status Bit 395" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB393 ,Group Status Bit 393" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB392 ,Group Status Bit 392" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB390 ,Group Status Bit 390" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB389 ,Group Status Bit 389" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB387 ,Group Status Bit 387" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB386 ,Group Status Bit 386" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB384 ,Group Status Bit 384" "Group 0,Group 1"
else
hgroup.long 0x00B0++0x03
hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD))
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)"
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD))
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB446 ,Group Status Bit 446" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB445 ,Group Status Bit 445" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB443 ,Group Status Bit 443" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB442 ,Group Status Bit 442" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB440 ,Group Status Bit 440" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB439 ,Group Status Bit 439" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB437 ,Group Status Bit 437" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB436 ,Group Status Bit 436" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB434 ,Group Status Bit 434" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB433 ,Group Status Bit 433" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB431 ,Group Status Bit 431" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB430 ,Group Status Bit 430" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB428 ,Group Status Bit 428" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB427 ,Group Status Bit 427" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB425 ,Group Status Bit 425" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB424 ,Group Status Bit 424" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB422 ,Group Status Bit 422" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB421 ,Group Status Bit 421" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB419 ,Group Status Bit 419" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB418 ,Group Status Bit 418" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB416 ,Group Status Bit 416" "Group 0,Group 1"
else
hgroup.long 0x00B4++0x03
hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE))
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)"
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE))
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB478 ,Group Status Bit 478" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB477 ,Group Status Bit 477" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB475 ,Group Status Bit 475" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB474 ,Group Status Bit 474" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB472 ,Group Status Bit 472" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB471 ,Group Status Bit 471" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB469 ,Group Status Bit 469" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB468 ,Group Status Bit 468" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB466 ,Group Status Bit 466" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB465 ,Group Status Bit 465" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB463 ,Group Status Bit 463" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB462 ,Group Status Bit 462" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB460 ,Group Status Bit 460" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB459 ,Group Status Bit 459" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB457 ,Group Status Bit 457" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB456 ,Group Status Bit 456" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB454 ,Group Status Bit 454" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB453 ,Group Status Bit 453" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB451 ,Group Status Bit 451" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB450 ,Group Status Bit 450" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB448 ,Group Status Bit 448" "Group 0,Group 1"
else
hgroup.long 0x00B8++0x03
hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF))
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)"
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF))
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB510 ,Group Status Bit 510" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB509 ,Group Status Bit 509" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB507 ,Group Status Bit 507" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB506 ,Group Status Bit 506" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB504 ,Group Status Bit 504" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB503 ,Group Status Bit 503" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB501 ,Group Status Bit 501" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB500 ,Group Status Bit 500" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB498 ,Group Status Bit 498" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB497 ,Group Status Bit 497" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB495 ,Group Status Bit 495" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB494 ,Group Status Bit 494" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB492 ,Group Status Bit 492" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB491 ,Group Status Bit 491" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB489 ,Group Status Bit 489" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB488 ,Group Status Bit 488" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB486 ,Group Status Bit 486" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB485 ,Group Status Bit 485" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB483 ,Group Status Bit 483" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB482 ,Group Status Bit 482" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB480 ,Group Status Bit 480" "Group 0,Group 1"
else
hgroup.long 0x00BC++0x03
hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)"
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB542 ,Group Status Bit 542" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB541 ,Group Status Bit 541" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB539 ,Group Status Bit 539" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB538 ,Group Status Bit 538" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB536 ,Group Status Bit 536" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB535 ,Group Status Bit 535" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB533 ,Group Status Bit 533" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB532 ,Group Status Bit 532" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB530 ,Group Status Bit 530" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB529 ,Group Status Bit 529" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB527 ,Group Status Bit 527" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB526 ,Group Status Bit 526" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB524 ,Group Status Bit 524" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB523 ,Group Status Bit 523" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB521 ,Group Status Bit 521" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB520 ,Group Status Bit 520" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB518 ,Group Status Bit 518" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB517 ,Group Status Bit 517" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB515 ,Group Status Bit 515" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB514 ,Group Status Bit 514" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB512 ,Group Status Bit 512" "Group 0,Group 1"
else
hgroup.long 0x00C0++0x03
hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)"
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB574 ,Group Status Bit 574" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB573 ,Group Status Bit 573" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB571 ,Group Status Bit 571" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB570 ,Group Status Bit 570" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB568 ,Group Status Bit 568" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB567 ,Group Status Bit 567" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB565 ,Group Status Bit 565" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB564 ,Group Status Bit 564" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB562 ,Group Status Bit 562" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB561 ,Group Status Bit 561" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB559 ,Group Status Bit 559" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB558 ,Group Status Bit 558" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB556 ,Group Status Bit 556" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB555 ,Group Status Bit 555" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB553 ,Group Status Bit 553" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB552 ,Group Status Bit 552" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB550 ,Group Status Bit 550" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB549 ,Group Status Bit 549" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB547 ,Group Status Bit 547" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB546 ,Group Status Bit 546" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB544 ,Group Status Bit 544" "Group 0,Group 1"
else
hgroup.long 0x00C4++0x03
hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)"
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB606 ,Group Status Bit 606" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB605 ,Group Status Bit 605" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB603 ,Group Status Bit 603" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB602 ,Group Status Bit 602" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB600 ,Group Status Bit 600" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB599 ,Group Status Bit 599" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB597 ,Group Status Bit 597" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB596 ,Group Status Bit 596" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB594 ,Group Status Bit 594" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB593 ,Group Status Bit 593" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB591 ,Group Status Bit 591" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB590 ,Group Status Bit 590" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB588 ,Group Status Bit 588" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB587 ,Group Status Bit 587" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB585 ,Group Status Bit 585" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB584 ,Group Status Bit 584" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB582 ,Group Status Bit 582" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB581 ,Group Status Bit 581" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB579 ,Group Status Bit 579" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB578 ,Group Status Bit 578" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB576 ,Group Status Bit 576" "Group 0,Group 1"
else
hgroup.long 0x00C8++0x03
hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)"
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB638 ,Group Status Bit 638" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB637 ,Group Status Bit 637" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB635 ,Group Status Bit 635" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB634 ,Group Status Bit 634" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB632 ,Group Status Bit 632" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB631 ,Group Status Bit 631" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB629 ,Group Status Bit 629" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB628 ,Group Status Bit 628" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB626 ,Group Status Bit 626" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB625 ,Group Status Bit 625" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB623 ,Group Status Bit 623" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB622 ,Group Status Bit 622" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB620 ,Group Status Bit 620" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB619 ,Group Status Bit 619" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB617 ,Group Status Bit 617" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB616 ,Group Status Bit 616" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB614 ,Group Status Bit 614" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB613 ,Group Status Bit 613" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB611 ,Group Status Bit 611" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB610 ,Group Status Bit 610" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB608 ,Group Status Bit 608" "Group 0,Group 1"
else
hgroup.long 0x00CC++0x03
hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)"
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB670 ,Group Status Bit 670" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB669 ,Group Status Bit 669" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB667 ,Group Status Bit 667" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB666 ,Group Status Bit 666" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB664 ,Group Status Bit 664" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB663 ,Group Status Bit 663" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB661 ,Group Status Bit 661" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB660 ,Group Status Bit 660" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB658 ,Group Status Bit 658" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB657 ,Group Status Bit 657" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB655 ,Group Status Bit 655" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB654 ,Group Status Bit 654" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB652 ,Group Status Bit 652" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB651 ,Group Status Bit 651" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB649 ,Group Status Bit 649" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB648 ,Group Status Bit 648" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB646 ,Group Status Bit 646" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB645 ,Group Status Bit 645" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB643 ,Group Status Bit 643" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB642 ,Group Status Bit 642" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB640 ,Group Status Bit 640" "Group 0,Group 1"
else
hgroup.long 0x00D0++0x03
hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)"
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB702 ,Group Status Bit 702" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB701 ,Group Status Bit 701" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB699 ,Group Status Bit 699" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB698 ,Group Status Bit 698" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB696 ,Group Status Bit 696" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB695 ,Group Status Bit 695" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB693 ,Group Status Bit 693" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB692 ,Group Status Bit 692" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB690 ,Group Status Bit 690" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB689 ,Group Status Bit 689" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB687 ,Group Status Bit 687" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB686 ,Group Status Bit 686" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB684 ,Group Status Bit 684" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB683 ,Group Status Bit 683" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB681 ,Group Status Bit 681" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB680 ,Group Status Bit 680" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB678 ,Group Status Bit 678" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB677 ,Group Status Bit 677" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB675 ,Group Status Bit 675" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB674 ,Group Status Bit 674" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB672 ,Group Status Bit 672" "Group 0,Group 1"
else
hgroup.long 0x00D4++0x03
hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)"
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB734 ,Group Status Bit 734" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB733 ,Group Status Bit 733" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB731 ,Group Status Bit 731" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB730 ,Group Status Bit 730" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB728 ,Group Status Bit 728" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB727 ,Group Status Bit 727" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB725 ,Group Status Bit 725" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB724 ,Group Status Bit 724" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB722 ,Group Status Bit 722" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB721 ,Group Status Bit 721" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB719 ,Group Status Bit 719" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB718 ,Group Status Bit 718" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB716 ,Group Status Bit 716" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB715 ,Group Status Bit 715" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB713 ,Group Status Bit 713" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB712 ,Group Status Bit 712" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB710 ,Group Status Bit 710" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB709 ,Group Status Bit 709" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB707 ,Group Status Bit 707" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB706 ,Group Status Bit 706" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB704 ,Group Status Bit 704" "Group 0,Group 1"
else
hgroup.long 0x00D8++0x03
hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)"
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB766 ,Group Status Bit 766" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB765 ,Group Status Bit 765" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB763 ,Group Status Bit 763" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB762 ,Group Status Bit 762" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB760 ,Group Status Bit 760" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB759 ,Group Status Bit 759" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB757 ,Group Status Bit 757" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB756 ,Group Status Bit 756" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB754 ,Group Status Bit 754" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB753 ,Group Status Bit 753" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB751 ,Group Status Bit 751" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB750 ,Group Status Bit 750" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB748 ,Group Status Bit 748" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB747 ,Group Status Bit 747" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB745 ,Group Status Bit 745" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB744 ,Group Status Bit 744" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB742 ,Group Status Bit 742" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB741 ,Group Status Bit 741" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB739 ,Group Status Bit 739" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB738 ,Group Status Bit 738" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB736 ,Group Status Bit 736" "Group 0,Group 1"
else
hgroup.long 0x00DC++0x03
hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)"
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB798 ,Group Status Bit 798" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB797 ,Group Status Bit 797" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB795 ,Group Status Bit 795" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB794 ,Group Status Bit 794" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB792 ,Group Status Bit 792" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB791 ,Group Status Bit 791" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB789 ,Group Status Bit 789" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB788 ,Group Status Bit 788" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB786 ,Group Status Bit 786" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB785 ,Group Status Bit 785" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB783 ,Group Status Bit 783" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB782 ,Group Status Bit 782" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB780 ,Group Status Bit 780" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB779 ,Group Status Bit 779" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB777 ,Group Status Bit 777" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB776 ,Group Status Bit 776" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB774 ,Group Status Bit 774" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB773 ,Group Status Bit 773" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB771 ,Group Status Bit 771" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB770 ,Group Status Bit 770" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB768 ,Group Status Bit 768" "Group 0,Group 1"
else
hgroup.long 0x00E0++0x03
hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)"
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB830 ,Group Status Bit 830" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB829 ,Group Status Bit 829" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB827 ,Group Status Bit 827" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB826 ,Group Status Bit 826" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB824 ,Group Status Bit 824" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB823 ,Group Status Bit 823" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB821 ,Group Status Bit 821" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB820 ,Group Status Bit 820" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB818 ,Group Status Bit 818" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB817 ,Group Status Bit 817" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB815 ,Group Status Bit 815" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB814 ,Group Status Bit 814" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB812 ,Group Status Bit 812" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB811 ,Group Status Bit 811" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB809 ,Group Status Bit 809" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB808 ,Group Status Bit 808" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB806 ,Group Status Bit 806" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB805 ,Group Status Bit 805" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB803 ,Group Status Bit 803" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB802 ,Group Status Bit 802" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB800 ,Group Status Bit 800" "Group 0,Group 1"
else
hgroup.long 0x00E4++0x03
hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A))
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)"
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A))
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB862 ,Group Status Bit 862" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB861 ,Group Status Bit 861" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB859 ,Group Status Bit 859" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB858 ,Group Status Bit 858" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB856 ,Group Status Bit 856" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB855 ,Group Status Bit 855" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB853 ,Group Status Bit 853" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB852 ,Group Status Bit 852" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB850 ,Group Status Bit 850" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB849 ,Group Status Bit 849" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB847 ,Group Status Bit 847" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB846 ,Group Status Bit 846" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB844 ,Group Status Bit 844" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB843 ,Group Status Bit 843" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB841 ,Group Status Bit 841" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB840 ,Group Status Bit 840" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB838 ,Group Status Bit 838" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB837 ,Group Status Bit 837" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB835 ,Group Status Bit 835" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB834 ,Group Status Bit 834" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB832 ,Group Status Bit 832" "Group 0,Group 1"
else
hgroup.long 0x00E8++0x03
hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)"
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB894 ,Group Status Bit 894" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB893 ,Group Status Bit 893" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB891 ,Group Status Bit 891" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB890 ,Group Status Bit 890" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB888 ,Group Status Bit 888" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB887 ,Group Status Bit 887" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB885 ,Group Status Bit 885" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB884 ,Group Status Bit 884" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB882 ,Group Status Bit 882" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB881 ,Group Status Bit 881" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB879 ,Group Status Bit 879" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB878 ,Group Status Bit 878" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB876 ,Group Status Bit 876" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB875 ,Group Status Bit 875" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB873 ,Group Status Bit 873" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB872 ,Group Status Bit 872" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB870 ,Group Status Bit 870" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB869 ,Group Status Bit 869" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB867 ,Group Status Bit 867" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB866 ,Group Status Bit 866" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB864 ,Group Status Bit 864" "Group 0,Group 1"
else
hgroup.long 0x00EC++0x03
hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)"
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB926 ,Group Status Bit 926" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB925 ,Group Status Bit 925" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB923 ,Group Status Bit 923" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB922 ,Group Status Bit 922" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB920 ,Group Status Bit 920" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB919 ,Group Status Bit 919" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB917 ,Group Status Bit 917" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB916 ,Group Status Bit 916" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB914 ,Group Status Bit 914" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB913 ,Group Status Bit 913" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB911 ,Group Status Bit 911" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB910 ,Group Status Bit 910" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB908 ,Group Status Bit 908" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB907 ,Group Status Bit 907" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB905 ,Group Status Bit 905" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB904 ,Group Status Bit 904" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB902 ,Group Status Bit 902" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB901 ,Group Status Bit 901" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB899 ,Group Status Bit 899" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB898 ,Group Status Bit 898" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB896 ,Group Status Bit 896" "Group 0,Group 1"
else
hgroup.long 0x00F0++0x03
hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)"
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB958 ,Group Status Bit 958" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB957 ,Group Status Bit 957" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB955 ,Group Status Bit 955" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB954 ,Group Status Bit 954" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB952 ,Group Status Bit 952" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB951 ,Group Status Bit 951" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB949 ,Group Status Bit 949" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB948 ,Group Status Bit 948" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB946 ,Group Status Bit 946" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB945 ,Group Status Bit 945" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB943 ,Group Status Bit 943" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB942 ,Group Status Bit 942" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB940 ,Group Status Bit 940" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB939 ,Group Status Bit 939" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB937 ,Group Status Bit 937" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB936 ,Group Status Bit 936" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB934 ,Group Status Bit 934" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB933 ,Group Status Bit 933" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB931 ,Group Status Bit 931" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB930 ,Group Status Bit 930" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB928 ,Group Status Bit 928" "Group 0,Group 1"
else
hgroup.long 0x00F4++0x03
hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)"
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB990 ,Group Status Bit 990" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB989 ,Group Status Bit 989" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB987 ,Group Status Bit 987" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB986 ,Group Status Bit 986" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB984 ,Group Status Bit 984" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB983 ,Group Status Bit 983" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB981 ,Group Status Bit 981" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB980 ,Group Status Bit 980" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB978 ,Group Status Bit 978" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB977 ,Group Status Bit 977" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB975 ,Group Status Bit 975" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB974 ,Group Status Bit 974" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB972 ,Group Status Bit 972" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB971 ,Group Status Bit 971" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB969 ,Group Status Bit 969" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB968 ,Group Status Bit 968" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB966 ,Group Status Bit 966" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB965 ,Group Status Bit 965" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB963 ,Group Status Bit 963" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB962 ,Group Status Bit 962" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB960 ,Group Status Bit 960" "Group 0,Group 1"
else
hgroup.long 0x00F8++0x03
hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
endif
tree.end
width 24.
tree "Set/Clear Enable Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0100++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0100++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31   ,Set/Clear Enable Bit 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB30   ,Set/Clear Enable Bit 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB29   ,Set/Clear Enable Bit 29" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28   ,Set/Clear Enable Bit 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB27   ,Set/Clear Enable Bit 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB26   ,Set/Clear Enable Bit 26" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25   ,Set/Clear Enable Bit 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB24   ,Set/Clear Enable Bit 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB23   ,Set/Clear Enable Bit 23" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22   ,Set/Clear Enable Bit 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB21   ,Set/Clear Enable Bit 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB20   ,Set/Clear Enable Bit 20" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19   ,Set/Clear Enable Bit 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB18   ,Set/Clear Enable Bit 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB17   ,Set/Clear Enable Bit 17" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16   ,Set/Clear Enable Bit 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB15   ,Set/Clear Enable Bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB14   ,Set/Clear Enable Bit 14" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13   ,Set/Clear Enable Bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB12   ,Set/Clear Enable Bit 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB11   ,Set/Clear Enable Bit 11" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10   ,Set/Clear Enable Bit 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB9    ,Set/Clear Enable Bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB8    ,Set/Clear Enable Bit 8" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7    ,Set/Clear Enable Bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB6    ,Set/Clear Enable Bit 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB5    ,Set/Clear Enable Bit 5" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4    ,Set/Clear Enable Bit 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB3    ,Set/Clear Enable Bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB2    ,Set/Clear Enable Bit 2" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1    ,Set/Clear Enable Bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB0    ,Set/Clear Enable Bit 0" "Disabled,Enabled"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0104++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63   ,Set/Clear Enable Bit 63" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB62   ,Set/Clear Enable Bit 62" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB61   ,Set/Clear Enable Bit 61" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60   ,Set/Clear Enable Bit 60" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB59   ,Set/Clear Enable Bit 59" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB58   ,Set/Clear Enable Bit 58" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57   ,Set/Clear Enable Bit 57" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB56   ,Set/Clear Enable Bit 56" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB55   ,Set/Clear Enable Bit 55" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54   ,Set/Clear Enable Bit 54" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB53   ,Set/Clear Enable Bit 53" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB52   ,Set/Clear Enable Bit 52" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51   ,Set/Clear Enable Bit 51" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB50   ,Set/Clear Enable Bit 50" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB49   ,Set/Clear Enable Bit 49" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48   ,Set/Clear Enable Bit 48" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB47   ,Set/Clear Enable Bit 47" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB46   ,Set/Clear Enable Bit 46" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45   ,Set/Clear Enable Bit 45" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB44   ,Set/Clear Enable Bit 44" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB43   ,Set/Clear Enable Bit 43" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42   ,Set/Clear Enable Bit 42" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB41   ,Set/Clear Enable Bit 41" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB40   ,Set/Clear Enable Bit 40" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39   ,Set/Clear Enable Bit 39" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB38   ,Set/Clear Enable Bit 38" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB37   ,Set/Clear Enable Bit 37" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36   ,Set/Clear Enable Bit 36" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB35   ,Set/Clear Enable Bit 35" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB34   ,Set/Clear Enable Bit 34" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33   ,Set/Clear Enable Bit 33" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB32   ,Set/Clear Enable Bit 32" "Disabled,Enabled"
else
hgroup.long 0x0104++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0108++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95   ,Set/Clear Enable Bit 95" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB94   ,Set/Clear Enable Bit 94" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB93   ,Set/Clear Enable Bit 93" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92   ,Set/Clear Enable Bit 92" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB91   ,Set/Clear Enable Bit 91" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB90   ,Set/Clear Enable Bit 90" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89   ,Set/Clear Enable Bit 89" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB88   ,Set/Clear Enable Bit 88" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB87   ,Set/Clear Enable Bit 87" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86   ,Set/Clear Enable Bit 86" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB85   ,Set/Clear Enable Bit 85" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB84   ,Set/Clear Enable Bit 84" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83   ,Set/Clear Enable Bit 83" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB82   ,Set/Clear Enable Bit 82" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB81   ,Set/Clear Enable Bit 81" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80   ,Set/Clear Enable Bit 80" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB79   ,Set/Clear Enable Bit 79" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB78   ,Set/Clear Enable Bit 78" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77   ,Set/Clear Enable Bit 77" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB76   ,Set/Clear Enable Bit 76" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB75   ,Set/Clear Enable Bit 75" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74   ,Set/Clear Enable Bit 74" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB73   ,Set/Clear Enable Bit 73" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB72   ,Set/Clear Enable Bit 72" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71   ,Set/Clear Enable Bit 71" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB70   ,Set/Clear Enable Bit 70" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB69   ,Set/Clear Enable Bit 69" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68   ,Set/Clear Enable Bit 68" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB67   ,Set/Clear Enable Bit 67" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB66   ,Set/Clear Enable Bit 66" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65   ,Set/Clear Enable Bit 65" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB64   ,Set/Clear Enable Bit 64" "Disabled,Enabled"
else
hgroup.long 0x0108++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x010C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127  ,Set/Clear Enable Bit 127" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB126  ,Set/Clear Enable Bit 126" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB125  ,Set/Clear Enable Bit 125" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124  ,Set/Clear Enable Bit 124" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB123  ,Set/Clear Enable Bit 123" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB122  ,Set/Clear Enable Bit 122" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121  ,Set/Clear Enable Bit 121" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB120  ,Set/Clear Enable Bit 120" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB119  ,Set/Clear Enable Bit 119" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118  ,Set/Clear Enable Bit 118" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB117  ,Set/Clear Enable Bit 117" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB116  ,Set/Clear Enable Bit 116" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115  ,Set/Clear Enable Bit 115" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB114  ,Set/Clear Enable Bit 114" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB113  ,Set/Clear Enable Bit 113" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112  ,Set/Clear Enable Bit 112" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB111  ,Set/Clear Enable Bit 111" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB110  ,Set/Clear Enable Bit 110" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109  ,Set/Clear Enable Bit 109" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB108  ,Set/Clear Enable Bit 108" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB107  ,Set/Clear Enable Bit 107" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106  ,Set/Clear Enable Bit 106" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB105  ,Set/Clear Enable Bit 105" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB104  ,Set/Clear Enable Bit 104" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103  ,Set/Clear Enable Bit 103" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB102  ,Set/Clear Enable Bit 102" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB101  ,Set/Clear Enable Bit 101" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100  ,Set/Clear Enable Bit 100" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB99   ,Set/Clear Enable Bit 99" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB98   ,Set/Clear Enable Bit 98" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97   ,Set/Clear Enable Bit 97" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB96   ,Set/Clear Enable Bit 96" "Disabled,Enabled"
else
hgroup.long 0x010C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0110++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159  ,Set/Clear Enable Bit 159" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB158  ,Set/Clear Enable Bit 158" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB157  ,Set/Clear Enable Bit 157" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156  ,Set/Clear Enable Bit 156" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB155  ,Set/Clear Enable Bit 155" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB154  ,Set/Clear Enable Bit 154" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153  ,Set/Clear Enable Bit 153" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB152  ,Set/Clear Enable Bit 152" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB151  ,Set/Clear Enable Bit 151" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150  ,Set/Clear Enable Bit 150" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB149  ,Set/Clear Enable Bit 149" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB148  ,Set/Clear Enable Bit 148" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147  ,Set/Clear Enable Bit 147" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB146  ,Set/Clear Enable Bit 146" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB145  ,Set/Clear Enable Bit 145" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144  ,Set/Clear Enable Bit 144" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB143  ,Set/Clear Enable Bit 143" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB142  ,Set/Clear Enable Bit 142" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141  ,Set/Clear Enable Bit 141" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB140  ,Set/Clear Enable Bit 140" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB139  ,Set/Clear Enable Bit 139" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138  ,Set/Clear Enable Bit 138" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB137  ,Set/Clear Enable Bit 137" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB136  ,Set/Clear Enable Bit 136" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135  ,Set/Clear Enable Bit 135" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB134  ,Set/Clear Enable Bit 134" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB133  ,Set/Clear Enable Bit 133" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132  ,Set/Clear Enable Bit 132" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB131  ,Set/Clear Enable Bit 131" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB130  ,Set/Clear Enable Bit 130" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129  ,Set/Clear Enable Bit 129" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB128  ,Set/Clear Enable Bit 128" "Disabled,Enabled"
else
hgroup.long 0x0110++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0114++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191  ,Set/Clear Enable Bit 191" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB190  ,Set/Clear Enable Bit 190" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB189  ,Set/Clear Enable Bit 189" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188  ,Set/Clear Enable Bit 188" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB187  ,Set/Clear Enable Bit 187" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB186  ,Set/Clear Enable Bit 186" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185  ,Set/Clear Enable Bit 185" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB184  ,Set/Clear Enable Bit 184" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB183  ,Set/Clear Enable Bit 183" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182  ,Set/Clear Enable Bit 182" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB181  ,Set/Clear Enable Bit 181" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB180  ,Set/Clear Enable Bit 180" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179  ,Set/Clear Enable Bit 179" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB178  ,Set/Clear Enable Bit 178" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB177  ,Set/Clear Enable Bit 177" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176  ,Set/Clear Enable Bit 176" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB175  ,Set/Clear Enable Bit 175" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB174  ,Set/Clear Enable Bit 174" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173  ,Set/Clear Enable Bit 173" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB172  ,Set/Clear Enable Bit 172" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB171  ,Set/Clear Enable Bit 171" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170  ,Set/Clear Enable Bit 170" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB169  ,Set/Clear Enable Bit 169" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB168  ,Set/Clear Enable Bit 168" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167  ,Set/Clear Enable Bit 167" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB166  ,Set/Clear Enable Bit 166" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB165  ,Set/Clear Enable Bit 165" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164  ,Set/Clear Enable Bit 164" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB163  ,Set/Clear Enable Bit 163" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB162  ,Set/Clear Enable Bit 162" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161  ,Set/Clear Enable Bit 161" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB160  ,Set/Clear Enable Bit 160" "Disabled,Enabled"
else
hgroup.long 0x0114++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0118++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223  ,Set/Clear Enable Bit 223" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB222  ,Set/Clear Enable Bit 222" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB221  ,Set/Clear Enable Bit 221" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220  ,Set/Clear Enable Bit 220" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB219  ,Set/Clear Enable Bit 219" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB218  ,Set/Clear Enable Bit 218" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217  ,Set/Clear Enable Bit 217" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB216  ,Set/Clear Enable Bit 216" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB215  ,Set/Clear Enable Bit 215" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214  ,Set/Clear Enable Bit 214" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB213  ,Set/Clear Enable Bit 213" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB212  ,Set/Clear Enable Bit 212" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211  ,Set/Clear Enable Bit 211" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB210  ,Set/Clear Enable Bit 210" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB209  ,Set/Clear Enable Bit 209" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208  ,Set/Clear Enable Bit 208" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB207  ,Set/Clear Enable Bit 207" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB206  ,Set/Clear Enable Bit 206" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205  ,Set/Clear Enable Bit 205" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB204  ,Set/Clear Enable Bit 204" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB203  ,Set/Clear Enable Bit 203" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202  ,Set/Clear Enable Bit 202" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB201  ,Set/Clear Enable Bit 201" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB200  ,Set/Clear Enable Bit 200" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199  ,Set/Clear Enable Bit 199" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB198  ,Set/Clear Enable Bit 198" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB197  ,Set/Clear Enable Bit 197" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196  ,Set/Clear Enable Bit 196" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB195  ,Set/Clear Enable Bit 195" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB194  ,Set/Clear Enable Bit 194" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193  ,Set/Clear Enable Bit 193" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB192  ,Set/Clear Enable Bit 192" "Disabled,Enabled"
else
hgroup.long 0x0118++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x011C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255  ,Set/Clear Enable Bit 255" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB254  ,Set/Clear Enable Bit 254" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB253  ,Set/Clear Enable Bit 253" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252  ,Set/Clear Enable Bit 252" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB251  ,Set/Clear Enable Bit 251" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB250  ,Set/Clear Enable Bit 250" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249  ,Set/Clear Enable Bit 249" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB248  ,Set/Clear Enable Bit 248" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB247  ,Set/Clear Enable Bit 247" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246  ,Set/Clear Enable Bit 246" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB245  ,Set/Clear Enable Bit 245" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB244  ,Set/Clear Enable Bit 244" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243  ,Set/Clear Enable Bit 243" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB242  ,Set/Clear Enable Bit 242" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB241  ,Set/Clear Enable Bit 241" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240  ,Set/Clear Enable Bit 240" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB239  ,Set/Clear Enable Bit 239" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB238  ,Set/Clear Enable Bit 238" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237  ,Set/Clear Enable Bit 237" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB236  ,Set/Clear Enable Bit 236" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB235  ,Set/Clear Enable Bit 235" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234  ,Set/Clear Enable Bit 234" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB233  ,Set/Clear Enable Bit 233" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB232  ,Set/Clear Enable Bit 232" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231  ,Set/Clear Enable Bit 231" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB230  ,Set/Clear Enable Bit 230" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB229  ,Set/Clear Enable Bit 229" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228  ,Set/Clear Enable Bit 228" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB227  ,Set/Clear Enable Bit 227" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB226  ,Set/Clear Enable Bit 226" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225  ,Set/Clear Enable Bit 225" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB224  ,Set/Clear Enable Bit 224" "Disabled,Enabled"
else
hgroup.long 0x011C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0120++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287  ,Set/Clear Enable Bit 287" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB286  ,Set/Clear Enable Bit 286" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB285  ,Set/Clear Enable Bit 285" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284  ,Set/Clear Enable Bit 284" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB283  ,Set/Clear Enable Bit 283" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB282  ,Set/Clear Enable Bit 282" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281  ,Set/Clear Enable Bit 281" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB280  ,Set/Clear Enable Bit 280" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB279  ,Set/Clear Enable Bit 279" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278  ,Set/Clear Enable Bit 278" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB277  ,Set/Clear Enable Bit 277" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB276  ,Set/Clear Enable Bit 276" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275  ,Set/Clear Enable Bit 275" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB274  ,Set/Clear Enable Bit 274" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB273  ,Set/Clear Enable Bit 273" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272  ,Set/Clear Enable Bit 272" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB271  ,Set/Clear Enable Bit 271" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB270  ,Set/Clear Enable Bit 270" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269  ,Set/Clear Enable Bit 269" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB268  ,Set/Clear Enable Bit 268" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB267  ,Set/Clear Enable Bit 267" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266  ,Set/Clear Enable Bit 266" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB265  ,Set/Clear Enable Bit 265" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB264  ,Set/Clear Enable Bit 264" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263  ,Set/Clear Enable Bit 263" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB262  ,Set/Clear Enable Bit 262" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB261  ,Set/Clear Enable Bit 261" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260  ,Set/Clear Enable Bit 260" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB259  ,Set/Clear Enable Bit 259" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB258  ,Set/Clear Enable Bit 258" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257  ,Set/Clear Enable Bit 257" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB256  ,Set/Clear Enable Bit 256" "Disabled,Enabled"
else
hgroup.long 0x0120++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0124++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319  ,Set/Clear Enable Bit 319" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB318  ,Set/Clear Enable Bit 318" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB317  ,Set/Clear Enable Bit 317" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316  ,Set/Clear Enable Bit 316" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB315  ,Set/Clear Enable Bit 315" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB314  ,Set/Clear Enable Bit 314" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313  ,Set/Clear Enable Bit 313" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB312  ,Set/Clear Enable Bit 312" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB311  ,Set/Clear Enable Bit 311" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310  ,Set/Clear Enable Bit 310" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB309  ,Set/Clear Enable Bit 309" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB308  ,Set/Clear Enable Bit 308" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307  ,Set/Clear Enable Bit 307" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB306  ,Set/Clear Enable Bit 306" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB305  ,Set/Clear Enable Bit 305" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304  ,Set/Clear Enable Bit 304" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB303  ,Set/Clear Enable Bit 303" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB302  ,Set/Clear Enable Bit 302" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301  ,Set/Clear Enable Bit 301" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB300  ,Set/Clear Enable Bit 300" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB299  ,Set/Clear Enable Bit 299" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298  ,Set/Clear Enable Bit 298" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB297  ,Set/Clear Enable Bit 297" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB296  ,Set/Clear Enable Bit 296" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295  ,Set/Clear Enable Bit 295" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB294  ,Set/Clear Enable Bit 294" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB293  ,Set/Clear Enable Bit 293" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292  ,Set/Clear Enable Bit 292" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB291  ,Set/Clear Enable Bit 291" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB290  ,Set/Clear Enable Bit 290" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289  ,Set/Clear Enable Bit 289" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB288  ,Set/Clear Enable Bit 288" "Disabled,Enabled"
else
hgroup.long 0x0124++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0128++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351  ,Set/Clear Enable Bit 351" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB350  ,Set/Clear Enable Bit 350" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB349  ,Set/Clear Enable Bit 349" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348  ,Set/Clear Enable Bit 348" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB347  ,Set/Clear Enable Bit 347" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB346  ,Set/Clear Enable Bit 346" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345  ,Set/Clear Enable Bit 345" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB344  ,Set/Clear Enable Bit 344" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB343  ,Set/Clear Enable Bit 343" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342  ,Set/Clear Enable Bit 342" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB341  ,Set/Clear Enable Bit 341" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB340  ,Set/Clear Enable Bit 340" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339  ,Set/Clear Enable Bit 339" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB338  ,Set/Clear Enable Bit 338" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB337  ,Set/Clear Enable Bit 337" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336  ,Set/Clear Enable Bit 336" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB335  ,Set/Clear Enable Bit 335" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB334  ,Set/Clear Enable Bit 334" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333  ,Set/Clear Enable Bit 333" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB332  ,Set/Clear Enable Bit 332" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB331  ,Set/Clear Enable Bit 331" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330  ,Set/Clear Enable Bit 330" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB329  ,Set/Clear Enable Bit 329" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB328  ,Set/Clear Enable Bit 328" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327  ,Set/Clear Enable Bit 327" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB326  ,Set/Clear Enable Bit 326" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB325  ,Set/Clear Enable Bit 325" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324  ,Set/Clear Enable Bit 324" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB323  ,Set/Clear Enable Bit 323" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB322  ,Set/Clear Enable Bit 322" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321  ,Set/Clear Enable Bit 321" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB320  ,Set/Clear Enable Bit 320" "Disabled,Enabled"
else
hgroup.long 0x0128++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x012C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383  ,Set/Clear Enable Bit 383" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB382  ,Set/Clear Enable Bit 382" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB381  ,Set/Clear Enable Bit 381" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380  ,Set/Clear Enable Bit 380" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB379  ,Set/Clear Enable Bit 379" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB378  ,Set/Clear Enable Bit 378" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377  ,Set/Clear Enable Bit 377" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB376  ,Set/Clear Enable Bit 376" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB375  ,Set/Clear Enable Bit 375" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374  ,Set/Clear Enable Bit 374" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB373  ,Set/Clear Enable Bit 373" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB372  ,Set/Clear Enable Bit 372" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371  ,Set/Clear Enable Bit 371" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB370  ,Set/Clear Enable Bit 370" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB369  ,Set/Clear Enable Bit 369" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368  ,Set/Clear Enable Bit 368" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB367  ,Set/Clear Enable Bit 367" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB366  ,Set/Clear Enable Bit 366" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365  ,Set/Clear Enable Bit 365" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB364  ,Set/Clear Enable Bit 364" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB363  ,Set/Clear Enable Bit 363" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362  ,Set/Clear Enable Bit 362" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB361  ,Set/Clear Enable Bit 361" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB360  ,Set/Clear Enable Bit 360" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359  ,Set/Clear Enable Bit 359" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB358  ,Set/Clear Enable Bit 358" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB357  ,Set/Clear Enable Bit 357" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356  ,Set/Clear Enable Bit 356" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB355  ,Set/Clear Enable Bit 355" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB354  ,Set/Clear Enable Bit 354" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353  ,Set/Clear Enable Bit 353" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB352  ,Set/Clear Enable Bit 352" "Disabled,Enabled"
else
hgroup.long 0x012C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0130++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415  ,Set/Clear Enable Bit 415" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB414  ,Set/Clear Enable Bit 414" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB413  ,Set/Clear Enable Bit 413" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412  ,Set/Clear Enable Bit 412" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB411  ,Set/Clear Enable Bit 411" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB410  ,Set/Clear Enable Bit 410" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409  ,Set/Clear Enable Bit 409" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB408  ,Set/Clear Enable Bit 408" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB407  ,Set/Clear Enable Bit 407" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406  ,Set/Clear Enable Bit 406" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB405  ,Set/Clear Enable Bit 405" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB404  ,Set/Clear Enable Bit 404" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403  ,Set/Clear Enable Bit 403" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB402  ,Set/Clear Enable Bit 402" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB401  ,Set/Clear Enable Bit 401" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400  ,Set/Clear Enable Bit 400" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB399  ,Set/Clear Enable Bit 399" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB398  ,Set/Clear Enable Bit 398" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397  ,Set/Clear Enable Bit 397" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB396  ,Set/Clear Enable Bit 396" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB395  ,Set/Clear Enable Bit 395" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394  ,Set/Clear Enable Bit 394" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB393  ,Set/Clear Enable Bit 393" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB392  ,Set/Clear Enable Bit 392" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391  ,Set/Clear Enable Bit 391" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB390  ,Set/Clear Enable Bit 390" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB389  ,Set/Clear Enable Bit 389" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388  ,Set/Clear Enable Bit 388" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB387  ,Set/Clear Enable Bit 387" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB386  ,Set/Clear Enable Bit 386" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385  ,Set/Clear Enable Bit 385" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB384  ,Set/Clear Enable Bit 384" "Disabled,Enabled"
else
hgroup.long 0x0130++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0134++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447  ,Set/Clear Enable Bit 447" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB446  ,Set/Clear Enable Bit 446" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB445  ,Set/Clear Enable Bit 445" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444  ,Set/Clear Enable Bit 444" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB443  ,Set/Clear Enable Bit 443" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB442  ,Set/Clear Enable Bit 442" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441  ,Set/Clear Enable Bit 441" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB440  ,Set/Clear Enable Bit 440" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB439  ,Set/Clear Enable Bit 439" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438  ,Set/Clear Enable Bit 438" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB437  ,Set/Clear Enable Bit 437" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB436  ,Set/Clear Enable Bit 436" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435  ,Set/Clear Enable Bit 435" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB434  ,Set/Clear Enable Bit 434" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB433  ,Set/Clear Enable Bit 433" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432  ,Set/Clear Enable Bit 432" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB431  ,Set/Clear Enable Bit 431" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB430  ,Set/Clear Enable Bit 430" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429  ,Set/Clear Enable Bit 429" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB428  ,Set/Clear Enable Bit 428" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB427  ,Set/Clear Enable Bit 427" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426  ,Set/Clear Enable Bit 426" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB425  ,Set/Clear Enable Bit 425" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB424  ,Set/Clear Enable Bit 424" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423  ,Set/Clear Enable Bit 423" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB422  ,Set/Clear Enable Bit 422" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB421  ,Set/Clear Enable Bit 421" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420  ,Set/Clear Enable Bit 420" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB419  ,Set/Clear Enable Bit 419" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB418  ,Set/Clear Enable Bit 418" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417  ,Set/Clear Enable Bit 417" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB416  ,Set/Clear Enable Bit 416" "Disabled,Enabled"
else
hgroup.long 0x0134++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0138++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479  ,Set/Clear Enable Bit 479" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB478  ,Set/Clear Enable Bit 478" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB477  ,Set/Clear Enable Bit 477" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476  ,Set/Clear Enable Bit 476" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB475  ,Set/Clear Enable Bit 475" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB474  ,Set/Clear Enable Bit 474" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473  ,Set/Clear Enable Bit 473" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB472  ,Set/Clear Enable Bit 472" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB471  ,Set/Clear Enable Bit 471" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470  ,Set/Clear Enable Bit 470" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB469  ,Set/Clear Enable Bit 469" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB468  ,Set/Clear Enable Bit 468" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467  ,Set/Clear Enable Bit 467" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB466  ,Set/Clear Enable Bit 466" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB465  ,Set/Clear Enable Bit 465" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464  ,Set/Clear Enable Bit 464" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB463  ,Set/Clear Enable Bit 463" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB462  ,Set/Clear Enable Bit 462" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461  ,Set/Clear Enable Bit 461" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB460  ,Set/Clear Enable Bit 460" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB459  ,Set/Clear Enable Bit 459" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458  ,Set/Clear Enable Bit 458" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB457  ,Set/Clear Enable Bit 457" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB456  ,Set/Clear Enable Bit 456" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455  ,Set/Clear Enable Bit 455" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB454  ,Set/Clear Enable Bit 454" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB453  ,Set/Clear Enable Bit 453" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452  ,Set/Clear Enable Bit 452" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB451  ,Set/Clear Enable Bit 451" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB450  ,Set/Clear Enable Bit 450" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449  ,Set/Clear Enable Bit 449" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB448  ,Set/Clear Enable Bit 448" "Disabled,Enabled"
else
hgroup.long 0x0138++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x013C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511  ,Set/Clear Enable Bit 511" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB510  ,Set/Clear Enable Bit 510" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB509  ,Set/Clear Enable Bit 509" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508  ,Set/Clear Enable Bit 508" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB507  ,Set/Clear Enable Bit 507" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB506  ,Set/Clear Enable Bit 506" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505  ,Set/Clear Enable Bit 505" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB504  ,Set/Clear Enable Bit 504" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB503  ,Set/Clear Enable Bit 503" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502  ,Set/Clear Enable Bit 502" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB501  ,Set/Clear Enable Bit 501" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB500  ,Set/Clear Enable Bit 500" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499  ,Set/Clear Enable Bit 499" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB498  ,Set/Clear Enable Bit 498" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB497  ,Set/Clear Enable Bit 497" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496  ,Set/Clear Enable Bit 496" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB495  ,Set/Clear Enable Bit 495" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB494  ,Set/Clear Enable Bit 494" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493  ,Set/Clear Enable Bit 493" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB492  ,Set/Clear Enable Bit 492" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB491  ,Set/Clear Enable Bit 491" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490  ,Set/Clear Enable Bit 490" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB489  ,Set/Clear Enable Bit 489" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB488  ,Set/Clear Enable Bit 488" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487  ,Set/Clear Enable Bit 487" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB486  ,Set/Clear Enable Bit 486" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB485  ,Set/Clear Enable Bit 485" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484  ,Set/Clear Enable Bit 484" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB483  ,Set/Clear Enable Bit 483" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB482  ,Set/Clear Enable Bit 482" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481  ,Set/Clear Enable Bit 481" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB480  ,Set/Clear Enable Bit 480" "Disabled,Enabled"
else
hgroup.long 0x013C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0140++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543  ,Set/Clear Enable Bit 543" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB542  ,Set/Clear Enable Bit 542" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB541  ,Set/Clear Enable Bit 541" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540  ,Set/Clear Enable Bit 540" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB539  ,Set/Clear Enable Bit 539" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB538  ,Set/Clear Enable Bit 538" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537  ,Set/Clear Enable Bit 537" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB536  ,Set/Clear Enable Bit 536" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB535  ,Set/Clear Enable Bit 535" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534  ,Set/Clear Enable Bit 534" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB533  ,Set/Clear Enable Bit 533" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB532  ,Set/Clear Enable Bit 532" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531  ,Set/Clear Enable Bit 531" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB530  ,Set/Clear Enable Bit 530" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB529  ,Set/Clear Enable Bit 529" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528  ,Set/Clear Enable Bit 528" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB527  ,Set/Clear Enable Bit 527" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB526  ,Set/Clear Enable Bit 526" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525  ,Set/Clear Enable Bit 525" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB524  ,Set/Clear Enable Bit 524" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB523  ,Set/Clear Enable Bit 523" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522  ,Set/Clear Enable Bit 522" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB521  ,Set/Clear Enable Bit 521" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB520  ,Set/Clear Enable Bit 520" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519  ,Set/Clear Enable Bit 519" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB518  ,Set/Clear Enable Bit 518" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB517  ,Set/Clear Enable Bit 517" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516  ,Set/Clear Enable Bit 516" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB515  ,Set/Clear Enable Bit 515" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB514  ,Set/Clear Enable Bit 514" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513  ,Set/Clear Enable Bit 513" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB512  ,Set/Clear Enable Bit 512" "Disabled,Enabled"
else
hgroup.long 0x0140++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0144++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575  ,Set/Clear Enable Bit 575" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB574  ,Set/Clear Enable Bit 574" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB573  ,Set/Clear Enable Bit 573" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572  ,Set/Clear Enable Bit 572" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB571  ,Set/Clear Enable Bit 571" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB570  ,Set/Clear Enable Bit 570" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569  ,Set/Clear Enable Bit 569" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB568  ,Set/Clear Enable Bit 568" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB567  ,Set/Clear Enable Bit 567" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566  ,Set/Clear Enable Bit 566" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB565  ,Set/Clear Enable Bit 565" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB564  ,Set/Clear Enable Bit 564" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563  ,Set/Clear Enable Bit 563" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB562  ,Set/Clear Enable Bit 562" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB561  ,Set/Clear Enable Bit 561" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560  ,Set/Clear Enable Bit 560" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB559  ,Set/Clear Enable Bit 559" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB558  ,Set/Clear Enable Bit 558" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557  ,Set/Clear Enable Bit 557" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB556  ,Set/Clear Enable Bit 556" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB555  ,Set/Clear Enable Bit 555" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554  ,Set/Clear Enable Bit 554" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB553  ,Set/Clear Enable Bit 553" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB552  ,Set/Clear Enable Bit 552" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551  ,Set/Clear Enable Bit 551" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB550  ,Set/Clear Enable Bit 550" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB549  ,Set/Clear Enable Bit 549" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548  ,Set/Clear Enable Bit 548" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB547  ,Set/Clear Enable Bit 547" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB546  ,Set/Clear Enable Bit 546" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545  ,Set/Clear Enable Bit 545" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB544  ,Set/Clear Enable Bit 544" "Disabled,Enabled"
else
hgroup.long 0x0144++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0148++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607  ,Set/Clear Enable Bit 607" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB606  ,Set/Clear Enable Bit 606" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB605  ,Set/Clear Enable Bit 605" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604  ,Set/Clear Enable Bit 604" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB603  ,Set/Clear Enable Bit 603" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB602  ,Set/Clear Enable Bit 602" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601  ,Set/Clear Enable Bit 601" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB600  ,Set/Clear Enable Bit 600" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB599  ,Set/Clear Enable Bit 599" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598  ,Set/Clear Enable Bit 598" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB597  ,Set/Clear Enable Bit 597" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB596  ,Set/Clear Enable Bit 596" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595  ,Set/Clear Enable Bit 595" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB594  ,Set/Clear Enable Bit 594" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB593  ,Set/Clear Enable Bit 593" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592  ,Set/Clear Enable Bit 592" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB591  ,Set/Clear Enable Bit 591" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB590  ,Set/Clear Enable Bit 590" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589  ,Set/Clear Enable Bit 589" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB588  ,Set/Clear Enable Bit 588" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB587  ,Set/Clear Enable Bit 587" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586  ,Set/Clear Enable Bit 586" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB585  ,Set/Clear Enable Bit 585" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB584  ,Set/Clear Enable Bit 584" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583  ,Set/Clear Enable Bit 583" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB582  ,Set/Clear Enable Bit 582" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB581  ,Set/Clear Enable Bit 581" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580  ,Set/Clear Enable Bit 580" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB579  ,Set/Clear Enable Bit 579" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB578  ,Set/Clear Enable Bit 578" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577  ,Set/Clear Enable Bit 577" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB576  ,Set/Clear Enable Bit 576" "Disabled,Enabled"
else
hgroup.long 0x0148++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x014C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639  ,Set/Clear Enable Bit 639" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB638  ,Set/Clear Enable Bit 638" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB637  ,Set/Clear Enable Bit 637" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636  ,Set/Clear Enable Bit 636" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB635  ,Set/Clear Enable Bit 635" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB634  ,Set/Clear Enable Bit 634" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633  ,Set/Clear Enable Bit 633" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB632  ,Set/Clear Enable Bit 632" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB631  ,Set/Clear Enable Bit 631" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630  ,Set/Clear Enable Bit 630" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB629  ,Set/Clear Enable Bit 629" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB628  ,Set/Clear Enable Bit 628" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627  ,Set/Clear Enable Bit 627" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB626  ,Set/Clear Enable Bit 626" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB625  ,Set/Clear Enable Bit 625" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624  ,Set/Clear Enable Bit 624" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB623  ,Set/Clear Enable Bit 623" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB622  ,Set/Clear Enable Bit 622" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621  ,Set/Clear Enable Bit 621" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB620  ,Set/Clear Enable Bit 620" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB619  ,Set/Clear Enable Bit 619" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618  ,Set/Clear Enable Bit 618" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB617  ,Set/Clear Enable Bit 617" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB616  ,Set/Clear Enable Bit 616" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615  ,Set/Clear Enable Bit 615" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB614  ,Set/Clear Enable Bit 614" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB613  ,Set/Clear Enable Bit 613" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612  ,Set/Clear Enable Bit 612" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB611  ,Set/Clear Enable Bit 611" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB610  ,Set/Clear Enable Bit 610" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609  ,Set/Clear Enable Bit 609" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB608  ,Set/Clear Enable Bit 608" "Disabled,Enabled"
else
hgroup.long 0x014C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0150++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671  ,Set/Clear Enable Bit 671" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB670  ,Set/Clear Enable Bit 670" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB669  ,Set/Clear Enable Bit 669" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668  ,Set/Clear Enable Bit 668" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB667  ,Set/Clear Enable Bit 667" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB666  ,Set/Clear Enable Bit 666" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665  ,Set/Clear Enable Bit 665" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB664  ,Set/Clear Enable Bit 664" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB663  ,Set/Clear Enable Bit 663" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662  ,Set/Clear Enable Bit 662" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB661  ,Set/Clear Enable Bit 661" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB660  ,Set/Clear Enable Bit 660" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659  ,Set/Clear Enable Bit 659" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB658  ,Set/Clear Enable Bit 658" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB657  ,Set/Clear Enable Bit 657" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656  ,Set/Clear Enable Bit 656" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB655  ,Set/Clear Enable Bit 655" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB654  ,Set/Clear Enable Bit 654" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653  ,Set/Clear Enable Bit 653" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB652  ,Set/Clear Enable Bit 652" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB651  ,Set/Clear Enable Bit 651" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650  ,Set/Clear Enable Bit 650" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB649  ,Set/Clear Enable Bit 649" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB648  ,Set/Clear Enable Bit 648" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647  ,Set/Clear Enable Bit 647" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB646  ,Set/Clear Enable Bit 646" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB645  ,Set/Clear Enable Bit 645" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644  ,Set/Clear Enable Bit 644" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB643  ,Set/Clear Enable Bit 643" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB642  ,Set/Clear Enable Bit 642" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641  ,Set/Clear Enable Bit 641" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB640  ,Set/Clear Enable Bit 640" "Disabled,Enabled"
else
hgroup.long 0x0150++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0154++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703  ,Set/Clear Enable Bit 703" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB702  ,Set/Clear Enable Bit 702" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB701  ,Set/Clear Enable Bit 701" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700  ,Set/Clear Enable Bit 700" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB699  ,Set/Clear Enable Bit 699" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB698  ,Set/Clear Enable Bit 698" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697  ,Set/Clear Enable Bit 697" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB696  ,Set/Clear Enable Bit 696" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB695  ,Set/Clear Enable Bit 695" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694  ,Set/Clear Enable Bit 694" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB693  ,Set/Clear Enable Bit 693" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB692  ,Set/Clear Enable Bit 692" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691  ,Set/Clear Enable Bit 691" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB690  ,Set/Clear Enable Bit 690" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB689  ,Set/Clear Enable Bit 689" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688  ,Set/Clear Enable Bit 688" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB687  ,Set/Clear Enable Bit 687" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB686  ,Set/Clear Enable Bit 686" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685  ,Set/Clear Enable Bit 685" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB684  ,Set/Clear Enable Bit 684" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB683  ,Set/Clear Enable Bit 683" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682  ,Set/Clear Enable Bit 682" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB681  ,Set/Clear Enable Bit 681" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB680  ,Set/Clear Enable Bit 680" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679  ,Set/Clear Enable Bit 679" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB678  ,Set/Clear Enable Bit 678" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB677  ,Set/Clear Enable Bit 677" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676  ,Set/Clear Enable Bit 676" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB675  ,Set/Clear Enable Bit 675" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB674  ,Set/Clear Enable Bit 674" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673  ,Set/Clear Enable Bit 673" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB672  ,Set/Clear Enable Bit 672" "Disabled,Enabled"
else
hgroup.long 0x0154++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0158++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735  ,Set/Clear Enable Bit 735" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB734  ,Set/Clear Enable Bit 734" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB733  ,Set/Clear Enable Bit 733" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732  ,Set/Clear Enable Bit 732" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB731  ,Set/Clear Enable Bit 731" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB730  ,Set/Clear Enable Bit 730" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729  ,Set/Clear Enable Bit 729" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB728  ,Set/Clear Enable Bit 728" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB727  ,Set/Clear Enable Bit 727" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726  ,Set/Clear Enable Bit 726" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB725  ,Set/Clear Enable Bit 725" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB724  ,Set/Clear Enable Bit 724" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723  ,Set/Clear Enable Bit 723" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB722  ,Set/Clear Enable Bit 722" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB721  ,Set/Clear Enable Bit 721" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720  ,Set/Clear Enable Bit 720" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB719  ,Set/Clear Enable Bit 719" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB718  ,Set/Clear Enable Bit 718" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717  ,Set/Clear Enable Bit 717" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB716  ,Set/Clear Enable Bit 716" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB715  ,Set/Clear Enable Bit 715" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714  ,Set/Clear Enable Bit 714" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB713  ,Set/Clear Enable Bit 713" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB712  ,Set/Clear Enable Bit 712" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711  ,Set/Clear Enable Bit 711" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB710  ,Set/Clear Enable Bit 710" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB709  ,Set/Clear Enable Bit 709" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708  ,Set/Clear Enable Bit 708" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB707  ,Set/Clear Enable Bit 707" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB706  ,Set/Clear Enable Bit 706" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705  ,Set/Clear Enable Bit 705" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB704  ,Set/Clear Enable Bit 704" "Disabled,Enabled"
else
hgroup.long 0x0158++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x015C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767  ,Set/Clear Enable Bit 767" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB766  ,Set/Clear Enable Bit 766" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB765  ,Set/Clear Enable Bit 765" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764  ,Set/Clear Enable Bit 764" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB763  ,Set/Clear Enable Bit 763" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB762  ,Set/Clear Enable Bit 762" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761  ,Set/Clear Enable Bit 761" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB760  ,Set/Clear Enable Bit 760" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB759  ,Set/Clear Enable Bit 759" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758  ,Set/Clear Enable Bit 758" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB757  ,Set/Clear Enable Bit 757" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB756  ,Set/Clear Enable Bit 756" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755  ,Set/Clear Enable Bit 755" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB754  ,Set/Clear Enable Bit 754" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB753  ,Set/Clear Enable Bit 753" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752  ,Set/Clear Enable Bit 752" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB751  ,Set/Clear Enable Bit 751" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB750  ,Set/Clear Enable Bit 750" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749  ,Set/Clear Enable Bit 749" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB748  ,Set/Clear Enable Bit 748" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB747  ,Set/Clear Enable Bit 747" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746  ,Set/Clear Enable Bit 746" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB745  ,Set/Clear Enable Bit 745" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB744  ,Set/Clear Enable Bit 744" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743  ,Set/Clear Enable Bit 743" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB742  ,Set/Clear Enable Bit 742" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB741  ,Set/Clear Enable Bit 741" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740  ,Set/Clear Enable Bit 740" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB739  ,Set/Clear Enable Bit 739" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB738  ,Set/Clear Enable Bit 738" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737  ,Set/Clear Enable Bit 737" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB736  ,Set/Clear Enable Bit 736" "Disabled,Enabled"
else
hgroup.long 0x015C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0160++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799  ,Set/Clear Enable Bit 799" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB798  ,Set/Clear Enable Bit 798" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB797  ,Set/Clear Enable Bit 797" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796  ,Set/Clear Enable Bit 796" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB795  ,Set/Clear Enable Bit 795" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB794  ,Set/Clear Enable Bit 794" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793  ,Set/Clear Enable Bit 793" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB792  ,Set/Clear Enable Bit 792" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB791  ,Set/Clear Enable Bit 791" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790  ,Set/Clear Enable Bit 790" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB789  ,Set/Clear Enable Bit 789" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB788  ,Set/Clear Enable Bit 788" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787  ,Set/Clear Enable Bit 787" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB786  ,Set/Clear Enable Bit 786" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB785  ,Set/Clear Enable Bit 785" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784  ,Set/Clear Enable Bit 784" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB783  ,Set/Clear Enable Bit 783" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB782  ,Set/Clear Enable Bit 782" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781  ,Set/Clear Enable Bit 781" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB780  ,Set/Clear Enable Bit 780" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB779  ,Set/Clear Enable Bit 779" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778  ,Set/Clear Enable Bit 778" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB777  ,Set/Clear Enable Bit 777" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB776  ,Set/Clear Enable Bit 776" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775  ,Set/Clear Enable Bit 775" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB774  ,Set/Clear Enable Bit 774" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB773  ,Set/Clear Enable Bit 773" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772  ,Set/Clear Enable Bit 772" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB771  ,Set/Clear Enable Bit 771" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB770  ,Set/Clear Enable Bit 770" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769  ,Set/Clear Enable Bit 769" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB768  ,Set/Clear Enable Bit 768" "Disabled,Enabled"
else
hgroup.long 0x0160++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0164++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831  ,Set/Clear Enable Bit 831" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB830  ,Set/Clear Enable Bit 830" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB829  ,Set/Clear Enable Bit 829" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828  ,Set/Clear Enable Bit 828" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB827  ,Set/Clear Enable Bit 827" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB826  ,Set/Clear Enable Bit 826" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825  ,Set/Clear Enable Bit 825" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB824  ,Set/Clear Enable Bit 824" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB823  ,Set/Clear Enable Bit 823" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822  ,Set/Clear Enable Bit 822" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB821  ,Set/Clear Enable Bit 821" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB820  ,Set/Clear Enable Bit 820" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819  ,Set/Clear Enable Bit 819" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB818  ,Set/Clear Enable Bit 818" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB817  ,Set/Clear Enable Bit 817" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816  ,Set/Clear Enable Bit 816" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB815  ,Set/Clear Enable Bit 815" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB814  ,Set/Clear Enable Bit 814" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813  ,Set/Clear Enable Bit 813" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB812  ,Set/Clear Enable Bit 812" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB811  ,Set/Clear Enable Bit 811" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810  ,Set/Clear Enable Bit 810" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB809  ,Set/Clear Enable Bit 809" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB808  ,Set/Clear Enable Bit 808" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807  ,Set/Clear Enable Bit 807" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB806  ,Set/Clear Enable Bit 806" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB805  ,Set/Clear Enable Bit 805" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804  ,Set/Clear Enable Bit 804" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB803  ,Set/Clear Enable Bit 803" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB802  ,Set/Clear Enable Bit 802" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801  ,Set/Clear Enable Bit 801" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB800  ,Set/Clear Enable Bit 800" "Disabled,Enabled"
else
hgroup.long 0x0164++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0168++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863  ,Set/Clear Enable Bit 863" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB862  ,Set/Clear Enable Bit 862" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB861  ,Set/Clear Enable Bit 861" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860  ,Set/Clear Enable Bit 860" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB859  ,Set/Clear Enable Bit 859" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB858  ,Set/Clear Enable Bit 858" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857  ,Set/Clear Enable Bit 857" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB856  ,Set/Clear Enable Bit 856" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB855  ,Set/Clear Enable Bit 855" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854  ,Set/Clear Enable Bit 854" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB853  ,Set/Clear Enable Bit 853" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB852  ,Set/Clear Enable Bit 852" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851  ,Set/Clear Enable Bit 851" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB850  ,Set/Clear Enable Bit 850" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB849  ,Set/Clear Enable Bit 849" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848  ,Set/Clear Enable Bit 848" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB847  ,Set/Clear Enable Bit 847" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB846  ,Set/Clear Enable Bit 846" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845  ,Set/Clear Enable Bit 845" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB844  ,Set/Clear Enable Bit 844" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB843  ,Set/Clear Enable Bit 843" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842  ,Set/Clear Enable Bit 842" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB841  ,Set/Clear Enable Bit 841" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB840  ,Set/Clear Enable Bit 840" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839  ,Set/Clear Enable Bit 839" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB838  ,Set/Clear Enable Bit 838" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB837  ,Set/Clear Enable Bit 837" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836  ,Set/Clear Enable Bit 836" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB835  ,Set/Clear Enable Bit 835" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB834  ,Set/Clear Enable Bit 834" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833  ,Set/Clear Enable Bit 833" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB832  ,Set/Clear Enable Bit 832" "Disabled,Enabled"
else
hgroup.long 0x0168++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x016C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895  ,Set/Clear Enable Bit 895" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB894  ,Set/Clear Enable Bit 894" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB893  ,Set/Clear Enable Bit 893" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892  ,Set/Clear Enable Bit 892" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB891  ,Set/Clear Enable Bit 891" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB890  ,Set/Clear Enable Bit 890" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889  ,Set/Clear Enable Bit 889" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB888  ,Set/Clear Enable Bit 888" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB887  ,Set/Clear Enable Bit 887" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886  ,Set/Clear Enable Bit 886" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB885  ,Set/Clear Enable Bit 885" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB884  ,Set/Clear Enable Bit 884" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883  ,Set/Clear Enable Bit 883" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB882  ,Set/Clear Enable Bit 882" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB881  ,Set/Clear Enable Bit 881" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880  ,Set/Clear Enable Bit 880" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB879  ,Set/Clear Enable Bit 879" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB878  ,Set/Clear Enable Bit 878" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877  ,Set/Clear Enable Bit 877" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB876  ,Set/Clear Enable Bit 876" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB875  ,Set/Clear Enable Bit 875" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874  ,Set/Clear Enable Bit 874" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB873  ,Set/Clear Enable Bit 873" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB872  ,Set/Clear Enable Bit 872" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871  ,Set/Clear Enable Bit 871" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB870  ,Set/Clear Enable Bit 870" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB869  ,Set/Clear Enable Bit 869" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868  ,Set/Clear Enable Bit 868" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB867  ,Set/Clear Enable Bit 867" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB866  ,Set/Clear Enable Bit 866" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865  ,Set/Clear Enable Bit 865" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB864  ,Set/Clear Enable Bit 864" "Disabled,Enabled"
else
hgroup.long 0x016C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0170++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927  ,Set/Clear Enable Bit 927" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB926  ,Set/Clear Enable Bit 926" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB925  ,Set/Clear Enable Bit 925" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924  ,Set/Clear Enable Bit 924" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB923  ,Set/Clear Enable Bit 923" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB922  ,Set/Clear Enable Bit 922" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921  ,Set/Clear Enable Bit 921" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB920  ,Set/Clear Enable Bit 920" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB919  ,Set/Clear Enable Bit 919" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918  ,Set/Clear Enable Bit 918" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB917  ,Set/Clear Enable Bit 917" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB916  ,Set/Clear Enable Bit 916" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915  ,Set/Clear Enable Bit 915" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB914  ,Set/Clear Enable Bit 914" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB913  ,Set/Clear Enable Bit 913" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912  ,Set/Clear Enable Bit 912" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB911  ,Set/Clear Enable Bit 911" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB910  ,Set/Clear Enable Bit 910" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909  ,Set/Clear Enable Bit 909" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB908  ,Set/Clear Enable Bit 908" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB907  ,Set/Clear Enable Bit 907" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906  ,Set/Clear Enable Bit 906" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB905  ,Set/Clear Enable Bit 905" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB904  ,Set/Clear Enable Bit 904" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903  ,Set/Clear Enable Bit 903" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB902  ,Set/Clear Enable Bit 902" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB901  ,Set/Clear Enable Bit 901" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900  ,Set/Clear Enable Bit 900" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB899  ,Set/Clear Enable Bit 899" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB898  ,Set/Clear Enable Bit 898" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897  ,Set/Clear Enable Bit 897" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB896  ,Set/Clear Enable Bit 896" "Disabled,Enabled"
else
hgroup.long 0x0170++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0174++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959  ,Set/Clear Enable Bit 959" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB958  ,Set/Clear Enable Bit 958" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB957  ,Set/Clear Enable Bit 957" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956  ,Set/Clear Enable Bit 956" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB955  ,Set/Clear Enable Bit 955" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB954  ,Set/Clear Enable Bit 954" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953  ,Set/Clear Enable Bit 953" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB952  ,Set/Clear Enable Bit 952" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB951  ,Set/Clear Enable Bit 951" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950  ,Set/Clear Enable Bit 950" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB949  ,Set/Clear Enable Bit 949" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB948  ,Set/Clear Enable Bit 948" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947  ,Set/Clear Enable Bit 947" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB946  ,Set/Clear Enable Bit 946" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB945  ,Set/Clear Enable Bit 945" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944  ,Set/Clear Enable Bit 944" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB943  ,Set/Clear Enable Bit 943" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB942  ,Set/Clear Enable Bit 942" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941  ,Set/Clear Enable Bit 941" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB940  ,Set/Clear Enable Bit 940" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB939  ,Set/Clear Enable Bit 939" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938  ,Set/Clear Enable Bit 938" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB937  ,Set/Clear Enable Bit 937" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB936  ,Set/Clear Enable Bit 936" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935  ,Set/Clear Enable Bit 935" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB934  ,Set/Clear Enable Bit 934" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB933  ,Set/Clear Enable Bit 933" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932  ,Set/Clear Enable Bit 932" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB931  ,Set/Clear Enable Bit 931" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB930  ,Set/Clear Enable Bit 930" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929  ,Set/Clear Enable Bit 929" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB928  ,Set/Clear Enable Bit 928" "Disabled,Enabled"
else
hgroup.long 0x0174++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0178++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991  ,Set/Clear Enable Bit 991" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB990  ,Set/Clear Enable Bit 990" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB989  ,Set/Clear Enable Bit 989" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988  ,Set/Clear Enable Bit 988" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB987  ,Set/Clear Enable Bit 987" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB986  ,Set/Clear Enable Bit 986" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985  ,Set/Clear Enable Bit 985" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB984  ,Set/Clear Enable Bit 984" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB983  ,Set/Clear Enable Bit 983" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982  ,Set/Clear Enable Bit 982" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB981  ,Set/Clear Enable Bit 981" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB980  ,Set/Clear Enable Bit 980" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979  ,Set/Clear Enable Bit 979" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB978  ,Set/Clear Enable Bit 978" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB977  ,Set/Clear Enable Bit 977" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976  ,Set/Clear Enable Bit 976" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB975  ,Set/Clear Enable Bit 975" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB974  ,Set/Clear Enable Bit 974" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973  ,Set/Clear Enable Bit 973" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB972  ,Set/Clear Enable Bit 972" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB971  ,Set/Clear Enable Bit 971" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970  ,Set/Clear Enable Bit 970" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB969  ,Set/Clear Enable Bit 969" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB968  ,Set/Clear Enable Bit 968" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967  ,Set/Clear Enable Bit 967" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB966  ,Set/Clear Enable Bit 966" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB965  ,Set/Clear Enable Bit 965" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964  ,Set/Clear Enable Bit 964" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB963  ,Set/Clear Enable Bit 963" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB962  ,Set/Clear Enable Bit 962" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961  ,Set/Clear Enable Bit 961" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB960  ,Set/Clear Enable Bit 960" "Disabled,Enabled"
else
hgroup.long 0x0178++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
endif
tree.end
width 22.
tree "Set/Clear Pending Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0200++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0200++0x03
line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31   ,Set/Clear Pending Bit 31" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND30   ,Set/Clear Pending Bit 30" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND29   ,Set/Clear Pending Bit 29" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28   ,Set/Clear Pending Bit 28" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND27   ,Set/Clear Pending Bit 27" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND26   ,Set/Clear Pending Bit 26" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25   ,Set/Clear Pending Bit 25" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND24   ,Set/Clear Pending Bit 24" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND23   ,Set/Clear Pending Bit 23" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22   ,Set/Clear Pending Bit 22" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND21   ,Set/Clear Pending Bit 21" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND20   ,Set/Clear Pending Bit 20" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19   ,Set/Clear Pending Bit 19" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND18   ,Set/Clear Pending Bit 18" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND17   ,Set/Clear Pending Bit 17" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16   ,Set/Clear Pending Bit 16" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND15   ,Set/Clear Pending Bit 15" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND14   ,Set/Clear Pending Bit 14" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13   ,Set/Clear Pending Bit 13" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND12   ,Set/Clear Pending Bit 12" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND11   ,Set/Clear Pending Bit 11" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10   ,Set/Clear Pending Bit 10" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND9    ,Set/Clear Pending Bit 9" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND8    ,Set/Clear Pending Bit 8" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7    ,Set/Clear Pending Bit 7" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND6    ,Set/Clear Pending Bit 6" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND5    ,Set/Clear Pending Bit 5" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4    ,Set/Clear Pending Bit 4" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND3    ,Set/Clear Pending Bit 3" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND2    ,Set/Clear Pending Bit 2" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1    ,Set/Clear Pending Bit 1" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND0    ,Set/Clear Pending Bit 0" "Not pending,Pending"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0204++0x03
line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63   ,Set/Clear Pending Bit 63" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND62   ,Set/Clear Pending Bit 62" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND61   ,Set/Clear Pending Bit 61" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60   ,Set/Clear Pending Bit 60" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND59   ,Set/Clear Pending Bit 59" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND58   ,Set/Clear Pending Bit 58" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57   ,Set/Clear Pending Bit 57" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND56   ,Set/Clear Pending Bit 56" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND55   ,Set/Clear Pending Bit 55" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54   ,Set/Clear Pending Bit 54" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND53   ,Set/Clear Pending Bit 53" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND52   ,Set/Clear Pending Bit 52" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51   ,Set/Clear Pending Bit 51" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND50   ,Set/Clear Pending Bit 50" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND49   ,Set/Clear Pending Bit 49" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48   ,Set/Clear Pending Bit 48" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND47   ,Set/Clear Pending Bit 47" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND46   ,Set/Clear Pending Bit 46" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45   ,Set/Clear Pending Bit 45" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND44   ,Set/Clear Pending Bit 44" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND43   ,Set/Clear Pending Bit 43" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42   ,Set/Clear Pending Bit 42" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND41   ,Set/Clear Pending Bit 41" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND40   ,Set/Clear Pending Bit 40" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39   ,Set/Clear Pending Bit 39" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND38   ,Set/Clear Pending Bit 38" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND37   ,Set/Clear Pending Bit 37" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36   ,Set/Clear Pending Bit 36" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND35   ,Set/Clear Pending Bit 35" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND34   ,Set/Clear Pending Bit 34" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33   ,Set/Clear Pending Bit 33" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND32   ,Set/Clear Pending Bit 32" "Not pending,Pending"
else
hgroup.long 0x0204++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0208++0x03
line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95   ,Set/Clear Pending Bit 95" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND94   ,Set/Clear Pending Bit 94" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND93   ,Set/Clear Pending Bit 93" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92   ,Set/Clear Pending Bit 92" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND91   ,Set/Clear Pending Bit 91" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND90   ,Set/Clear Pending Bit 90" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89   ,Set/Clear Pending Bit 89" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND88   ,Set/Clear Pending Bit 88" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND87   ,Set/Clear Pending Bit 87" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86   ,Set/Clear Pending Bit 86" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND85   ,Set/Clear Pending Bit 85" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND84   ,Set/Clear Pending Bit 84" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83   ,Set/Clear Pending Bit 83" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND82   ,Set/Clear Pending Bit 82" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND81   ,Set/Clear Pending Bit 81" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80   ,Set/Clear Pending Bit 80" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND79   ,Set/Clear Pending Bit 79" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND78   ,Set/Clear Pending Bit 78" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77   ,Set/Clear Pending Bit 77" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND76   ,Set/Clear Pending Bit 76" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND75   ,Set/Clear Pending Bit 75" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74   ,Set/Clear Pending Bit 74" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND73   ,Set/Clear Pending Bit 73" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND72   ,Set/Clear Pending Bit 72" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71   ,Set/Clear Pending Bit 71" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND70   ,Set/Clear Pending Bit 70" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND69   ,Set/Clear Pending Bit 69" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68   ,Set/Clear Pending Bit 68" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND67   ,Set/Clear Pending Bit 67" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND66   ,Set/Clear Pending Bit 66" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65   ,Set/Clear Pending Bit 65" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND64   ,Set/Clear Pending Bit 64" "Not pending,Pending"
else
hgroup.long 0x0208++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x020C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127  ,Set/Clear Pending Bit 127" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND126  ,Set/Clear Pending Bit 126" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND125  ,Set/Clear Pending Bit 125" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124  ,Set/Clear Pending Bit 124" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND123  ,Set/Clear Pending Bit 123" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND122  ,Set/Clear Pending Bit 122" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121  ,Set/Clear Pending Bit 121" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND120  ,Set/Clear Pending Bit 120" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND119  ,Set/Clear Pending Bit 119" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118  ,Set/Clear Pending Bit 118" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND117  ,Set/Clear Pending Bit 117" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND116  ,Set/Clear Pending Bit 116" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115  ,Set/Clear Pending Bit 115" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND114  ,Set/Clear Pending Bit 114" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND113  ,Set/Clear Pending Bit 113" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112  ,Set/Clear Pending Bit 112" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND111  ,Set/Clear Pending Bit 111" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND110  ,Set/Clear Pending Bit 110" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109  ,Set/Clear Pending Bit 109" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND108  ,Set/Clear Pending Bit 108" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND107  ,Set/Clear Pending Bit 107" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106  ,Set/Clear Pending Bit 106" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND105  ,Set/Clear Pending Bit 105" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND104  ,Set/Clear Pending Bit 104" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103  ,Set/Clear Pending Bit 103" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND102  ,Set/Clear Pending Bit 102" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND101  ,Set/Clear Pending Bit 101" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100  ,Set/Clear Pending Bit 100" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND99   ,Set/Clear Pending Bit 99" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND98   ,Set/Clear Pending Bit 98" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97   ,Set/Clear Pending Bit 97" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND96   ,Set/Clear Pending Bit 96" "Not pending,Pending"
else
hgroup.long 0x020C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0210++0x03
line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159  ,Set/Clear Pending Bit 159" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND158  ,Set/Clear Pending Bit 158" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND157  ,Set/Clear Pending Bit 157" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156  ,Set/Clear Pending Bit 156" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND155  ,Set/Clear Pending Bit 155" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND154  ,Set/Clear Pending Bit 154" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153  ,Set/Clear Pending Bit 153" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND152  ,Set/Clear Pending Bit 152" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND151  ,Set/Clear Pending Bit 151" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150  ,Set/Clear Pending Bit 150" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND149  ,Set/Clear Pending Bit 149" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND148  ,Set/Clear Pending Bit 148" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147  ,Set/Clear Pending Bit 147" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND146  ,Set/Clear Pending Bit 146" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND145  ,Set/Clear Pending Bit 145" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144  ,Set/Clear Pending Bit 144" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND143  ,Set/Clear Pending Bit 143" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND142  ,Set/Clear Pending Bit 142" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141  ,Set/Clear Pending Bit 141" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND140  ,Set/Clear Pending Bit 140" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND139  ,Set/Clear Pending Bit 139" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138  ,Set/Clear Pending Bit 138" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND137  ,Set/Clear Pending Bit 137" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND136  ,Set/Clear Pending Bit 136" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135  ,Set/Clear Pending Bit 135" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND134  ,Set/Clear Pending Bit 134" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND133  ,Set/Clear Pending Bit 133" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132  ,Set/Clear Pending Bit 132" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND131  ,Set/Clear Pending Bit 131" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND130  ,Set/Clear Pending Bit 130" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129  ,Set/Clear Pending Bit 129" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND128  ,Set/Clear Pending Bit 128" "Not pending,Pending"
else
hgroup.long 0x0210++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0214++0x03
line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191  ,Set/Clear Pending Bit 191" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND190  ,Set/Clear Pending Bit 190" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND189  ,Set/Clear Pending Bit 189" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188  ,Set/Clear Pending Bit 188" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND187  ,Set/Clear Pending Bit 187" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND186  ,Set/Clear Pending Bit 186" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185  ,Set/Clear Pending Bit 185" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND184  ,Set/Clear Pending Bit 184" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND183  ,Set/Clear Pending Bit 183" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182  ,Set/Clear Pending Bit 182" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND181  ,Set/Clear Pending Bit 181" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND180  ,Set/Clear Pending Bit 180" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179  ,Set/Clear Pending Bit 179" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND178  ,Set/Clear Pending Bit 178" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND177  ,Set/Clear Pending Bit 177" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176  ,Set/Clear Pending Bit 176" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND175  ,Set/Clear Pending Bit 175" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND174  ,Set/Clear Pending Bit 174" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173  ,Set/Clear Pending Bit 173" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND172  ,Set/Clear Pending Bit 172" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND171  ,Set/Clear Pending Bit 171" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170  ,Set/Clear Pending Bit 170" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND169  ,Set/Clear Pending Bit 169" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND168  ,Set/Clear Pending Bit 168" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167  ,Set/Clear Pending Bit 167" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND166  ,Set/Clear Pending Bit 166" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND165  ,Set/Clear Pending Bit 165" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164  ,Set/Clear Pending Bit 164" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND163  ,Set/Clear Pending Bit 163" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND162  ,Set/Clear Pending Bit 162" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161  ,Set/Clear Pending Bit 161" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND160  ,Set/Clear Pending Bit 160" "Not pending,Pending"
else
hgroup.long 0x0214++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0218++0x03
line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223  ,Set/Clear Pending Bit 223" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND222  ,Set/Clear Pending Bit 222" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND221  ,Set/Clear Pending Bit 221" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220  ,Set/Clear Pending Bit 220" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND219  ,Set/Clear Pending Bit 219" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND218  ,Set/Clear Pending Bit 218" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217  ,Set/Clear Pending Bit 217" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND216  ,Set/Clear Pending Bit 216" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND215  ,Set/Clear Pending Bit 215" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214  ,Set/Clear Pending Bit 214" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND213  ,Set/Clear Pending Bit 213" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND212  ,Set/Clear Pending Bit 212" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211  ,Set/Clear Pending Bit 211" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND210  ,Set/Clear Pending Bit 210" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND209  ,Set/Clear Pending Bit 209" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208  ,Set/Clear Pending Bit 208" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND207  ,Set/Clear Pending Bit 207" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND206  ,Set/Clear Pending Bit 206" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205  ,Set/Clear Pending Bit 205" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND204  ,Set/Clear Pending Bit 204" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND203  ,Set/Clear Pending Bit 203" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202  ,Set/Clear Pending Bit 202" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND201  ,Set/Clear Pending Bit 201" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND200  ,Set/Clear Pending Bit 200" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199  ,Set/Clear Pending Bit 199" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND198  ,Set/Clear Pending Bit 198" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND197  ,Set/Clear Pending Bit 197" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196  ,Set/Clear Pending Bit 196" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND195  ,Set/Clear Pending Bit 195" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND194  ,Set/Clear Pending Bit 194" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193  ,Set/Clear Pending Bit 193" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND192  ,Set/Clear Pending Bit 192" "Not pending,Pending"
else
hgroup.long 0x0218++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x021C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255  ,Set/Clear Pending Bit 255" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND254  ,Set/Clear Pending Bit 254" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND253  ,Set/Clear Pending Bit 253" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252  ,Set/Clear Pending Bit 252" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND251  ,Set/Clear Pending Bit 251" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND250  ,Set/Clear Pending Bit 250" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249  ,Set/Clear Pending Bit 249" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND248  ,Set/Clear Pending Bit 248" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND247  ,Set/Clear Pending Bit 247" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246  ,Set/Clear Pending Bit 246" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND245  ,Set/Clear Pending Bit 245" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND244  ,Set/Clear Pending Bit 244" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243  ,Set/Clear Pending Bit 243" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND242  ,Set/Clear Pending Bit 242" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND241  ,Set/Clear Pending Bit 241" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240  ,Set/Clear Pending Bit 240" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND239  ,Set/Clear Pending Bit 239" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND238  ,Set/Clear Pending Bit 238" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237  ,Set/Clear Pending Bit 237" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND236  ,Set/Clear Pending Bit 236" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND235  ,Set/Clear Pending Bit 235" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234  ,Set/Clear Pending Bit 234" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND233  ,Set/Clear Pending Bit 233" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND232  ,Set/Clear Pending Bit 232" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231  ,Set/Clear Pending Bit 231" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND230  ,Set/Clear Pending Bit 230" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND229  ,Set/Clear Pending Bit 229" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228  ,Set/Clear Pending Bit 228" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND227  ,Set/Clear Pending Bit 227" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND226  ,Set/Clear Pending Bit 226" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225  ,Set/Clear Pending Bit 225" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND224  ,Set/Clear Pending Bit 224" "Not pending,Pending"
else
hgroup.long 0x021C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0220++0x03
line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287  ,Set/Clear Pending Bit 287" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND286  ,Set/Clear Pending Bit 286" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND285  ,Set/Clear Pending Bit 285" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284  ,Set/Clear Pending Bit 284" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND283  ,Set/Clear Pending Bit 283" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND282  ,Set/Clear Pending Bit 282" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281  ,Set/Clear Pending Bit 281" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND280  ,Set/Clear Pending Bit 280" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND279  ,Set/Clear Pending Bit 279" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278  ,Set/Clear Pending Bit 278" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND277  ,Set/Clear Pending Bit 277" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND276  ,Set/Clear Pending Bit 276" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275  ,Set/Clear Pending Bit 275" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND274  ,Set/Clear Pending Bit 274" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND273  ,Set/Clear Pending Bit 273" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272  ,Set/Clear Pending Bit 272" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND271  ,Set/Clear Pending Bit 271" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND270  ,Set/Clear Pending Bit 270" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269  ,Set/Clear Pending Bit 269" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND268  ,Set/Clear Pending Bit 268" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND267  ,Set/Clear Pending Bit 267" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266  ,Set/Clear Pending Bit 266" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND265  ,Set/Clear Pending Bit 265" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND264  ,Set/Clear Pending Bit 264" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263  ,Set/Clear Pending Bit 263" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND262  ,Set/Clear Pending Bit 262" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND261  ,Set/Clear Pending Bit 261" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260  ,Set/Clear Pending Bit 260" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND259  ,Set/Clear Pending Bit 259" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND258  ,Set/Clear Pending Bit 258" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257  ,Set/Clear Pending Bit 257" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND256  ,Set/Clear Pending Bit 256" "Not pending,Pending"
else
hgroup.long 0x0220++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0224++0x03
line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319  ,Set/Clear Pending Bit 319" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND318  ,Set/Clear Pending Bit 318" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND317  ,Set/Clear Pending Bit 317" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316  ,Set/Clear Pending Bit 316" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND315  ,Set/Clear Pending Bit 315" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND314  ,Set/Clear Pending Bit 314" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313  ,Set/Clear Pending Bit 313" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND312  ,Set/Clear Pending Bit 312" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND311  ,Set/Clear Pending Bit 311" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310  ,Set/Clear Pending Bit 310" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND309  ,Set/Clear Pending Bit 309" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND308  ,Set/Clear Pending Bit 308" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307  ,Set/Clear Pending Bit 307" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND306  ,Set/Clear Pending Bit 306" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND305  ,Set/Clear Pending Bit 305" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304  ,Set/Clear Pending Bit 304" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND303  ,Set/Clear Pending Bit 303" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND302  ,Set/Clear Pending Bit 302" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301  ,Set/Clear Pending Bit 301" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND300  ,Set/Clear Pending Bit 300" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND299  ,Set/Clear Pending Bit 299" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298  ,Set/Clear Pending Bit 298" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND297  ,Set/Clear Pending Bit 297" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND296  ,Set/Clear Pending Bit 296" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295  ,Set/Clear Pending Bit 295" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND294  ,Set/Clear Pending Bit 294" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND293  ,Set/Clear Pending Bit 293" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292  ,Set/Clear Pending Bit 292" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND291  ,Set/Clear Pending Bit 291" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND290  ,Set/Clear Pending Bit 290" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289  ,Set/Clear Pending Bit 289" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND288  ,Set/Clear Pending Bit 288" "Not pending,Pending"
else
hgroup.long 0x0224++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0228++0x03
line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351  ,Set/Clear Pending Bit 351" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND350  ,Set/Clear Pending Bit 350" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND349  ,Set/Clear Pending Bit 349" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348  ,Set/Clear Pending Bit 348" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND347  ,Set/Clear Pending Bit 347" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND346  ,Set/Clear Pending Bit 346" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345  ,Set/Clear Pending Bit 345" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND344  ,Set/Clear Pending Bit 344" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND343  ,Set/Clear Pending Bit 343" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342  ,Set/Clear Pending Bit 342" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND341  ,Set/Clear Pending Bit 341" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND340  ,Set/Clear Pending Bit 340" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339  ,Set/Clear Pending Bit 339" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND338  ,Set/Clear Pending Bit 338" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND337  ,Set/Clear Pending Bit 337" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336  ,Set/Clear Pending Bit 336" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND335  ,Set/Clear Pending Bit 335" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND334  ,Set/Clear Pending Bit 334" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333  ,Set/Clear Pending Bit 333" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND332  ,Set/Clear Pending Bit 332" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND331  ,Set/Clear Pending Bit 331" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330  ,Set/Clear Pending Bit 330" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND329  ,Set/Clear Pending Bit 329" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND328  ,Set/Clear Pending Bit 328" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327  ,Set/Clear Pending Bit 327" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND326  ,Set/Clear Pending Bit 326" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND325  ,Set/Clear Pending Bit 325" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324  ,Set/Clear Pending Bit 324" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND323  ,Set/Clear Pending Bit 323" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND322  ,Set/Clear Pending Bit 322" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321  ,Set/Clear Pending Bit 321" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND320  ,Set/Clear Pending Bit 320" "Not pending,Pending"
else
hgroup.long 0x0228++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x022C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383  ,Set/Clear Pending Bit 383" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND382  ,Set/Clear Pending Bit 382" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND381  ,Set/Clear Pending Bit 381" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380  ,Set/Clear Pending Bit 380" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND379  ,Set/Clear Pending Bit 379" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND378  ,Set/Clear Pending Bit 378" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377  ,Set/Clear Pending Bit 377" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND376  ,Set/Clear Pending Bit 376" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND375  ,Set/Clear Pending Bit 375" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374  ,Set/Clear Pending Bit 374" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND373  ,Set/Clear Pending Bit 373" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND372  ,Set/Clear Pending Bit 372" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371  ,Set/Clear Pending Bit 371" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND370  ,Set/Clear Pending Bit 370" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND369  ,Set/Clear Pending Bit 369" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368  ,Set/Clear Pending Bit 368" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND367  ,Set/Clear Pending Bit 367" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND366  ,Set/Clear Pending Bit 366" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365  ,Set/Clear Pending Bit 365" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND364  ,Set/Clear Pending Bit 364" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND363  ,Set/Clear Pending Bit 363" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362  ,Set/Clear Pending Bit 362" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND361  ,Set/Clear Pending Bit 361" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND360  ,Set/Clear Pending Bit 360" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359  ,Set/Clear Pending Bit 359" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND358  ,Set/Clear Pending Bit 358" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND357  ,Set/Clear Pending Bit 357" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356  ,Set/Clear Pending Bit 356" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND355  ,Set/Clear Pending Bit 355" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND354  ,Set/Clear Pending Bit 354" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353  ,Set/Clear Pending Bit 353" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND352  ,Set/Clear Pending Bit 352" "Not pending,Pending"
else
hgroup.long 0x022C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0230++0x03
line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415  ,Set/Clear Pending Bit 415" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND414  ,Set/Clear Pending Bit 414" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND413  ,Set/Clear Pending Bit 413" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412  ,Set/Clear Pending Bit 412" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND411  ,Set/Clear Pending Bit 411" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND410  ,Set/Clear Pending Bit 410" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409  ,Set/Clear Pending Bit 409" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND408  ,Set/Clear Pending Bit 408" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND407  ,Set/Clear Pending Bit 407" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406  ,Set/Clear Pending Bit 406" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND405  ,Set/Clear Pending Bit 405" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND404  ,Set/Clear Pending Bit 404" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403  ,Set/Clear Pending Bit 403" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND402  ,Set/Clear Pending Bit 402" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND401  ,Set/Clear Pending Bit 401" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400  ,Set/Clear Pending Bit 400" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND399  ,Set/Clear Pending Bit 399" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND398  ,Set/Clear Pending Bit 398" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397  ,Set/Clear Pending Bit 397" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND396  ,Set/Clear Pending Bit 396" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND395  ,Set/Clear Pending Bit 395" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394  ,Set/Clear Pending Bit 394" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND393  ,Set/Clear Pending Bit 393" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND392  ,Set/Clear Pending Bit 392" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391  ,Set/Clear Pending Bit 391" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND390  ,Set/Clear Pending Bit 390" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND389  ,Set/Clear Pending Bit 389" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388  ,Set/Clear Pending Bit 388" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND387  ,Set/Clear Pending Bit 387" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND386  ,Set/Clear Pending Bit 386" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385  ,Set/Clear Pending Bit 385" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND384  ,Set/Clear Pending Bit 384" "Not pending,Pending"
else
hgroup.long 0x0230++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0234++0x03
line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447  ,Set/Clear Pending Bit 447" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND446  ,Set/Clear Pending Bit 446" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND445  ,Set/Clear Pending Bit 445" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444  ,Set/Clear Pending Bit 444" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND443  ,Set/Clear Pending Bit 443" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND442  ,Set/Clear Pending Bit 442" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441  ,Set/Clear Pending Bit 441" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND440  ,Set/Clear Pending Bit 440" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND439  ,Set/Clear Pending Bit 439" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438  ,Set/Clear Pending Bit 438" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND437  ,Set/Clear Pending Bit 437" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND436  ,Set/Clear Pending Bit 436" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435  ,Set/Clear Pending Bit 435" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND434  ,Set/Clear Pending Bit 434" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND433  ,Set/Clear Pending Bit 433" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432  ,Set/Clear Pending Bit 432" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND431  ,Set/Clear Pending Bit 431" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND430  ,Set/Clear Pending Bit 430" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429  ,Set/Clear Pending Bit 429" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND428  ,Set/Clear Pending Bit 428" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND427  ,Set/Clear Pending Bit 427" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426  ,Set/Clear Pending Bit 426" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND425  ,Set/Clear Pending Bit 425" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND424  ,Set/Clear Pending Bit 424" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423  ,Set/Clear Pending Bit 423" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND422  ,Set/Clear Pending Bit 422" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND421  ,Set/Clear Pending Bit 421" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420  ,Set/Clear Pending Bit 420" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND419  ,Set/Clear Pending Bit 419" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND418  ,Set/Clear Pending Bit 418" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417  ,Set/Clear Pending Bit 417" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND416  ,Set/Clear Pending Bit 416" "Not pending,Pending"
else
hgroup.long 0x0234++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0238++0x03
line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479  ,Set/Clear Pending Bit 479" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND478  ,Set/Clear Pending Bit 478" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND477  ,Set/Clear Pending Bit 477" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476  ,Set/Clear Pending Bit 476" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND475  ,Set/Clear Pending Bit 475" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND474  ,Set/Clear Pending Bit 474" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473  ,Set/Clear Pending Bit 473" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND472  ,Set/Clear Pending Bit 472" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND471  ,Set/Clear Pending Bit 471" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470  ,Set/Clear Pending Bit 470" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND469  ,Set/Clear Pending Bit 469" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND468  ,Set/Clear Pending Bit 468" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467  ,Set/Clear Pending Bit 467" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND466  ,Set/Clear Pending Bit 466" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND465  ,Set/Clear Pending Bit 465" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464  ,Set/Clear Pending Bit 464" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND463  ,Set/Clear Pending Bit 463" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND462  ,Set/Clear Pending Bit 462" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461  ,Set/Clear Pending Bit 461" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND460  ,Set/Clear Pending Bit 460" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND459  ,Set/Clear Pending Bit 459" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458  ,Set/Clear Pending Bit 458" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND457  ,Set/Clear Pending Bit 457" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND456  ,Set/Clear Pending Bit 456" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455  ,Set/Clear Pending Bit 455" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND454  ,Set/Clear Pending Bit 454" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND453  ,Set/Clear Pending Bit 453" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452  ,Set/Clear Pending Bit 452" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND451  ,Set/Clear Pending Bit 451" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND450  ,Set/Clear Pending Bit 450" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449  ,Set/Clear Pending Bit 449" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND448  ,Set/Clear Pending Bit 448" "Not pending,Pending"
else
hgroup.long 0x0238++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x023C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511  ,Set/Clear Pending Bit 511" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND510  ,Set/Clear Pending Bit 510" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND509  ,Set/Clear Pending Bit 509" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508  ,Set/Clear Pending Bit 508" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND507  ,Set/Clear Pending Bit 507" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND506  ,Set/Clear Pending Bit 506" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505  ,Set/Clear Pending Bit 505" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND504  ,Set/Clear Pending Bit 504" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND503  ,Set/Clear Pending Bit 503" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502  ,Set/Clear Pending Bit 502" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND501  ,Set/Clear Pending Bit 501" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND500  ,Set/Clear Pending Bit 500" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499  ,Set/Clear Pending Bit 499" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND498  ,Set/Clear Pending Bit 498" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND497  ,Set/Clear Pending Bit 497" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496  ,Set/Clear Pending Bit 496" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND495  ,Set/Clear Pending Bit 495" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND494  ,Set/Clear Pending Bit 494" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493  ,Set/Clear Pending Bit 493" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND492  ,Set/Clear Pending Bit 492" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND491  ,Set/Clear Pending Bit 491" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490  ,Set/Clear Pending Bit 490" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND489  ,Set/Clear Pending Bit 489" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND488  ,Set/Clear Pending Bit 488" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487  ,Set/Clear Pending Bit 487" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND486  ,Set/Clear Pending Bit 486" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND485  ,Set/Clear Pending Bit 485" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484  ,Set/Clear Pending Bit 484" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND483  ,Set/Clear Pending Bit 483" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND482  ,Set/Clear Pending Bit 482" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481  ,Set/Clear Pending Bit 481" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND480  ,Set/Clear Pending Bit 480" "Not pending,Pending"
else
hgroup.long 0x023C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0240++0x03
line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543  ,Set/Clear Pending Bit 543" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND542  ,Set/Clear Pending Bit 542" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND541  ,Set/Clear Pending Bit 541" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540  ,Set/Clear Pending Bit 540" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND539  ,Set/Clear Pending Bit 539" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND538  ,Set/Clear Pending Bit 538" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537  ,Set/Clear Pending Bit 537" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND536  ,Set/Clear Pending Bit 536" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND535  ,Set/Clear Pending Bit 535" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534  ,Set/Clear Pending Bit 534" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND533  ,Set/Clear Pending Bit 533" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND532  ,Set/Clear Pending Bit 532" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531  ,Set/Clear Pending Bit 531" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND530  ,Set/Clear Pending Bit 530" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND529  ,Set/Clear Pending Bit 529" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528  ,Set/Clear Pending Bit 528" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND527  ,Set/Clear Pending Bit 527" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND526  ,Set/Clear Pending Bit 526" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525  ,Set/Clear Pending Bit 525" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND524  ,Set/Clear Pending Bit 524" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND523  ,Set/Clear Pending Bit 523" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522  ,Set/Clear Pending Bit 522" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND521  ,Set/Clear Pending Bit 521" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND520  ,Set/Clear Pending Bit 520" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519  ,Set/Clear Pending Bit 519" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND518  ,Set/Clear Pending Bit 518" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND517  ,Set/Clear Pending Bit 517" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516  ,Set/Clear Pending Bit 516" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND515  ,Set/Clear Pending Bit 515" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND514  ,Set/Clear Pending Bit 514" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513  ,Set/Clear Pending Bit 513" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND512  ,Set/Clear Pending Bit 512" "Not pending,Pending"
else
hgroup.long 0x0240++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0244++0x03
line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575  ,Set/Clear Pending Bit 575" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND574  ,Set/Clear Pending Bit 574" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND573  ,Set/Clear Pending Bit 573" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572  ,Set/Clear Pending Bit 572" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND571  ,Set/Clear Pending Bit 571" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND570  ,Set/Clear Pending Bit 570" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569  ,Set/Clear Pending Bit 569" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND568  ,Set/Clear Pending Bit 568" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND567  ,Set/Clear Pending Bit 567" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566  ,Set/Clear Pending Bit 566" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND565  ,Set/Clear Pending Bit 565" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND564  ,Set/Clear Pending Bit 564" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563  ,Set/Clear Pending Bit 563" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND562  ,Set/Clear Pending Bit 562" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND561  ,Set/Clear Pending Bit 561" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560  ,Set/Clear Pending Bit 560" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND559  ,Set/Clear Pending Bit 559" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND558  ,Set/Clear Pending Bit 558" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557  ,Set/Clear Pending Bit 557" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND556  ,Set/Clear Pending Bit 556" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND555  ,Set/Clear Pending Bit 555" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554  ,Set/Clear Pending Bit 554" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND553  ,Set/Clear Pending Bit 553" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND552  ,Set/Clear Pending Bit 552" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551  ,Set/Clear Pending Bit 551" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND550  ,Set/Clear Pending Bit 550" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND549  ,Set/Clear Pending Bit 549" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548  ,Set/Clear Pending Bit 548" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND547  ,Set/Clear Pending Bit 547" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND546  ,Set/Clear Pending Bit 546" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545  ,Set/Clear Pending Bit 545" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND544  ,Set/Clear Pending Bit 544" "Not pending,Pending"
else
hgroup.long 0x0244++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0248++0x03
line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607  ,Set/Clear Pending Bit 607" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND606  ,Set/Clear Pending Bit 606" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND605  ,Set/Clear Pending Bit 605" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604  ,Set/Clear Pending Bit 604" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND603  ,Set/Clear Pending Bit 603" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND602  ,Set/Clear Pending Bit 602" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601  ,Set/Clear Pending Bit 601" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND600  ,Set/Clear Pending Bit 600" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND599  ,Set/Clear Pending Bit 599" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598  ,Set/Clear Pending Bit 598" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND597  ,Set/Clear Pending Bit 597" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND596  ,Set/Clear Pending Bit 596" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595  ,Set/Clear Pending Bit 595" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND594  ,Set/Clear Pending Bit 594" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND593  ,Set/Clear Pending Bit 593" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592  ,Set/Clear Pending Bit 592" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND591  ,Set/Clear Pending Bit 591" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND590  ,Set/Clear Pending Bit 590" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589  ,Set/Clear Pending Bit 589" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND588  ,Set/Clear Pending Bit 588" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND587  ,Set/Clear Pending Bit 587" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586  ,Set/Clear Pending Bit 586" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND585  ,Set/Clear Pending Bit 585" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND584  ,Set/Clear Pending Bit 584" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583  ,Set/Clear Pending Bit 583" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND582  ,Set/Clear Pending Bit 582" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND581  ,Set/Clear Pending Bit 581" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580  ,Set/Clear Pending Bit 580" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND579  ,Set/Clear Pending Bit 579" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND578  ,Set/Clear Pending Bit 578" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577  ,Set/Clear Pending Bit 577" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND576  ,Set/Clear Pending Bit 576" "Not pending,Pending"
else
hgroup.long 0x0248++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x024C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639  ,Set/Clear Pending Bit 639" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND638  ,Set/Clear Pending Bit 638" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND637  ,Set/Clear Pending Bit 637" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636  ,Set/Clear Pending Bit 636" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND635  ,Set/Clear Pending Bit 635" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND634  ,Set/Clear Pending Bit 634" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633  ,Set/Clear Pending Bit 633" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND632  ,Set/Clear Pending Bit 632" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND631  ,Set/Clear Pending Bit 631" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630  ,Set/Clear Pending Bit 630" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND629  ,Set/Clear Pending Bit 629" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND628  ,Set/Clear Pending Bit 628" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627  ,Set/Clear Pending Bit 627" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND626  ,Set/Clear Pending Bit 626" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND625  ,Set/Clear Pending Bit 625" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624  ,Set/Clear Pending Bit 624" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND623  ,Set/Clear Pending Bit 623" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND622  ,Set/Clear Pending Bit 622" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621  ,Set/Clear Pending Bit 621" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND620  ,Set/Clear Pending Bit 620" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND619  ,Set/Clear Pending Bit 619" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618  ,Set/Clear Pending Bit 618" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND617  ,Set/Clear Pending Bit 617" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND616  ,Set/Clear Pending Bit 616" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615  ,Set/Clear Pending Bit 615" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND614  ,Set/Clear Pending Bit 614" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND613  ,Set/Clear Pending Bit 613" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612  ,Set/Clear Pending Bit 612" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND611  ,Set/Clear Pending Bit 611" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND610  ,Set/Clear Pending Bit 610" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609  ,Set/Clear Pending Bit 609" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND608  ,Set/Clear Pending Bit 608" "Not pending,Pending"
else
hgroup.long 0x024C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0250++0x03
line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671  ,Set/Clear Pending Bit 671" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND670  ,Set/Clear Pending Bit 670" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND669  ,Set/Clear Pending Bit 669" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668  ,Set/Clear Pending Bit 668" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND667  ,Set/Clear Pending Bit 667" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND666  ,Set/Clear Pending Bit 666" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665  ,Set/Clear Pending Bit 665" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND664  ,Set/Clear Pending Bit 664" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND663  ,Set/Clear Pending Bit 663" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662  ,Set/Clear Pending Bit 662" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND661  ,Set/Clear Pending Bit 661" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND660  ,Set/Clear Pending Bit 660" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659  ,Set/Clear Pending Bit 659" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND658  ,Set/Clear Pending Bit 658" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND657  ,Set/Clear Pending Bit 657" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656  ,Set/Clear Pending Bit 656" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND655  ,Set/Clear Pending Bit 655" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND654  ,Set/Clear Pending Bit 654" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653  ,Set/Clear Pending Bit 653" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND652  ,Set/Clear Pending Bit 652" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND651  ,Set/Clear Pending Bit 651" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650  ,Set/Clear Pending Bit 650" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND649  ,Set/Clear Pending Bit 649" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND648  ,Set/Clear Pending Bit 648" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647  ,Set/Clear Pending Bit 647" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND646  ,Set/Clear Pending Bit 646" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND645  ,Set/Clear Pending Bit 645" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644  ,Set/Clear Pending Bit 644" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND643  ,Set/Clear Pending Bit 643" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND642  ,Set/Clear Pending Bit 642" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641  ,Set/Clear Pending Bit 641" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND640  ,Set/Clear Pending Bit 640" "Not pending,Pending"
else
hgroup.long 0x0250++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0254++0x03
line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703  ,Set/Clear Pending Bit 703" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND702  ,Set/Clear Pending Bit 702" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND701  ,Set/Clear Pending Bit 701" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700  ,Set/Clear Pending Bit 700" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND699  ,Set/Clear Pending Bit 699" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND698  ,Set/Clear Pending Bit 698" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697  ,Set/Clear Pending Bit 697" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND696  ,Set/Clear Pending Bit 696" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND695  ,Set/Clear Pending Bit 695" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694  ,Set/Clear Pending Bit 694" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND693  ,Set/Clear Pending Bit 693" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND692  ,Set/Clear Pending Bit 692" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691  ,Set/Clear Pending Bit 691" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND690  ,Set/Clear Pending Bit 690" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND689  ,Set/Clear Pending Bit 689" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688  ,Set/Clear Pending Bit 688" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND687  ,Set/Clear Pending Bit 687" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND686  ,Set/Clear Pending Bit 686" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685  ,Set/Clear Pending Bit 685" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND684  ,Set/Clear Pending Bit 684" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND683  ,Set/Clear Pending Bit 683" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682  ,Set/Clear Pending Bit 682" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND681  ,Set/Clear Pending Bit 681" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND680  ,Set/Clear Pending Bit 680" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679  ,Set/Clear Pending Bit 679" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND678  ,Set/Clear Pending Bit 678" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND677  ,Set/Clear Pending Bit 677" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676  ,Set/Clear Pending Bit 676" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND675  ,Set/Clear Pending Bit 675" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND674  ,Set/Clear Pending Bit 674" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673  ,Set/Clear Pending Bit 673" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND672  ,Set/Clear Pending Bit 672" "Not pending,Pending"
else
hgroup.long 0x0254++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0258++0x03
line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735  ,Set/Clear Pending Bit 735" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND734  ,Set/Clear Pending Bit 734" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND733  ,Set/Clear Pending Bit 733" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732  ,Set/Clear Pending Bit 732" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND731  ,Set/Clear Pending Bit 731" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND730  ,Set/Clear Pending Bit 730" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729  ,Set/Clear Pending Bit 729" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND728  ,Set/Clear Pending Bit 728" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND727  ,Set/Clear Pending Bit 727" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726  ,Set/Clear Pending Bit 726" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND725  ,Set/Clear Pending Bit 725" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND724  ,Set/Clear Pending Bit 724" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723  ,Set/Clear Pending Bit 723" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND722  ,Set/Clear Pending Bit 722" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND721  ,Set/Clear Pending Bit 721" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720  ,Set/Clear Pending Bit 720" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND719  ,Set/Clear Pending Bit 719" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND718  ,Set/Clear Pending Bit 718" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717  ,Set/Clear Pending Bit 717" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND716  ,Set/Clear Pending Bit 716" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND715  ,Set/Clear Pending Bit 715" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714  ,Set/Clear Pending Bit 714" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND713  ,Set/Clear Pending Bit 713" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND712  ,Set/Clear Pending Bit 712" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711  ,Set/Clear Pending Bit 711" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND710  ,Set/Clear Pending Bit 710" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND709  ,Set/Clear Pending Bit 709" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708  ,Set/Clear Pending Bit 708" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND707  ,Set/Clear Pending Bit 707" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND706  ,Set/Clear Pending Bit 706" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705  ,Set/Clear Pending Bit 705" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND704  ,Set/Clear Pending Bit 704" "Not pending,Pending"
else
hgroup.long 0x0258++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x025C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767  ,Set/Clear Pending Bit 767" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND766  ,Set/Clear Pending Bit 766" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND765  ,Set/Clear Pending Bit 765" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764  ,Set/Clear Pending Bit 764" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND763  ,Set/Clear Pending Bit 763" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND762  ,Set/Clear Pending Bit 762" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761  ,Set/Clear Pending Bit 761" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND760  ,Set/Clear Pending Bit 760" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND759  ,Set/Clear Pending Bit 759" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758  ,Set/Clear Pending Bit 758" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND757  ,Set/Clear Pending Bit 757" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND756  ,Set/Clear Pending Bit 756" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755  ,Set/Clear Pending Bit 755" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND754  ,Set/Clear Pending Bit 754" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND753  ,Set/Clear Pending Bit 753" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752  ,Set/Clear Pending Bit 752" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND751  ,Set/Clear Pending Bit 751" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND750  ,Set/Clear Pending Bit 750" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749  ,Set/Clear Pending Bit 749" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND748  ,Set/Clear Pending Bit 748" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND747  ,Set/Clear Pending Bit 747" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746  ,Set/Clear Pending Bit 746" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND745  ,Set/Clear Pending Bit 745" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND744  ,Set/Clear Pending Bit 744" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743  ,Set/Clear Pending Bit 743" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND742  ,Set/Clear Pending Bit 742" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND741  ,Set/Clear Pending Bit 741" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740  ,Set/Clear Pending Bit 740" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND739  ,Set/Clear Pending Bit 739" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND738  ,Set/Clear Pending Bit 738" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737  ,Set/Clear Pending Bit 737" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND736  ,Set/Clear Pending Bit 736" "Not pending,Pending"
else
hgroup.long 0x025C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0260++0x03
line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799  ,Set/Clear Pending Bit 799" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND798  ,Set/Clear Pending Bit 798" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND797  ,Set/Clear Pending Bit 797" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796  ,Set/Clear Pending Bit 796" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND795  ,Set/Clear Pending Bit 795" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND794  ,Set/Clear Pending Bit 794" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793  ,Set/Clear Pending Bit 793" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND792  ,Set/Clear Pending Bit 792" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND791  ,Set/Clear Pending Bit 791" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790  ,Set/Clear Pending Bit 790" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND789  ,Set/Clear Pending Bit 789" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND788  ,Set/Clear Pending Bit 788" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787  ,Set/Clear Pending Bit 787" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND786  ,Set/Clear Pending Bit 786" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND785  ,Set/Clear Pending Bit 785" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784  ,Set/Clear Pending Bit 784" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND783  ,Set/Clear Pending Bit 783" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND782  ,Set/Clear Pending Bit 782" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781  ,Set/Clear Pending Bit 781" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND780  ,Set/Clear Pending Bit 780" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND779  ,Set/Clear Pending Bit 779" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778  ,Set/Clear Pending Bit 778" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND777  ,Set/Clear Pending Bit 777" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND776  ,Set/Clear Pending Bit 776" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775  ,Set/Clear Pending Bit 775" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND774  ,Set/Clear Pending Bit 774" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND773  ,Set/Clear Pending Bit 773" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772  ,Set/Clear Pending Bit 772" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND771  ,Set/Clear Pending Bit 771" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND770  ,Set/Clear Pending Bit 770" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769  ,Set/Clear Pending Bit 769" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND768  ,Set/Clear Pending Bit 768" "Not pending,Pending"
else
hgroup.long 0x0260++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0264++0x03
line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831  ,Set/Clear Pending Bit 831" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND830  ,Set/Clear Pending Bit 830" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND829  ,Set/Clear Pending Bit 829" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828  ,Set/Clear Pending Bit 828" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND827  ,Set/Clear Pending Bit 827" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND826  ,Set/Clear Pending Bit 826" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825  ,Set/Clear Pending Bit 825" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND824  ,Set/Clear Pending Bit 824" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND823  ,Set/Clear Pending Bit 823" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822  ,Set/Clear Pending Bit 822" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND821  ,Set/Clear Pending Bit 821" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND820  ,Set/Clear Pending Bit 820" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819  ,Set/Clear Pending Bit 819" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND818  ,Set/Clear Pending Bit 818" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND817  ,Set/Clear Pending Bit 817" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816  ,Set/Clear Pending Bit 816" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND815  ,Set/Clear Pending Bit 815" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND814  ,Set/Clear Pending Bit 814" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813  ,Set/Clear Pending Bit 813" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND812  ,Set/Clear Pending Bit 812" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND811  ,Set/Clear Pending Bit 811" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810  ,Set/Clear Pending Bit 810" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND809  ,Set/Clear Pending Bit 809" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND808  ,Set/Clear Pending Bit 808" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807  ,Set/Clear Pending Bit 807" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND806  ,Set/Clear Pending Bit 806" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND805  ,Set/Clear Pending Bit 805" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804  ,Set/Clear Pending Bit 804" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND803  ,Set/Clear Pending Bit 803" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND802  ,Set/Clear Pending Bit 802" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801  ,Set/Clear Pending Bit 801" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND800  ,Set/Clear Pending Bit 800" "Not pending,Pending"
else
hgroup.long 0x0264++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0268++0x03
line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863  ,Set/Clear Pending Bit 863" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND862  ,Set/Clear Pending Bit 862" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND861  ,Set/Clear Pending Bit 861" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860  ,Set/Clear Pending Bit 860" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND859  ,Set/Clear Pending Bit 859" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND858  ,Set/Clear Pending Bit 858" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857  ,Set/Clear Pending Bit 857" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND856  ,Set/Clear Pending Bit 856" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND855  ,Set/Clear Pending Bit 855" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854  ,Set/Clear Pending Bit 854" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND853  ,Set/Clear Pending Bit 853" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND852  ,Set/Clear Pending Bit 852" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851  ,Set/Clear Pending Bit 851" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND850  ,Set/Clear Pending Bit 850" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND849  ,Set/Clear Pending Bit 849" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848  ,Set/Clear Pending Bit 848" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND847  ,Set/Clear Pending Bit 847" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND846  ,Set/Clear Pending Bit 846" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845  ,Set/Clear Pending Bit 845" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND844  ,Set/Clear Pending Bit 844" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND843  ,Set/Clear Pending Bit 843" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842  ,Set/Clear Pending Bit 842" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND841  ,Set/Clear Pending Bit 841" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND840  ,Set/Clear Pending Bit 840" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839  ,Set/Clear Pending Bit 839" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND838  ,Set/Clear Pending Bit 838" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND837  ,Set/Clear Pending Bit 837" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836  ,Set/Clear Pending Bit 836" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND835  ,Set/Clear Pending Bit 835" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND834  ,Set/Clear Pending Bit 834" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833  ,Set/Clear Pending Bit 833" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND832  ,Set/Clear Pending Bit 832" "Not pending,Pending"
else
hgroup.long 0x0268++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x026C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895  ,Set/Clear Pending Bit 895" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND894  ,Set/Clear Pending Bit 894" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND893  ,Set/Clear Pending Bit 893" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892  ,Set/Clear Pending Bit 892" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND891  ,Set/Clear Pending Bit 891" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND890  ,Set/Clear Pending Bit 890" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889  ,Set/Clear Pending Bit 889" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND888  ,Set/Clear Pending Bit 888" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND887  ,Set/Clear Pending Bit 887" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886  ,Set/Clear Pending Bit 886" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND885  ,Set/Clear Pending Bit 885" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND884  ,Set/Clear Pending Bit 884" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883  ,Set/Clear Pending Bit 883" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND882  ,Set/Clear Pending Bit 882" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND881  ,Set/Clear Pending Bit 881" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880  ,Set/Clear Pending Bit 880" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND879  ,Set/Clear Pending Bit 879" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND878  ,Set/Clear Pending Bit 878" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877  ,Set/Clear Pending Bit 877" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND876  ,Set/Clear Pending Bit 876" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND875  ,Set/Clear Pending Bit 875" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874  ,Set/Clear Pending Bit 874" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND873  ,Set/Clear Pending Bit 873" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND872  ,Set/Clear Pending Bit 872" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871  ,Set/Clear Pending Bit 871" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND870  ,Set/Clear Pending Bit 870" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND869  ,Set/Clear Pending Bit 869" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868  ,Set/Clear Pending Bit 868" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND867  ,Set/Clear Pending Bit 867" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND866  ,Set/Clear Pending Bit 866" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865  ,Set/Clear Pending Bit 865" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND864  ,Set/Clear Pending Bit 864" "Not pending,Pending"
else
hgroup.long 0x026C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0270++0x03
line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927  ,Set/Clear Pending Bit 927" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND926  ,Set/Clear Pending Bit 926" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND925  ,Set/Clear Pending Bit 925" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924  ,Set/Clear Pending Bit 924" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND923  ,Set/Clear Pending Bit 923" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND922  ,Set/Clear Pending Bit 922" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921  ,Set/Clear Pending Bit 921" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND920  ,Set/Clear Pending Bit 920" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND919  ,Set/Clear Pending Bit 919" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918  ,Set/Clear Pending Bit 918" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND917  ,Set/Clear Pending Bit 917" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND916  ,Set/Clear Pending Bit 916" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915  ,Set/Clear Pending Bit 915" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND914  ,Set/Clear Pending Bit 914" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND913  ,Set/Clear Pending Bit 913" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912  ,Set/Clear Pending Bit 912" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND911  ,Set/Clear Pending Bit 911" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND910  ,Set/Clear Pending Bit 910" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909  ,Set/Clear Pending Bit 909" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND908  ,Set/Clear Pending Bit 908" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND907  ,Set/Clear Pending Bit 907" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906  ,Set/Clear Pending Bit 906" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND905  ,Set/Clear Pending Bit 905" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND904  ,Set/Clear Pending Bit 904" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903  ,Set/Clear Pending Bit 903" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND902  ,Set/Clear Pending Bit 902" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND901  ,Set/Clear Pending Bit 901" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900  ,Set/Clear Pending Bit 900" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND899  ,Set/Clear Pending Bit 899" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND898  ,Set/Clear Pending Bit 898" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897  ,Set/Clear Pending Bit 897" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND896  ,Set/Clear Pending Bit 896" "Not pending,Pending"
else
hgroup.long 0x0270++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0274++0x03
line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959  ,Set/Clear Pending Bit 959" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND958  ,Set/Clear Pending Bit 958" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND957  ,Set/Clear Pending Bit 957" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956  ,Set/Clear Pending Bit 956" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND955  ,Set/Clear Pending Bit 955" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND954  ,Set/Clear Pending Bit 954" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953  ,Set/Clear Pending Bit 953" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND952  ,Set/Clear Pending Bit 952" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND951  ,Set/Clear Pending Bit 951" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950  ,Set/Clear Pending Bit 950" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND949  ,Set/Clear Pending Bit 949" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND948  ,Set/Clear Pending Bit 948" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947  ,Set/Clear Pending Bit 947" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND946  ,Set/Clear Pending Bit 946" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND945  ,Set/Clear Pending Bit 945" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944  ,Set/Clear Pending Bit 944" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND943  ,Set/Clear Pending Bit 943" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND942  ,Set/Clear Pending Bit 942" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941  ,Set/Clear Pending Bit 941" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND940  ,Set/Clear Pending Bit 940" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND939  ,Set/Clear Pending Bit 939" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938  ,Set/Clear Pending Bit 938" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND937  ,Set/Clear Pending Bit 937" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND936  ,Set/Clear Pending Bit 936" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935  ,Set/Clear Pending Bit 935" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND934  ,Set/Clear Pending Bit 934" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND933  ,Set/Clear Pending Bit 933" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932  ,Set/Clear Pending Bit 932" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND931  ,Set/Clear Pending Bit 931" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND930  ,Set/Clear Pending Bit 930" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929  ,Set/Clear Pending Bit 929" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND928  ,Set/Clear Pending Bit 928" "Not pending,Pending"
else
hgroup.long 0x0274++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0278++0x03
line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991  ,Set/Clear Pending Bit 991" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND990  ,Set/Clear Pending Bit 990" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND989  ,Set/Clear Pending Bit 989" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988  ,Set/Clear Pending Bit 988" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND987  ,Set/Clear Pending Bit 987" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND986  ,Set/Clear Pending Bit 986" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985  ,Set/Clear Pending Bit 985" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND984  ,Set/Clear Pending Bit 984" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND983  ,Set/Clear Pending Bit 983" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982  ,Set/Clear Pending Bit 982" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND981  ,Set/Clear Pending Bit 981" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND980  ,Set/Clear Pending Bit 980" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979  ,Set/Clear Pending Bit 979" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND978  ,Set/Clear Pending Bit 978" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND977  ,Set/Clear Pending Bit 977" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976  ,Set/Clear Pending Bit 976" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND975  ,Set/Clear Pending Bit 975" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND974  ,Set/Clear Pending Bit 974" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973  ,Set/Clear Pending Bit 973" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND972  ,Set/Clear Pending Bit 972" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND971  ,Set/Clear Pending Bit 971" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970  ,Set/Clear Pending Bit 970" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND969  ,Set/Clear Pending Bit 969" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND968  ,Set/Clear Pending Bit 968" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967  ,Set/Clear Pending Bit 967" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND966  ,Set/Clear Pending Bit 966" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND965  ,Set/Clear Pending Bit 965" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964  ,Set/Clear Pending Bit 964" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND963  ,Set/Clear Pending Bit 963" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND962  ,Set/Clear Pending Bit 962" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961  ,Set/Clear Pending Bit 961" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND960  ,Set/Clear Pending Bit 960" "Not pending,Pending"
else
hgroup.long 0x0278++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
endif
tree.end
width 24.
tree "Set/Clear Active Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0300++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0300++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31  ,Set/Clear Active Bit 31" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE30  ,Set/Clear Active Bit 30" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE29  ,Set/Clear Active Bit 29" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28  ,Set/Clear Active Bit 28" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE27  ,Set/Clear Active Bit 27" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE26  ,Set/Clear Active Bit 26" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25  ,Set/Clear Active Bit 25" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE24  ,Set/Clear Active Bit 24" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE23  ,Set/Clear Active Bit 23" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22  ,Set/Clear Active Bit 22" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE21  ,Set/Clear Active Bit 21" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE20  ,Set/Clear Active Bit 20" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19  ,Set/Clear Active Bit 19" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE18  ,Set/Clear Active Bit 18" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE17  ,Set/Clear Active Bit 17" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16  ,Set/Clear Active Bit 16" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE15  ,Set/Clear Active Bit 15" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE14  ,Set/Clear Active Bit 14" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13  ,Set/Clear Active Bit 13" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE12  ,Set/Clear Active Bit 12" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE11  ,Set/Clear Active Bit 11" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10  ,Set/Clear Active Bit 10" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE9   ,Set/Clear Active Bit 9" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE8   ,Set/Clear Active Bit 8" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7   ,Set/Clear Active Bit 7" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE6   ,Set/Clear Active Bit 6" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE5   ,Set/Clear Active Bit 5" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4   ,Set/Clear Active Bit 4" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE3   ,Set/Clear Active Bit 3" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE2   ,Set/Clear Active Bit 2" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1   ,Set/Clear Active Bit 1" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE0   ,Set/Clear Active Bit 0" "Not active,Active"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0304++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63  ,Set/Clear Active Bit 63" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE62  ,Set/Clear Active Bit 62" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE61  ,Set/Clear Active Bit 61" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60  ,Set/Clear Active Bit 60" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE59  ,Set/Clear Active Bit 59" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE58  ,Set/Clear Active Bit 58" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57  ,Set/Clear Active Bit 57" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE56  ,Set/Clear Active Bit 56" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE55  ,Set/Clear Active Bit 55" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54  ,Set/Clear Active Bit 54" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE53  ,Set/Clear Active Bit 53" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE52  ,Set/Clear Active Bit 52" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51  ,Set/Clear Active Bit 51" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE50  ,Set/Clear Active Bit 50" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE49  ,Set/Clear Active Bit 49" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48  ,Set/Clear Active Bit 48" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE47  ,Set/Clear Active Bit 47" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE46  ,Set/Clear Active Bit 46" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45  ,Set/Clear Active Bit 45" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE44  ,Set/Clear Active Bit 44" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE43  ,Set/Clear Active Bit 43" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42  ,Set/Clear Active Bit 42" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE41  ,Set/Clear Active Bit 41" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE40  ,Set/Clear Active Bit 40" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39  ,Set/Clear Active Bit 39" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE38  ,Set/Clear Active Bit 38" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE37  ,Set/Clear Active Bit 37" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36  ,Set/Clear Active Bit 36" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE35  ,Set/Clear Active Bit 35" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE34  ,Set/Clear Active Bit 34" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33  ,Set/Clear Active Bit 33" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE32  ,Set/Clear Active Bit 32" "Not active,Active"
else
hgroup.long 0x0304++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0308++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95  ,Set/Clear Active Bit 95" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE94  ,Set/Clear Active Bit 94" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE93  ,Set/Clear Active Bit 93" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92  ,Set/Clear Active Bit 92" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE91  ,Set/Clear Active Bit 91" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE90  ,Set/Clear Active Bit 90" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89  ,Set/Clear Active Bit 89" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE88  ,Set/Clear Active Bit 88" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE87  ,Set/Clear Active Bit 87" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86  ,Set/Clear Active Bit 86" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE85  ,Set/Clear Active Bit 85" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE84  ,Set/Clear Active Bit 84" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83  ,Set/Clear Active Bit 83" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE82  ,Set/Clear Active Bit 82" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE81  ,Set/Clear Active Bit 81" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80  ,Set/Clear Active Bit 80" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE79  ,Set/Clear Active Bit 79" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE78  ,Set/Clear Active Bit 78" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77  ,Set/Clear Active Bit 77" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE76  ,Set/Clear Active Bit 76" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE75  ,Set/Clear Active Bit 75" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74  ,Set/Clear Active Bit 74" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE73  ,Set/Clear Active Bit 73" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE72  ,Set/Clear Active Bit 72" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71  ,Set/Clear Active Bit 71" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE70  ,Set/Clear Active Bit 70" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE69  ,Set/Clear Active Bit 69" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68  ,Set/Clear Active Bit 68" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE67  ,Set/Clear Active Bit 67" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE66  ,Set/Clear Active Bit 66" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65  ,Set/Clear Active Bit 65" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE64  ,Set/Clear Active Bit 64" "Not active,Active"
else
hgroup.long 0x0308++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x030C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE99  ,Set/Clear Active Bit 99" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE98  ,Set/Clear Active Bit 98" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97  ,Set/Clear Active Bit 97" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE96  ,Set/Clear Active Bit 96" "Not active,Active"
else
hgroup.long 0x030C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0310++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active"
else
hgroup.long 0x0310++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0314++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active"
else
hgroup.long 0x0314++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0318++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active"
else
hgroup.long 0x0318++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x031C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active"
else
hgroup.long 0x031C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0320++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active"
else
hgroup.long 0x0320++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0324++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active"
else
hgroup.long 0x0324++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0328++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active"
else
hgroup.long 0x0328++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x032C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active"
else
hgroup.long 0x032C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0330++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active"
else
hgroup.long 0x0330++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0334++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active"
else
hgroup.long 0x0334++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0338++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active"
else
hgroup.long 0x0338++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x033C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active"
else
hgroup.long 0x033C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0340++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active"
else
hgroup.long 0x0340++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0344++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active"
else
hgroup.long 0x0344++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0348++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active"
else
hgroup.long 0x0348++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x034C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active"
else
hgroup.long 0x034C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0350++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active"
else
hgroup.long 0x0350++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0354++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active"
else
hgroup.long 0x0354++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0358++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active"
else
hgroup.long 0x0358++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x035C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active"
else
hgroup.long 0x035C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0360++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active"
else
hgroup.long 0x0360++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0364++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active"
else
hgroup.long 0x0364++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0368++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active"
else
hgroup.long 0x0368++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x036C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active"
else
hgroup.long 0x036C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0370++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active"
else
hgroup.long 0x0370++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0374++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active"
else
hgroup.long 0x0374++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0378++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active"
else
hgroup.long 0x0378++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
endif
tree.end
width 20.
tree "Priority Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x400++0x03
hide.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
hgroup.long 0x404++0x03
hide.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
hgroup.long 0x408++0x03
hide.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
hgroup.long 0x40C++0x03
hide.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
hgroup.long 0x410++0x03
hide.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
hgroup.long 0x414++0x03
hide.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
hgroup.long 0x418++0x03
hide.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
hgroup.long 0x41C++0x03
hide.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
else
group.long 0x400++0x03
line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
hexmask.long.byte 0x00 24.--31. 1. " INTID3    ,Interrupt ID3    Priority/Priority Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID2    ,Interrupt ID2     Priority/Priority Byte Offset 2   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID1    ,Interrupt ID1    Priority/Priority Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID0    ,Interrupt ID0     Priority/Priority Byte Offset 0   "
group.long 0x404++0x03
line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " INTID7    ,Interrupt ID7    Priority/Priority Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID6    ,Interrupt ID6     Priority/Priority Byte Offset 6   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID5    ,Interrupt ID5    Priority/Priority Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID4    ,Interrupt ID4     Priority/Priority Byte Offset 4   "
group.long 0x408++0x03
line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
hexmask.long.byte 0x00 24.--31. 1. " INTID11   ,Interrupt ID11   Priority/Priority Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID10   ,Interrupt ID10    Priority/Priority Byte Offset 10  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID9    ,Interrupt ID9    Priority/Priority Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID8    ,Interrupt ID8     Priority/Priority Byte Offset 8   "
group.long 0x40C++0x03
line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
hexmask.long.byte 0x00 24.--31. 1. " INTID15   ,Interrupt ID15   Priority/Priority Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID14   ,Interrupt ID14    Priority/Priority Byte Offset 14  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID13   ,Interrupt ID13   Priority/Priority Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID12   ,Interrupt ID12    Priority/Priority Byte Offset 12  "
group.long 0x410++0x03
line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
hexmask.long.byte 0x00 24.--31. 1. " INTID19   ,Interrupt ID19   Priority/Priority Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID18   ,Interrupt ID18    Priority/Priority Byte Offset 18  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID17   ,Interrupt ID17   Priority/Priority Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID16   ,Interrupt ID16    Priority/Priority Byte Offset 16  "
group.long 0x414++0x03
line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
hexmask.long.byte 0x00 24.--31. 1. " INTID23   ,Interrupt ID23   Priority/Priority Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID22   ,Interrupt ID22    Priority/Priority Byte Offset 22  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID21   ,Interrupt ID21   Priority/Priority Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID20   ,Interrupt ID20    Priority/Priority Byte Offset 20  "
group.long 0x418++0x03
line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
hexmask.long.byte 0x00 24.--31. 1. " INTID27   ,Interrupt ID27   Priority/Priority Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID26   ,Interrupt ID26    Priority/Priority Byte Offset 26  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID25   ,Interrupt ID25   Priority/Priority Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID24   ,Interrupt ID24    Priority/Priority Byte Offset 24  "
group.long 0x41C++0x03
line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
hexmask.long.byte 0x00 24.--31. 1. " INTID31   ,Interrupt ID31   Priority/Priority Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID30   ,Interrupt ID30    Priority/Priority Byte Offset 30  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID29   ,Interrupt ID29   Priority/Priority Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID28   ,Interrupt ID28    Priority/Priority Byte Offset 28  "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x420++0x03
line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
hexmask.long.byte 0x00 24.--31. 1. " INTID35   ,Interrupt ID35   Priority/Priority Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID34   ,Interrupt ID34    Priority/Priority Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID33   ,Interrupt ID33   Priority/Priority Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID32   ,Interrupt ID32    Priority/Priority Byte Offset 32  "
group.long 0x424++0x03
line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
hexmask.long.byte 0x00 24.--31. 1. " INTID39   ,Interrupt ID39   Priority/Priority Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID38   ,Interrupt ID38    Priority/Priority Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID37   ,Interrupt ID37   Priority/Priority Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID36   ,Interrupt ID36    Priority/Priority Byte Offset 36  "
group.long 0x428++0x03
line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
hexmask.long.byte 0x00 24.--31. 1. " INTID43   ,Interrupt ID43   Priority/Priority Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID42   ,Interrupt ID42    Priority/Priority Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID41   ,Interrupt ID41   Priority/Priority Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID40   ,Interrupt ID40    Priority/Priority Byte Offset 40  "
group.long 0x42C++0x03
line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
hexmask.long.byte 0x00 24.--31. 1. " INTID47   ,Interrupt ID47   Priority/Priority Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID46   ,Interrupt ID46    Priority/Priority Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID45   ,Interrupt ID45   Priority/Priority Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID44   ,Interrupt ID44    Priority/Priority Byte Offset 44  "
group.long 0x430++0x03
line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
hexmask.long.byte 0x00 24.--31. 1. " INTID51   ,Interrupt ID51   Priority/Priority Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID50   ,Interrupt ID50    Priority/Priority Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID49   ,Interrupt ID49   Priority/Priority Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID48   ,Interrupt ID48    Priority/Priority Byte Offset 48  "
group.long 0x434++0x03
line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
hexmask.long.byte 0x00 24.--31. 1. " INTID55   ,Interrupt ID55   Priority/Priority Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID54   ,Interrupt ID54    Priority/Priority Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID53   ,Interrupt ID53   Priority/Priority Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID52   ,Interrupt ID52    Priority/Priority Byte Offset 52  "
group.long 0x438++0x03
line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
hexmask.long.byte 0x00 24.--31. 1. " INTID59   ,Interrupt ID59   Priority/Priority Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID58   ,Interrupt ID58    Priority/Priority Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID57   ,Interrupt ID57   Priority/Priority Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID56   ,Interrupt ID56    Priority/Priority Byte Offset 56  "
group.long 0x43C++0x03
line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
hexmask.long.byte 0x00 24.--31. 1. " INTID63   ,Interrupt ID63   Priority/Priority Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID62   ,Interrupt ID62    Priority/Priority Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID61   ,Interrupt ID61   Priority/Priority Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID60   ,Interrupt ID60    Priority/Priority Byte Offset 60  "
else
hgroup.long 0x420++0x03
hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
hgroup.long 0x424++0x03
hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
hgroup.long 0x428++0x03
hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
hgroup.long 0x42C++0x03
hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
hgroup.long 0x430++0x03
hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
hgroup.long 0x434++0x03
hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
hgroup.long 0x438++0x03
hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
hgroup.long 0x43C++0x03
hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x440++0x03
line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
hexmask.long.byte 0x00 24.--31. 1. " INTID67   ,Interrupt ID67   Priority/Priority Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID66   ,Interrupt ID66    Priority/Priority Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID65   ,Interrupt ID65   Priority/Priority Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID64   ,Interrupt ID64    Priority/Priority Byte Offset 64  "
group.long 0x444++0x03
line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
hexmask.long.byte 0x00 24.--31. 1. " INTID71   ,Interrupt ID71   Priority/Priority Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID70   ,Interrupt ID70    Priority/Priority Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID69   ,Interrupt ID69   Priority/Priority Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID68   ,Interrupt ID68    Priority/Priority Byte Offset 68  "
group.long 0x448++0x03
line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
hexmask.long.byte 0x00 24.--31. 1. " INTID75   ,Interrupt ID75   Priority/Priority Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID74   ,Interrupt ID74    Priority/Priority Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID73   ,Interrupt ID73   Priority/Priority Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID72   ,Interrupt ID72    Priority/Priority Byte Offset 72  "
group.long 0x44C++0x03
line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
hexmask.long.byte 0x00 24.--31. 1. " INTID79   ,Interrupt ID79   Priority/Priority Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID78   ,Interrupt ID78    Priority/Priority Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID77   ,Interrupt ID77   Priority/Priority Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID76   ,Interrupt ID76    Priority/Priority Byte Offset 76  "
group.long 0x450++0x03
line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
hexmask.long.byte 0x00 24.--31. 1. " INTID83   ,Interrupt ID83   Priority/Priority Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID82   ,Interrupt ID82    Priority/Priority Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID81   ,Interrupt ID81   Priority/Priority Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID80   ,Interrupt ID80    Priority/Priority Byte Offset 80  "
group.long 0x454++0x03
line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
hexmask.long.byte 0x00 24.--31. 1. " INTID87   ,Interrupt ID87   Priority/Priority Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID86   ,Interrupt ID86    Priority/Priority Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID85   ,Interrupt ID85   Priority/Priority Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID84   ,Interrupt ID84    Priority/Priority Byte Offset 84  "
group.long 0x458++0x03
line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
hexmask.long.byte 0x00 24.--31. 1. " INTID91   ,Interrupt ID91   Priority/Priority Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID90   ,Interrupt ID90    Priority/Priority Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID89   ,Interrupt ID89   Priority/Priority Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID88   ,Interrupt ID88    Priority/Priority Byte Offset 88  "
group.long 0x45C++0x03
line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
hexmask.long.byte 0x00 24.--31. 1. " INTID95   ,Interrupt ID95   Priority/Priority Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID94   ,Interrupt ID94    Priority/Priority Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID93   ,Interrupt ID93   Priority/Priority Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID92   ,Interrupt ID92    Priority/Priority Byte Offset 92  "
else
hgroup.long 0x440++0x03
hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
hgroup.long 0x444++0x03
hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
hgroup.long 0x448++0x03
hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
hgroup.long 0x44C++0x03
hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
hgroup.long 0x450++0x03
hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
hgroup.long 0x454++0x03
hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
hgroup.long 0x458++0x03
hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
hgroup.long 0x45C++0x03
hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x460++0x03
line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
hexmask.long.byte 0x00 24.--31. 1. " INTID99   ,Interrupt ID99   Priority/Priority Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID98   ,Interrupt ID98    Priority/Priority Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID97   ,Interrupt ID97   Priority/Priority Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID96   ,Interrupt ID96    Priority/Priority Byte Offset 96  "
group.long 0x464++0x03
line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
hexmask.long.byte 0x00 24.--31. 1. " INTID103  ,Interrupt ID103  Priority/Priority Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID102  ,Interrupt ID102   Priority/Priority Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID101  ,Interrupt ID101  Priority/Priority Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID100  ,Interrupt ID100   Priority/Priority Byte Offset 100 "
group.long 0x468++0x03
line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
hexmask.long.byte 0x00 24.--31. 1. " INTID107  ,Interrupt ID107  Priority/Priority Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID106  ,Interrupt ID106   Priority/Priority Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID105  ,Interrupt ID105  Priority/Priority Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID104  ,Interrupt ID104   Priority/Priority Byte Offset 104 "
group.long 0x46C++0x03
line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
hexmask.long.byte 0x00 24.--31. 1. " INTID111  ,Interrupt ID111  Priority/Priority Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID110  ,Interrupt ID110   Priority/Priority Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID109  ,Interrupt ID109  Priority/Priority Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID108  ,Interrupt ID108   Priority/Priority Byte Offset 108 "
group.long 0x470++0x03
line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
hexmask.long.byte 0x00 24.--31. 1. " INTID115  ,Interrupt ID115  Priority/Priority Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID114  ,Interrupt ID114   Priority/Priority Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID113  ,Interrupt ID113  Priority/Priority Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID112  ,Interrupt ID112   Priority/Priority Byte Offset 112 "
group.long 0x474++0x03
line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
hexmask.long.byte 0x00 24.--31. 1. " INTID119  ,Interrupt ID119  Priority/Priority Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID118  ,Interrupt ID118   Priority/Priority Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID117  ,Interrupt ID117  Priority/Priority Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID116  ,Interrupt ID116   Priority/Priority Byte Offset 116 "
group.long 0x478++0x03
line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
hexmask.long.byte 0x00 24.--31. 1. " INTID123  ,Interrupt ID123  Priority/Priority Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID122  ,Interrupt ID122   Priority/Priority Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID121  ,Interrupt ID121  Priority/Priority Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID120  ,Interrupt ID120   Priority/Priority Byte Offset 120 "
group.long 0x47C++0x03
line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
hexmask.long.byte 0x00 24.--31. 1. " INTID127  ,Interrupt ID127  Priority/Priority Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID126  ,Interrupt ID126   Priority/Priority Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID125  ,Interrupt ID125  Priority/Priority Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID124  ,Interrupt ID124   Priority/Priority Byte Offset 124 "
else
hgroup.long 0x460++0x03
hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
hgroup.long 0x464++0x03
hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
hgroup.long 0x468++0x03
hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
hgroup.long 0x46C++0x03
hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
hgroup.long 0x470++0x03
hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
hgroup.long 0x474++0x03
hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
hgroup.long 0x478++0x03
hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
hgroup.long 0x47C++0x03
hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x480++0x03
line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
hexmask.long.byte 0x00 24.--31. 1. " INTID131  ,Interrupt ID131  Priority/Priority Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID130  ,Interrupt ID130   Priority/Priority Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID129  ,Interrupt ID129  Priority/Priority Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID128  ,Interrupt ID128   Priority/Priority Byte Offset 128 "
group.long 0x484++0x03
line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
hexmask.long.byte 0x00 24.--31. 1. " INTID135  ,Interrupt ID135  Priority/Priority Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID134  ,Interrupt ID134   Priority/Priority Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID133  ,Interrupt ID133  Priority/Priority Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID132  ,Interrupt ID132   Priority/Priority Byte Offset 132 "
group.long 0x488++0x03
line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
hexmask.long.byte 0x00 24.--31. 1. " INTID139  ,Interrupt ID139  Priority/Priority Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID138  ,Interrupt ID138   Priority/Priority Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID137  ,Interrupt ID137  Priority/Priority Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID136  ,Interrupt ID136   Priority/Priority Byte Offset 136 "
group.long 0x48C++0x03
line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
hexmask.long.byte 0x00 24.--31. 1. " INTID143  ,Interrupt ID143  Priority/Priority Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID142  ,Interrupt ID142   Priority/Priority Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID141  ,Interrupt ID141  Priority/Priority Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID140  ,Interrupt ID140   Priority/Priority Byte Offset 140 "
group.long 0x490++0x03
line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
hexmask.long.byte 0x00 24.--31. 1. " INTID147  ,Interrupt ID147  Priority/Priority Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID146  ,Interrupt ID146   Priority/Priority Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID145  ,Interrupt ID145  Priority/Priority Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID144  ,Interrupt ID144   Priority/Priority Byte Offset 144 "
group.long 0x494++0x03
line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
hexmask.long.byte 0x00 24.--31. 1. " INTID151  ,Interrupt ID151  Priority/Priority Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID150  ,Interrupt ID150   Priority/Priority Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID149  ,Interrupt ID149  Priority/Priority Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID148  ,Interrupt ID148   Priority/Priority Byte Offset 148 "
group.long 0x498++0x03
line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
hexmask.long.byte 0x00 24.--31. 1. " INTID155  ,Interrupt ID155  Priority/Priority Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID154  ,Interrupt ID154   Priority/Priority Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID153  ,Interrupt ID153  Priority/Priority Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID152  ,Interrupt ID152   Priority/Priority Byte Offset 152 "
group.long 0x49C++0x03
line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
hexmask.long.byte 0x00 24.--31. 1. " INTID159  ,Interrupt ID159  Priority/Priority Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID158  ,Interrupt ID158   Priority/Priority Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID157  ,Interrupt ID157  Priority/Priority Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID156  ,Interrupt ID156   Priority/Priority Byte Offset 156 "
else
hgroup.long 0x480++0x03
hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
hgroup.long 0x484++0x03
hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
hgroup.long 0x488++0x03
hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
hgroup.long 0x48C++0x03
hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
hgroup.long 0x490++0x03
hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
hgroup.long 0x494++0x03
hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
hgroup.long 0x498++0x03
hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
hgroup.long 0x49C++0x03
hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x4A0++0x03
line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
hexmask.long.byte 0x00 24.--31. 1. " INTID163  ,Interrupt ID163  Priority/Priority Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID162  ,Interrupt ID162   Priority/Priority Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID161  ,Interrupt ID161  Priority/Priority Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID160  ,Interrupt ID160   Priority/Priority Byte Offset 160 "
group.long 0x4A4++0x03
line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
hexmask.long.byte 0x00 24.--31. 1. " INTID167  ,Interrupt ID167  Priority/Priority Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID166  ,Interrupt ID166   Priority/Priority Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID165  ,Interrupt ID165  Priority/Priority Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID164  ,Interrupt ID164   Priority/Priority Byte Offset 164 "
group.long 0x4A8++0x03
line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
hexmask.long.byte 0x00 24.--31. 1. " INTID171  ,Interrupt ID171  Priority/Priority Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID170  ,Interrupt ID170   Priority/Priority Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID169  ,Interrupt ID169  Priority/Priority Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID168  ,Interrupt ID168   Priority/Priority Byte Offset 168 "
group.long 0x4AC++0x03
line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
hexmask.long.byte 0x00 24.--31. 1. " INTID175  ,Interrupt ID175  Priority/Priority Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID174  ,Interrupt ID174   Priority/Priority Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID173  ,Interrupt ID173  Priority/Priority Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID172  ,Interrupt ID172   Priority/Priority Byte Offset 172 "
group.long 0x4B0++0x03
line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
hexmask.long.byte 0x00 24.--31. 1. " INTID179  ,Interrupt ID179  Priority/Priority Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID178  ,Interrupt ID178   Priority/Priority Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID177  ,Interrupt ID177  Priority/Priority Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID176  ,Interrupt ID176   Priority/Priority Byte Offset 176 "
group.long 0x4B4++0x03
line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
hexmask.long.byte 0x00 24.--31. 1. " INTID183  ,Interrupt ID183  Priority/Priority Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID182  ,Interrupt ID182   Priority/Priority Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID181  ,Interrupt ID181  Priority/Priority Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID180  ,Interrupt ID180   Priority/Priority Byte Offset 180 "
group.long 0x4B8++0x03
line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
hexmask.long.byte 0x00 24.--31. 1. " INTID187  ,Interrupt ID187  Priority/Priority Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID186  ,Interrupt ID186   Priority/Priority Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID185  ,Interrupt ID185  Priority/Priority Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID184  ,Interrupt ID184   Priority/Priority Byte Offset 184 "
group.long 0x4BC++0x03
line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
hexmask.long.byte 0x00 24.--31. 1. " INTID191  ,Interrupt ID191  Priority/Priority Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID190  ,Interrupt ID190   Priority/Priority Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID189  ,Interrupt ID189  Priority/Priority Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID188  ,Interrupt ID188   Priority/Priority Byte Offset 188 "
else
hgroup.long 0x4A0++0x03
hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
hgroup.long 0x4A4++0x03
hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
hgroup.long 0x4A8++0x03
hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
hgroup.long 0x4AC++0x03
hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
hgroup.long 0x4B0++0x03
hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
hgroup.long 0x4B4++0x03
hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
hgroup.long 0x4B8++0x03
hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
hgroup.long 0x4BC++0x03
hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x4C0++0x03
line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
hexmask.long.byte 0x00 24.--31. 1. " INTID195  ,Interrupt ID195  Priority/Priority Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID194  ,Interrupt ID194   Priority/Priority Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID193  ,Interrupt ID193  Priority/Priority Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID192  ,Interrupt ID192   Priority/Priority Byte Offset 192 "
group.long 0x4C4++0x03
line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
hexmask.long.byte 0x00 24.--31. 1. " INTID199  ,Interrupt ID199  Priority/Priority Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID198  ,Interrupt ID198   Priority/Priority Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID197  ,Interrupt ID197  Priority/Priority Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID196  ,Interrupt ID196   Priority/Priority Byte Offset 196 "
group.long 0x4C8++0x03
line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
hexmask.long.byte 0x00 24.--31. 1. " INTID203  ,Interrupt ID203  Priority/Priority Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID202  ,Interrupt ID202   Priority/Priority Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID201  ,Interrupt ID201  Priority/Priority Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID200  ,Interrupt ID200   Priority/Priority Byte Offset 200 "
group.long 0x4CC++0x03
line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
hexmask.long.byte 0x00 24.--31. 1. " INTID207  ,Interrupt ID207  Priority/Priority Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID206  ,Interrupt ID206   Priority/Priority Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID205  ,Interrupt ID205  Priority/Priority Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID204  ,Interrupt ID204   Priority/Priority Byte Offset 204 "
group.long 0x4D0++0x03
line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
hexmask.long.byte 0x00 24.--31. 1. " INTID211  ,Interrupt ID211  Priority/Priority Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID210  ,Interrupt ID210   Priority/Priority Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID209  ,Interrupt ID209  Priority/Priority Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID208  ,Interrupt ID208   Priority/Priority Byte Offset 208 "
group.long 0x4D4++0x03
line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
hexmask.long.byte 0x00 24.--31. 1. " INTID215  ,Interrupt ID215  Priority/Priority Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID214  ,Interrupt ID214   Priority/Priority Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID213  ,Interrupt ID213  Priority/Priority Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID212  ,Interrupt ID212   Priority/Priority Byte Offset 212 "
group.long 0x4D8++0x03
line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
hexmask.long.byte 0x00 24.--31. 1. " INTID219  ,Interrupt ID219  Priority/Priority Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID218  ,Interrupt ID218   Priority/Priority Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID217  ,Interrupt ID217  Priority/Priority Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID216  ,Interrupt ID216   Priority/Priority Byte Offset 216 "
group.long 0x4DC++0x03
line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
hexmask.long.byte 0x00 24.--31. 1. " INTID223  ,Interrupt ID223  Priority/Priority Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID222  ,Interrupt ID222   Priority/Priority Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID221  ,Interrupt ID221  Priority/Priority Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID220  ,Interrupt ID220   Priority/Priority Byte Offset 220 "
else
hgroup.long 0x4C0++0x03
hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
hgroup.long 0x4C4++0x03
hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
hgroup.long 0x4C8++0x03
hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
hgroup.long 0x4CC++0x03
hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
hgroup.long 0x4D0++0x03
hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
hgroup.long 0x4D4++0x03
hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
hgroup.long 0x4D8++0x03
hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
hgroup.long 0x4DC++0x03
hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x4E0++0x03
line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
hexmask.long.byte 0x00 24.--31. 1. " INTID227  ,Interrupt ID227  Priority/Priority Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID226  ,Interrupt ID226   Priority/Priority Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID225  ,Interrupt ID225  Priority/Priority Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID224  ,Interrupt ID224   Priority/Priority Byte Offset 224 "
group.long 0x4E4++0x03
line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
hexmask.long.byte 0x00 24.--31. 1. " INTID231  ,Interrupt ID231  Priority/Priority Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID230  ,Interrupt ID230   Priority/Priority Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID229  ,Interrupt ID229  Priority/Priority Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID228  ,Interrupt ID228   Priority/Priority Byte Offset 228 "
group.long 0x4E8++0x03
line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
hexmask.long.byte 0x00 24.--31. 1. " INTID235  ,Interrupt ID235  Priority/Priority Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID234  ,Interrupt ID234   Priority/Priority Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID233  ,Interrupt ID233  Priority/Priority Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID232  ,Interrupt ID232   Priority/Priority Byte Offset 232 "
group.long 0x4EC++0x03
line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
hexmask.long.byte 0x00 24.--31. 1. " INTID239  ,Interrupt ID239  Priority/Priority Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID238  ,Interrupt ID238   Priority/Priority Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID237  ,Interrupt ID237  Priority/Priority Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID236  ,Interrupt ID236   Priority/Priority Byte Offset 236 "
group.long 0x4F0++0x03
line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
hexmask.long.byte 0x00 24.--31. 1. " INTID243  ,Interrupt ID243  Priority/Priority Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID242  ,Interrupt ID242   Priority/Priority Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID241  ,Interrupt ID241  Priority/Priority Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID240  ,Interrupt ID240   Priority/Priority Byte Offset 240 "
group.long 0x4F4++0x03
line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
hexmask.long.byte 0x00 24.--31. 1. " INTID247  ,Interrupt ID247  Priority/Priority Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID246  ,Interrupt ID246   Priority/Priority Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID245  ,Interrupt ID245  Priority/Priority Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID244  ,Interrupt ID244   Priority/Priority Byte Offset 244 "
group.long 0x4F8++0x03
line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
hexmask.long.byte 0x00 24.--31. 1. " INTID251  ,Interrupt ID251  Priority/Priority Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID250  ,Interrupt ID250   Priority/Priority Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID249  ,Interrupt ID249  Priority/Priority Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID248  ,Interrupt ID248   Priority/Priority Byte Offset 248 "
group.long 0x4FC++0x03
line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
hexmask.long.byte 0x00 24.--31. 1. " INTID255  ,Interrupt ID255  Priority/Priority Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID254  ,Interrupt ID254   Priority/Priority Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID253  ,Interrupt ID253  Priority/Priority Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID252  ,Interrupt ID252   Priority/Priority Byte Offset 252 "
else
hgroup.long 0x4E0++0x03
hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
hgroup.long 0x4E4++0x03
hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
hgroup.long 0x4E8++0x03
hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
hgroup.long 0x4EC++0x03
hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
hgroup.long 0x4F0++0x03
hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
hgroup.long 0x4F4++0x03
hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
hgroup.long 0x4F8++0x03
hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
hgroup.long 0x4FC++0x03
hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x500++0x03
line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
hexmask.long.byte 0x00 24.--31. 1. " INTID259  ,Interrupt ID259  Priority/Priority Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID258  ,Interrupt ID258   Priority/Priority Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID257  ,Interrupt ID257  Priority/Priority Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID256  ,Interrupt ID256   Priority/Priority Byte Offset 256 "
group.long 0x504++0x03
line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
hexmask.long.byte 0x00 24.--31. 1. " INTID263  ,Interrupt ID263  Priority/Priority Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID262  ,Interrupt ID262   Priority/Priority Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID261  ,Interrupt ID261  Priority/Priority Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID260  ,Interrupt ID260   Priority/Priority Byte Offset 260 "
group.long 0x508++0x03
line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
hexmask.long.byte 0x00 24.--31. 1. " INTID267  ,Interrupt ID267  Priority/Priority Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID266  ,Interrupt ID266   Priority/Priority Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID265  ,Interrupt ID265  Priority/Priority Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID264  ,Interrupt ID264   Priority/Priority Byte Offset 264 "
group.long 0x50C++0x03
line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
hexmask.long.byte 0x00 24.--31. 1. " INTID271  ,Interrupt ID271  Priority/Priority Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID270  ,Interrupt ID270   Priority/Priority Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID269  ,Interrupt ID269  Priority/Priority Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID268  ,Interrupt ID268   Priority/Priority Byte Offset 268 "
group.long 0x510++0x03
line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
hexmask.long.byte 0x00 24.--31. 1. " INTID275  ,Interrupt ID275  Priority/Priority Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID274  ,Interrupt ID274   Priority/Priority Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID273  ,Interrupt ID273  Priority/Priority Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID272  ,Interrupt ID272   Priority/Priority Byte Offset 272 "
group.long 0x514++0x03
line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
hexmask.long.byte 0x00 24.--31. 1. " INTID279  ,Interrupt ID279  Priority/Priority Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID278  ,Interrupt ID278   Priority/Priority Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID277  ,Interrupt ID277  Priority/Priority Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID276  ,Interrupt ID276   Priority/Priority Byte Offset 276 "
group.long 0x518++0x03
line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
hexmask.long.byte 0x00 24.--31. 1. " INTID283  ,Interrupt ID283  Priority/Priority Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID282  ,Interrupt ID282   Priority/Priority Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID281  ,Interrupt ID281  Priority/Priority Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID280  ,Interrupt ID280   Priority/Priority Byte Offset 280 "
group.long 0x51C++0x03
line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
hexmask.long.byte 0x00 24.--31. 1. " INTID287  ,Interrupt ID287  Priority/Priority Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID286  ,Interrupt ID286   Priority/Priority Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID285  ,Interrupt ID285  Priority/Priority Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID284  ,Interrupt ID284   Priority/Priority Byte Offset 284 "
else
hgroup.long 0x500++0x03
hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
hgroup.long 0x504++0x03
hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
hgroup.long 0x508++0x03
hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
hgroup.long 0x50C++0x03
hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
hgroup.long 0x510++0x03
hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
hgroup.long 0x514++0x03
hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
hgroup.long 0x518++0x03
hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
hgroup.long 0x51C++0x03
hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x520++0x03
line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
hexmask.long.byte 0x00 24.--31. 1. " INTID291  ,Interrupt ID291  Priority/Priority Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID290  ,Interrupt ID290   Priority/Priority Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID289  ,Interrupt ID289  Priority/Priority Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID288  ,Interrupt ID288   Priority/Priority Byte Offset 288 "
group.long 0x524++0x03
line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
hexmask.long.byte 0x00 24.--31. 1. " INTID295  ,Interrupt ID295  Priority/Priority Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID294  ,Interrupt ID294   Priority/Priority Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID293  ,Interrupt ID293  Priority/Priority Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID292  ,Interrupt ID292   Priority/Priority Byte Offset 292 "
group.long 0x528++0x03
line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
hexmask.long.byte 0x00 24.--31. 1. " INTID299  ,Interrupt ID299  Priority/Priority Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID298  ,Interrupt ID298   Priority/Priority Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID297  ,Interrupt ID297  Priority/Priority Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID296  ,Interrupt ID296   Priority/Priority Byte Offset 296 "
group.long 0x52C++0x03
line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
hexmask.long.byte 0x00 24.--31. 1. " INTID303  ,Interrupt ID303  Priority/Priority Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID302  ,Interrupt ID302   Priority/Priority Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID301  ,Interrupt ID301  Priority/Priority Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID300  ,Interrupt ID300   Priority/Priority Byte Offset 300 "
group.long 0x530++0x03
line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
hexmask.long.byte 0x00 24.--31. 1. " INTID307  ,Interrupt ID307  Priority/Priority Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID306  ,Interrupt ID306   Priority/Priority Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID305  ,Interrupt ID305  Priority/Priority Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID304  ,Interrupt ID304   Priority/Priority Byte Offset 304 "
group.long 0x534++0x03
line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
hexmask.long.byte 0x00 24.--31. 1. " INTID311  ,Interrupt ID311  Priority/Priority Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID310  ,Interrupt ID310   Priority/Priority Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID309  ,Interrupt ID309  Priority/Priority Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID308  ,Interrupt ID308   Priority/Priority Byte Offset 308 "
group.long 0x538++0x03
line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
hexmask.long.byte 0x00 24.--31. 1. " INTID315  ,Interrupt ID315  Priority/Priority Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID314  ,Interrupt ID314   Priority/Priority Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID313  ,Interrupt ID313  Priority/Priority Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID312  ,Interrupt ID312   Priority/Priority Byte Offset 312 "
group.long 0x53C++0x03
line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
hexmask.long.byte 0x00 24.--31. 1. " INTID319  ,Interrupt ID319  Priority/Priority Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID318  ,Interrupt ID318   Priority/Priority Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID317  ,Interrupt ID317  Priority/Priority Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID316  ,Interrupt ID316   Priority/Priority Byte Offset 316 "
else
hgroup.long 0x520++0x03
hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
hgroup.long 0x524++0x03
hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
hgroup.long 0x528++0x03
hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
hgroup.long 0x52C++0x03
hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
hgroup.long 0x530++0x03
hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
hgroup.long 0x534++0x03
hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
hgroup.long 0x538++0x03
hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
hgroup.long 0x53C++0x03
hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x540++0x03
line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
hexmask.long.byte 0x00 24.--31. 1. " INTID323  ,Interrupt ID323  Priority/Priority Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID322  ,Interrupt ID322   Priority/Priority Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID321  ,Interrupt ID321  Priority/Priority Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID320  ,Interrupt ID320   Priority/Priority Byte Offset 320 "
group.long 0x544++0x03
line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
hexmask.long.byte 0x00 24.--31. 1. " INTID327  ,Interrupt ID327  Priority/Priority Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID326  ,Interrupt ID326   Priority/Priority Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID325  ,Interrupt ID325  Priority/Priority Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID324  ,Interrupt ID324   Priority/Priority Byte Offset 324 "
group.long 0x548++0x03
line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
hexmask.long.byte 0x00 24.--31. 1. " INTID331  ,Interrupt ID331  Priority/Priority Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID330  ,Interrupt ID330   Priority/Priority Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID329  ,Interrupt ID329  Priority/Priority Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID328  ,Interrupt ID328   Priority/Priority Byte Offset 328 "
group.long 0x54C++0x03
line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
hexmask.long.byte 0x00 24.--31. 1. " INTID335  ,Interrupt ID335  Priority/Priority Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID334  ,Interrupt ID334   Priority/Priority Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID333  ,Interrupt ID333  Priority/Priority Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID332  ,Interrupt ID332   Priority/Priority Byte Offset 332 "
group.long 0x550++0x03
line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
hexmask.long.byte 0x00 24.--31. 1. " INTID339  ,Interrupt ID339  Priority/Priority Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID338  ,Interrupt ID338   Priority/Priority Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID337  ,Interrupt ID337  Priority/Priority Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID336  ,Interrupt ID336   Priority/Priority Byte Offset 336 "
group.long 0x554++0x03
line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
hexmask.long.byte 0x00 24.--31. 1. " INTID343  ,Interrupt ID343  Priority/Priority Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID342  ,Interrupt ID342   Priority/Priority Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID341  ,Interrupt ID341  Priority/Priority Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID340  ,Interrupt ID340   Priority/Priority Byte Offset 340 "
group.long 0x558++0x03
line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
hexmask.long.byte 0x00 24.--31. 1. " INTID347  ,Interrupt ID347  Priority/Priority Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID346  ,Interrupt ID346   Priority/Priority Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID345  ,Interrupt ID345  Priority/Priority Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID344  ,Interrupt ID344   Priority/Priority Byte Offset 344 "
group.long 0x55C++0x03
line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
hexmask.long.byte 0x00 24.--31. 1. " INTID351  ,Interrupt ID351  Priority/Priority Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID350  ,Interrupt ID350   Priority/Priority Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID349  ,Interrupt ID349  Priority/Priority Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID348  ,Interrupt ID348   Priority/Priority Byte Offset 348 "
else
hgroup.long 0x540++0x03
hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
hgroup.long 0x544++0x03
hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
hgroup.long 0x548++0x03
hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
hgroup.long 0x54C++0x03
hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
hgroup.long 0x550++0x03
hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
hgroup.long 0x554++0x03
hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
hgroup.long 0x558++0x03
hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
hgroup.long 0x55C++0x03
hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x560++0x03
line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
hexmask.long.byte 0x00 24.--31. 1. " INTID355  ,Interrupt ID355  Priority/Priority Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID354  ,Interrupt ID354   Priority/Priority Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID353  ,Interrupt ID353  Priority/Priority Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID352  ,Interrupt ID352   Priority/Priority Byte Offset 352 "
group.long 0x564++0x03
line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
hexmask.long.byte 0x00 24.--31. 1. " INTID359  ,Interrupt ID359  Priority/Priority Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID358  ,Interrupt ID358   Priority/Priority Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID357  ,Interrupt ID357  Priority/Priority Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID356  ,Interrupt ID356   Priority/Priority Byte Offset 356 "
group.long 0x568++0x03
line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
hexmask.long.byte 0x00 24.--31. 1. " INTID363  ,Interrupt ID363  Priority/Priority Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID362  ,Interrupt ID362   Priority/Priority Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID361  ,Interrupt ID361  Priority/Priority Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID360  ,Interrupt ID360   Priority/Priority Byte Offset 360 "
group.long 0x56C++0x03
line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
hexmask.long.byte 0x00 24.--31. 1. " INTID367  ,Interrupt ID367  Priority/Priority Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID366  ,Interrupt ID366   Priority/Priority Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID365  ,Interrupt ID365  Priority/Priority Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID364  ,Interrupt ID364   Priority/Priority Byte Offset 364 "
group.long 0x570++0x03
line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
hexmask.long.byte 0x00 24.--31. 1. " INTID371  ,Interrupt ID371  Priority/Priority Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID370  ,Interrupt ID370   Priority/Priority Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID369  ,Interrupt ID369  Priority/Priority Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID368  ,Interrupt ID368   Priority/Priority Byte Offset 368 "
group.long 0x574++0x03
line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
hexmask.long.byte 0x00 24.--31. 1. " INTID375  ,Interrupt ID375  Priority/Priority Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID374  ,Interrupt ID374   Priority/Priority Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID373  ,Interrupt ID373  Priority/Priority Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID372  ,Interrupt ID372   Priority/Priority Byte Offset 372 "
group.long 0x578++0x03
line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
hexmask.long.byte 0x00 24.--31. 1. " INTID379  ,Interrupt ID379  Priority/Priority Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID378  ,Interrupt ID378   Priority/Priority Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID377  ,Interrupt ID377  Priority/Priority Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID376  ,Interrupt ID376   Priority/Priority Byte Offset 376 "
group.long 0x57C++0x03
line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
hexmask.long.byte 0x00 24.--31. 1. " INTID383  ,Interrupt ID383  Priority/Priority Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID382  ,Interrupt ID382   Priority/Priority Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID381  ,Interrupt ID381  Priority/Priority Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID380  ,Interrupt ID380   Priority/Priority Byte Offset 380 "
else
hgroup.long 0x560++0x03
hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
hgroup.long 0x564++0x03
hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
hgroup.long 0x568++0x03
hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
hgroup.long 0x56C++0x03
hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
hgroup.long 0x570++0x03
hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
hgroup.long 0x574++0x03
hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
hgroup.long 0x578++0x03
hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
hgroup.long 0x57C++0x03
hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x580++0x03
line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
hexmask.long.byte 0x00 24.--31. 1. " INTID387  ,Interrupt ID387  Priority/Priority Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID386  ,Interrupt ID386   Priority/Priority Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID385  ,Interrupt ID385  Priority/Priority Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID384  ,Interrupt ID384   Priority/Priority Byte Offset 384 "
group.long 0x584++0x03
line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
hexmask.long.byte 0x00 24.--31. 1. " INTID391  ,Interrupt ID391  Priority/Priority Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID390  ,Interrupt ID390   Priority/Priority Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID389  ,Interrupt ID389  Priority/Priority Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID388  ,Interrupt ID388   Priority/Priority Byte Offset 388 "
group.long 0x588++0x03
line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
hexmask.long.byte 0x00 24.--31. 1. " INTID395  ,Interrupt ID395  Priority/Priority Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID394  ,Interrupt ID394   Priority/Priority Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID393  ,Interrupt ID393  Priority/Priority Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID392  ,Interrupt ID392   Priority/Priority Byte Offset 392 "
group.long 0x58C++0x03
line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
hexmask.long.byte 0x00 24.--31. 1. " INTID399  ,Interrupt ID399  Priority/Priority Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID398  ,Interrupt ID398   Priority/Priority Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID397  ,Interrupt ID397  Priority/Priority Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID396  ,Interrupt ID396   Priority/Priority Byte Offset 396 "
group.long 0x590++0x03
line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
hexmask.long.byte 0x00 24.--31. 1. " INTID403  ,Interrupt ID403  Priority/Priority Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID402  ,Interrupt ID402   Priority/Priority Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID401  ,Interrupt ID401  Priority/Priority Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID400  ,Interrupt ID400   Priority/Priority Byte Offset 400 "
group.long 0x594++0x03
line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
hexmask.long.byte 0x00 24.--31. 1. " INTID407  ,Interrupt ID407  Priority/Priority Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID406  ,Interrupt ID406   Priority/Priority Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID405  ,Interrupt ID405  Priority/Priority Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID404  ,Interrupt ID404   Priority/Priority Byte Offset 404 "
group.long 0x598++0x03
line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
hexmask.long.byte 0x00 24.--31. 1. " INTID411  ,Interrupt ID411  Priority/Priority Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID410  ,Interrupt ID410   Priority/Priority Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID409  ,Interrupt ID409  Priority/Priority Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID408  ,Interrupt ID408   Priority/Priority Byte Offset 408 "
group.long 0x59C++0x03
line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
hexmask.long.byte 0x00 24.--31. 1. " INTID415  ,Interrupt ID415  Priority/Priority Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID414  ,Interrupt ID414   Priority/Priority Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID413  ,Interrupt ID413  Priority/Priority Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID412  ,Interrupt ID412   Priority/Priority Byte Offset 412 "
else
hgroup.long 0x580++0x03
hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
hgroup.long 0x584++0x03
hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
hgroup.long 0x588++0x03
hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
hgroup.long 0x58C++0x03
hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
hgroup.long 0x590++0x03
hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
hgroup.long 0x594++0x03
hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
hgroup.long 0x598++0x03
hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
hgroup.long 0x59C++0x03
hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x5A0++0x03
line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
hexmask.long.byte 0x00 24.--31. 1. " INTID419  ,Interrupt ID419  Priority/Priority Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID418  ,Interrupt ID418   Priority/Priority Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID417  ,Interrupt ID417  Priority/Priority Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID416  ,Interrupt ID416   Priority/Priority Byte Offset 416 "
group.long 0x5A4++0x03
line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
hexmask.long.byte 0x00 24.--31. 1. " INTID423  ,Interrupt ID423  Priority/Priority Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID422  ,Interrupt ID422   Priority/Priority Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID421  ,Interrupt ID421  Priority/Priority Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID420  ,Interrupt ID420   Priority/Priority Byte Offset 420 "
group.long 0x5A8++0x03
line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
hexmask.long.byte 0x00 24.--31. 1. " INTID427  ,Interrupt ID427  Priority/Priority Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID426  ,Interrupt ID426   Priority/Priority Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID425  ,Interrupt ID425  Priority/Priority Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID424  ,Interrupt ID424   Priority/Priority Byte Offset 424 "
group.long 0x5AC++0x03
line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
hexmask.long.byte 0x00 24.--31. 1. " INTID431  ,Interrupt ID431  Priority/Priority Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID430  ,Interrupt ID430   Priority/Priority Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID429  ,Interrupt ID429  Priority/Priority Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID428  ,Interrupt ID428   Priority/Priority Byte Offset 428 "
group.long 0x5B0++0x03
line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
hexmask.long.byte 0x00 24.--31. 1. " INTID435  ,Interrupt ID435  Priority/Priority Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID434  ,Interrupt ID434   Priority/Priority Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID433  ,Interrupt ID433  Priority/Priority Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID432  ,Interrupt ID432   Priority/Priority Byte Offset 432 "
group.long 0x5B4++0x03
line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
hexmask.long.byte 0x00 24.--31. 1. " INTID439  ,Interrupt ID439  Priority/Priority Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID438  ,Interrupt ID438   Priority/Priority Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID437  ,Interrupt ID437  Priority/Priority Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID436  ,Interrupt ID436   Priority/Priority Byte Offset 436 "
group.long 0x5B8++0x03
line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
hexmask.long.byte 0x00 24.--31. 1. " INTID443  ,Interrupt ID443  Priority/Priority Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID442  ,Interrupt ID442   Priority/Priority Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID441  ,Interrupt ID441  Priority/Priority Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID440  ,Interrupt ID440   Priority/Priority Byte Offset 440 "
group.long 0x5BC++0x03
line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
hexmask.long.byte 0x00 24.--31. 1. " INTID447  ,Interrupt ID447  Priority/Priority Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID446  ,Interrupt ID446   Priority/Priority Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID445  ,Interrupt ID445  Priority/Priority Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID444  ,Interrupt ID444   Priority/Priority Byte Offset 444 "
else
hgroup.long 0x5A0++0x03
hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
hgroup.long 0x5A4++0x03
hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
hgroup.long 0x5A8++0x03
hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
hgroup.long 0x5AC++0x03
hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
hgroup.long 0x5B0++0x03
hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
hgroup.long 0x5B4++0x03
hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
hgroup.long 0x5B8++0x03
hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
hgroup.long 0x5BC++0x03
hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x5C0++0x03
line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
hexmask.long.byte 0x00 24.--31. 1. " INTID451  ,Interrupt ID451  Priority/Priority Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID450  ,Interrupt ID450   Priority/Priority Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID449  ,Interrupt ID449  Priority/Priority Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID448  ,Interrupt ID448   Priority/Priority Byte Offset 448 "
group.long 0x5C4++0x03
line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
hexmask.long.byte 0x00 24.--31. 1. " INTID455  ,Interrupt ID455  Priority/Priority Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID454  ,Interrupt ID454   Priority/Priority Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID453  ,Interrupt ID453  Priority/Priority Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID452  ,Interrupt ID452   Priority/Priority Byte Offset 452 "
group.long 0x5C8++0x03
line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
hexmask.long.byte 0x00 24.--31. 1. " INTID459  ,Interrupt ID459  Priority/Priority Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID458  ,Interrupt ID458   Priority/Priority Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID457  ,Interrupt ID457  Priority/Priority Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID456  ,Interrupt ID456   Priority/Priority Byte Offset 456 "
group.long 0x5CC++0x03
line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
hexmask.long.byte 0x00 24.--31. 1. " INTID463  ,Interrupt ID463  Priority/Priority Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID462  ,Interrupt ID462   Priority/Priority Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID461  ,Interrupt ID461  Priority/Priority Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID460  ,Interrupt ID460   Priority/Priority Byte Offset 460 "
group.long 0x5D0++0x03
line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
hexmask.long.byte 0x00 24.--31. 1. " INTID467  ,Interrupt ID467  Priority/Priority Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID466  ,Interrupt ID466   Priority/Priority Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID465  ,Interrupt ID465  Priority/Priority Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID464  ,Interrupt ID464   Priority/Priority Byte Offset 464 "
group.long 0x5D4++0x03
line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
hexmask.long.byte 0x00 24.--31. 1. " INTID471  ,Interrupt ID471  Priority/Priority Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID470  ,Interrupt ID470   Priority/Priority Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID469  ,Interrupt ID469  Priority/Priority Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID468  ,Interrupt ID468   Priority/Priority Byte Offset 468 "
group.long 0x5D8++0x03
line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
hexmask.long.byte 0x00 24.--31. 1. " INTID475  ,Interrupt ID475  Priority/Priority Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID474  ,Interrupt ID474   Priority/Priority Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID473  ,Interrupt ID473  Priority/Priority Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID472  ,Interrupt ID472   Priority/Priority Byte Offset 472 "
group.long 0x5DC++0x03
line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
hexmask.long.byte 0x00 24.--31. 1. " INTID479  ,Interrupt ID479  Priority/Priority Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID478  ,Interrupt ID478   Priority/Priority Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID477  ,Interrupt ID477  Priority/Priority Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID476  ,Interrupt ID476   Priority/Priority Byte Offset 476 "
else
hgroup.long 0x5C0++0x03
hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
hgroup.long 0x5C4++0x03
hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
hgroup.long 0x5C8++0x03
hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
hgroup.long 0x5CC++0x03
hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
hgroup.long 0x5D0++0x03
hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
hgroup.long 0x5D4++0x03
hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
hgroup.long 0x5D8++0x03
hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
hgroup.long 0x5DC++0x03
hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x5E0++0x03
line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
hexmask.long.byte 0x00 24.--31. 1. " INTID483  ,Interrupt ID483  Priority/Priority Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID482  ,Interrupt ID482   Priority/Priority Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID481  ,Interrupt ID481  Priority/Priority Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID480  ,Interrupt ID480   Priority/Priority Byte Offset 480 "
group.long 0x5E4++0x03
line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
hexmask.long.byte 0x00 24.--31. 1. " INTID487  ,Interrupt ID487  Priority/Priority Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID486  ,Interrupt ID486   Priority/Priority Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID485  ,Interrupt ID485  Priority/Priority Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID484  ,Interrupt ID484   Priority/Priority Byte Offset 484 "
group.long 0x5E8++0x03
line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
hexmask.long.byte 0x00 24.--31. 1. " INTID491  ,Interrupt ID491  Priority/Priority Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID490  ,Interrupt ID490   Priority/Priority Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID489  ,Interrupt ID489  Priority/Priority Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID488  ,Interrupt ID488   Priority/Priority Byte Offset 488 "
group.long 0x5EC++0x03
line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
hexmask.long.byte 0x00 24.--31. 1. " INTID495  ,Interrupt ID495  Priority/Priority Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID494  ,Interrupt ID494   Priority/Priority Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID493  ,Interrupt ID493  Priority/Priority Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID492  ,Interrupt ID492   Priority/Priority Byte Offset 492 "
group.long 0x5F0++0x03
line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
hexmask.long.byte 0x00 24.--31. 1. " INTID499  ,Interrupt ID499  Priority/Priority Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID498  ,Interrupt ID498   Priority/Priority Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID497  ,Interrupt ID497  Priority/Priority Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID496  ,Interrupt ID496   Priority/Priority Byte Offset 496 "
group.long 0x5F4++0x03
line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
hexmask.long.byte 0x00 24.--31. 1. " INTID503  ,Interrupt ID503  Priority/Priority Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID502  ,Interrupt ID502   Priority/Priority Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID501  ,Interrupt ID501  Priority/Priority Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID500  ,Interrupt ID500   Priority/Priority Byte Offset 500 "
group.long 0x5F8++0x03
line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
hexmask.long.byte 0x00 24.--31. 1. " INTID507  ,Interrupt ID507  Priority/Priority Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID506  ,Interrupt ID506   Priority/Priority Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID505  ,Interrupt ID505  Priority/Priority Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID504  ,Interrupt ID504   Priority/Priority Byte Offset 504 "
group.long 0x5FC++0x03
line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
hexmask.long.byte 0x00 24.--31. 1. " INTID511  ,Interrupt ID511  Priority/Priority Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID510  ,Interrupt ID510   Priority/Priority Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID509  ,Interrupt ID509  Priority/Priority Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID508  ,Interrupt ID508   Priority/Priority Byte Offset 508 "
else
hgroup.long 0x5E0++0x03
hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
hgroup.long 0x5E4++0x03
hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
hgroup.long 0x5E8++0x03
hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
hgroup.long 0x5EC++0x03
hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
hgroup.long 0x5F0++0x03
hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
hgroup.long 0x5F4++0x03
hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
hgroup.long 0x5F8++0x03
hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
hgroup.long 0x5FC++0x03
hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x600++0x03
line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
hexmask.long.byte 0x00 24.--31. 1. " INTID515  ,Interrupt ID515  Priority/Priority Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID514  ,Interrupt ID514   Priority/Priority Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID513  ,Interrupt ID513  Priority/Priority Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID512  ,Interrupt ID512   Priority/Priority Byte Offset 512 "
group.long 0x604++0x03
line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
hexmask.long.byte 0x00 24.--31. 1. " INTID519  ,Interrupt ID519  Priority/Priority Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID518  ,Interrupt ID518   Priority/Priority Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID517  ,Interrupt ID517  Priority/Priority Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID516  ,Interrupt ID516   Priority/Priority Byte Offset 516 "
group.long 0x608++0x03
line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
hexmask.long.byte 0x00 24.--31. 1. " INTID523  ,Interrupt ID523  Priority/Priority Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID522  ,Interrupt ID522   Priority/Priority Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID521  ,Interrupt ID521  Priority/Priority Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID520  ,Interrupt ID520   Priority/Priority Byte Offset 520 "
group.long 0x60C++0x03
line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
hexmask.long.byte 0x00 24.--31. 1. " INTID527  ,Interrupt ID527  Priority/Priority Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID526  ,Interrupt ID526   Priority/Priority Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID525  ,Interrupt ID525  Priority/Priority Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID524  ,Interrupt ID524   Priority/Priority Byte Offset 524 "
group.long 0x610++0x03
line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
hexmask.long.byte 0x00 24.--31. 1. " INTID531  ,Interrupt ID531  Priority/Priority Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID530  ,Interrupt ID530   Priority/Priority Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID529  ,Interrupt ID529  Priority/Priority Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID528  ,Interrupt ID528   Priority/Priority Byte Offset 528 "
group.long 0x614++0x03
line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
hexmask.long.byte 0x00 24.--31. 1. " INTID535  ,Interrupt ID535  Priority/Priority Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID534  ,Interrupt ID534   Priority/Priority Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID533  ,Interrupt ID533  Priority/Priority Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID532  ,Interrupt ID532   Priority/Priority Byte Offset 532 "
group.long 0x618++0x03
line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
hexmask.long.byte 0x00 24.--31. 1. " INTID539  ,Interrupt ID539  Priority/Priority Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID538  ,Interrupt ID538   Priority/Priority Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID537  ,Interrupt ID537  Priority/Priority Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID536  ,Interrupt ID536   Priority/Priority Byte Offset 536 "
group.long 0x61C++0x03
line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
hexmask.long.byte 0x00 24.--31. 1. " INTID543  ,Interrupt ID543  Priority/Priority Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID542  ,Interrupt ID542   Priority/Priority Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID541  ,Interrupt ID541  Priority/Priority Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID540  ,Interrupt ID540   Priority/Priority Byte Offset 540 "
else
hgroup.long 0x600++0x03
hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
hgroup.long 0x604++0x03
hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
hgroup.long 0x608++0x03
hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
hgroup.long 0x60C++0x03
hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
hgroup.long 0x610++0x03
hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
hgroup.long 0x614++0x03
hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
hgroup.long 0x618++0x03
hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
hgroup.long 0x61C++0x03
hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x620++0x03
line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
hexmask.long.byte 0x00 24.--31. 1. " INTID547  ,Interrupt ID547  Priority/Priority Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID546  ,Interrupt ID546   Priority/Priority Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID545  ,Interrupt ID545  Priority/Priority Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID544  ,Interrupt ID544   Priority/Priority Byte Offset 544 "
group.long 0x624++0x03
line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
hexmask.long.byte 0x00 24.--31. 1. " INTID551  ,Interrupt ID551  Priority/Priority Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID550  ,Interrupt ID550   Priority/Priority Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID549  ,Interrupt ID549  Priority/Priority Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID548  ,Interrupt ID548   Priority/Priority Byte Offset 548 "
group.long 0x628++0x03
line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
hexmask.long.byte 0x00 24.--31. 1. " INTID555  ,Interrupt ID555  Priority/Priority Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID554  ,Interrupt ID554   Priority/Priority Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID553  ,Interrupt ID553  Priority/Priority Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID552  ,Interrupt ID552   Priority/Priority Byte Offset 552 "
group.long 0x62C++0x03
line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
hexmask.long.byte 0x00 24.--31. 1. " INTID559  ,Interrupt ID559  Priority/Priority Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID558  ,Interrupt ID558   Priority/Priority Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID557  ,Interrupt ID557  Priority/Priority Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID556  ,Interrupt ID556   Priority/Priority Byte Offset 556 "
group.long 0x630++0x03
line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
hexmask.long.byte 0x00 24.--31. 1. " INTID563  ,Interrupt ID563  Priority/Priority Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID562  ,Interrupt ID562   Priority/Priority Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID561  ,Interrupt ID561  Priority/Priority Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID560  ,Interrupt ID560   Priority/Priority Byte Offset 560 "
group.long 0x634++0x03
line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
hexmask.long.byte 0x00 24.--31. 1. " INTID567  ,Interrupt ID567  Priority/Priority Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID566  ,Interrupt ID566   Priority/Priority Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID565  ,Interrupt ID565  Priority/Priority Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID564  ,Interrupt ID564   Priority/Priority Byte Offset 564 "
group.long 0x638++0x03
line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
hexmask.long.byte 0x00 24.--31. 1. " INTID571  ,Interrupt ID571  Priority/Priority Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID570  ,Interrupt ID570   Priority/Priority Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID569  ,Interrupt ID569  Priority/Priority Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID568  ,Interrupt ID568   Priority/Priority Byte Offset 568 "
group.long 0x63C++0x03
line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
hexmask.long.byte 0x00 24.--31. 1. " INTID575  ,Interrupt ID575  Priority/Priority Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID574  ,Interrupt ID574   Priority/Priority Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID573  ,Interrupt ID573  Priority/Priority Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID572  ,Interrupt ID572   Priority/Priority Byte Offset 572 "
else
hgroup.long 0x620++0x03
hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
hgroup.long 0x624++0x03
hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
hgroup.long 0x628++0x03
hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
hgroup.long 0x62C++0x03
hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
hgroup.long 0x630++0x03
hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
hgroup.long 0x634++0x03
hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
hgroup.long 0x638++0x03
hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
hgroup.long 0x63C++0x03
hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x640++0x03
line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
hexmask.long.byte 0x00 24.--31. 1. " INTID579  ,Interrupt ID579  Priority/Priority Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID578  ,Interrupt ID578   Priority/Priority Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID577  ,Interrupt ID577  Priority/Priority Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID576  ,Interrupt ID576   Priority/Priority Byte Offset 576 "
group.long 0x644++0x03
line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
hexmask.long.byte 0x00 24.--31. 1. " INTID583  ,Interrupt ID583  Priority/Priority Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID582  ,Interrupt ID582   Priority/Priority Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID581  ,Interrupt ID581  Priority/Priority Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID580  ,Interrupt ID580   Priority/Priority Byte Offset 580 "
group.long 0x648++0x03
line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
hexmask.long.byte 0x00 24.--31. 1. " INTID587  ,Interrupt ID587  Priority/Priority Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID586  ,Interrupt ID586   Priority/Priority Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID585  ,Interrupt ID585  Priority/Priority Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID584  ,Interrupt ID584   Priority/Priority Byte Offset 584 "
group.long 0x64C++0x03
line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
hexmask.long.byte 0x00 24.--31. 1. " INTID591  ,Interrupt ID591  Priority/Priority Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID590  ,Interrupt ID590   Priority/Priority Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID589  ,Interrupt ID589  Priority/Priority Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID588  ,Interrupt ID588   Priority/Priority Byte Offset 588 "
group.long 0x650++0x03
line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
hexmask.long.byte 0x00 24.--31. 1. " INTID595  ,Interrupt ID595  Priority/Priority Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID594  ,Interrupt ID594   Priority/Priority Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID593  ,Interrupt ID593  Priority/Priority Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID592  ,Interrupt ID592   Priority/Priority Byte Offset 592 "
group.long 0x654++0x03
line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
hexmask.long.byte 0x00 24.--31. 1. " INTID599  ,Interrupt ID599  Priority/Priority Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID598  ,Interrupt ID598   Priority/Priority Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID597  ,Interrupt ID597  Priority/Priority Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID596  ,Interrupt ID596   Priority/Priority Byte Offset 596 "
group.long 0x658++0x03
line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
hexmask.long.byte 0x00 24.--31. 1. " INTID603  ,Interrupt ID603  Priority/Priority Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID602  ,Interrupt ID602   Priority/Priority Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID601  ,Interrupt ID601  Priority/Priority Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID600  ,Interrupt ID600   Priority/Priority Byte Offset 600 "
group.long 0x65C++0x03
line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
hexmask.long.byte 0x00 24.--31. 1. " INTID607  ,Interrupt ID607  Priority/Priority Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID606  ,Interrupt ID606   Priority/Priority Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID605  ,Interrupt ID605  Priority/Priority Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID604  ,Interrupt ID604   Priority/Priority Byte Offset 604 "
else
hgroup.long 0x640++0x03
hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
hgroup.long 0x644++0x03
hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
hgroup.long 0x648++0x03
hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
hgroup.long 0x64C++0x03
hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
hgroup.long 0x650++0x03
hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
hgroup.long 0x654++0x03
hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
hgroup.long 0x658++0x03
hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
hgroup.long 0x65C++0x03
hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x660++0x03
line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
hexmask.long.byte 0x00 24.--31. 1. " INTID611  ,Interrupt ID611  Priority/Priority Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID610  ,Interrupt ID610   Priority/Priority Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID609  ,Interrupt ID609  Priority/Priority Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID608  ,Interrupt ID608   Priority/Priority Byte Offset 608 "
group.long 0x664++0x03
line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
hexmask.long.byte 0x00 24.--31. 1. " INTID615  ,Interrupt ID615  Priority/Priority Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID614  ,Interrupt ID614   Priority/Priority Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID613  ,Interrupt ID613  Priority/Priority Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID612  ,Interrupt ID612   Priority/Priority Byte Offset 612 "
group.long 0x668++0x03
line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
hexmask.long.byte 0x00 24.--31. 1. " INTID619  ,Interrupt ID619  Priority/Priority Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID618  ,Interrupt ID618   Priority/Priority Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID617  ,Interrupt ID617  Priority/Priority Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID616  ,Interrupt ID616   Priority/Priority Byte Offset 616 "
group.long 0x66C++0x03
line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
hexmask.long.byte 0x00 24.--31. 1. " INTID623  ,Interrupt ID623  Priority/Priority Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID622  ,Interrupt ID622   Priority/Priority Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID621  ,Interrupt ID621  Priority/Priority Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID620  ,Interrupt ID620   Priority/Priority Byte Offset 620 "
group.long 0x670++0x03
line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
hexmask.long.byte 0x00 24.--31. 1. " INTID627  ,Interrupt ID627  Priority/Priority Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID626  ,Interrupt ID626   Priority/Priority Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID625  ,Interrupt ID625  Priority/Priority Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID624  ,Interrupt ID624   Priority/Priority Byte Offset 624 "
group.long 0x674++0x03
line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
hexmask.long.byte 0x00 24.--31. 1. " INTID631  ,Interrupt ID631  Priority/Priority Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID630  ,Interrupt ID630   Priority/Priority Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID629  ,Interrupt ID629  Priority/Priority Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID628  ,Interrupt ID628   Priority/Priority Byte Offset 628 "
group.long 0x678++0x03
line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
hexmask.long.byte 0x00 24.--31. 1. " INTID635  ,Interrupt ID635  Priority/Priority Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID634  ,Interrupt ID634   Priority/Priority Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID633  ,Interrupt ID633  Priority/Priority Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID632  ,Interrupt ID632   Priority/Priority Byte Offset 632 "
group.long 0x67C++0x03
line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
hexmask.long.byte 0x00 24.--31. 1. " INTID639  ,Interrupt ID639  Priority/Priority Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID638  ,Interrupt ID638   Priority/Priority Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID637  ,Interrupt ID637  Priority/Priority Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID636  ,Interrupt ID636   Priority/Priority Byte Offset 636 "
else
hgroup.long 0x660++0x03
hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
hgroup.long 0x664++0x03
hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
hgroup.long 0x668++0x03
hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
hgroup.long 0x66C++0x03
hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
hgroup.long 0x670++0x03
hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
hgroup.long 0x674++0x03
hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
hgroup.long 0x678++0x03
hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
hgroup.long 0x67C++0x03
hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x680++0x03
line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
hexmask.long.byte 0x00 24.--31. 1. " INTID643  ,Interrupt ID643  Priority/Priority Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID642  ,Interrupt ID642   Priority/Priority Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID641  ,Interrupt ID641  Priority/Priority Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID640  ,Interrupt ID640   Priority/Priority Byte Offset 640 "
group.long 0x684++0x03
line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
hexmask.long.byte 0x00 24.--31. 1. " INTID647  ,Interrupt ID647  Priority/Priority Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID646  ,Interrupt ID646   Priority/Priority Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID645  ,Interrupt ID645  Priority/Priority Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID644  ,Interrupt ID644   Priority/Priority Byte Offset 644 "
group.long 0x688++0x03
line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
hexmask.long.byte 0x00 24.--31. 1. " INTID651  ,Interrupt ID651  Priority/Priority Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID650  ,Interrupt ID650   Priority/Priority Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID649  ,Interrupt ID649  Priority/Priority Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID648  ,Interrupt ID648   Priority/Priority Byte Offset 648 "
group.long 0x68C++0x03
line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
hexmask.long.byte 0x00 24.--31. 1. " INTID655  ,Interrupt ID655  Priority/Priority Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID654  ,Interrupt ID654   Priority/Priority Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID653  ,Interrupt ID653  Priority/Priority Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID652  ,Interrupt ID652   Priority/Priority Byte Offset 652 "
group.long 0x690++0x03
line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
hexmask.long.byte 0x00 24.--31. 1. " INTID659  ,Interrupt ID659  Priority/Priority Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID658  ,Interrupt ID658   Priority/Priority Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID657  ,Interrupt ID657  Priority/Priority Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID656  ,Interrupt ID656   Priority/Priority Byte Offset 656 "
group.long 0x694++0x03
line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
hexmask.long.byte 0x00 24.--31. 1. " INTID663  ,Interrupt ID663  Priority/Priority Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID662  ,Interrupt ID662   Priority/Priority Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID661  ,Interrupt ID661  Priority/Priority Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID660  ,Interrupt ID660   Priority/Priority Byte Offset 660 "
group.long 0x698++0x03
line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
hexmask.long.byte 0x00 24.--31. 1. " INTID667  ,Interrupt ID667  Priority/Priority Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID666  ,Interrupt ID666   Priority/Priority Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID665  ,Interrupt ID665  Priority/Priority Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID664  ,Interrupt ID664   Priority/Priority Byte Offset 664 "
group.long 0x69C++0x03
line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
hexmask.long.byte 0x00 24.--31. 1. " INTID671  ,Interrupt ID671  Priority/Priority Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID670  ,Interrupt ID670   Priority/Priority Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID669  ,Interrupt ID669  Priority/Priority Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID668  ,Interrupt ID668   Priority/Priority Byte Offset 668 "
else
hgroup.long 0x680++0x03
hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
hgroup.long 0x684++0x03
hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
hgroup.long 0x688++0x03
hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
hgroup.long 0x68C++0x03
hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
hgroup.long 0x690++0x03
hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
hgroup.long 0x694++0x03
hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
hgroup.long 0x698++0x03
hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
hgroup.long 0x69C++0x03
hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x6A0++0x03
line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
hexmask.long.byte 0x00 24.--31. 1. " INTID675  ,Interrupt ID675  Priority/Priority Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID674  ,Interrupt ID674   Priority/Priority Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID673  ,Interrupt ID673  Priority/Priority Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID672  ,Interrupt ID672   Priority/Priority Byte Offset 672 "
group.long 0x6A4++0x03
line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
hexmask.long.byte 0x00 24.--31. 1. " INTID679  ,Interrupt ID679  Priority/Priority Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID678  ,Interrupt ID678   Priority/Priority Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID677  ,Interrupt ID677  Priority/Priority Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID676  ,Interrupt ID676   Priority/Priority Byte Offset 676 "
group.long 0x6A8++0x03
line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
hexmask.long.byte 0x00 24.--31. 1. " INTID683  ,Interrupt ID683  Priority/Priority Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID682  ,Interrupt ID682   Priority/Priority Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID681  ,Interrupt ID681  Priority/Priority Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID680  ,Interrupt ID680   Priority/Priority Byte Offset 680 "
group.long 0x6AC++0x03
line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
hexmask.long.byte 0x00 24.--31. 1. " INTID687  ,Interrupt ID687  Priority/Priority Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID686  ,Interrupt ID686   Priority/Priority Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID685  ,Interrupt ID685  Priority/Priority Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID684  ,Interrupt ID684   Priority/Priority Byte Offset 684 "
group.long 0x6B0++0x03
line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
hexmask.long.byte 0x00 24.--31. 1. " INTID691  ,Interrupt ID691  Priority/Priority Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID690  ,Interrupt ID690   Priority/Priority Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID689  ,Interrupt ID689  Priority/Priority Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID688  ,Interrupt ID688   Priority/Priority Byte Offset 688 "
group.long 0x6B4++0x03
line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
hexmask.long.byte 0x00 24.--31. 1. " INTID695  ,Interrupt ID695  Priority/Priority Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID694  ,Interrupt ID694   Priority/Priority Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID693  ,Interrupt ID693  Priority/Priority Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID692  ,Interrupt ID692   Priority/Priority Byte Offset 692 "
group.long 0x6B8++0x03
line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
hexmask.long.byte 0x00 24.--31. 1. " INTID699  ,Interrupt ID699  Priority/Priority Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID698  ,Interrupt ID698   Priority/Priority Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID697  ,Interrupt ID697  Priority/Priority Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID696  ,Interrupt ID696   Priority/Priority Byte Offset 696 "
group.long 0x6BC++0x03
line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
hexmask.long.byte 0x00 24.--31. 1. " INTID703  ,Interrupt ID703  Priority/Priority Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID702  ,Interrupt ID702   Priority/Priority Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID701  ,Interrupt ID701  Priority/Priority Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID700  ,Interrupt ID700   Priority/Priority Byte Offset 700 "
else
hgroup.long 0x6A0++0x03
hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
hgroup.long 0x6A4++0x03
hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
hgroup.long 0x6A8++0x03
hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
hgroup.long 0x6AC++0x03
hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
hgroup.long 0x6B0++0x03
hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
hgroup.long 0x6B4++0x03
hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
hgroup.long 0x6B8++0x03
hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
hgroup.long 0x6BC++0x03
hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x6C0++0x03
line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
hexmask.long.byte 0x00 24.--31. 1. " INTID707  ,Interrupt ID707  Priority/Priority Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID706  ,Interrupt ID706   Priority/Priority Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID705  ,Interrupt ID705  Priority/Priority Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID704  ,Interrupt ID704   Priority/Priority Byte Offset 704 "
group.long 0x6C4++0x03
line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
hexmask.long.byte 0x00 24.--31. 1. " INTID711  ,Interrupt ID711  Priority/Priority Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID710  ,Interrupt ID710   Priority/Priority Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID709  ,Interrupt ID709  Priority/Priority Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID708  ,Interrupt ID708   Priority/Priority Byte Offset 708 "
group.long 0x6C8++0x03
line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
hexmask.long.byte 0x00 24.--31. 1. " INTID715  ,Interrupt ID715  Priority/Priority Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID714  ,Interrupt ID714   Priority/Priority Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID713  ,Interrupt ID713  Priority/Priority Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID712  ,Interrupt ID712   Priority/Priority Byte Offset 712 "
group.long 0x6CC++0x03
line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
hexmask.long.byte 0x00 24.--31. 1. " INTID719  ,Interrupt ID719  Priority/Priority Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID718  ,Interrupt ID718   Priority/Priority Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID717  ,Interrupt ID717  Priority/Priority Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID716  ,Interrupt ID716   Priority/Priority Byte Offset 716 "
group.long 0x6D0++0x03
line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
hexmask.long.byte 0x00 24.--31. 1. " INTID723  ,Interrupt ID723  Priority/Priority Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID722  ,Interrupt ID722   Priority/Priority Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID721  ,Interrupt ID721  Priority/Priority Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID720  ,Interrupt ID720   Priority/Priority Byte Offset 720 "
group.long 0x6D4++0x03
line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
hexmask.long.byte 0x00 24.--31. 1. " INTID727  ,Interrupt ID727  Priority/Priority Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID726  ,Interrupt ID726   Priority/Priority Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID725  ,Interrupt ID725  Priority/Priority Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID724  ,Interrupt ID724   Priority/Priority Byte Offset 724 "
group.long 0x6D8++0x03
line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
hexmask.long.byte 0x00 24.--31. 1. " INTID731  ,Interrupt ID731  Priority/Priority Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID730  ,Interrupt ID730   Priority/Priority Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID729  ,Interrupt ID729  Priority/Priority Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID728  ,Interrupt ID728   Priority/Priority Byte Offset 728 "
group.long 0x6DC++0x03
line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
hexmask.long.byte 0x00 24.--31. 1. " INTID735  ,Interrupt ID735  Priority/Priority Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID734  ,Interrupt ID734   Priority/Priority Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID733  ,Interrupt ID733  Priority/Priority Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID732  ,Interrupt ID732   Priority/Priority Byte Offset 732 "
else
hgroup.long 0x6C0++0x03
hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
hgroup.long 0x6C4++0x03
hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
hgroup.long 0x6C8++0x03
hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
hgroup.long 0x6CC++0x03
hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
hgroup.long 0x6D0++0x03
hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
hgroup.long 0x6D4++0x03
hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
hgroup.long 0x6D8++0x03
hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
hgroup.long 0x6DC++0x03
hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x6E0++0x03
line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
hexmask.long.byte 0x00 24.--31. 1. " INTID739  ,Interrupt ID739  Priority/Priority Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID738  ,Interrupt ID738   Priority/Priority Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID737  ,Interrupt ID737  Priority/Priority Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID736  ,Interrupt ID736   Priority/Priority Byte Offset 736 "
group.long 0x6E4++0x03
line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
hexmask.long.byte 0x00 24.--31. 1. " INTID743  ,Interrupt ID743  Priority/Priority Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID742  ,Interrupt ID742   Priority/Priority Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID741  ,Interrupt ID741  Priority/Priority Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID740  ,Interrupt ID740   Priority/Priority Byte Offset 740 "
group.long 0x6E8++0x03
line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
hexmask.long.byte 0x00 24.--31. 1. " INTID747  ,Interrupt ID747  Priority/Priority Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID746  ,Interrupt ID746   Priority/Priority Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID745  ,Interrupt ID745  Priority/Priority Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID744  ,Interrupt ID744   Priority/Priority Byte Offset 744 "
group.long 0x6EC++0x03
line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
hexmask.long.byte 0x00 24.--31. 1. " INTID751  ,Interrupt ID751  Priority/Priority Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID750  ,Interrupt ID750   Priority/Priority Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID749  ,Interrupt ID749  Priority/Priority Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID748  ,Interrupt ID748   Priority/Priority Byte Offset 748 "
group.long 0x6F0++0x03
line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
hexmask.long.byte 0x00 24.--31. 1. " INTID755  ,Interrupt ID755  Priority/Priority Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID754  ,Interrupt ID754   Priority/Priority Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID753  ,Interrupt ID753  Priority/Priority Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID752  ,Interrupt ID752   Priority/Priority Byte Offset 752 "
group.long 0x6F4++0x03
line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
hexmask.long.byte 0x00 24.--31. 1. " INTID759  ,Interrupt ID759  Priority/Priority Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID758  ,Interrupt ID758   Priority/Priority Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID757  ,Interrupt ID757  Priority/Priority Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID756  ,Interrupt ID756   Priority/Priority Byte Offset 756 "
group.long 0x6F8++0x03
line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
hexmask.long.byte 0x00 24.--31. 1. " INTID763  ,Interrupt ID763  Priority/Priority Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID762  ,Interrupt ID762   Priority/Priority Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID761  ,Interrupt ID761  Priority/Priority Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID760  ,Interrupt ID760   Priority/Priority Byte Offset 760 "
group.long 0x6FC++0x03
line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
hexmask.long.byte 0x00 24.--31. 1. " INTID767  ,Interrupt ID767  Priority/Priority Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID766  ,Interrupt ID766   Priority/Priority Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID765  ,Interrupt ID765  Priority/Priority Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID764  ,Interrupt ID764   Priority/Priority Byte Offset 764 "
else
hgroup.long 0x6E0++0x03
hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
hgroup.long 0x6E4++0x03
hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
hgroup.long 0x6E8++0x03
hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
hgroup.long 0x6EC++0x03
hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
hgroup.long 0x6F0++0x03
hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
hgroup.long 0x6F4++0x03
hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
hgroup.long 0x6F8++0x03
hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
hgroup.long 0x6FC++0x03
hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x700++0x03
line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
hexmask.long.byte 0x00 24.--31. 1. " INTID771  ,Interrupt ID771  Priority/Priority Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID770  ,Interrupt ID770   Priority/Priority Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID769  ,Interrupt ID769  Priority/Priority Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID768  ,Interrupt ID768   Priority/Priority Byte Offset 768 "
group.long 0x704++0x03
line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
hexmask.long.byte 0x00 24.--31. 1. " INTID775  ,Interrupt ID775  Priority/Priority Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID774  ,Interrupt ID774   Priority/Priority Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID773  ,Interrupt ID773  Priority/Priority Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID772  ,Interrupt ID772   Priority/Priority Byte Offset 772 "
group.long 0x708++0x03
line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
hexmask.long.byte 0x00 24.--31. 1. " INTID779  ,Interrupt ID779  Priority/Priority Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID778  ,Interrupt ID778   Priority/Priority Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID777  ,Interrupt ID777  Priority/Priority Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID776  ,Interrupt ID776   Priority/Priority Byte Offset 776 "
group.long 0x70C++0x03
line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
hexmask.long.byte 0x00 24.--31. 1. " INTID783  ,Interrupt ID783  Priority/Priority Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID782  ,Interrupt ID782   Priority/Priority Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID781  ,Interrupt ID781  Priority/Priority Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID780  ,Interrupt ID780   Priority/Priority Byte Offset 780 "
group.long 0x710++0x03
line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
hexmask.long.byte 0x00 24.--31. 1. " INTID787  ,Interrupt ID787  Priority/Priority Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID786  ,Interrupt ID786   Priority/Priority Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID785  ,Interrupt ID785  Priority/Priority Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID784  ,Interrupt ID784   Priority/Priority Byte Offset 784 "
group.long 0x714++0x03
line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
hexmask.long.byte 0x00 24.--31. 1. " INTID791  ,Interrupt ID791  Priority/Priority Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID790  ,Interrupt ID790   Priority/Priority Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID789  ,Interrupt ID789  Priority/Priority Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID788  ,Interrupt ID788   Priority/Priority Byte Offset 788 "
group.long 0x718++0x03
line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
hexmask.long.byte 0x00 24.--31. 1. " INTID795  ,Interrupt ID795  Priority/Priority Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID794  ,Interrupt ID794   Priority/Priority Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID793  ,Interrupt ID793  Priority/Priority Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID792  ,Interrupt ID792   Priority/Priority Byte Offset 792 "
group.long 0x71C++0x03
line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
hexmask.long.byte 0x00 24.--31. 1. " INTID799  ,Interrupt ID799  Priority/Priority Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID798  ,Interrupt ID798   Priority/Priority Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID797  ,Interrupt ID797  Priority/Priority Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID796  ,Interrupt ID796   Priority/Priority Byte Offset 796 "
else
hgroup.long 0x700++0x03
hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
hgroup.long 0x704++0x03
hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
hgroup.long 0x708++0x03
hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
hgroup.long 0x70C++0x03
hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
hgroup.long 0x710++0x03
hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
hgroup.long 0x714++0x03
hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
hgroup.long 0x718++0x03
hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
hgroup.long 0x71C++0x03
hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x720++0x03
line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
hexmask.long.byte 0x00 24.--31. 1. " INTID803  ,Interrupt ID803  Priority/Priority Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID802  ,Interrupt ID802   Priority/Priority Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID801  ,Interrupt ID801  Priority/Priority Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID800  ,Interrupt ID800   Priority/Priority Byte Offset 800 "
group.long 0x724++0x03
line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
hexmask.long.byte 0x00 24.--31. 1. " INTID807  ,Interrupt ID807  Priority/Priority Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID806  ,Interrupt ID806   Priority/Priority Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID805  ,Interrupt ID805  Priority/Priority Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID804  ,Interrupt ID804   Priority/Priority Byte Offset 804 "
group.long 0x728++0x03
line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
hexmask.long.byte 0x00 24.--31. 1. " INTID811  ,Interrupt ID811  Priority/Priority Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID810  ,Interrupt ID810   Priority/Priority Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID809  ,Interrupt ID809  Priority/Priority Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID808  ,Interrupt ID808   Priority/Priority Byte Offset 808 "
group.long 0x72C++0x03
line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
hexmask.long.byte 0x00 24.--31. 1. " INTID815  ,Interrupt ID815  Priority/Priority Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID814  ,Interrupt ID814   Priority/Priority Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID813  ,Interrupt ID813  Priority/Priority Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID812  ,Interrupt ID812   Priority/Priority Byte Offset 812 "
group.long 0x730++0x03
line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
hexmask.long.byte 0x00 24.--31. 1. " INTID819  ,Interrupt ID819  Priority/Priority Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID818  ,Interrupt ID818   Priority/Priority Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID817  ,Interrupt ID817  Priority/Priority Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID816  ,Interrupt ID816   Priority/Priority Byte Offset 816 "
group.long 0x734++0x03
line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
hexmask.long.byte 0x00 24.--31. 1. " INTID823  ,Interrupt ID823  Priority/Priority Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID822  ,Interrupt ID822   Priority/Priority Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID821  ,Interrupt ID821  Priority/Priority Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID820  ,Interrupt ID820   Priority/Priority Byte Offset 820 "
group.long 0x738++0x03
line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
hexmask.long.byte 0x00 24.--31. 1. " INTID827  ,Interrupt ID827  Priority/Priority Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID826  ,Interrupt ID826   Priority/Priority Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID825  ,Interrupt ID825  Priority/Priority Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID824  ,Interrupt ID824   Priority/Priority Byte Offset 824 "
group.long 0x73C++0x03
line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
hexmask.long.byte 0x00 24.--31. 1. " INTID831  ,Interrupt ID831  Priority/Priority Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID830  ,Interrupt ID830   Priority/Priority Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID829  ,Interrupt ID829  Priority/Priority Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID828  ,Interrupt ID828   Priority/Priority Byte Offset 828 "
else
hgroup.long 0x720++0x03
hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
hgroup.long 0x724++0x03
hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
hgroup.long 0x728++0x03
hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
hgroup.long 0x72C++0x03
hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
hgroup.long 0x730++0x03
hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
hgroup.long 0x734++0x03
hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
hgroup.long 0x738++0x03
hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
hgroup.long 0x73C++0x03
hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x740++0x03
line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
hexmask.long.byte 0x00 24.--31. 1. " INTID835  ,Interrupt ID835  Priority/Priority Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID834  ,Interrupt ID834   Priority/Priority Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID833  ,Interrupt ID833  Priority/Priority Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID832  ,Interrupt ID832   Priority/Priority Byte Offset 832 "
group.long 0x744++0x03
line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
hexmask.long.byte 0x00 24.--31. 1. " INTID839  ,Interrupt ID839  Priority/Priority Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID838  ,Interrupt ID838   Priority/Priority Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID837  ,Interrupt ID837  Priority/Priority Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID836  ,Interrupt ID836   Priority/Priority Byte Offset 836 "
group.long 0x748++0x03
line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
hexmask.long.byte 0x00 24.--31. 1. " INTID843  ,Interrupt ID843  Priority/Priority Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID842  ,Interrupt ID842   Priority/Priority Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID841  ,Interrupt ID841  Priority/Priority Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID840  ,Interrupt ID840   Priority/Priority Byte Offset 840 "
group.long 0x74C++0x03
line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
hexmask.long.byte 0x00 24.--31. 1. " INTID847  ,Interrupt ID847  Priority/Priority Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID846  ,Interrupt ID846   Priority/Priority Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID845  ,Interrupt ID845  Priority/Priority Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID844  ,Interrupt ID844   Priority/Priority Byte Offset 844 "
group.long 0x750++0x03
line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
hexmask.long.byte 0x00 24.--31. 1. " INTID851  ,Interrupt ID851  Priority/Priority Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID850  ,Interrupt ID850   Priority/Priority Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID849  ,Interrupt ID849  Priority/Priority Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID848  ,Interrupt ID848   Priority/Priority Byte Offset 848 "
group.long 0x754++0x03
line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
hexmask.long.byte 0x00 24.--31. 1. " INTID855  ,Interrupt ID855  Priority/Priority Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID854  ,Interrupt ID854   Priority/Priority Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID853  ,Interrupt ID853  Priority/Priority Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID852  ,Interrupt ID852   Priority/Priority Byte Offset 852 "
group.long 0x758++0x03
line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
hexmask.long.byte 0x00 24.--31. 1. " INTID859  ,Interrupt ID859  Priority/Priority Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID858  ,Interrupt ID858   Priority/Priority Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID857  ,Interrupt ID857  Priority/Priority Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID856  ,Interrupt ID856   Priority/Priority Byte Offset 856 "
group.long 0x75C++0x03
line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
hexmask.long.byte 0x00 24.--31. 1. " INTID863  ,Interrupt ID863  Priority/Priority Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID862  ,Interrupt ID862   Priority/Priority Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID861  ,Interrupt ID861  Priority/Priority Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID860  ,Interrupt ID860   Priority/Priority Byte Offset 860 "
else
hgroup.long 0x740++0x03
hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
hgroup.long 0x744++0x03
hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
hgroup.long 0x748++0x03
hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
hgroup.long 0x74C++0x03
hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
hgroup.long 0x750++0x03
hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
hgroup.long 0x754++0x03
hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
hgroup.long 0x758++0x03
hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
hgroup.long 0x75C++0x03
hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x760++0x03
line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
hexmask.long.byte 0x00 24.--31. 1. " INTID867  ,Interrupt ID867  Priority/Priority Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID866  ,Interrupt ID866   Priority/Priority Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID865  ,Interrupt ID865  Priority/Priority Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID864  ,Interrupt ID864   Priority/Priority Byte Offset 864 "
group.long 0x764++0x03
line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
hexmask.long.byte 0x00 24.--31. 1. " INTID871  ,Interrupt ID871  Priority/Priority Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID870  ,Interrupt ID870   Priority/Priority Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID869  ,Interrupt ID869  Priority/Priority Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID868  ,Interrupt ID868   Priority/Priority Byte Offset 868 "
group.long 0x768++0x03
line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
hexmask.long.byte 0x00 24.--31. 1. " INTID875  ,Interrupt ID875  Priority/Priority Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID874  ,Interrupt ID874   Priority/Priority Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID873  ,Interrupt ID873  Priority/Priority Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID872  ,Interrupt ID872   Priority/Priority Byte Offset 872 "
group.long 0x76C++0x03
line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
hexmask.long.byte 0x00 24.--31. 1. " INTID879  ,Interrupt ID879  Priority/Priority Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID878  ,Interrupt ID878   Priority/Priority Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID877  ,Interrupt ID877  Priority/Priority Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID876  ,Interrupt ID876   Priority/Priority Byte Offset 876 "
group.long 0x770++0x03
line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
hexmask.long.byte 0x00 24.--31. 1. " INTID883  ,Interrupt ID883  Priority/Priority Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID882  ,Interrupt ID882   Priority/Priority Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID881  ,Interrupt ID881  Priority/Priority Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID880  ,Interrupt ID880   Priority/Priority Byte Offset 880 "
group.long 0x774++0x03
line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
hexmask.long.byte 0x00 24.--31. 1. " INTID887  ,Interrupt ID887  Priority/Priority Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID886  ,Interrupt ID886   Priority/Priority Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID885  ,Interrupt ID885  Priority/Priority Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID884  ,Interrupt ID884   Priority/Priority Byte Offset 884 "
group.long 0x778++0x03
line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
hexmask.long.byte 0x00 24.--31. 1. " INTID891  ,Interrupt ID891  Priority/Priority Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID890  ,Interrupt ID890   Priority/Priority Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID889  ,Interrupt ID889  Priority/Priority Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID888  ,Interrupt ID888   Priority/Priority Byte Offset 888 "
group.long 0x77C++0x03
line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
hexmask.long.byte 0x00 24.--31. 1. " INTID895  ,Interrupt ID895  Priority/Priority Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID894  ,Interrupt ID894   Priority/Priority Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID893  ,Interrupt ID893  Priority/Priority Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID892  ,Interrupt ID892   Priority/Priority Byte Offset 892 "
else
hgroup.long 0x760++0x03
hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
hgroup.long 0x764++0x03
hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
hgroup.long 0x768++0x03
hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
hgroup.long 0x76C++0x03
hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
hgroup.long 0x770++0x03
hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
hgroup.long 0x774++0x03
hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
hgroup.long 0x778++0x03
hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
hgroup.long 0x77C++0x03
hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x780++0x03
line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
hexmask.long.byte 0x00 24.--31. 1. " INTID899  ,Interrupt ID899  Priority/Priority Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID898  ,Interrupt ID898   Priority/Priority Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID897  ,Interrupt ID897  Priority/Priority Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID896  ,Interrupt ID896   Priority/Priority Byte Offset 896 "
group.long 0x784++0x03
line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
hexmask.long.byte 0x00 24.--31. 1. " INTID903  ,Interrupt ID903  Priority/Priority Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID902  ,Interrupt ID902   Priority/Priority Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID901  ,Interrupt ID901  Priority/Priority Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID900  ,Interrupt ID900   Priority/Priority Byte Offset 900 "
group.long 0x788++0x03
line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
hexmask.long.byte 0x00 24.--31. 1. " INTID907  ,Interrupt ID907  Priority/Priority Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID906  ,Interrupt ID906   Priority/Priority Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID905  ,Interrupt ID905  Priority/Priority Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID904  ,Interrupt ID904   Priority/Priority Byte Offset 904 "
group.long 0x78C++0x03
line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
hexmask.long.byte 0x00 24.--31. 1. " INTID911  ,Interrupt ID911  Priority/Priority Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID910  ,Interrupt ID910   Priority/Priority Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID909  ,Interrupt ID909  Priority/Priority Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID908  ,Interrupt ID908   Priority/Priority Byte Offset 908 "
group.long 0x790++0x03
line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
hexmask.long.byte 0x00 24.--31. 1. " INTID915  ,Interrupt ID915  Priority/Priority Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID914  ,Interrupt ID914   Priority/Priority Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID913  ,Interrupt ID913  Priority/Priority Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID912  ,Interrupt ID912   Priority/Priority Byte Offset 912 "
group.long 0x794++0x03
line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
hexmask.long.byte 0x00 24.--31. 1. " INTID919  ,Interrupt ID919  Priority/Priority Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID918  ,Interrupt ID918   Priority/Priority Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID917  ,Interrupt ID917  Priority/Priority Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID916  ,Interrupt ID916   Priority/Priority Byte Offset 916 "
group.long 0x798++0x03
line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
hexmask.long.byte 0x00 24.--31. 1. " INTID923  ,Interrupt ID923  Priority/Priority Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID922  ,Interrupt ID922   Priority/Priority Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID921  ,Interrupt ID921  Priority/Priority Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID920  ,Interrupt ID920   Priority/Priority Byte Offset 920 "
group.long 0x79C++0x03
line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
hexmask.long.byte 0x00 24.--31. 1. " INTID927  ,Interrupt ID927  Priority/Priority Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID926  ,Interrupt ID926   Priority/Priority Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID925  ,Interrupt ID925  Priority/Priority Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID924  ,Interrupt ID924   Priority/Priority Byte Offset 924 "
else
hgroup.long 0x780++0x03
hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
hgroup.long 0x784++0x03
hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
hgroup.long 0x788++0x03
hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
hgroup.long 0x78C++0x03
hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
hgroup.long 0x790++0x03
hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
hgroup.long 0x794++0x03
hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
hgroup.long 0x798++0x03
hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
hgroup.long 0x79C++0x03
hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x7A0++0x03
line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
hexmask.long.byte 0x00 24.--31. 1. " INTID931  ,Interrupt ID931  Priority/Priority Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID930  ,Interrupt ID930   Priority/Priority Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID929  ,Interrupt ID929  Priority/Priority Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID928  ,Interrupt ID928   Priority/Priority Byte Offset 928 "
group.long 0x7A4++0x03
line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
hexmask.long.byte 0x00 24.--31. 1. " INTID935  ,Interrupt ID935  Priority/Priority Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID934  ,Interrupt ID934   Priority/Priority Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID933  ,Interrupt ID933  Priority/Priority Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID932  ,Interrupt ID932   Priority/Priority Byte Offset 932 "
group.long 0x7A8++0x03
line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
hexmask.long.byte 0x00 24.--31. 1. " INTID939  ,Interrupt ID939  Priority/Priority Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID938  ,Interrupt ID938   Priority/Priority Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID937  ,Interrupt ID937  Priority/Priority Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID936  ,Interrupt ID936   Priority/Priority Byte Offset 936 "
group.long 0x7AC++0x03
line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
hexmask.long.byte 0x00 24.--31. 1. " INTID943  ,Interrupt ID943  Priority/Priority Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID942  ,Interrupt ID942   Priority/Priority Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID941  ,Interrupt ID941  Priority/Priority Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID940  ,Interrupt ID940   Priority/Priority Byte Offset 940 "
group.long 0x7B0++0x03
line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
hexmask.long.byte 0x00 24.--31. 1. " INTID947  ,Interrupt ID947  Priority/Priority Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID946  ,Interrupt ID946   Priority/Priority Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID945  ,Interrupt ID945  Priority/Priority Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID944  ,Interrupt ID944   Priority/Priority Byte Offset 944 "
group.long 0x7B4++0x03
line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
hexmask.long.byte 0x00 24.--31. 1. " INTID951  ,Interrupt ID951  Priority/Priority Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID950  ,Interrupt ID950   Priority/Priority Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID949  ,Interrupt ID949  Priority/Priority Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID948  ,Interrupt ID948   Priority/Priority Byte Offset 948 "
group.long 0x7B8++0x03
line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
hexmask.long.byte 0x00 24.--31. 1. " INTID955  ,Interrupt ID955  Priority/Priority Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID954  ,Interrupt ID954   Priority/Priority Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID953  ,Interrupt ID953  Priority/Priority Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID952  ,Interrupt ID952   Priority/Priority Byte Offset 952 "
group.long 0x7BC++0x03
line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
hexmask.long.byte 0x00 24.--31. 1. " INTID959  ,Interrupt ID959  Priority/Priority Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID958  ,Interrupt ID958   Priority/Priority Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID957  ,Interrupt ID957  Priority/Priority Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID956  ,Interrupt ID956   Priority/Priority Byte Offset 956 "
else
hgroup.long 0x7A0++0x03
hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
hgroup.long 0x7A4++0x03
hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
hgroup.long 0x7A8++0x03
hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
hgroup.long 0x7AC++0x03
hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
hgroup.long 0x7B0++0x03
hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
hgroup.long 0x7B4++0x03
hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
hgroup.long 0x7B8++0x03
hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
hgroup.long 0x7BC++0x03
hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x7C0++0x03
line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
hexmask.long.byte 0x00 24.--31. 1. " INTID963  ,Interrupt ID963  Priority/Priority Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID962  ,Interrupt ID962   Priority/Priority Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID961  ,Interrupt ID961  Priority/Priority Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID960  ,Interrupt ID960   Priority/Priority Byte Offset 960 "
group.long 0x7C4++0x03
line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
hexmask.long.byte 0x00 24.--31. 1. " INTID967  ,Interrupt ID967  Priority/Priority Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID966  ,Interrupt ID966   Priority/Priority Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID965  ,Interrupt ID965  Priority/Priority Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID964  ,Interrupt ID964   Priority/Priority Byte Offset 964 "
group.long 0x7C8++0x03
line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
hexmask.long.byte 0x00 24.--31. 1. " INTID971  ,Interrupt ID971  Priority/Priority Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID970  ,Interrupt ID970   Priority/Priority Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID969  ,Interrupt ID969  Priority/Priority Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID968  ,Interrupt ID968   Priority/Priority Byte Offset 968 "
group.long 0x7CC++0x03
line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
hexmask.long.byte 0x00 24.--31. 1. " INTID975  ,Interrupt ID975  Priority/Priority Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID974  ,Interrupt ID974   Priority/Priority Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID973  ,Interrupt ID973  Priority/Priority Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID972  ,Interrupt ID972   Priority/Priority Byte Offset 972 "
group.long 0x7D0++0x03
line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
hexmask.long.byte 0x00 24.--31. 1. " INTID979  ,Interrupt ID979  Priority/Priority Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID978  ,Interrupt ID978   Priority/Priority Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID977  ,Interrupt ID977  Priority/Priority Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID976  ,Interrupt ID976   Priority/Priority Byte Offset 976 "
group.long 0x7D4++0x03
line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
hexmask.long.byte 0x00 24.--31. 1. " INTID983  ,Interrupt ID983  Priority/Priority Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID982  ,Interrupt ID982   Priority/Priority Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID981  ,Interrupt ID981  Priority/Priority Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID980  ,Interrupt ID980   Priority/Priority Byte Offset 980 "
group.long 0x7D8++0x03
line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
hexmask.long.byte 0x00 24.--31. 1. " INTID987  ,Interrupt ID987  Priority/Priority Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID986  ,Interrupt ID986   Priority/Priority Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID985  ,Interrupt ID985  Priority/Priority Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID984  ,Interrupt ID984   Priority/Priority Byte Offset 984 "
group.long 0x7DC++0x03
line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
hexmask.long.byte 0x00 24.--31. 1. " INTID991  ,Interrupt ID991  Priority/Priority Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID990  ,Interrupt ID990   Priority/Priority Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID989  ,Interrupt ID989  Priority/Priority Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID988  ,Interrupt ID988   Priority/Priority Byte Offset 988 "
else
hgroup.long 0x7C0++0x03
hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
hgroup.long 0x7C4++0x03
hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
hgroup.long 0x7C8++0x03
hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
hgroup.long 0x7CC++0x03
hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
hgroup.long 0x7D0++0x03
hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
hgroup.long 0x7D4++0x03
hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
hgroup.long 0x7D8++0x03
hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
hgroup.long 0x7DC++0x03
hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
endif
tree.end
width 19.
tree "Interrupt Targets Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x000000E0)>0x1)
hgroup.long 0x800++0x03
hide.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0"
hgroup.long 0x804++0x03
hide.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1"
hgroup.long 0x808++0x03
hide.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2"
hgroup.long 0x80C++0x03
hide.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3"
hgroup.long 0x810++0x03
hide.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4"
hgroup.long 0x814++0x03
hide.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5"
hgroup.long 0x818++0x03
hide.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6"
hgroup.long 0x81C++0x03
hide.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x820++0x03
line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35   ,CPU Targets Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO34   ,CPU Targets Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO33   ,CPU Targets Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO32   ,CPU Targets Byte Offset 32  "
group.long 0x824++0x03
line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39   ,CPU Targets Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO38   ,CPU Targets Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO37   ,CPU Targets Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO36   ,CPU Targets Byte Offset 36  "
group.long 0x828++0x03
line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43   ,CPU Targets Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO42   ,CPU Targets Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO41   ,CPU Targets Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO40   ,CPU Targets Byte Offset 40  "
group.long 0x82C++0x03
line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47   ,CPU Targets Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO46   ,CPU Targets Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO45   ,CPU Targets Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO44   ,CPU Targets Byte Offset 44  "
group.long 0x830++0x03
line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51   ,CPU Targets Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO50   ,CPU Targets Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO49   ,CPU Targets Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO48   ,CPU Targets Byte Offset 48  "
group.long 0x834++0x03
line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55   ,CPU Targets Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO54   ,CPU Targets Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO53   ,CPU Targets Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO52   ,CPU Targets Byte Offset 52  "
group.long 0x838++0x03
line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59   ,CPU Targets Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO58   ,CPU Targets Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO57   ,CPU Targets Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO56   ,CPU Targets Byte Offset 56  "
group.long 0x83C++0x03
line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63   ,CPU Targets Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO62   ,CPU Targets Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO61   ,CPU Targets Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO60   ,CPU Targets Byte Offset 60  "
else
hgroup.long 0x820++0x03
hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
hgroup.long 0x824++0x03
hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
hgroup.long 0x828++0x03
hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
hgroup.long 0x82C++0x03
hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
hgroup.long 0x830++0x03
hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
hgroup.long 0x834++0x03
hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
hgroup.long 0x838++0x03
hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
hgroup.long 0x83C++0x03
hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x840++0x03
line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67   ,CPU Targets Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO66   ,CPU Targets Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO65   ,CPU Targets Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO64   ,CPU Targets Byte Offset 64  "
group.long 0x844++0x03
line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71   ,CPU Targets Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO70   ,CPU Targets Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO69   ,CPU Targets Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO68   ,CPU Targets Byte Offset 68  "
group.long 0x848++0x03
line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75   ,CPU Targets Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO74   ,CPU Targets Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO73   ,CPU Targets Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO72   ,CPU Targets Byte Offset 72  "
group.long 0x84C++0x03
line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79   ,CPU Targets Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO78   ,CPU Targets Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO77   ,CPU Targets Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO76   ,CPU Targets Byte Offset 76  "
group.long 0x850++0x03
line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83   ,CPU Targets Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO82   ,CPU Targets Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO81   ,CPU Targets Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO80   ,CPU Targets Byte Offset 80  "
group.long 0x854++0x03
line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87   ,CPU Targets Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO86   ,CPU Targets Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO85   ,CPU Targets Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO84   ,CPU Targets Byte Offset 84  "
group.long 0x858++0x03
line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91   ,CPU Targets Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO90   ,CPU Targets Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO89   ,CPU Targets Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO88   ,CPU Targets Byte Offset 88  "
group.long 0x85C++0x03
line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95   ,CPU Targets Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO94   ,CPU Targets Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO93   ,CPU Targets Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO92   ,CPU Targets Byte Offset 92  "
else
hgroup.long 0x840++0x03
hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
hgroup.long 0x844++0x03
hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
hgroup.long 0x848++0x03
hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
hgroup.long 0x84C++0x03
hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
hgroup.long 0x850++0x03
hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
hgroup.long 0x854++0x03
hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
hgroup.long 0x858++0x03
hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
hgroup.long 0x85C++0x03
hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x860++0x03
line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99   ,CPU Targets Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO98   ,CPU Targets Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO97   ,CPU Targets Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO96   ,CPU Targets Byte Offset 96  "
group.long 0x864++0x03
line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103  ,CPU Targets Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO102  ,CPU Targets Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO101  ,CPU Targets Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO100  ,CPU Targets Byte Offset 100 "
group.long 0x868++0x03
line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107  ,CPU Targets Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO106  ,CPU Targets Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO105  ,CPU Targets Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO104  ,CPU Targets Byte Offset 104 "
group.long 0x86C++0x03
line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111  ,CPU Targets Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO110  ,CPU Targets Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO109  ,CPU Targets Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO108  ,CPU Targets Byte Offset 108 "
group.long 0x870++0x03
line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115  ,CPU Targets Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO114  ,CPU Targets Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO113  ,CPU Targets Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO112  ,CPU Targets Byte Offset 112 "
group.long 0x874++0x03
line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119  ,CPU Targets Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO118  ,CPU Targets Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO117  ,CPU Targets Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO116  ,CPU Targets Byte Offset 116 "
group.long 0x878++0x03
line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123  ,CPU Targets Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO122  ,CPU Targets Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO121  ,CPU Targets Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO120  ,CPU Targets Byte Offset 120 "
group.long 0x87C++0x03
line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127  ,CPU Targets Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO126  ,CPU Targets Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO125  ,CPU Targets Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO124  ,CPU Targets Byte Offset 124 "
else
hgroup.long 0x860++0x03
hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
hgroup.long 0x864++0x03
hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
hgroup.long 0x868++0x03
hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
hgroup.long 0x86C++0x03
hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
hgroup.long 0x870++0x03
hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
hgroup.long 0x874++0x03
hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
hgroup.long 0x878++0x03
hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
hgroup.long 0x87C++0x03
hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x880++0x03
line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131  ,CPU Targets Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO130  ,CPU Targets Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO129  ,CPU Targets Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO128  ,CPU Targets Byte Offset 128 "
group.long 0x884++0x03
line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135  ,CPU Targets Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO134  ,CPU Targets Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO133  ,CPU Targets Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO132  ,CPU Targets Byte Offset 132 "
group.long 0x888++0x03
line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139  ,CPU Targets Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO138  ,CPU Targets Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO137  ,CPU Targets Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO136  ,CPU Targets Byte Offset 136 "
group.long 0x88C++0x03
line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143  ,CPU Targets Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO142  ,CPU Targets Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO141  ,CPU Targets Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO140  ,CPU Targets Byte Offset 140 "
group.long 0x890++0x03
line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147  ,CPU Targets Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO146  ,CPU Targets Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO145  ,CPU Targets Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO144  ,CPU Targets Byte Offset 144 "
group.long 0x894++0x03
line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151  ,CPU Targets Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO150  ,CPU Targets Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO149  ,CPU Targets Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO148  ,CPU Targets Byte Offset 148 "
group.long 0x898++0x03
line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155  ,CPU Targets Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO154  ,CPU Targets Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO153  ,CPU Targets Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO152  ,CPU Targets Byte Offset 152 "
group.long 0x89C++0x03
line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159  ,CPU Targets Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO158  ,CPU Targets Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO157  ,CPU Targets Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO156  ,CPU Targets Byte Offset 156 "
else
hgroup.long 0x880++0x03
hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
hgroup.long 0x884++0x03
hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
hgroup.long 0x888++0x03
hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
hgroup.long 0x88C++0x03
hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
hgroup.long 0x890++0x03
hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
hgroup.long 0x894++0x03
hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
hgroup.long 0x898++0x03
hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
hgroup.long 0x89C++0x03
hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x8A0++0x03
line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163  ,CPU Targets Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO162  ,CPU Targets Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO161  ,CPU Targets Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO160  ,CPU Targets Byte Offset 160 "
group.long 0x8A4++0x03
line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167  ,CPU Targets Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO166  ,CPU Targets Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO165  ,CPU Targets Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO164  ,CPU Targets Byte Offset 164 "
group.long 0x8A8++0x03
line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171  ,CPU Targets Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO170  ,CPU Targets Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO169  ,CPU Targets Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO168  ,CPU Targets Byte Offset 168 "
group.long 0x8AC++0x03
line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175  ,CPU Targets Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO174  ,CPU Targets Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO173  ,CPU Targets Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO172  ,CPU Targets Byte Offset 172 "
group.long 0x8B0++0x03
line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179  ,CPU Targets Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO178  ,CPU Targets Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO177  ,CPU Targets Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO176  ,CPU Targets Byte Offset 176 "
group.long 0x8B4++0x03
line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183  ,CPU Targets Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO182  ,CPU Targets Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO181  ,CPU Targets Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO180  ,CPU Targets Byte Offset 180 "
group.long 0x8B8++0x03
line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187  ,CPU Targets Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO186  ,CPU Targets Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO185  ,CPU Targets Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO184  ,CPU Targets Byte Offset 184 "
group.long 0x8BC++0x03
line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191  ,CPU Targets Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO190  ,CPU Targets Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO189  ,CPU Targets Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO188  ,CPU Targets Byte Offset 188 "
else
hgroup.long 0x8A0++0x03
hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
hgroup.long 0x8A4++0x03
hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
hgroup.long 0x8A8++0x03
hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
hgroup.long 0x8AC++0x03
hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
hgroup.long 0x8B0++0x03
hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
hgroup.long 0x8B4++0x03
hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
hgroup.long 0x8B8++0x03
hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
hgroup.long 0x8BC++0x03
hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x8C0++0x03
line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195  ,CPU Targets Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO194  ,CPU Targets Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO193  ,CPU Targets Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO192  ,CPU Targets Byte Offset 192 "
group.long 0x8C4++0x03
line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199  ,CPU Targets Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO198  ,CPU Targets Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO197  ,CPU Targets Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO196  ,CPU Targets Byte Offset 196 "
group.long 0x8C8++0x03
line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203  ,CPU Targets Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO202  ,CPU Targets Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO201  ,CPU Targets Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO200  ,CPU Targets Byte Offset 200 "
group.long 0x8CC++0x03
line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207  ,CPU Targets Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO206  ,CPU Targets Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO205  ,CPU Targets Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO204  ,CPU Targets Byte Offset 204 "
group.long 0x8D0++0x03
line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211  ,CPU Targets Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO210  ,CPU Targets Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO209  ,CPU Targets Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO208  ,CPU Targets Byte Offset 208 "
group.long 0x8D4++0x03
line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215  ,CPU Targets Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO214  ,CPU Targets Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO213  ,CPU Targets Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO212  ,CPU Targets Byte Offset 212 "
group.long 0x8D8++0x03
line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219  ,CPU Targets Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO218  ,CPU Targets Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO217  ,CPU Targets Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO216  ,CPU Targets Byte Offset 216 "
group.long 0x8DC++0x03
line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223  ,CPU Targets Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO222  ,CPU Targets Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO221  ,CPU Targets Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO220  ,CPU Targets Byte Offset 220 "
else
hgroup.long 0x8C0++0x03
hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
hgroup.long 0x8C4++0x03
hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
hgroup.long 0x8C8++0x03
hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
hgroup.long 0x8CC++0x03
hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
hgroup.long 0x8D0++0x03
hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
hgroup.long 0x8D4++0x03
hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
hgroup.long 0x8D8++0x03
hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
hgroup.long 0x8DC++0x03
hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x8E0++0x03
line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227  ,CPU Targets Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO226  ,CPU Targets Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO225  ,CPU Targets Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO224  ,CPU Targets Byte Offset 224 "
group.long 0x8E4++0x03
line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231  ,CPU Targets Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO230  ,CPU Targets Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO229  ,CPU Targets Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO228  ,CPU Targets Byte Offset 228 "
group.long 0x8E8++0x03
line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235  ,CPU Targets Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO234  ,CPU Targets Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO233  ,CPU Targets Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO232  ,CPU Targets Byte Offset 232 "
group.long 0x8EC++0x03
line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239  ,CPU Targets Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO238  ,CPU Targets Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO237  ,CPU Targets Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO236  ,CPU Targets Byte Offset 236 "
group.long 0x8F0++0x03
line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243  ,CPU Targets Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO242  ,CPU Targets Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO241  ,CPU Targets Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO240  ,CPU Targets Byte Offset 240 "
group.long 0x8F4++0x03
line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247  ,CPU Targets Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO246  ,CPU Targets Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO245  ,CPU Targets Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO244  ,CPU Targets Byte Offset 244 "
group.long 0x8F8++0x03
line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251  ,CPU Targets Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO250  ,CPU Targets Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO249  ,CPU Targets Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO248  ,CPU Targets Byte Offset 248 "
group.long 0x8FC++0x03
line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255  ,CPU Targets Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO254  ,CPU Targets Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO253  ,CPU Targets Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO252  ,CPU Targets Byte Offset 252 "
else
hgroup.long 0x8E0++0x03
hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
hgroup.long 0x8E4++0x03
hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
hgroup.long 0x8E8++0x03
hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
hgroup.long 0x8EC++0x03
hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
hgroup.long 0x8F0++0x03
hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
hgroup.long 0x8F4++0x03
hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
hgroup.long 0x8F8++0x03
hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
hgroup.long 0x8FC++0x03
hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x900++0x03
line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259  ,CPU Targets Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO258  ,CPU Targets Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO257  ,CPU Targets Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO256  ,CPU Targets Byte Offset 256 "
group.long 0x904++0x03
line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263  ,CPU Targets Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO262  ,CPU Targets Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO261  ,CPU Targets Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO260  ,CPU Targets Byte Offset 260 "
group.long 0x908++0x03
line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267  ,CPU Targets Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO266  ,CPU Targets Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO265  ,CPU Targets Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO264  ,CPU Targets Byte Offset 264 "
group.long 0x90C++0x03
line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271  ,CPU Targets Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO270  ,CPU Targets Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO269  ,CPU Targets Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO268  ,CPU Targets Byte Offset 268 "
group.long 0x910++0x03
line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275  ,CPU Targets Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO274  ,CPU Targets Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO273  ,CPU Targets Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO272  ,CPU Targets Byte Offset 272 "
group.long 0x914++0x03
line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279  ,CPU Targets Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO278  ,CPU Targets Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO277  ,CPU Targets Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO276  ,CPU Targets Byte Offset 276 "
group.long 0x918++0x03
line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283  ,CPU Targets Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO282  ,CPU Targets Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO281  ,CPU Targets Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO280  ,CPU Targets Byte Offset 280 "
group.long 0x91C++0x03
line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287  ,CPU Targets Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO286  ,CPU Targets Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO285  ,CPU Targets Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO284  ,CPU Targets Byte Offset 284 "
else
hgroup.long 0x900++0x03
hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
hgroup.long 0x904++0x03
hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
hgroup.long 0x908++0x03
hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
hgroup.long 0x90C++0x03
hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
hgroup.long 0x910++0x03
hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
hgroup.long 0x914++0x03
hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
hgroup.long 0x918++0x03
hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
hgroup.long 0x91C++0x03
hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x920++0x03
line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291  ,CPU Targets Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO290  ,CPU Targets Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO289  ,CPU Targets Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO288  ,CPU Targets Byte Offset 288 "
group.long 0x924++0x03
line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295  ,CPU Targets Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO294  ,CPU Targets Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO293  ,CPU Targets Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO292  ,CPU Targets Byte Offset 292 "
group.long 0x928++0x03
line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299  ,CPU Targets Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO298  ,CPU Targets Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO297  ,CPU Targets Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO296  ,CPU Targets Byte Offset 296 "
group.long 0x92C++0x03
line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303  ,CPU Targets Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO302  ,CPU Targets Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO301  ,CPU Targets Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO300  ,CPU Targets Byte Offset 300 "
group.long 0x930++0x03
line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307  ,CPU Targets Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO306  ,CPU Targets Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO305  ,CPU Targets Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO304  ,CPU Targets Byte Offset 304 "
group.long 0x934++0x03
line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311  ,CPU Targets Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO310  ,CPU Targets Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO309  ,CPU Targets Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO308  ,CPU Targets Byte Offset 308 "
group.long 0x938++0x03
line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315  ,CPU Targets Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO314  ,CPU Targets Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO313  ,CPU Targets Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO312  ,CPU Targets Byte Offset 312 "
group.long 0x93C++0x03
line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319  ,CPU Targets Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO318  ,CPU Targets Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO317  ,CPU Targets Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO316  ,CPU Targets Byte Offset 316 "
else
hgroup.long 0x920++0x03
hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
hgroup.long 0x924++0x03
hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
hgroup.long 0x928++0x03
hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
hgroup.long 0x92C++0x03
hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
hgroup.long 0x930++0x03
hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
hgroup.long 0x934++0x03
hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
hgroup.long 0x938++0x03
hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
hgroup.long 0x93C++0x03
hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x940++0x03
line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323  ,CPU Targets Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO322  ,CPU Targets Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO321  ,CPU Targets Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO320  ,CPU Targets Byte Offset 320 "
group.long 0x944++0x03
line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327  ,CPU Targets Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO326  ,CPU Targets Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO325  ,CPU Targets Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO324  ,CPU Targets Byte Offset 324 "
group.long 0x948++0x03
line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331  ,CPU Targets Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO330  ,CPU Targets Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO329  ,CPU Targets Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO328  ,CPU Targets Byte Offset 328 "
group.long 0x94C++0x03
line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335  ,CPU Targets Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO334  ,CPU Targets Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO333  ,CPU Targets Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO332  ,CPU Targets Byte Offset 332 "
group.long 0x950++0x03
line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339  ,CPU Targets Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO338  ,CPU Targets Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO337  ,CPU Targets Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO336  ,CPU Targets Byte Offset 336 "
group.long 0x954++0x03
line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343  ,CPU Targets Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO342  ,CPU Targets Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO341  ,CPU Targets Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO340  ,CPU Targets Byte Offset 340 "
group.long 0x958++0x03
line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347  ,CPU Targets Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO346  ,CPU Targets Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO345  ,CPU Targets Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO344  ,CPU Targets Byte Offset 344 "
group.long 0x95C++0x03
line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351  ,CPU Targets Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO350  ,CPU Targets Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO349  ,CPU Targets Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO348  ,CPU Targets Byte Offset 348 "
else
hgroup.long 0x940++0x03
hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
hgroup.long 0x944++0x03
hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
hgroup.long 0x948++0x03
hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
hgroup.long 0x94C++0x03
hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
hgroup.long 0x950++0x03
hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
hgroup.long 0x954++0x03
hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
hgroup.long 0x958++0x03
hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
hgroup.long 0x95C++0x03
hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x960++0x03
line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355  ,CPU Targets Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO354  ,CPU Targets Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO353  ,CPU Targets Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO352  ,CPU Targets Byte Offset 352 "
group.long 0x964++0x03
line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359  ,CPU Targets Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO358  ,CPU Targets Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO357  ,CPU Targets Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO356  ,CPU Targets Byte Offset 356 "
group.long 0x968++0x03
line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363  ,CPU Targets Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO362  ,CPU Targets Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO361  ,CPU Targets Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO360  ,CPU Targets Byte Offset 360 "
group.long 0x96C++0x03
line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367  ,CPU Targets Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO366  ,CPU Targets Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO365  ,CPU Targets Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO364  ,CPU Targets Byte Offset 364 "
group.long 0x970++0x03
line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371  ,CPU Targets Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO370  ,CPU Targets Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO369  ,CPU Targets Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO368  ,CPU Targets Byte Offset 368 "
group.long 0x974++0x03
line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375  ,CPU Targets Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO374  ,CPU Targets Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO373  ,CPU Targets Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO372  ,CPU Targets Byte Offset 372 "
group.long 0x978++0x03
line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379  ,CPU Targets Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO378  ,CPU Targets Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO377  ,CPU Targets Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO376  ,CPU Targets Byte Offset 376 "
group.long 0x97C++0x03
line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383  ,CPU Targets Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO382  ,CPU Targets Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO381  ,CPU Targets Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO380  ,CPU Targets Byte Offset 380 "
else
hgroup.long 0x960++0x03
hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
hgroup.long 0x964++0x03
hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
hgroup.long 0x968++0x03
hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
hgroup.long 0x96C++0x03
hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
hgroup.long 0x970++0x03
hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
hgroup.long 0x974++0x03
hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
hgroup.long 0x978++0x03
hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
hgroup.long 0x97C++0x03
hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x980++0x03
line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387  ,CPU Targets Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO386  ,CPU Targets Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO385  ,CPU Targets Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO384  ,CPU Targets Byte Offset 384 "
group.long 0x984++0x03
line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391  ,CPU Targets Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO390  ,CPU Targets Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO389  ,CPU Targets Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO388  ,CPU Targets Byte Offset 388 "
group.long 0x988++0x03
line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395  ,CPU Targets Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO394  ,CPU Targets Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO393  ,CPU Targets Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO392  ,CPU Targets Byte Offset 392 "
group.long 0x98C++0x03
line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399  ,CPU Targets Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO398  ,CPU Targets Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO397  ,CPU Targets Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO396  ,CPU Targets Byte Offset 396 "
group.long 0x990++0x03
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403  ,CPU Targets Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO402  ,CPU Targets Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO401  ,CPU Targets Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO400  ,CPU Targets Byte Offset 400 "
group.long 0x994++0x03
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407  ,CPU Targets Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO406  ,CPU Targets Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO405  ,CPU Targets Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO404  ,CPU Targets Byte Offset 404 "
group.long 0x998++0x03
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411  ,CPU Targets Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO410  ,CPU Targets Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO409  ,CPU Targets Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO408  ,CPU Targets Byte Offset 408 "
group.long 0x99C++0x03
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415  ,CPU Targets Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO414  ,CPU Targets Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO413  ,CPU Targets Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO412  ,CPU Targets Byte Offset 412 "
else
hgroup.long 0x980++0x03
hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
hgroup.long 0x984++0x03
hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
hgroup.long 0x988++0x03
hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
hgroup.long 0x98C++0x03
hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
hgroup.long 0x990++0x03
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hgroup.long 0x994++0x03
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hgroup.long 0x998++0x03
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hgroup.long 0x99C++0x03
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x9A0++0x03
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419  ,CPU Targets Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO418  ,CPU Targets Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO417  ,CPU Targets Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO416  ,CPU Targets Byte Offset 416 "
group.long 0x9A4++0x03
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423  ,CPU Targets Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO422  ,CPU Targets Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO421  ,CPU Targets Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO420  ,CPU Targets Byte Offset 420 "
group.long 0x9A8++0x03
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427  ,CPU Targets Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO426  ,CPU Targets Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO425  ,CPU Targets Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO424  ,CPU Targets Byte Offset 424 "
group.long 0x9AC++0x03
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431  ,CPU Targets Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO430  ,CPU Targets Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO429  ,CPU Targets Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO428  ,CPU Targets Byte Offset 428 "
group.long 0x9B0++0x03
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435  ,CPU Targets Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO434  ,CPU Targets Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO433  ,CPU Targets Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO432  ,CPU Targets Byte Offset 432 "
group.long 0x9B4++0x03
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439  ,CPU Targets Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO438  ,CPU Targets Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO437  ,CPU Targets Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO436  ,CPU Targets Byte Offset 436 "
group.long 0x9B8++0x03
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443  ,CPU Targets Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO442  ,CPU Targets Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO441  ,CPU Targets Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO440  ,CPU Targets Byte Offset 440 "
group.long 0x9BC++0x03
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447  ,CPU Targets Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO446  ,CPU Targets Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO445  ,CPU Targets Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO444  ,CPU Targets Byte Offset 444 "
else
hgroup.long 0x9A0++0x03
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hgroup.long 0x9A4++0x03
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hgroup.long 0x9A8++0x03
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hgroup.long 0x9AC++0x03
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hgroup.long 0x9B0++0x03
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hgroup.long 0x9B4++0x03
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hgroup.long 0x9B8++0x03
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hgroup.long 0x9BC++0x03
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x9C0++0x03
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451  ,CPU Targets Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO450  ,CPU Targets Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO449  ,CPU Targets Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO448  ,CPU Targets Byte Offset 448 "
group.long 0x9C4++0x03
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455  ,CPU Targets Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO454  ,CPU Targets Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO453  ,CPU Targets Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO452  ,CPU Targets Byte Offset 452 "
group.long 0x9C8++0x03
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459  ,CPU Targets Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO458  ,CPU Targets Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO457  ,CPU Targets Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO456  ,CPU Targets Byte Offset 456 "
group.long 0x9CC++0x03
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463  ,CPU Targets Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO462  ,CPU Targets Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO461  ,CPU Targets Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO460  ,CPU Targets Byte Offset 460 "
group.long 0x9D0++0x03
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467  ,CPU Targets Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO466  ,CPU Targets Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO465  ,CPU Targets Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO464  ,CPU Targets Byte Offset 464 "
group.long 0x9D4++0x03
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471  ,CPU Targets Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO470  ,CPU Targets Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO469  ,CPU Targets Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO468  ,CPU Targets Byte Offset 468 "
group.long 0x9D8++0x03
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475  ,CPU Targets Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO474  ,CPU Targets Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO473  ,CPU Targets Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO472  ,CPU Targets Byte Offset 472 "
group.long 0x9DC++0x03
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479  ,CPU Targets Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO478  ,CPU Targets Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO477  ,CPU Targets Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO476  ,CPU Targets Byte Offset 476 "
else
hgroup.long 0x9C0++0x03
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hgroup.long 0x9C4++0x03
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hgroup.long 0x9C8++0x03
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hgroup.long 0x9CC++0x03
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hgroup.long 0x9D0++0x03
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hgroup.long 0x9D4++0x03
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hgroup.long 0x9D8++0x03
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hgroup.long 0x9DC++0x03
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x9E0++0x03
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483  ,CPU Targets Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO482  ,CPU Targets Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO481  ,CPU Targets Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO480  ,CPU Targets Byte Offset 480 "
group.long 0x9E4++0x03
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487  ,CPU Targets Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO486  ,CPU Targets Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO485  ,CPU Targets Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO484  ,CPU Targets Byte Offset 484 "
group.long 0x9E8++0x03
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491  ,CPU Targets Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO490  ,CPU Targets Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO489  ,CPU Targets Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO488  ,CPU Targets Byte Offset 488 "
group.long 0x9EC++0x03
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495  ,CPU Targets Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO494  ,CPU Targets Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO493  ,CPU Targets Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO492  ,CPU Targets Byte Offset 492 "
group.long 0x9F0++0x03
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499  ,CPU Targets Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO498  ,CPU Targets Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO497  ,CPU Targets Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO496  ,CPU Targets Byte Offset 496 "
group.long 0x9F4++0x03
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503  ,CPU Targets Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO502  ,CPU Targets Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO501  ,CPU Targets Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO500  ,CPU Targets Byte Offset 500 "
group.long 0x9F8++0x03
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507  ,CPU Targets Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO506  ,CPU Targets Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO505  ,CPU Targets Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO504  ,CPU Targets Byte Offset 504 "
group.long 0x9FC++0x03
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511  ,CPU Targets Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO510  ,CPU Targets Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO509  ,CPU Targets Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO508  ,CPU Targets Byte Offset 508 "
else
hgroup.long 0x9E0++0x03
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hgroup.long 0x9E4++0x03
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hgroup.long 0x9E8++0x03
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hgroup.long 0x9EC++0x03
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hgroup.long 0x9F0++0x03
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hgroup.long 0x9F4++0x03
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hgroup.long 0x9F8++0x03
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hgroup.long 0x9FC++0x03
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0xA00++0x03
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515  ,CPU Targets Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO514  ,CPU Targets Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO513  ,CPU Targets Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO512  ,CPU Targets Byte Offset 512 "
group.long 0xA04++0x03
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519  ,CPU Targets Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO518  ,CPU Targets Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO517  ,CPU Targets Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO516  ,CPU Targets Byte Offset 516 "
group.long 0xA08++0x03
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523  ,CPU Targets Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO522  ,CPU Targets Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO521  ,CPU Targets Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO520  ,CPU Targets Byte Offset 520 "
group.long 0xA0C++0x03
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527  ,CPU Targets Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO526  ,CPU Targets Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO525  ,CPU Targets Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO524  ,CPU Targets Byte Offset 524 "
group.long 0xA10++0x03
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531  ,CPU Targets Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO530  ,CPU Targets Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO529  ,CPU Targets Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO528  ,CPU Targets Byte Offset 528 "
group.long 0xA14++0x03
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535  ,CPU Targets Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO534  ,CPU Targets Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO533  ,CPU Targets Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO532  ,CPU Targets Byte Offset 532 "
group.long 0xA18++0x03
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539  ,CPU Targets Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO538  ,CPU Targets Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO537  ,CPU Targets Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO536  ,CPU Targets Byte Offset 536 "
group.long 0xA1C++0x03
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543  ,CPU Targets Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO542  ,CPU Targets Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO541  ,CPU Targets Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO540  ,CPU Targets Byte Offset 540 "
else
hgroup.long 0xA00++0x03
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hgroup.long 0xA04++0x03
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hgroup.long 0xA08++0x03
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hgroup.long 0xA0C++0x03
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hgroup.long 0xA10++0x03
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hgroup.long 0xA14++0x03
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hgroup.long 0xA18++0x03
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hgroup.long 0xA1C++0x03
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0xA20++0x03
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547  ,CPU Targets Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO546  ,CPU Targets Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO545  ,CPU Targets Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO544  ,CPU Targets Byte Offset 544 "
group.long 0xA24++0x03
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551  ,CPU Targets Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO550  ,CPU Targets Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO549  ,CPU Targets Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO548  ,CPU Targets Byte Offset 548 "
group.long 0xA28++0x03
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555  ,CPU Targets Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO554  ,CPU Targets Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO553  ,CPU Targets Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO552  ,CPU Targets Byte Offset 552 "
group.long 0xA2C++0x03
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559  ,CPU Targets Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO558  ,CPU Targets Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO557  ,CPU Targets Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO556  ,CPU Targets Byte Offset 556 "
group.long 0xA30++0x03
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563  ,CPU Targets Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO562  ,CPU Targets Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO561  ,CPU Targets Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO560  ,CPU Targets Byte Offset 560 "
group.long 0xA34++0x03
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567  ,CPU Targets Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO566  ,CPU Targets Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO565  ,CPU Targets Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO564  ,CPU Targets Byte Offset 564 "
group.long 0xA38++0x03
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571  ,CPU Targets Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO570  ,CPU Targets Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO569  ,CPU Targets Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO568  ,CPU Targets Byte Offset 568 "
group.long 0xA3C++0x03
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575  ,CPU Targets Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO574  ,CPU Targets Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO573  ,CPU Targets Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO572  ,CPU Targets Byte Offset 572 "
else
hgroup.long 0xA20++0x03
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hgroup.long 0xA24++0x03
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hgroup.long 0xA28++0x03
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hgroup.long 0xA2C++0x03
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hgroup.long 0xA30++0x03
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hgroup.long 0xA34++0x03
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hgroup.long 0xA38++0x03
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hgroup.long 0xA3C++0x03
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0xA40++0x03
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579  ,CPU Targets Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO578  ,CPU Targets Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO577  ,CPU Targets Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO576  ,CPU Targets Byte Offset 576 "
group.long 0xA44++0x03
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583  ,CPU Targets Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO582  ,CPU Targets Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO581  ,CPU Targets Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO580  ,CPU Targets Byte Offset 580 "
group.long 0xA48++0x03
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587  ,CPU Targets Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO586  ,CPU Targets Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO585  ,CPU Targets Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO584  ,CPU Targets Byte Offset 584 "
group.long 0xA4C++0x03
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591  ,CPU Targets Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO590  ,CPU Targets Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO589  ,CPU Targets Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO588  ,CPU Targets Byte Offset 588 "
group.long 0xA50++0x03
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595  ,CPU Targets Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO594  ,CPU Targets Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO593  ,CPU Targets Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO592  ,CPU Targets Byte Offset 592 "
group.long 0xA54++0x03
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599  ,CPU Targets Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO598  ,CPU Targets Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO597  ,CPU Targets Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO596  ,CPU Targets Byte Offset 596 "
group.long 0xA58++0x03
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603  ,CPU Targets Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO602  ,CPU Targets Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO601  ,CPU Targets Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO600  ,CPU Targets Byte Offset 600 "
group.long 0xA5C++0x03
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607  ,CPU Targets Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO606  ,CPU Targets Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO605  ,CPU Targets Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO604  ,CPU Targets Byte Offset 604 "
else
hgroup.long 0xA40++0x03
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hgroup.long 0xA44++0x03
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hgroup.long 0xA48++0x03
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hgroup.long 0xA4C++0x03
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hgroup.long 0xA50++0x03
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hgroup.long 0xA54++0x03
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hgroup.long 0xA58++0x03
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hgroup.long 0xA5C++0x03
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0xA60++0x03
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611  ,CPU Targets Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO610  ,CPU Targets Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO609  ,CPU Targets Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO608  ,CPU Targets Byte Offset 608 "
group.long 0xA64++0x03
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615  ,CPU Targets Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO614  ,CPU Targets Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO613  ,CPU Targets Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO612  ,CPU Targets Byte Offset 612 "
group.long 0xA68++0x03
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619  ,CPU Targets Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO618  ,CPU Targets Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO617  ,CPU Targets Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO616  ,CPU Targets Byte Offset 616 "
group.long 0xA6C++0x03
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623  ,CPU Targets Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO622  ,CPU Targets Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO621  ,CPU Targets Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO620  ,CPU Targets Byte Offset 620 "
group.long 0xA70++0x03
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627  ,CPU Targets Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO626  ,CPU Targets Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO625  ,CPU Targets Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO624  ,CPU Targets Byte Offset 624 "
group.long 0xA74++0x03
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631  ,CPU Targets Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO630  ,CPU Targets Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO629  ,CPU Targets Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO628  ,CPU Targets Byte Offset 628 "
group.long 0xA78++0x03
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635  ,CPU Targets Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO634  ,CPU Targets Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO633  ,CPU Targets Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO632  ,CPU Targets Byte Offset 632 "
group.long 0xA7C++0x03
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639  ,CPU Targets Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO638  ,CPU Targets Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO637  ,CPU Targets Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO636  ,CPU Targets Byte Offset 636 "
else
hgroup.long 0xA60++0x03
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hgroup.long 0xA64++0x03
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hgroup.long 0xA68++0x03
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hgroup.long 0xA6C++0x03
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hgroup.long 0xA70++0x03
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hgroup.long 0xA74++0x03
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hgroup.long 0xA78++0x03
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hgroup.long 0xA7C++0x03
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0xA80++0x03
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643  ,CPU Targets Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO642  ,CPU Targets Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO641  ,CPU Targets Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO640  ,CPU Targets Byte Offset 640 "
group.long 0xA84++0x03
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647  ,CPU Targets Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO646  ,CPU Targets Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO645  ,CPU Targets Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO644  ,CPU Targets Byte Offset 644 "
group.long 0xA88++0x03
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651  ,CPU Targets Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO650  ,CPU Targets Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO649  ,CPU Targets Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO648  ,CPU Targets Byte Offset 648 "
group.long 0xA8C++0x03
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655  ,CPU Targets Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO654  ,CPU Targets Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO653  ,CPU Targets Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO652  ,CPU Targets Byte Offset 652 "
group.long 0xA90++0x03
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659  ,CPU Targets Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO658  ,CPU Targets Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO657  ,CPU Targets Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO656  ,CPU Targets Byte Offset 656 "
group.long 0xA94++0x03
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663  ,CPU Targets Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO662  ,CPU Targets Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO661  ,CPU Targets Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO660  ,CPU Targets Byte Offset 660 "
group.long 0xA98++0x03
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667  ,CPU Targets Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO666  ,CPU Targets Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO665  ,CPU Targets Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO664  ,CPU Targets Byte Offset 664 "
group.long 0xA9C++0x03
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671  ,CPU Targets Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO670  ,CPU Targets Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO669  ,CPU Targets Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO668  ,CPU Targets Byte Offset 668 "
else
hgroup.long 0xA80++0x03
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hgroup.long 0xA84++0x03
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hgroup.long 0xA88++0x03
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hgroup.long 0xA8C++0x03
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hgroup.long 0xA90++0x03
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hgroup.long 0xA94++0x03
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hgroup.long 0xA98++0x03
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hgroup.long 0xA9C++0x03
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0xAA0++0x03
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675  ,CPU Targets Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO674  ,CPU Targets Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO673  ,CPU Targets Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO672  ,CPU Targets Byte Offset 672 "
group.long 0xAA4++0x03
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679  ,CPU Targets Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO678  ,CPU Targets Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO677  ,CPU Targets Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO676  ,CPU Targets Byte Offset 676 "
group.long 0xAA8++0x03
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683  ,CPU Targets Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO682  ,CPU Targets Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO681  ,CPU Targets Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO680  ,CPU Targets Byte Offset 680 "
group.long 0xAAC++0x03
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687  ,CPU Targets Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO686  ,CPU Targets Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO685  ,CPU Targets Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO684  ,CPU Targets Byte Offset 684 "
group.long 0xAB0++0x03
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691  ,CPU Targets Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO690  ,CPU Targets Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO689  ,CPU Targets Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO688  ,CPU Targets Byte Offset 688 "
group.long 0xAB4++0x03
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695  ,CPU Targets Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO694  ,CPU Targets Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO693  ,CPU Targets Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO692  ,CPU Targets Byte Offset 692 "
group.long 0xAB8++0x03
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699  ,CPU Targets Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO698  ,CPU Targets Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO697  ,CPU Targets Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO696  ,CPU Targets Byte Offset 696 "
group.long 0xABC++0x03
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703  ,CPU Targets Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO702  ,CPU Targets Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO701  ,CPU Targets Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO700  ,CPU Targets Byte Offset 700 "
else
hgroup.long 0xAA0++0x03
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hgroup.long 0xAA4++0x03
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hgroup.long 0xAA8++0x03
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hgroup.long 0xAAC++0x03
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hgroup.long 0xAB0++0x03
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hgroup.long 0xAB4++0x03
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hgroup.long 0xAB8++0x03
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hgroup.long 0xABC++0x03
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0xAC0++0x03
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707  ,CPU Targets Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO706  ,CPU Targets Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO705  ,CPU Targets Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO704  ,CPU Targets Byte Offset 704 "
group.long 0xAC4++0x03
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711  ,CPU Targets Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO710  ,CPU Targets Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO709  ,CPU Targets Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO708  ,CPU Targets Byte Offset 708 "
group.long 0xAC8++0x03
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715  ,CPU Targets Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO714  ,CPU Targets Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO713  ,CPU Targets Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO712  ,CPU Targets Byte Offset 712 "
group.long 0xACC++0x03
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719  ,CPU Targets Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO718  ,CPU Targets Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO717  ,CPU Targets Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO716  ,CPU Targets Byte Offset 716 "
group.long 0xAD0++0x03
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723  ,CPU Targets Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO722  ,CPU Targets Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO721  ,CPU Targets Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO720  ,CPU Targets Byte Offset 720 "
group.long 0xAD4++0x03
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727  ,CPU Targets Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO726  ,CPU Targets Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO725  ,CPU Targets Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO724  ,CPU Targets Byte Offset 724 "
group.long 0xAD8++0x03
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731  ,CPU Targets Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO730  ,CPU Targets Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO729  ,CPU Targets Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO728  ,CPU Targets Byte Offset 728 "
group.long 0xADC++0x03
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735  ,CPU Targets Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO734  ,CPU Targets Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO733  ,CPU Targets Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO732  ,CPU Targets Byte Offset 732 "
else
hgroup.long 0xAC0++0x03
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hgroup.long 0xAC4++0x03
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hgroup.long 0xAC8++0x03
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hgroup.long 0xACC++0x03
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hgroup.long 0xAD0++0x03
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hgroup.long 0xAD4++0x03
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hgroup.long 0xAD8++0x03
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hgroup.long 0xADC++0x03
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0xAE0++0x03
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739  ,CPU Targets Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO738  ,CPU Targets Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO737  ,CPU Targets Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO736  ,CPU Targets Byte Offset 736 "
group.long 0xAE4++0x03
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743  ,CPU Targets Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO742  ,CPU Targets Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO741  ,CPU Targets Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO740  ,CPU Targets Byte Offset 740 "
group.long 0xAE8++0x03
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747  ,CPU Targets Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO746  ,CPU Targets Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO745  ,CPU Targets Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO744  ,CPU Targets Byte Offset 744 "
group.long 0xAEC++0x03
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751  ,CPU Targets Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO750  ,CPU Targets Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO749  ,CPU Targets Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO748  ,CPU Targets Byte Offset 748 "
group.long 0xAF0++0x03
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755  ,CPU Targets Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO754  ,CPU Targets Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO753  ,CPU Targets Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO752  ,CPU Targets Byte Offset 752 "
group.long 0xAF4++0x03
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759  ,CPU Targets Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO758  ,CPU Targets Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO757  ,CPU Targets Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO756  ,CPU Targets Byte Offset 756 "
group.long 0xAF8++0x03
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763  ,CPU Targets Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO762  ,CPU Targets Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO761  ,CPU Targets Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO760  ,CPU Targets Byte Offset 760 "
group.long 0xAFC++0x03
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767  ,CPU Targets Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO766  ,CPU Targets Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO765  ,CPU Targets Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO764  ,CPU Targets Byte Offset 764 "
else
hgroup.long 0xAE0++0x03
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hgroup.long 0xAE4++0x03
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hgroup.long 0xAE8++0x03
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hgroup.long 0xAEC++0x03
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hgroup.long 0xAF0++0x03
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hgroup.long 0xAF4++0x03
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hgroup.long 0xAF8++0x03
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hgroup.long 0xAFC++0x03
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0xB00++0x03
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771  ,CPU Targets Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO770  ,CPU Targets Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO769  ,CPU Targets Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO768  ,CPU Targets Byte Offset 768 "
group.long 0xB04++0x03
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775  ,CPU Targets Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO774  ,CPU Targets Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO773  ,CPU Targets Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO772  ,CPU Targets Byte Offset 772 "
group.long 0xB08++0x03
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779  ,CPU Targets Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO778  ,CPU Targets Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO777  ,CPU Targets Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO776  ,CPU Targets Byte Offset 776 "
group.long 0xB0C++0x03
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783  ,CPU Targets Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO782  ,CPU Targets Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO781  ,CPU Targets Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO780  ,CPU Targets Byte Offset 780 "
group.long 0xB10++0x03
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787  ,CPU Targets Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO786  ,CPU Targets Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO785  ,CPU Targets Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO784  ,CPU Targets Byte Offset 784 "
group.long 0xB14++0x03
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791  ,CPU Targets Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO790  ,CPU Targets Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO789  ,CPU Targets Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO788  ,CPU Targets Byte Offset 788 "
group.long 0xB18++0x03
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795  ,CPU Targets Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO794  ,CPU Targets Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO793  ,CPU Targets Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO792  ,CPU Targets Byte Offset 792 "
group.long 0xB1C++0x03
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799  ,CPU Targets Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO798  ,CPU Targets Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO797  ,CPU Targets Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO796  ,CPU Targets Byte Offset 796 "
else
hgroup.long 0xB00++0x03
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hgroup.long 0xB04++0x03
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hgroup.long 0xB08++0x03
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hgroup.long 0xB0C++0x03
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hgroup.long 0xB10++0x03
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hgroup.long 0xB14++0x03
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hgroup.long 0xB18++0x03
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hgroup.long 0xB1C++0x03
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0xB20++0x03
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803  ,CPU Targets Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO802  ,CPU Targets Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO801  ,CPU Targets Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO800  ,CPU Targets Byte Offset 800 "
group.long 0xB24++0x03
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807  ,CPU Targets Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO806  ,CPU Targets Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO805  ,CPU Targets Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO804  ,CPU Targets Byte Offset 804 "
group.long 0xB28++0x03
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811  ,CPU Targets Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO810  ,CPU Targets Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO809  ,CPU Targets Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO808  ,CPU Targets Byte Offset 808 "
group.long 0xB2C++0x03
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815  ,CPU Targets Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO814  ,CPU Targets Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO813  ,CPU Targets Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO812  ,CPU Targets Byte Offset 812 "
group.long 0xB30++0x03
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819  ,CPU Targets Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO818  ,CPU Targets Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO817  ,CPU Targets Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO816  ,CPU Targets Byte Offset 816 "
group.long 0xB34++0x03
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823  ,CPU Targets Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO822  ,CPU Targets Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO821  ,CPU Targets Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO820  ,CPU Targets Byte Offset 820 "
group.long 0xB38++0x03
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827  ,CPU Targets Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO826  ,CPU Targets Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO825  ,CPU Targets Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO824  ,CPU Targets Byte Offset 824 "
group.long 0xB3C++0x03
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831  ,CPU Targets Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO830  ,CPU Targets Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO829  ,CPU Targets Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO828  ,CPU Targets Byte Offset 828 "
else
hgroup.long 0xB20++0x03
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hgroup.long 0xB24++0x03
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hgroup.long 0xB28++0x03
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hgroup.long 0xB2C++0x03
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hgroup.long 0xB30++0x03
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hgroup.long 0xB34++0x03
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hgroup.long 0xB38++0x03
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hgroup.long 0xB3C++0x03
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0xB40++0x03
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835  ,CPU Targets Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO834  ,CPU Targets Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO833  ,CPU Targets Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO832  ,CPU Targets Byte Offset 832 "
group.long 0xB44++0x03
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839  ,CPU Targets Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO838  ,CPU Targets Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO837  ,CPU Targets Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO836  ,CPU Targets Byte Offset 836 "
group.long 0xB48++0x03
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843  ,CPU Targets Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO842  ,CPU Targets Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO841  ,CPU Targets Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO840  ,CPU Targets Byte Offset 840 "
group.long 0xB4C++0x03
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847  ,CPU Targets Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO846  ,CPU Targets Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO845  ,CPU Targets Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO844  ,CPU Targets Byte Offset 844 "
group.long 0xB50++0x03
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851  ,CPU Targets Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO850  ,CPU Targets Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO849  ,CPU Targets Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO848  ,CPU Targets Byte Offset 848 "
group.long 0xB54++0x03
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855  ,CPU Targets Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO854  ,CPU Targets Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO853  ,CPU Targets Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO852  ,CPU Targets Byte Offset 852 "
group.long 0xB58++0x03
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859  ,CPU Targets Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO858  ,CPU Targets Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO857  ,CPU Targets Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO856  ,CPU Targets Byte Offset 856 "
group.long 0xB5C++0x03
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863  ,CPU Targets Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO862  ,CPU Targets Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO861  ,CPU Targets Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO860  ,CPU Targets Byte Offset 860 "
else
hgroup.long 0xB40++0x03
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hgroup.long 0xB44++0x03
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hgroup.long 0xB48++0x03
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hgroup.long 0xB4C++0x03
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hgroup.long 0xB50++0x03
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hgroup.long 0xB54++0x03
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hgroup.long 0xB58++0x03
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hgroup.long 0xB5C++0x03
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0xB60++0x03
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867  ,CPU Targets Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO866  ,CPU Targets Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO865  ,CPU Targets Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO864  ,CPU Targets Byte Offset 864 "
group.long 0xB64++0x03
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871  ,CPU Targets Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO870  ,CPU Targets Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO869  ,CPU Targets Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO868  ,CPU Targets Byte Offset 868 "
group.long 0xB68++0x03
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875  ,CPU Targets Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO874  ,CPU Targets Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO873  ,CPU Targets Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO872  ,CPU Targets Byte Offset 872 "
group.long 0xB6C++0x03
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879  ,CPU Targets Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO878  ,CPU Targets Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO877  ,CPU Targets Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO876  ,CPU Targets Byte Offset 876 "
group.long 0xB70++0x03
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883  ,CPU Targets Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO882  ,CPU Targets Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO881  ,CPU Targets Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO880  ,CPU Targets Byte Offset 880 "
group.long 0xB74++0x03
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887  ,CPU Targets Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO886  ,CPU Targets Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO885  ,CPU Targets Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO884  ,CPU Targets Byte Offset 884 "
group.long 0xB78++0x03
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891  ,CPU Targets Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO890  ,CPU Targets Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO889  ,CPU Targets Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO888  ,CPU Targets Byte Offset 888 "
group.long 0xB7C++0x03
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895  ,CPU Targets Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO894  ,CPU Targets Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO893  ,CPU Targets Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO892  ,CPU Targets Byte Offset 892 "
else
hgroup.long 0xB60++0x03
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hgroup.long 0xB64++0x03
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hgroup.long 0xB68++0x03
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hgroup.long 0xB6C++0x03
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hgroup.long 0xB70++0x03
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hgroup.long 0xB74++0x03
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hgroup.long 0xB78++0x03
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hgroup.long 0xB7C++0x03
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0xB80++0x03
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899  ,CPU Targets Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO898  ,CPU Targets Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO897  ,CPU Targets Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO896  ,CPU Targets Byte Offset 896 "
group.long 0xB84++0x03
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903  ,CPU Targets Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO902  ,CPU Targets Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO901  ,CPU Targets Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO900  ,CPU Targets Byte Offset 900 "
group.long 0xB88++0x03
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907  ,CPU Targets Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO906  ,CPU Targets Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO905  ,CPU Targets Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO904  ,CPU Targets Byte Offset 904 "
group.long 0xB8C++0x03
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911  ,CPU Targets Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO910  ,CPU Targets Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO909  ,CPU Targets Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO908  ,CPU Targets Byte Offset 908 "
group.long 0xB90++0x03
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915  ,CPU Targets Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO914  ,CPU Targets Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO913  ,CPU Targets Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO912  ,CPU Targets Byte Offset 912 "
group.long 0xB94++0x03
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919  ,CPU Targets Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO918  ,CPU Targets Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO917  ,CPU Targets Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO916  ,CPU Targets Byte Offset 916 "
group.long 0xB98++0x03
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923  ,CPU Targets Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO922  ,CPU Targets Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO921  ,CPU Targets Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO920  ,CPU Targets Byte Offset 920 "
group.long 0xB9C++0x03
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927  ,CPU Targets Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO926  ,CPU Targets Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO925  ,CPU Targets Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO924  ,CPU Targets Byte Offset 924 "
else
hgroup.long 0xB80++0x03
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hgroup.long 0xB84++0x03
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hgroup.long 0xB88++0x03
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hgroup.long 0xB8C++0x03
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hgroup.long 0xB90++0x03
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hgroup.long 0xB94++0x03
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hgroup.long 0xB98++0x03
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hgroup.long 0xB9C++0x03
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0xBA0++0x03
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931  ,CPU Targets Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO930  ,CPU Targets Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO929  ,CPU Targets Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO928  ,CPU Targets Byte Offset 928 "
group.long 0xBA4++0x03
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935  ,CPU Targets Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO934  ,CPU Targets Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO933  ,CPU Targets Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO932  ,CPU Targets Byte Offset 932 "
group.long 0xBA8++0x03
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939  ,CPU Targets Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO938  ,CPU Targets Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO937  ,CPU Targets Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO936  ,CPU Targets Byte Offset 936 "
group.long 0xBAC++0x03
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943  ,CPU Targets Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO942  ,CPU Targets Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO941  ,CPU Targets Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO940  ,CPU Targets Byte Offset 940 "
group.long 0xBB0++0x03
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947  ,CPU Targets Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO946  ,CPU Targets Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO945  ,CPU Targets Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO944  ,CPU Targets Byte Offset 944 "
group.long 0xBB4++0x03
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951  ,CPU Targets Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO950  ,CPU Targets Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO949  ,CPU Targets Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO948  ,CPU Targets Byte Offset 948 "
group.long 0xBB8++0x03
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955  ,CPU Targets Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO954  ,CPU Targets Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO953  ,CPU Targets Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO952  ,CPU Targets Byte Offset 952 "
group.long 0xBBC++0x03
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959  ,CPU Targets Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO958  ,CPU Targets Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO957  ,CPU Targets Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO956  ,CPU Targets Byte Offset 956 "
else
hgroup.long 0xBA0++0x03
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hgroup.long 0xBA4++0x03
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hgroup.long 0xBA8++0x03
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hgroup.long 0xBAC++0x03
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hgroup.long 0xBB0++0x03
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hgroup.long 0xBB4++0x03
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hgroup.long 0xBB8++0x03
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hgroup.long 0xBBC++0x03
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0xBC0++0x03
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963  ,CPU Targets Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO962  ,CPU Targets Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO961  ,CPU Targets Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO960  ,CPU Targets Byte Offset 960 "
group.long 0xBC4++0x03
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967  ,CPU Targets Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO966  ,CPU Targets Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO965  ,CPU Targets Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO964  ,CPU Targets Byte Offset 964 "
group.long 0xBC8++0x03
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971  ,CPU Targets Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO970  ,CPU Targets Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO969  ,CPU Targets Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO968  ,CPU Targets Byte Offset 968 "
group.long 0xBCC++0x03
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975  ,CPU Targets Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO974  ,CPU Targets Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO973  ,CPU Targets Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO972  ,CPU Targets Byte Offset 972 "
group.long 0xBD0++0x03
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979  ,CPU Targets Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO978  ,CPU Targets Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO977  ,CPU Targets Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO976  ,CPU Targets Byte Offset 976 "
group.long 0xBD4++0x03
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983  ,CPU Targets Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO982  ,CPU Targets Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO981  ,CPU Targets Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO980  ,CPU Targets Byte Offset 980 "
group.long 0xBD8++0x03
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987  ,CPU Targets Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO986  ,CPU Targets Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO985  ,CPU Targets Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO984  ,CPU Targets Byte Offset 984 "
group.long 0xBDC++0x03
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991  ,CPU Targets Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO990  ,CPU Targets Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO989  ,CPU Targets Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO988  ,CPU Targets Byte Offset 988 "
else
hgroup.long 0xBC0++0x03
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hgroup.long 0xBC4++0x03
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hgroup.long 0xBC8++0x03
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hgroup.long 0xBCC++0x03
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hgroup.long 0xBD0++0x03
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hgroup.long 0xBD4++0x03
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hgroup.long 0xBD8++0x03
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hgroup.long 0xBDC++0x03
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
endif
else
hgroup.long 0x800++0x03
hide.long 0x00 "GICD_ITARGETSR0  ,Interrupt Processor Targets Register 0  "
hgroup.long 0x804++0x03
hide.long 0x00 "GICD_ITARGETSR1  ,Interrupt Processor Targets Register 1  "
hgroup.long 0x808++0x03
hide.long 0x00 "GICD_ITARGETSR2  ,Interrupt Processor Targets Register 2  "
hgroup.long 0x80C++0x03
hide.long 0x00 "GICD_ITARGETSR3  ,Interrupt Processor Targets Register 3  "
hgroup.long 0x810++0x03
hide.long 0x00 "GICD_ITARGETSR4  ,Interrupt Processor Targets Register 4  "
hgroup.long 0x814++0x03
hide.long 0x00 "GICD_ITARGETSR5  ,Interrupt Processor Targets Register 5  "
hgroup.long 0x818++0x03
hide.long 0x00 "GICD_ITARGETSR6  ,Interrupt Processor Targets Register 6  "
hgroup.long 0x81C++0x03
hide.long 0x00 "GICD_ITARGETSR7  ,Interrupt Processor Targets Register 7  "
hgroup.long 0x820++0x03
hide.long 0x00 "GICD_ITARGETSR8  ,Interrupt Processor Targets Register 8  "
hgroup.long 0x824++0x03
hide.long 0x00 "GICD_ITARGETSR9  ,Interrupt Processor Targets Register 9  "
hgroup.long 0x828++0x03
hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 "
hgroup.long 0x82C++0x03
hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 "
hgroup.long 0x830++0x03
hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 "
hgroup.long 0x834++0x03
hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 "
hgroup.long 0x838++0x03
hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 "
hgroup.long 0x83C++0x03
hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 "
hgroup.long 0x840++0x03
hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 "
hgroup.long 0x844++0x03
hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 "
hgroup.long 0x848++0x03
hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 "
hgroup.long 0x84C++0x03
hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 "
hgroup.long 0x850++0x03
hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 "
hgroup.long 0x854++0x03
hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 "
hgroup.long 0x858++0x03
hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 "
hgroup.long 0x85C++0x03
hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 "
hgroup.long 0x860++0x03
hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 "
hgroup.long 0x864++0x03
hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 "
hgroup.long 0x868++0x03
hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 "
hgroup.long 0x86C++0x03
hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 "
hgroup.long 0x870++0x03
hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 "
hgroup.long 0x874++0x03
hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 "
hgroup.long 0x878++0x03
hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 "
hgroup.long 0x87C++0x03
hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 "
hgroup.long 0x880++0x03
hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 "
hgroup.long 0x884++0x03
hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 "
hgroup.long 0x888++0x03
hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 "
hgroup.long 0x88C++0x03
hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 "
hgroup.long 0x890++0x03
hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 "
hgroup.long 0x894++0x03
hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 "
hgroup.long 0x898++0x03
hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 "
hgroup.long 0x89C++0x03
hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 "
hgroup.long 0x8A0++0x03
hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 "
hgroup.long 0x8A4++0x03
hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 "
hgroup.long 0x8A8++0x03
hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 "
hgroup.long 0x8AC++0x03
hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 "
hgroup.long 0x8B0++0x03
hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 "
hgroup.long 0x8B4++0x03
hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 "
hgroup.long 0x8B8++0x03
hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 "
hgroup.long 0x8BC++0x03
hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 "
hgroup.long 0x8C0++0x03
hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 "
hgroup.long 0x8C4++0x03
hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 "
hgroup.long 0x8C8++0x03
hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 "
hgroup.long 0x8CC++0x03
hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 "
hgroup.long 0x8D0++0x03
hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 "
hgroup.long 0x8D4++0x03
hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 "
hgroup.long 0x8D8++0x03
hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 "
hgroup.long 0x8DC++0x03
hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 "
hgroup.long 0x8E0++0x03
hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 "
hgroup.long 0x8E4++0x03
hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 "
hgroup.long 0x8E8++0x03
hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 "
hgroup.long 0x8EC++0x03
hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 "
hgroup.long 0x8F0++0x03
hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 "
hgroup.long 0x8F4++0x03
hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 "
hgroup.long 0x8F8++0x03
hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 "
hgroup.long 0x8FC++0x03
hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 "
hgroup.long 0x900++0x03
hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 "
hgroup.long 0x904++0x03
hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 "
hgroup.long 0x908++0x03
hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 "
hgroup.long 0x90C++0x03
hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 "
hgroup.long 0x910++0x03
hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 "
hgroup.long 0x914++0x03
hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 "
hgroup.long 0x918++0x03
hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 "
hgroup.long 0x91C++0x03
hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 "
hgroup.long 0x920++0x03
hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 "
hgroup.long 0x924++0x03
hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 "
hgroup.long 0x928++0x03
hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 "
hgroup.long 0x92C++0x03
hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 "
hgroup.long 0x930++0x03
hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 "
hgroup.long 0x934++0x03
hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 "
hgroup.long 0x938++0x03
hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 "
hgroup.long 0x93C++0x03
hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 "
hgroup.long 0x940++0x03
hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 "
hgroup.long 0x944++0x03
hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 "
hgroup.long 0x948++0x03
hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 "
hgroup.long 0x94C++0x03
hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 "
hgroup.long 0x950++0x03
hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 "
hgroup.long 0x954++0x03
hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 "
hgroup.long 0x958++0x03
hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 "
hgroup.long 0x95C++0x03
hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 "
hgroup.long 0x960++0x03
hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 "
hgroup.long 0x964++0x03
hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 "
hgroup.long 0x968++0x03
hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 "
hgroup.long 0x96C++0x03
hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 "
hgroup.long 0x970++0x03
hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 "
hgroup.long 0x974++0x03
hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 "
hgroup.long 0x978++0x03
hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 "
hgroup.long 0x97C++0x03
hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 "
hgroup.long 0x980++0x03
hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 "
hgroup.long 0x984++0x03
hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 "
hgroup.long 0x988++0x03
hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 "
hgroup.long 0x98C++0x03
hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 "
hgroup.long 0x990++0x03
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hgroup.long 0x994++0x03
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hgroup.long 0x998++0x03
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hgroup.long 0x99C++0x03
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
hgroup.long 0x9A0++0x03
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hgroup.long 0x9A4++0x03
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hgroup.long 0x9A8++0x03
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hgroup.long 0x9AC++0x03
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hgroup.long 0x9B0++0x03
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hgroup.long 0x9B4++0x03
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hgroup.long 0x9B8++0x03
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hgroup.long 0x9BC++0x03
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
hgroup.long 0x9C0++0x03
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hgroup.long 0x9C4++0x03
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hgroup.long 0x9C8++0x03
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hgroup.long 0x9CC++0x03
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hgroup.long 0x9D0++0x03
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hgroup.long 0x9D4++0x03
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hgroup.long 0x9D8++0x03
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hgroup.long 0x9DC++0x03
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
hgroup.long 0x9E0++0x03
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hgroup.long 0x9E4++0x03
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hgroup.long 0x9E8++0x03
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hgroup.long 0x9EC++0x03
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hgroup.long 0x9F0++0x03
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hgroup.long 0x9F4++0x03
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hgroup.long 0x9F8++0x03
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hgroup.long 0x9FC++0x03
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
hgroup.long 0xA00++0x03
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hgroup.long 0xA04++0x03
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hgroup.long 0xA08++0x03
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hgroup.long 0xA0C++0x03
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hgroup.long 0xA10++0x03
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hgroup.long 0xA14++0x03
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hgroup.long 0xA18++0x03
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hgroup.long 0xA1C++0x03
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
hgroup.long 0xA20++0x03
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hgroup.long 0xA24++0x03
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hgroup.long 0xA28++0x03
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hgroup.long 0xA2C++0x03
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hgroup.long 0xA30++0x03
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hgroup.long 0xA34++0x03
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hgroup.long 0xA38++0x03
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hgroup.long 0xA3C++0x03
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
hgroup.long 0xA40++0x03
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hgroup.long 0xA44++0x03
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hgroup.long 0xA48++0x03
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hgroup.long 0xA4C++0x03
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hgroup.long 0xA50++0x03
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hgroup.long 0xA54++0x03
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hgroup.long 0xA58++0x03
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hgroup.long 0xA5C++0x03
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
hgroup.long 0xA60++0x03
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hgroup.long 0xA64++0x03
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hgroup.long 0xA68++0x03
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hgroup.long 0xA6C++0x03
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hgroup.long 0xA70++0x03
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hgroup.long 0xA74++0x03
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hgroup.long 0xA78++0x03
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hgroup.long 0xA7C++0x03
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
hgroup.long 0xA80++0x03
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hgroup.long 0xA84++0x03
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hgroup.long 0xA88++0x03
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hgroup.long 0xA8C++0x03
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hgroup.long 0xA90++0x03
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hgroup.long 0xA94++0x03
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hgroup.long 0xA98++0x03
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hgroup.long 0xA9C++0x03
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
hgroup.long 0xAA0++0x03
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hgroup.long 0xAA4++0x03
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hgroup.long 0xAA8++0x03
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hgroup.long 0xAAC++0x03
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hgroup.long 0xAB0++0x03
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hgroup.long 0xAB4++0x03
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hgroup.long 0xAB8++0x03
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hgroup.long 0xABC++0x03
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
hgroup.long 0xAC0++0x03
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hgroup.long 0xAC4++0x03
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hgroup.long 0xAC8++0x03
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hgroup.long 0xACC++0x03
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hgroup.long 0xAD0++0x03
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hgroup.long 0xAD4++0x03
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hgroup.long 0xAD8++0x03
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hgroup.long 0xADC++0x03
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
hgroup.long 0xAE0++0x03
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hgroup.long 0xAE4++0x03
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hgroup.long 0xAE8++0x03
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hgroup.long 0xAEC++0x03
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hgroup.long 0xAF0++0x03
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hgroup.long 0xAF4++0x03
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hgroup.long 0xAF8++0x03
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hgroup.long 0xAFC++0x03
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
hgroup.long 0xB00++0x03
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hgroup.long 0xB04++0x03
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hgroup.long 0xB08++0x03
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hgroup.long 0xB0C++0x03
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hgroup.long 0xB10++0x03
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hgroup.long 0xB14++0x03
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hgroup.long 0xB18++0x03
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hgroup.long 0xB1C++0x03
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
hgroup.long 0xB20++0x03
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hgroup.long 0xB24++0x03
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hgroup.long 0xB28++0x03
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hgroup.long 0xB2C++0x03
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hgroup.long 0xB30++0x03
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hgroup.long 0xB34++0x03
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hgroup.long 0xB38++0x03
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hgroup.long 0xB3C++0x03
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
hgroup.long 0xB40++0x03
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hgroup.long 0xB44++0x03
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hgroup.long 0xB48++0x03
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hgroup.long 0xB4C++0x03
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hgroup.long 0xB50++0x03
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hgroup.long 0xB54++0x03
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hgroup.long 0xB58++0x03
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hgroup.long 0xB5C++0x03
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
hgroup.long 0xB60++0x03
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hgroup.long 0xB64++0x03
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hgroup.long 0xB68++0x03
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hgroup.long 0xB6C++0x03
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hgroup.long 0xB70++0x03
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hgroup.long 0xB74++0x03
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hgroup.long 0xB78++0x03
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hgroup.long 0xB7C++0x03
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
hgroup.long 0xB80++0x03
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hgroup.long 0xB84++0x03
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hgroup.long 0xB88++0x03
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hgroup.long 0xB8C++0x03
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hgroup.long 0xB90++0x03
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hgroup.long 0xB94++0x03
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hgroup.long 0xB98++0x03
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hgroup.long 0xB9C++0x03
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
hgroup.long 0xBA0++0x03
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hgroup.long 0xBA4++0x03
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hgroup.long 0xBA8++0x03
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hgroup.long 0xBAC++0x03
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hgroup.long 0xBB0++0x03
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hgroup.long 0xBB4++0x03
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hgroup.long 0xBB8++0x03
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hgroup.long 0xBBC++0x03
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
hgroup.long 0xBC0++0x03
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hgroup.long 0xBC4++0x03
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hgroup.long 0xBC8++0x03
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hgroup.long 0xBCC++0x03
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hgroup.long 0xBD0++0x03
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hgroup.long 0xBD4++0x03
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hgroup.long 0xBD8++0x03
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hgroup.long 0xBDC++0x03
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
endif
tree.end
width 14.
tree "Configuration Registers"
rgroup.long 0xC00++0x03
line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SGI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SGI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SGI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SGI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SGI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SGI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SGI)" "Level,Edge"
group.long 0xC04++0x03
line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (PPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (PPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (PPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (PPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (PPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (PPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (PPI)" "Level,Edge"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)
group.long 0xC08++0x03
line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC0C++0x03
line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC08++0x03
hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
hgroup.long 0xC0C++0x03
hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)
group.long 0xC10++0x03
line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC14++0x03
line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC10++0x03
hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
hgroup.long 0xC14++0x03
hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)
group.long 0xC18++0x03
line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC1C++0x03
line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC18++0x03
hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
hgroup.long 0xC1C++0x03
hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)
group.long 0xC20++0x03
line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC24++0x03
line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC20++0x03
hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
hgroup.long 0xC24++0x03
hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)
group.long 0xC28++0x03
line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC2C++0x03
line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC28++0x03
hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
hgroup.long 0xC2C++0x03
hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)
group.long 0xC30++0x03
line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC34++0x03
line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC30++0x03
hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
hgroup.long 0xC34++0x03
hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)
group.long 0xC38++0x03
line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC3C++0x03
line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC38++0x03
hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
hgroup.long 0xC3C++0x03
hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)
group.long 0xC40++0x03
line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC44++0x03
line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC40++0x03
hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
hgroup.long 0xC44++0x03
hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)
group.long 0xC48++0x03
line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC4C++0x03
line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC48++0x03
hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
hgroup.long 0xC4C++0x03
hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)
group.long 0xC50++0x03
line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC54++0x03
line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC50++0x03
hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
hgroup.long 0xC54++0x03
hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)
group.long 0xC58++0x03
line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC5C++0x03
line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC58++0x03
hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
hgroup.long 0xC5C++0x03
hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)
group.long 0xC60++0x03
line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC64++0x03
line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC60++0x03
hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
hgroup.long 0xC64++0x03
hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)
group.long 0xC68++0x03
line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC6C++0x03
line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC68++0x03
hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
hgroup.long 0xC6C++0x03
hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)
group.long 0xC70++0x03
line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC74++0x03
line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC70++0x03
hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
hgroup.long 0xC74++0x03
hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)
group.long 0xC78++0x03
line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC7C++0x03
line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC78++0x03
hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
hgroup.long 0xC7C++0x03
hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0xC80++0x03
line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC84++0x03
line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC80++0x03
hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
hgroup.long 0xC84++0x03
hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0xC88++0x03
line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC8C++0x03
line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC88++0x03
hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
hgroup.long 0xC8C++0x03
hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0xC90++0x03
line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC94++0x03
line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC90++0x03
hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
hgroup.long 0xC94++0x03
hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0xC98++0x03
line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC9C++0x03
line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC98++0x03
hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
hgroup.long 0xC9C++0x03
hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0xCA0++0x03
line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCA4++0x03
line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCA0++0x03
hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
hgroup.long 0xCA4++0x03
hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0xCA8++0x03
line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCAC++0x03
line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCA8++0x03
hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
hgroup.long 0xCAC++0x03
hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0xCB0++0x03
line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCB4++0x03
line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCB0++0x03
hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
hgroup.long 0xCB4++0x03
hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0xCB8++0x03
line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCBC++0x03
line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCB8++0x03
hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
hgroup.long 0xCBC++0x03
hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0xCC0++0x03
line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCC4++0x03
line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCC0++0x03
hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
hgroup.long 0xCC4++0x03
hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0xCC8++0x03
line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCCC++0x03
line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCC8++0x03
hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
hgroup.long 0xCCC++0x03
hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0xCD0++0x03
line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCD4++0x03
line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCD0++0x03
hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
hgroup.long 0xCD4++0x03
hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0xCD8++0x03
line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCDC++0x03
line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCD8++0x03
hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
hgroup.long 0xCDC++0x03
hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0xCE0++0x03
line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCE4++0x03
line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCE0++0x03
hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
hgroup.long 0xCE4++0x03
hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0xCE8++0x03
line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCEC++0x03
line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCE8++0x03
hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
hgroup.long 0xCEC++0x03
hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0xCF0++0x03
line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCF4++0x03
line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCF0++0x03
hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
hgroup.long 0xCF4++0x03
hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
endif
tree.end
width 17.
tree "Interrupt Group Modifier Registers"
hgroup.long 0x0D00++0x03
hide.long 0x0 "GICD_IGRPMODR0,Interrupt Group Modifier Register 0"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D00))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01))
group.long 0x0D04++0x03
line.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1"
bitfld.long 0x00 31. " GMB63  ,Group Modifier Bit 63" "0,1"
bitfld.long 0x00 30. "  GMB62  ,Group Modifier Bit 62" "0,1"
bitfld.long 0x00 29. "  GMB61  ,Group Modifier Bit 61" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB60  ,Group Modifier Bit 60" "0,1"
bitfld.long 0x00 27. "  GMB59  ,Group Modifier Bit 59" "0,1"
bitfld.long 0x00 26. "  GMB58  ,Group Modifier Bit 58" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB57  ,Group Modifier Bit 57" "0,1"
bitfld.long 0x00 24. "  GMB56  ,Group Modifier Bit 56" "0,1"
bitfld.long 0x00 23. "  GMB55  ,Group Modifier Bit 55" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB54  ,Group Modifier Bit 54" "0,1"
bitfld.long 0x00 21. "  GMB53  ,Group Modifier Bit 53" "0,1"
bitfld.long 0x00 20. "  GMB52  ,Group Modifier Bit 52" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB51  ,Group Modifier Bit 51" "0,1"
bitfld.long 0x00 18. "  GMB50  ,Group Modifier Bit 50" "0,1"
bitfld.long 0x00 17. "  GMB49  ,Group Modifier Bit 49" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB48  ,Group Modifier Bit 48" "0,1"
bitfld.long 0x00 15. "  GMB47  ,Group Modifier Bit 47" "0,1"
bitfld.long 0x00 14. "  GMB46  ,Group Modifier Bit 46" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB45  ,Group Modifier Bit 45" "0,1"
bitfld.long 0x00 12. "  GMB44  ,Group Modifier Bit 44" "0,1"
bitfld.long 0x00 11. "  GMB43  ,Group Modifier Bit 43" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB42  ,Group Modifier Bit 42" "0,1"
bitfld.long 0x00 9. "  GMB41  ,Group Modifier Bit 41" "0,1"
bitfld.long 0x00 8. "  GMB40  ,Group Modifier Bit 40" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB39  ,Group Modifier Bit 39" "0,1"
bitfld.long 0x00 6. "  GMB38  ,Group Modifier Bit 38" "0,1"
bitfld.long 0x00 5. "  GMB37  ,Group Modifier Bit 37" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB36  ,Group Modifier Bit 36" "0,1"
bitfld.long 0x00 3. "  GMB35  ,Group Modifier Bit 35" "0,1"
bitfld.long 0x00 2. "  GMB34  ,Group Modifier Bit 34" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB33  ,Group Modifier Bit 33" "0,1"
bitfld.long 0x00 0. "  GMB32  ,Group Modifier Bit 32" "0,1"
else
hgroup.long 0x0D04++0x03
hide.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D08))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02))
group.long 0x0D08++0x03
line.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2"
bitfld.long 0x00 31. " GMB95  ,Group Modifier Bit 95" "0,1"
bitfld.long 0x00 30. "  GMB94  ,Group Modifier Bit 94" "0,1"
bitfld.long 0x00 29. "  GMB93  ,Group Modifier Bit 93" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB92  ,Group Modifier Bit 92" "0,1"
bitfld.long 0x00 27. "  GMB91  ,Group Modifier Bit 91" "0,1"
bitfld.long 0x00 26. "  GMB90  ,Group Modifier Bit 90" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB89  ,Group Modifier Bit 89" "0,1"
bitfld.long 0x00 24. "  GMB88  ,Group Modifier Bit 88" "0,1"
bitfld.long 0x00 23. "  GMB87  ,Group Modifier Bit 87" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB86  ,Group Modifier Bit 86" "0,1"
bitfld.long 0x00 21. "  GMB85  ,Group Modifier Bit 85" "0,1"
bitfld.long 0x00 20. "  GMB84  ,Group Modifier Bit 84" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB83  ,Group Modifier Bit 83" "0,1"
bitfld.long 0x00 18. "  GMB82  ,Group Modifier Bit 82" "0,1"
bitfld.long 0x00 17. "  GMB81  ,Group Modifier Bit 81" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB80  ,Group Modifier Bit 80" "0,1"
bitfld.long 0x00 15. "  GMB79  ,Group Modifier Bit 79" "0,1"
bitfld.long 0x00 14. "  GMB78  ,Group Modifier Bit 78" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB77  ,Group Modifier Bit 77" "0,1"
bitfld.long 0x00 12. "  GMB76  ,Group Modifier Bit 76" "0,1"
bitfld.long 0x00 11. "  GMB75  ,Group Modifier Bit 75" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB74  ,Group Modifier Bit 74" "0,1"
bitfld.long 0x00 9. "  GMB73  ,Group Modifier Bit 73" "0,1"
bitfld.long 0x00 8. "  GMB72  ,Group Modifier Bit 72" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB71  ,Group Modifier Bit 71" "0,1"
bitfld.long 0x00 6. "  GMB70  ,Group Modifier Bit 70" "0,1"
bitfld.long 0x00 5. "  GMB69  ,Group Modifier Bit 69" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB68  ,Group Modifier Bit 68" "0,1"
bitfld.long 0x00 3. "  GMB67  ,Group Modifier Bit 67" "0,1"
bitfld.long 0x00 2. "  GMB66  ,Group Modifier Bit 66" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB65  ,Group Modifier Bit 65" "0,1"
bitfld.long 0x00 0. "  GMB64  ,Group Modifier Bit 64" "0,1"
else
hgroup.long 0x0D08++0x03
hide.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D0C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03))
group.long 0x0D0C++0x03
line.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3"
bitfld.long 0x00 31. " GMB127 ,Group Modifier Bit 127" "0,1"
bitfld.long 0x00 30. "  GMB126 ,Group Modifier Bit 126" "0,1"
bitfld.long 0x00 29. "  GMB125 ,Group Modifier Bit 125" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB124 ,Group Modifier Bit 124" "0,1"
bitfld.long 0x00 27. "  GMB123 ,Group Modifier Bit 123" "0,1"
bitfld.long 0x00 26. "  GMB122 ,Group Modifier Bit 122" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB121 ,Group Modifier Bit 121" "0,1"
bitfld.long 0x00 24. "  GMB120 ,Group Modifier Bit 120" "0,1"
bitfld.long 0x00 23. "  GMB119 ,Group Modifier Bit 119" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB118 ,Group Modifier Bit 118" "0,1"
bitfld.long 0x00 21. "  GMB117 ,Group Modifier Bit 117" "0,1"
bitfld.long 0x00 20. "  GMB116 ,Group Modifier Bit 116" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB115 ,Group Modifier Bit 115" "0,1"
bitfld.long 0x00 18. "  GMB114 ,Group Modifier Bit 114" "0,1"
bitfld.long 0x00 17. "  GMB113 ,Group Modifier Bit 113" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB112 ,Group Modifier Bit 112" "0,1"
bitfld.long 0x00 15. "  GMB111 ,Group Modifier Bit 111" "0,1"
bitfld.long 0x00 14. "  GMB110 ,Group Modifier Bit 110" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB109 ,Group Modifier Bit 109" "0,1"
bitfld.long 0x00 12. "  GMB108 ,Group Modifier Bit 108" "0,1"
bitfld.long 0x00 11. "  GMB107 ,Group Modifier Bit 107" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB106 ,Group Modifier Bit 106" "0,1"
bitfld.long 0x00 9. "  GMB105 ,Group Modifier Bit 105" "0,1"
bitfld.long 0x00 8. "  GMB104 ,Group Modifier Bit 104" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB103 ,Group Modifier Bit 103" "0,1"
bitfld.long 0x00 6. "  GMB102 ,Group Modifier Bit 102" "0,1"
bitfld.long 0x00 5. "  GMB101 ,Group Modifier Bit 101" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB100 ,Group Modifier Bit 100" "0,1"
bitfld.long 0x00 3. "  GMB99  ,Group Modifier Bit 99" "0,1"
bitfld.long 0x00 2. "  GMB98  ,Group Modifier Bit 98" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB97  ,Group Modifier Bit 97" "0,1"
bitfld.long 0x00 0. "  GMB96  ,Group Modifier Bit 96" "0,1"
else
hgroup.long 0x0D0C++0x03
hide.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D10))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04))
group.long 0x0D10++0x03
line.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4"
bitfld.long 0x00 31. " GMB159 ,Group Modifier Bit 159" "0,1"
bitfld.long 0x00 30. "  GMB158 ,Group Modifier Bit 158" "0,1"
bitfld.long 0x00 29. "  GMB157 ,Group Modifier Bit 157" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB156 ,Group Modifier Bit 156" "0,1"
bitfld.long 0x00 27. "  GMB155 ,Group Modifier Bit 155" "0,1"
bitfld.long 0x00 26. "  GMB154 ,Group Modifier Bit 154" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB153 ,Group Modifier Bit 153" "0,1"
bitfld.long 0x00 24. "  GMB152 ,Group Modifier Bit 152" "0,1"
bitfld.long 0x00 23. "  GMB151 ,Group Modifier Bit 151" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB150 ,Group Modifier Bit 150" "0,1"
bitfld.long 0x00 21. "  GMB149 ,Group Modifier Bit 149" "0,1"
bitfld.long 0x00 20. "  GMB148 ,Group Modifier Bit 148" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB147 ,Group Modifier Bit 147" "0,1"
bitfld.long 0x00 18. "  GMB146 ,Group Modifier Bit 146" "0,1"
bitfld.long 0x00 17. "  GMB145 ,Group Modifier Bit 145" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB144 ,Group Modifier Bit 144" "0,1"
bitfld.long 0x00 15. "  GMB143 ,Group Modifier Bit 143" "0,1"
bitfld.long 0x00 14. "  GMB142 ,Group Modifier Bit 142" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB141 ,Group Modifier Bit 141" "0,1"
bitfld.long 0x00 12. "  GMB140 ,Group Modifier Bit 140" "0,1"
bitfld.long 0x00 11. "  GMB139 ,Group Modifier Bit 139" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB138 ,Group Modifier Bit 138" "0,1"
bitfld.long 0x00 9. "  GMB137 ,Group Modifier Bit 137" "0,1"
bitfld.long 0x00 8. "  GMB136 ,Group Modifier Bit 136" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB135 ,Group Modifier Bit 135" "0,1"
bitfld.long 0x00 6. "  GMB134 ,Group Modifier Bit 134" "0,1"
bitfld.long 0x00 5. "  GMB133 ,Group Modifier Bit 133" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB132 ,Group Modifier Bit 132" "0,1"
bitfld.long 0x00 3. "  GMB131 ,Group Modifier Bit 131" "0,1"
bitfld.long 0x00 2. "  GMB130 ,Group Modifier Bit 130" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB129 ,Group Modifier Bit 129" "0,1"
bitfld.long 0x00 0. "  GMB128 ,Group Modifier Bit 128" "0,1"
else
hgroup.long 0x0D10++0x03
hide.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D14))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05))
group.long 0x0D14++0x03
line.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5"
bitfld.long 0x00 31. " GMB191 ,Group Modifier Bit 191" "0,1"
bitfld.long 0x00 30. "  GMB190 ,Group Modifier Bit 190" "0,1"
bitfld.long 0x00 29. "  GMB189 ,Group Modifier Bit 189" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB188 ,Group Modifier Bit 188" "0,1"
bitfld.long 0x00 27. "  GMB187 ,Group Modifier Bit 187" "0,1"
bitfld.long 0x00 26. "  GMB186 ,Group Modifier Bit 186" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB185 ,Group Modifier Bit 185" "0,1"
bitfld.long 0x00 24. "  GMB184 ,Group Modifier Bit 184" "0,1"
bitfld.long 0x00 23. "  GMB183 ,Group Modifier Bit 183" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB182 ,Group Modifier Bit 182" "0,1"
bitfld.long 0x00 21. "  GMB181 ,Group Modifier Bit 181" "0,1"
bitfld.long 0x00 20. "  GMB180 ,Group Modifier Bit 180" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB179 ,Group Modifier Bit 179" "0,1"
bitfld.long 0x00 18. "  GMB178 ,Group Modifier Bit 178" "0,1"
bitfld.long 0x00 17. "  GMB177 ,Group Modifier Bit 177" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB176 ,Group Modifier Bit 176" "0,1"
bitfld.long 0x00 15. "  GMB175 ,Group Modifier Bit 175" "0,1"
bitfld.long 0x00 14. "  GMB174 ,Group Modifier Bit 174" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB173 ,Group Modifier Bit 173" "0,1"
bitfld.long 0x00 12. "  GMB172 ,Group Modifier Bit 172" "0,1"
bitfld.long 0x00 11. "  GMB171 ,Group Modifier Bit 171" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB170 ,Group Modifier Bit 170" "0,1"
bitfld.long 0x00 9. "  GMB169 ,Group Modifier Bit 169" "0,1"
bitfld.long 0x00 8. "  GMB168 ,Group Modifier Bit 168" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB167 ,Group Modifier Bit 167" "0,1"
bitfld.long 0x00 6. "  GMB166 ,Group Modifier Bit 166" "0,1"
bitfld.long 0x00 5. "  GMB165 ,Group Modifier Bit 165" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB164 ,Group Modifier Bit 164" "0,1"
bitfld.long 0x00 3. "  GMB163 ,Group Modifier Bit 163" "0,1"
bitfld.long 0x00 2. "  GMB162 ,Group Modifier Bit 162" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB161 ,Group Modifier Bit 161" "0,1"
bitfld.long 0x00 0. "  GMB160 ,Group Modifier Bit 160" "0,1"
else
hgroup.long 0x0D14++0x03
hide.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D18))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06))
group.long 0x0D18++0x03
line.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6"
bitfld.long 0x00 31. " GMB223 ,Group Modifier Bit 223" "0,1"
bitfld.long 0x00 30. "  GMB222 ,Group Modifier Bit 222" "0,1"
bitfld.long 0x00 29. "  GMB221 ,Group Modifier Bit 221" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB220 ,Group Modifier Bit 220" "0,1"
bitfld.long 0x00 27. "  GMB219 ,Group Modifier Bit 219" "0,1"
bitfld.long 0x00 26. "  GMB218 ,Group Modifier Bit 218" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB217 ,Group Modifier Bit 217" "0,1"
bitfld.long 0x00 24. "  GMB216 ,Group Modifier Bit 216" "0,1"
bitfld.long 0x00 23. "  GMB215 ,Group Modifier Bit 215" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB214 ,Group Modifier Bit 214" "0,1"
bitfld.long 0x00 21. "  GMB213 ,Group Modifier Bit 213" "0,1"
bitfld.long 0x00 20. "  GMB212 ,Group Modifier Bit 212" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB211 ,Group Modifier Bit 211" "0,1"
bitfld.long 0x00 18. "  GMB210 ,Group Modifier Bit 210" "0,1"
bitfld.long 0x00 17. "  GMB209 ,Group Modifier Bit 209" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB208 ,Group Modifier Bit 208" "0,1"
bitfld.long 0x00 15. "  GMB207 ,Group Modifier Bit 207" "0,1"
bitfld.long 0x00 14. "  GMB206 ,Group Modifier Bit 206" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB205 ,Group Modifier Bit 205" "0,1"
bitfld.long 0x00 12. "  GMB204 ,Group Modifier Bit 204" "0,1"
bitfld.long 0x00 11. "  GMB203 ,Group Modifier Bit 203" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB202 ,Group Modifier Bit 202" "0,1"
bitfld.long 0x00 9. "  GMB201 ,Group Modifier Bit 201" "0,1"
bitfld.long 0x00 8. "  GMB200 ,Group Modifier Bit 200" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB199 ,Group Modifier Bit 199" "0,1"
bitfld.long 0x00 6. "  GMB198 ,Group Modifier Bit 198" "0,1"
bitfld.long 0x00 5. "  GMB197 ,Group Modifier Bit 197" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB196 ,Group Modifier Bit 196" "0,1"
bitfld.long 0x00 3. "  GMB195 ,Group Modifier Bit 195" "0,1"
bitfld.long 0x00 2. "  GMB194 ,Group Modifier Bit 194" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB193 ,Group Modifier Bit 193" "0,1"
bitfld.long 0x00 0. "  GMB192 ,Group Modifier Bit 192" "0,1"
else
hgroup.long 0x0D18++0x03
hide.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D1C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07))
group.long 0x0D1C++0x03
line.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7"
bitfld.long 0x00 31. " GMB255 ,Group Modifier Bit 255" "0,1"
bitfld.long 0x00 30. "  GMB254 ,Group Modifier Bit 254" "0,1"
bitfld.long 0x00 29. "  GMB253 ,Group Modifier Bit 253" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB252 ,Group Modifier Bit 252" "0,1"
bitfld.long 0x00 27. "  GMB251 ,Group Modifier Bit 251" "0,1"
bitfld.long 0x00 26. "  GMB250 ,Group Modifier Bit 250" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB249 ,Group Modifier Bit 249" "0,1"
bitfld.long 0x00 24. "  GMB248 ,Group Modifier Bit 248" "0,1"
bitfld.long 0x00 23. "  GMB247 ,Group Modifier Bit 247" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB246 ,Group Modifier Bit 246" "0,1"
bitfld.long 0x00 21. "  GMB245 ,Group Modifier Bit 245" "0,1"
bitfld.long 0x00 20. "  GMB244 ,Group Modifier Bit 244" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB243 ,Group Modifier Bit 243" "0,1"
bitfld.long 0x00 18. "  GMB242 ,Group Modifier Bit 242" "0,1"
bitfld.long 0x00 17. "  GMB241 ,Group Modifier Bit 241" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB240 ,Group Modifier Bit 240" "0,1"
bitfld.long 0x00 15. "  GMB239 ,Group Modifier Bit 239" "0,1"
bitfld.long 0x00 14. "  GMB238 ,Group Modifier Bit 238" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB237 ,Group Modifier Bit 237" "0,1"
bitfld.long 0x00 12. "  GMB236 ,Group Modifier Bit 236" "0,1"
bitfld.long 0x00 11. "  GMB235 ,Group Modifier Bit 235" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB234 ,Group Modifier Bit 234" "0,1"
bitfld.long 0x00 9. "  GMB233 ,Group Modifier Bit 233" "0,1"
bitfld.long 0x00 8. "  GMB232 ,Group Modifier Bit 232" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB231 ,Group Modifier Bit 231" "0,1"
bitfld.long 0x00 6. "  GMB230 ,Group Modifier Bit 230" "0,1"
bitfld.long 0x00 5. "  GMB229 ,Group Modifier Bit 229" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB228 ,Group Modifier Bit 228" "0,1"
bitfld.long 0x00 3. "  GMB227 ,Group Modifier Bit 227" "0,1"
bitfld.long 0x00 2. "  GMB226 ,Group Modifier Bit 226" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB225 ,Group Modifier Bit 225" "0,1"
bitfld.long 0x00 0. "  GMB224 ,Group Modifier Bit 224" "0,1"
else
hgroup.long 0x0D1C++0x03
hide.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D20))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08))
group.long 0x0D20++0x03
line.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8"
bitfld.long 0x00 31. " GMB287 ,Group Modifier Bit 287" "0,1"
bitfld.long 0x00 30. "  GMB286 ,Group Modifier Bit 286" "0,1"
bitfld.long 0x00 29. "  GMB285 ,Group Modifier Bit 285" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB284 ,Group Modifier Bit 284" "0,1"
bitfld.long 0x00 27. "  GMB283 ,Group Modifier Bit 283" "0,1"
bitfld.long 0x00 26. "  GMB282 ,Group Modifier Bit 282" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB281 ,Group Modifier Bit 281" "0,1"
bitfld.long 0x00 24. "  GMB280 ,Group Modifier Bit 280" "0,1"
bitfld.long 0x00 23. "  GMB279 ,Group Modifier Bit 279" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB278 ,Group Modifier Bit 278" "0,1"
bitfld.long 0x00 21. "  GMB277 ,Group Modifier Bit 277" "0,1"
bitfld.long 0x00 20. "  GMB276 ,Group Modifier Bit 276" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB275 ,Group Modifier Bit 275" "0,1"
bitfld.long 0x00 18. "  GMB274 ,Group Modifier Bit 274" "0,1"
bitfld.long 0x00 17. "  GMB273 ,Group Modifier Bit 273" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB272 ,Group Modifier Bit 272" "0,1"
bitfld.long 0x00 15. "  GMB271 ,Group Modifier Bit 271" "0,1"
bitfld.long 0x00 14. "  GMB270 ,Group Modifier Bit 270" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB269 ,Group Modifier Bit 269" "0,1"
bitfld.long 0x00 12. "  GMB268 ,Group Modifier Bit 268" "0,1"
bitfld.long 0x00 11. "  GMB267 ,Group Modifier Bit 267" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB266 ,Group Modifier Bit 266" "0,1"
bitfld.long 0x00 9. "  GMB265 ,Group Modifier Bit 265" "0,1"
bitfld.long 0x00 8. "  GMB264 ,Group Modifier Bit 264" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB263 ,Group Modifier Bit 263" "0,1"
bitfld.long 0x00 6. "  GMB262 ,Group Modifier Bit 262" "0,1"
bitfld.long 0x00 5. "  GMB261 ,Group Modifier Bit 261" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB260 ,Group Modifier Bit 260" "0,1"
bitfld.long 0x00 3. "  GMB259 ,Group Modifier Bit 259" "0,1"
bitfld.long 0x00 2. "  GMB258 ,Group Modifier Bit 258" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB257 ,Group Modifier Bit 257" "0,1"
bitfld.long 0x00 0. "  GMB256 ,Group Modifier Bit 256" "0,1"
else
hgroup.long 0x0D20++0x03
hide.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D24))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09))
group.long 0x0D24++0x03
line.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9"
bitfld.long 0x00 31. " GMB319 ,Group Modifier Bit 319" "0,1"
bitfld.long 0x00 30. "  GMB318 ,Group Modifier Bit 318" "0,1"
bitfld.long 0x00 29. "  GMB317 ,Group Modifier Bit 317" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB316 ,Group Modifier Bit 316" "0,1"
bitfld.long 0x00 27. "  GMB315 ,Group Modifier Bit 315" "0,1"
bitfld.long 0x00 26. "  GMB314 ,Group Modifier Bit 314" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB313 ,Group Modifier Bit 313" "0,1"
bitfld.long 0x00 24. "  GMB312 ,Group Modifier Bit 312" "0,1"
bitfld.long 0x00 23. "  GMB311 ,Group Modifier Bit 311" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB310 ,Group Modifier Bit 310" "0,1"
bitfld.long 0x00 21. "  GMB309 ,Group Modifier Bit 309" "0,1"
bitfld.long 0x00 20. "  GMB308 ,Group Modifier Bit 308" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB307 ,Group Modifier Bit 307" "0,1"
bitfld.long 0x00 18. "  GMB306 ,Group Modifier Bit 306" "0,1"
bitfld.long 0x00 17. "  GMB305 ,Group Modifier Bit 305" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB304 ,Group Modifier Bit 304" "0,1"
bitfld.long 0x00 15. "  GMB303 ,Group Modifier Bit 303" "0,1"
bitfld.long 0x00 14. "  GMB302 ,Group Modifier Bit 302" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB301 ,Group Modifier Bit 301" "0,1"
bitfld.long 0x00 12. "  GMB300 ,Group Modifier Bit 300" "0,1"
bitfld.long 0x00 11. "  GMB299 ,Group Modifier Bit 299" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB298 ,Group Modifier Bit 298" "0,1"
bitfld.long 0x00 9. "  GMB297 ,Group Modifier Bit 297" "0,1"
bitfld.long 0x00 8. "  GMB296 ,Group Modifier Bit 296" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB295 ,Group Modifier Bit 295" "0,1"
bitfld.long 0x00 6. "  GMB294 ,Group Modifier Bit 294" "0,1"
bitfld.long 0x00 5. "  GMB293 ,Group Modifier Bit 293" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB292 ,Group Modifier Bit 292" "0,1"
bitfld.long 0x00 3. "  GMB291 ,Group Modifier Bit 291" "0,1"
bitfld.long 0x00 2. "  GMB290 ,Group Modifier Bit 290" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB289 ,Group Modifier Bit 289" "0,1"
bitfld.long 0x00 0. "  GMB288 ,Group Modifier Bit 288" "0,1"
else
hgroup.long 0x0D24++0x03
hide.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D28))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A))
group.long 0x0D28++0x03
line.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10"
bitfld.long 0x00 31. " GMB351 ,Group Modifier Bit 351" "0,1"
bitfld.long 0x00 30. "  GMB350 ,Group Modifier Bit 350" "0,1"
bitfld.long 0x00 29. "  GMB349 ,Group Modifier Bit 349" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB348 ,Group Modifier Bit 348" "0,1"
bitfld.long 0x00 27. "  GMB347 ,Group Modifier Bit 347" "0,1"
bitfld.long 0x00 26. "  GMB346 ,Group Modifier Bit 346" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB345 ,Group Modifier Bit 345" "0,1"
bitfld.long 0x00 24. "  GMB344 ,Group Modifier Bit 344" "0,1"
bitfld.long 0x00 23. "  GMB343 ,Group Modifier Bit 343" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB342 ,Group Modifier Bit 342" "0,1"
bitfld.long 0x00 21. "  GMB341 ,Group Modifier Bit 341" "0,1"
bitfld.long 0x00 20. "  GMB340 ,Group Modifier Bit 340" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB339 ,Group Modifier Bit 339" "0,1"
bitfld.long 0x00 18. "  GMB338 ,Group Modifier Bit 338" "0,1"
bitfld.long 0x00 17. "  GMB337 ,Group Modifier Bit 337" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB336 ,Group Modifier Bit 336" "0,1"
bitfld.long 0x00 15. "  GMB335 ,Group Modifier Bit 335" "0,1"
bitfld.long 0x00 14. "  GMB334 ,Group Modifier Bit 334" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB333 ,Group Modifier Bit 333" "0,1"
bitfld.long 0x00 12. "  GMB332 ,Group Modifier Bit 332" "0,1"
bitfld.long 0x00 11. "  GMB331 ,Group Modifier Bit 331" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB330 ,Group Modifier Bit 330" "0,1"
bitfld.long 0x00 9. "  GMB329 ,Group Modifier Bit 329" "0,1"
bitfld.long 0x00 8. "  GMB328 ,Group Modifier Bit 328" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB327 ,Group Modifier Bit 327" "0,1"
bitfld.long 0x00 6. "  GMB326 ,Group Modifier Bit 326" "0,1"
bitfld.long 0x00 5. "  GMB325 ,Group Modifier Bit 325" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB324 ,Group Modifier Bit 324" "0,1"
bitfld.long 0x00 3. "  GMB323 ,Group Modifier Bit 323" "0,1"
bitfld.long 0x00 2. "  GMB322 ,Group Modifier Bit 322" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB321 ,Group Modifier Bit 321" "0,1"
bitfld.long 0x00 0. "  GMB320 ,Group Modifier Bit 320" "0,1"
else
hgroup.long 0x0D28++0x03
hide.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D2C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B))
group.long 0x0D2C++0x03
line.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11"
bitfld.long 0x00 31. " GMB383 ,Group Modifier Bit 383" "0,1"
bitfld.long 0x00 30. "  GMB382 ,Group Modifier Bit 382" "0,1"
bitfld.long 0x00 29. "  GMB381 ,Group Modifier Bit 381" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB380 ,Group Modifier Bit 380" "0,1"
bitfld.long 0x00 27. "  GMB379 ,Group Modifier Bit 379" "0,1"
bitfld.long 0x00 26. "  GMB378 ,Group Modifier Bit 378" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB377 ,Group Modifier Bit 377" "0,1"
bitfld.long 0x00 24. "  GMB376 ,Group Modifier Bit 376" "0,1"
bitfld.long 0x00 23. "  GMB375 ,Group Modifier Bit 375" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB374 ,Group Modifier Bit 374" "0,1"
bitfld.long 0x00 21. "  GMB373 ,Group Modifier Bit 373" "0,1"
bitfld.long 0x00 20. "  GMB372 ,Group Modifier Bit 372" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB371 ,Group Modifier Bit 371" "0,1"
bitfld.long 0x00 18. "  GMB370 ,Group Modifier Bit 370" "0,1"
bitfld.long 0x00 17. "  GMB369 ,Group Modifier Bit 369" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB368 ,Group Modifier Bit 368" "0,1"
bitfld.long 0x00 15. "  GMB367 ,Group Modifier Bit 367" "0,1"
bitfld.long 0x00 14. "  GMB366 ,Group Modifier Bit 366" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB365 ,Group Modifier Bit 365" "0,1"
bitfld.long 0x00 12. "  GMB364 ,Group Modifier Bit 364" "0,1"
bitfld.long 0x00 11. "  GMB363 ,Group Modifier Bit 363" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB362 ,Group Modifier Bit 362" "0,1"
bitfld.long 0x00 9. "  GMB361 ,Group Modifier Bit 361" "0,1"
bitfld.long 0x00 8. "  GMB360 ,Group Modifier Bit 360" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB359 ,Group Modifier Bit 359" "0,1"
bitfld.long 0x00 6. "  GMB358 ,Group Modifier Bit 358" "0,1"
bitfld.long 0x00 5. "  GMB357 ,Group Modifier Bit 357" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB356 ,Group Modifier Bit 356" "0,1"
bitfld.long 0x00 3. "  GMB355 ,Group Modifier Bit 355" "0,1"
bitfld.long 0x00 2. "  GMB354 ,Group Modifier Bit 354" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB353 ,Group Modifier Bit 353" "0,1"
bitfld.long 0x00 0. "  GMB352 ,Group Modifier Bit 352" "0,1"
else
hgroup.long 0x0D2C++0x03
hide.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D30))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C))
group.long 0x0D30++0x03
line.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12"
bitfld.long 0x00 31. " GMB415 ,Group Modifier Bit 415" "0,1"
bitfld.long 0x00 30. "  GMB414 ,Group Modifier Bit 414" "0,1"
bitfld.long 0x00 29. "  GMB413 ,Group Modifier Bit 413" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB412 ,Group Modifier Bit 412" "0,1"
bitfld.long 0x00 27. "  GMB411 ,Group Modifier Bit 411" "0,1"
bitfld.long 0x00 26. "  GMB410 ,Group Modifier Bit 410" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB409 ,Group Modifier Bit 409" "0,1"
bitfld.long 0x00 24. "  GMB408 ,Group Modifier Bit 408" "0,1"
bitfld.long 0x00 23. "  GMB407 ,Group Modifier Bit 407" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB406 ,Group Modifier Bit 406" "0,1"
bitfld.long 0x00 21. "  GMB405 ,Group Modifier Bit 405" "0,1"
bitfld.long 0x00 20. "  GMB404 ,Group Modifier Bit 404" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB403 ,Group Modifier Bit 403" "0,1"
bitfld.long 0x00 18. "  GMB402 ,Group Modifier Bit 402" "0,1"
bitfld.long 0x00 17. "  GMB401 ,Group Modifier Bit 401" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB400 ,Group Modifier Bit 400" "0,1"
bitfld.long 0x00 15. "  GMB399 ,Group Modifier Bit 399" "0,1"
bitfld.long 0x00 14. "  GMB398 ,Group Modifier Bit 398" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB397 ,Group Modifier Bit 397" "0,1"
bitfld.long 0x00 12. "  GMB396 ,Group Modifier Bit 396" "0,1"
bitfld.long 0x00 11. "  GMB395 ,Group Modifier Bit 395" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB394 ,Group Modifier Bit 394" "0,1"
bitfld.long 0x00 9. "  GMB393 ,Group Modifier Bit 393" "0,1"
bitfld.long 0x00 8. "  GMB392 ,Group Modifier Bit 392" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB391 ,Group Modifier Bit 391" "0,1"
bitfld.long 0x00 6. "  GMB390 ,Group Modifier Bit 390" "0,1"
bitfld.long 0x00 5. "  GMB389 ,Group Modifier Bit 389" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB388 ,Group Modifier Bit 388" "0,1"
bitfld.long 0x00 3. "  GMB387 ,Group Modifier Bit 387" "0,1"
bitfld.long 0x00 2. "  GMB386 ,Group Modifier Bit 386" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB385 ,Group Modifier Bit 385" "0,1"
bitfld.long 0x00 0. "  GMB384 ,Group Modifier Bit 384" "0,1"
else
hgroup.long 0x0D30++0x03
hide.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D34))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D))
group.long 0x0D34++0x03
line.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13"
bitfld.long 0x00 31. " GMB447 ,Group Modifier Bit 447" "0,1"
bitfld.long 0x00 30. "  GMB446 ,Group Modifier Bit 446" "0,1"
bitfld.long 0x00 29. "  GMB445 ,Group Modifier Bit 445" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB444 ,Group Modifier Bit 444" "0,1"
bitfld.long 0x00 27. "  GMB443 ,Group Modifier Bit 443" "0,1"
bitfld.long 0x00 26. "  GMB442 ,Group Modifier Bit 442" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB441 ,Group Modifier Bit 441" "0,1"
bitfld.long 0x00 24. "  GMB440 ,Group Modifier Bit 440" "0,1"
bitfld.long 0x00 23. "  GMB439 ,Group Modifier Bit 439" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB438 ,Group Modifier Bit 438" "0,1"
bitfld.long 0x00 21. "  GMB437 ,Group Modifier Bit 437" "0,1"
bitfld.long 0x00 20. "  GMB436 ,Group Modifier Bit 436" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB435 ,Group Modifier Bit 435" "0,1"
bitfld.long 0x00 18. "  GMB434 ,Group Modifier Bit 434" "0,1"
bitfld.long 0x00 17. "  GMB433 ,Group Modifier Bit 433" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB432 ,Group Modifier Bit 432" "0,1"
bitfld.long 0x00 15. "  GMB431 ,Group Modifier Bit 431" "0,1"
bitfld.long 0x00 14. "  GMB430 ,Group Modifier Bit 430" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB429 ,Group Modifier Bit 429" "0,1"
bitfld.long 0x00 12. "  GMB428 ,Group Modifier Bit 428" "0,1"
bitfld.long 0x00 11. "  GMB427 ,Group Modifier Bit 427" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB426 ,Group Modifier Bit 426" "0,1"
bitfld.long 0x00 9. "  GMB425 ,Group Modifier Bit 425" "0,1"
bitfld.long 0x00 8. "  GMB424 ,Group Modifier Bit 424" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB423 ,Group Modifier Bit 423" "0,1"
bitfld.long 0x00 6. "  GMB422 ,Group Modifier Bit 422" "0,1"
bitfld.long 0x00 5. "  GMB421 ,Group Modifier Bit 421" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB420 ,Group Modifier Bit 420" "0,1"
bitfld.long 0x00 3. "  GMB419 ,Group Modifier Bit 419" "0,1"
bitfld.long 0x00 2. "  GMB418 ,Group Modifier Bit 418" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB417 ,Group Modifier Bit 417" "0,1"
bitfld.long 0x00 0. "  GMB416 ,Group Modifier Bit 416" "0,1"
else
hgroup.long 0x0D34++0x03
hide.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D38))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E))
group.long 0x0D38++0x03
line.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14"
bitfld.long 0x00 31. " GMB479 ,Group Modifier Bit 479" "0,1"
bitfld.long 0x00 30. "  GMB478 ,Group Modifier Bit 478" "0,1"
bitfld.long 0x00 29. "  GMB477 ,Group Modifier Bit 477" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB476 ,Group Modifier Bit 476" "0,1"
bitfld.long 0x00 27. "  GMB475 ,Group Modifier Bit 475" "0,1"
bitfld.long 0x00 26. "  GMB474 ,Group Modifier Bit 474" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB473 ,Group Modifier Bit 473" "0,1"
bitfld.long 0x00 24. "  GMB472 ,Group Modifier Bit 472" "0,1"
bitfld.long 0x00 23. "  GMB471 ,Group Modifier Bit 471" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB470 ,Group Modifier Bit 470" "0,1"
bitfld.long 0x00 21. "  GMB469 ,Group Modifier Bit 469" "0,1"
bitfld.long 0x00 20. "  GMB468 ,Group Modifier Bit 468" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB467 ,Group Modifier Bit 467" "0,1"
bitfld.long 0x00 18. "  GMB466 ,Group Modifier Bit 466" "0,1"
bitfld.long 0x00 17. "  GMB465 ,Group Modifier Bit 465" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB464 ,Group Modifier Bit 464" "0,1"
bitfld.long 0x00 15. "  GMB463 ,Group Modifier Bit 463" "0,1"
bitfld.long 0x00 14. "  GMB462 ,Group Modifier Bit 462" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB461 ,Group Modifier Bit 461" "0,1"
bitfld.long 0x00 12. "  GMB460 ,Group Modifier Bit 460" "0,1"
bitfld.long 0x00 11. "  GMB459 ,Group Modifier Bit 459" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB458 ,Group Modifier Bit 458" "0,1"
bitfld.long 0x00 9. "  GMB457 ,Group Modifier Bit 457" "0,1"
bitfld.long 0x00 8. "  GMB456 ,Group Modifier Bit 456" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB455 ,Group Modifier Bit 455" "0,1"
bitfld.long 0x00 6. "  GMB454 ,Group Modifier Bit 454" "0,1"
bitfld.long 0x00 5. "  GMB453 ,Group Modifier Bit 453" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB452 ,Group Modifier Bit 452" "0,1"
bitfld.long 0x00 3. "  GMB451 ,Group Modifier Bit 451" "0,1"
bitfld.long 0x00 2. "  GMB450 ,Group Modifier Bit 450" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB449 ,Group Modifier Bit 449" "0,1"
bitfld.long 0x00 0. "  GMB448 ,Group Modifier Bit 448" "0,1"
else
hgroup.long 0x0D38++0x03
hide.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D3C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F))
group.long 0x0D3C++0x03
line.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15"
bitfld.long 0x00 31. " GMB511 ,Group Modifier Bit 511" "0,1"
bitfld.long 0x00 30. "  GMB510 ,Group Modifier Bit 510" "0,1"
bitfld.long 0x00 29. "  GMB509 ,Group Modifier Bit 509" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB508 ,Group Modifier Bit 508" "0,1"
bitfld.long 0x00 27. "  GMB507 ,Group Modifier Bit 507" "0,1"
bitfld.long 0x00 26. "  GMB506 ,Group Modifier Bit 506" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB505 ,Group Modifier Bit 505" "0,1"
bitfld.long 0x00 24. "  GMB504 ,Group Modifier Bit 504" "0,1"
bitfld.long 0x00 23. "  GMB503 ,Group Modifier Bit 503" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB502 ,Group Modifier Bit 502" "0,1"
bitfld.long 0x00 21. "  GMB501 ,Group Modifier Bit 501" "0,1"
bitfld.long 0x00 20. "  GMB500 ,Group Modifier Bit 500" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB499 ,Group Modifier Bit 499" "0,1"
bitfld.long 0x00 18. "  GMB498 ,Group Modifier Bit 498" "0,1"
bitfld.long 0x00 17. "  GMB497 ,Group Modifier Bit 497" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB496 ,Group Modifier Bit 496" "0,1"
bitfld.long 0x00 15. "  GMB495 ,Group Modifier Bit 495" "0,1"
bitfld.long 0x00 14. "  GMB494 ,Group Modifier Bit 494" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB493 ,Group Modifier Bit 493" "0,1"
bitfld.long 0x00 12. "  GMB492 ,Group Modifier Bit 492" "0,1"
bitfld.long 0x00 11. "  GMB491 ,Group Modifier Bit 491" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB490 ,Group Modifier Bit 490" "0,1"
bitfld.long 0x00 9. "  GMB489 ,Group Modifier Bit 489" "0,1"
bitfld.long 0x00 8. "  GMB488 ,Group Modifier Bit 488" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB487 ,Group Modifier Bit 487" "0,1"
bitfld.long 0x00 6. "  GMB486 ,Group Modifier Bit 486" "0,1"
bitfld.long 0x00 5. "  GMB485 ,Group Modifier Bit 485" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB484 ,Group Modifier Bit 484" "0,1"
bitfld.long 0x00 3. "  GMB483 ,Group Modifier Bit 483" "0,1"
bitfld.long 0x00 2. "  GMB482 ,Group Modifier Bit 482" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB481 ,Group Modifier Bit 481" "0,1"
bitfld.long 0x00 0. "  GMB480 ,Group Modifier Bit 480" "0,1"
else
hgroup.long 0x0D3C++0x03
hide.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D40))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x0D40++0x03
line.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16"
bitfld.long 0x00 31. " GMB543 ,Group Modifier Bit 543" "0,1"
bitfld.long 0x00 30. "  GMB542 ,Group Modifier Bit 542" "0,1"
bitfld.long 0x00 29. "  GMB541 ,Group Modifier Bit 541" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB540 ,Group Modifier Bit 540" "0,1"
bitfld.long 0x00 27. "  GMB539 ,Group Modifier Bit 539" "0,1"
bitfld.long 0x00 26. "  GMB538 ,Group Modifier Bit 538" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB537 ,Group Modifier Bit 537" "0,1"
bitfld.long 0x00 24. "  GMB536 ,Group Modifier Bit 536" "0,1"
bitfld.long 0x00 23. "  GMB535 ,Group Modifier Bit 535" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB534 ,Group Modifier Bit 534" "0,1"
bitfld.long 0x00 21. "  GMB533 ,Group Modifier Bit 533" "0,1"
bitfld.long 0x00 20. "  GMB532 ,Group Modifier Bit 532" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB531 ,Group Modifier Bit 531" "0,1"
bitfld.long 0x00 18. "  GMB530 ,Group Modifier Bit 530" "0,1"
bitfld.long 0x00 17. "  GMB529 ,Group Modifier Bit 529" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB528 ,Group Modifier Bit 528" "0,1"
bitfld.long 0x00 15. "  GMB527 ,Group Modifier Bit 527" "0,1"
bitfld.long 0x00 14. "  GMB526 ,Group Modifier Bit 526" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB525 ,Group Modifier Bit 525" "0,1"
bitfld.long 0x00 12. "  GMB524 ,Group Modifier Bit 524" "0,1"
bitfld.long 0x00 11. "  GMB523 ,Group Modifier Bit 523" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB522 ,Group Modifier Bit 522" "0,1"
bitfld.long 0x00 9. "  GMB521 ,Group Modifier Bit 521" "0,1"
bitfld.long 0x00 8. "  GMB520 ,Group Modifier Bit 520" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB519 ,Group Modifier Bit 519" "0,1"
bitfld.long 0x00 6. "  GMB518 ,Group Modifier Bit 518" "0,1"
bitfld.long 0x00 5. "  GMB517 ,Group Modifier Bit 517" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB516 ,Group Modifier Bit 516" "0,1"
bitfld.long 0x00 3. "  GMB515 ,Group Modifier Bit 515" "0,1"
bitfld.long 0x00 2. "  GMB514 ,Group Modifier Bit 514" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB513 ,Group Modifier Bit 513" "0,1"
bitfld.long 0x00 0. "  GMB512 ,Group Modifier Bit 512" "0,1"
else
hgroup.long 0x0D40++0x03
hide.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D44))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x0D44++0x03
line.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17"
bitfld.long 0x00 31. " GMB575 ,Group Modifier Bit 575" "0,1"
bitfld.long 0x00 30. "  GMB574 ,Group Modifier Bit 574" "0,1"
bitfld.long 0x00 29. "  GMB573 ,Group Modifier Bit 573" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB572 ,Group Modifier Bit 572" "0,1"
bitfld.long 0x00 27. "  GMB571 ,Group Modifier Bit 571" "0,1"
bitfld.long 0x00 26. "  GMB570 ,Group Modifier Bit 570" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB569 ,Group Modifier Bit 569" "0,1"
bitfld.long 0x00 24. "  GMB568 ,Group Modifier Bit 568" "0,1"
bitfld.long 0x00 23. "  GMB567 ,Group Modifier Bit 567" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB566 ,Group Modifier Bit 566" "0,1"
bitfld.long 0x00 21. "  GMB565 ,Group Modifier Bit 565" "0,1"
bitfld.long 0x00 20. "  GMB564 ,Group Modifier Bit 564" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB563 ,Group Modifier Bit 563" "0,1"
bitfld.long 0x00 18. "  GMB562 ,Group Modifier Bit 562" "0,1"
bitfld.long 0x00 17. "  GMB561 ,Group Modifier Bit 561" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB560 ,Group Modifier Bit 560" "0,1"
bitfld.long 0x00 15. "  GMB559 ,Group Modifier Bit 559" "0,1"
bitfld.long 0x00 14. "  GMB558 ,Group Modifier Bit 558" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB557 ,Group Modifier Bit 557" "0,1"
bitfld.long 0x00 12. "  GMB556 ,Group Modifier Bit 556" "0,1"
bitfld.long 0x00 11. "  GMB555 ,Group Modifier Bit 555" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB554 ,Group Modifier Bit 554" "0,1"
bitfld.long 0x00 9. "  GMB553 ,Group Modifier Bit 553" "0,1"
bitfld.long 0x00 8. "  GMB552 ,Group Modifier Bit 552" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB551 ,Group Modifier Bit 551" "0,1"
bitfld.long 0x00 6. "  GMB550 ,Group Modifier Bit 550" "0,1"
bitfld.long 0x00 5. "  GMB549 ,Group Modifier Bit 549" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB548 ,Group Modifier Bit 548" "0,1"
bitfld.long 0x00 3. "  GMB547 ,Group Modifier Bit 547" "0,1"
bitfld.long 0x00 2. "  GMB546 ,Group Modifier Bit 546" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB545 ,Group Modifier Bit 545" "0,1"
bitfld.long 0x00 0. "  GMB544 ,Group Modifier Bit 544" "0,1"
else
hgroup.long 0x0D44++0x03
hide.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D48))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x0D48++0x03
line.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18"
bitfld.long 0x00 31. " GMB607 ,Group Modifier Bit 607" "0,1"
bitfld.long 0x00 30. "  GMB606 ,Group Modifier Bit 606" "0,1"
bitfld.long 0x00 29. "  GMB605 ,Group Modifier Bit 605" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB604 ,Group Modifier Bit 604" "0,1"
bitfld.long 0x00 27. "  GMB603 ,Group Modifier Bit 603" "0,1"
bitfld.long 0x00 26. "  GMB602 ,Group Modifier Bit 602" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB601 ,Group Modifier Bit 601" "0,1"
bitfld.long 0x00 24. "  GMB600 ,Group Modifier Bit 600" "0,1"
bitfld.long 0x00 23. "  GMB599 ,Group Modifier Bit 599" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB598 ,Group Modifier Bit 598" "0,1"
bitfld.long 0x00 21. "  GMB597 ,Group Modifier Bit 597" "0,1"
bitfld.long 0x00 20. "  GMB596 ,Group Modifier Bit 596" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB595 ,Group Modifier Bit 595" "0,1"
bitfld.long 0x00 18. "  GMB594 ,Group Modifier Bit 594" "0,1"
bitfld.long 0x00 17. "  GMB593 ,Group Modifier Bit 593" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB592 ,Group Modifier Bit 592" "0,1"
bitfld.long 0x00 15. "  GMB591 ,Group Modifier Bit 591" "0,1"
bitfld.long 0x00 14. "  GMB590 ,Group Modifier Bit 590" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB589 ,Group Modifier Bit 589" "0,1"
bitfld.long 0x00 12. "  GMB588 ,Group Modifier Bit 588" "0,1"
bitfld.long 0x00 11. "  GMB587 ,Group Modifier Bit 587" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB586 ,Group Modifier Bit 586" "0,1"
bitfld.long 0x00 9. "  GMB585 ,Group Modifier Bit 585" "0,1"
bitfld.long 0x00 8. "  GMB584 ,Group Modifier Bit 584" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB583 ,Group Modifier Bit 583" "0,1"
bitfld.long 0x00 6. "  GMB582 ,Group Modifier Bit 582" "0,1"
bitfld.long 0x00 5. "  GMB581 ,Group Modifier Bit 581" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB580 ,Group Modifier Bit 580" "0,1"
bitfld.long 0x00 3. "  GMB579 ,Group Modifier Bit 579" "0,1"
bitfld.long 0x00 2. "  GMB578 ,Group Modifier Bit 578" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB577 ,Group Modifier Bit 577" "0,1"
bitfld.long 0x00 0. "  GMB576 ,Group Modifier Bit 576" "0,1"
else
hgroup.long 0x0D48++0x03
hide.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D4C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x0D4C++0x03
line.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19"
bitfld.long 0x00 31. " GMB639 ,Group Modifier Bit 639" "0,1"
bitfld.long 0x00 30. "  GMB638 ,Group Modifier Bit 638" "0,1"
bitfld.long 0x00 29. "  GMB637 ,Group Modifier Bit 637" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB636 ,Group Modifier Bit 636" "0,1"
bitfld.long 0x00 27. "  GMB635 ,Group Modifier Bit 635" "0,1"
bitfld.long 0x00 26. "  GMB634 ,Group Modifier Bit 634" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB633 ,Group Modifier Bit 633" "0,1"
bitfld.long 0x00 24. "  GMB632 ,Group Modifier Bit 632" "0,1"
bitfld.long 0x00 23. "  GMB631 ,Group Modifier Bit 631" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB630 ,Group Modifier Bit 630" "0,1"
bitfld.long 0x00 21. "  GMB629 ,Group Modifier Bit 629" "0,1"
bitfld.long 0x00 20. "  GMB628 ,Group Modifier Bit 628" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB627 ,Group Modifier Bit 627" "0,1"
bitfld.long 0x00 18. "  GMB626 ,Group Modifier Bit 626" "0,1"
bitfld.long 0x00 17. "  GMB625 ,Group Modifier Bit 625" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB624 ,Group Modifier Bit 624" "0,1"
bitfld.long 0x00 15. "  GMB623 ,Group Modifier Bit 623" "0,1"
bitfld.long 0x00 14. "  GMB622 ,Group Modifier Bit 622" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB621 ,Group Modifier Bit 621" "0,1"
bitfld.long 0x00 12. "  GMB620 ,Group Modifier Bit 620" "0,1"
bitfld.long 0x00 11. "  GMB619 ,Group Modifier Bit 619" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB618 ,Group Modifier Bit 618" "0,1"
bitfld.long 0x00 9. "  GMB617 ,Group Modifier Bit 617" "0,1"
bitfld.long 0x00 8. "  GMB616 ,Group Modifier Bit 616" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB615 ,Group Modifier Bit 615" "0,1"
bitfld.long 0x00 6. "  GMB614 ,Group Modifier Bit 614" "0,1"
bitfld.long 0x00 5. "  GMB613 ,Group Modifier Bit 613" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB612 ,Group Modifier Bit 612" "0,1"
bitfld.long 0x00 3. "  GMB611 ,Group Modifier Bit 611" "0,1"
bitfld.long 0x00 2. "  GMB610 ,Group Modifier Bit 610" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB609 ,Group Modifier Bit 609" "0,1"
bitfld.long 0x00 0. "  GMB608 ,Group Modifier Bit 608" "0,1"
else
hgroup.long 0x0D4C++0x03
hide.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D50))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x0D50++0x03
line.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20"
bitfld.long 0x00 31. " GMB671 ,Group Modifier Bit 671" "0,1"
bitfld.long 0x00 30. "  GMB670 ,Group Modifier Bit 670" "0,1"
bitfld.long 0x00 29. "  GMB669 ,Group Modifier Bit 669" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB668 ,Group Modifier Bit 668" "0,1"
bitfld.long 0x00 27. "  GMB667 ,Group Modifier Bit 667" "0,1"
bitfld.long 0x00 26. "  GMB666 ,Group Modifier Bit 666" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB665 ,Group Modifier Bit 665" "0,1"
bitfld.long 0x00 24. "  GMB664 ,Group Modifier Bit 664" "0,1"
bitfld.long 0x00 23. "  GMB663 ,Group Modifier Bit 663" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB662 ,Group Modifier Bit 662" "0,1"
bitfld.long 0x00 21. "  GMB661 ,Group Modifier Bit 661" "0,1"
bitfld.long 0x00 20. "  GMB660 ,Group Modifier Bit 660" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB659 ,Group Modifier Bit 659" "0,1"
bitfld.long 0x00 18. "  GMB658 ,Group Modifier Bit 658" "0,1"
bitfld.long 0x00 17. "  GMB657 ,Group Modifier Bit 657" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB656 ,Group Modifier Bit 656" "0,1"
bitfld.long 0x00 15. "  GMB655 ,Group Modifier Bit 655" "0,1"
bitfld.long 0x00 14. "  GMB654 ,Group Modifier Bit 654" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB653 ,Group Modifier Bit 653" "0,1"
bitfld.long 0x00 12. "  GMB652 ,Group Modifier Bit 652" "0,1"
bitfld.long 0x00 11. "  GMB651 ,Group Modifier Bit 651" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB650 ,Group Modifier Bit 650" "0,1"
bitfld.long 0x00 9. "  GMB649 ,Group Modifier Bit 649" "0,1"
bitfld.long 0x00 8. "  GMB648 ,Group Modifier Bit 648" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB647 ,Group Modifier Bit 647" "0,1"
bitfld.long 0x00 6. "  GMB646 ,Group Modifier Bit 646" "0,1"
bitfld.long 0x00 5. "  GMB645 ,Group Modifier Bit 645" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB644 ,Group Modifier Bit 644" "0,1"
bitfld.long 0x00 3. "  GMB643 ,Group Modifier Bit 643" "0,1"
bitfld.long 0x00 2. "  GMB642 ,Group Modifier Bit 642" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB641 ,Group Modifier Bit 641" "0,1"
bitfld.long 0x00 0. "  GMB640 ,Group Modifier Bit 640" "0,1"
else
hgroup.long 0x0D50++0x03
hide.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D54))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x0D54++0x03
line.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21"
bitfld.long 0x00 31. " GMB703 ,Group Modifier Bit 703" "0,1"
bitfld.long 0x00 30. "  GMB702 ,Group Modifier Bit 702" "0,1"
bitfld.long 0x00 29. "  GMB701 ,Group Modifier Bit 701" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB700 ,Group Modifier Bit 700" "0,1"
bitfld.long 0x00 27. "  GMB699 ,Group Modifier Bit 699" "0,1"
bitfld.long 0x00 26. "  GMB698 ,Group Modifier Bit 698" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB697 ,Group Modifier Bit 697" "0,1"
bitfld.long 0x00 24. "  GMB696 ,Group Modifier Bit 696" "0,1"
bitfld.long 0x00 23. "  GMB695 ,Group Modifier Bit 695" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB694 ,Group Modifier Bit 694" "0,1"
bitfld.long 0x00 21. "  GMB693 ,Group Modifier Bit 693" "0,1"
bitfld.long 0x00 20. "  GMB692 ,Group Modifier Bit 692" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB691 ,Group Modifier Bit 691" "0,1"
bitfld.long 0x00 18. "  GMB690 ,Group Modifier Bit 690" "0,1"
bitfld.long 0x00 17. "  GMB689 ,Group Modifier Bit 689" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB688 ,Group Modifier Bit 688" "0,1"
bitfld.long 0x00 15. "  GMB687 ,Group Modifier Bit 687" "0,1"
bitfld.long 0x00 14. "  GMB686 ,Group Modifier Bit 686" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB685 ,Group Modifier Bit 685" "0,1"
bitfld.long 0x00 12. "  GMB684 ,Group Modifier Bit 684" "0,1"
bitfld.long 0x00 11. "  GMB683 ,Group Modifier Bit 683" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB682 ,Group Modifier Bit 682" "0,1"
bitfld.long 0x00 9. "  GMB681 ,Group Modifier Bit 681" "0,1"
bitfld.long 0x00 8. "  GMB680 ,Group Modifier Bit 680" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB679 ,Group Modifier Bit 679" "0,1"
bitfld.long 0x00 6. "  GMB678 ,Group Modifier Bit 678" "0,1"
bitfld.long 0x00 5. "  GMB677 ,Group Modifier Bit 677" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB676 ,Group Modifier Bit 676" "0,1"
bitfld.long 0x00 3. "  GMB675 ,Group Modifier Bit 675" "0,1"
bitfld.long 0x00 2. "  GMB674 ,Group Modifier Bit 674" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB673 ,Group Modifier Bit 673" "0,1"
bitfld.long 0x00 0. "  GMB672 ,Group Modifier Bit 672" "0,1"
else
hgroup.long 0x0D54++0x03
hide.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D58))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x0D58++0x03
line.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22"
bitfld.long 0x00 31. " GMB735 ,Group Modifier Bit 735" "0,1"
bitfld.long 0x00 30. "  GMB734 ,Group Modifier Bit 734" "0,1"
bitfld.long 0x00 29. "  GMB733 ,Group Modifier Bit 733" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB732 ,Group Modifier Bit 732" "0,1"
bitfld.long 0x00 27. "  GMB731 ,Group Modifier Bit 731" "0,1"
bitfld.long 0x00 26. "  GMB730 ,Group Modifier Bit 730" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB729 ,Group Modifier Bit 729" "0,1"
bitfld.long 0x00 24. "  GMB728 ,Group Modifier Bit 728" "0,1"
bitfld.long 0x00 23. "  GMB727 ,Group Modifier Bit 727" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB726 ,Group Modifier Bit 726" "0,1"
bitfld.long 0x00 21. "  GMB725 ,Group Modifier Bit 725" "0,1"
bitfld.long 0x00 20. "  GMB724 ,Group Modifier Bit 724" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB723 ,Group Modifier Bit 723" "0,1"
bitfld.long 0x00 18. "  GMB722 ,Group Modifier Bit 722" "0,1"
bitfld.long 0x00 17. "  GMB721 ,Group Modifier Bit 721" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB720 ,Group Modifier Bit 720" "0,1"
bitfld.long 0x00 15. "  GMB719 ,Group Modifier Bit 719" "0,1"
bitfld.long 0x00 14. "  GMB718 ,Group Modifier Bit 718" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB717 ,Group Modifier Bit 717" "0,1"
bitfld.long 0x00 12. "  GMB716 ,Group Modifier Bit 716" "0,1"
bitfld.long 0x00 11. "  GMB715 ,Group Modifier Bit 715" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB714 ,Group Modifier Bit 714" "0,1"
bitfld.long 0x00 9. "  GMB713 ,Group Modifier Bit 713" "0,1"
bitfld.long 0x00 8. "  GMB712 ,Group Modifier Bit 712" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB711 ,Group Modifier Bit 711" "0,1"
bitfld.long 0x00 6. "  GMB710 ,Group Modifier Bit 710" "0,1"
bitfld.long 0x00 5. "  GMB709 ,Group Modifier Bit 709" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB708 ,Group Modifier Bit 708" "0,1"
bitfld.long 0x00 3. "  GMB707 ,Group Modifier Bit 707" "0,1"
bitfld.long 0x00 2. "  GMB706 ,Group Modifier Bit 706" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB705 ,Group Modifier Bit 705" "0,1"
bitfld.long 0x00 0. "  GMB704 ,Group Modifier Bit 704" "0,1"
else
hgroup.long 0x0D58++0x03
hide.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D5C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x0D5C++0x03
line.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23"
bitfld.long 0x00 31. " GMB767 ,Group Modifier Bit 767" "0,1"
bitfld.long 0x00 30. "  GMB766 ,Group Modifier Bit 766" "0,1"
bitfld.long 0x00 29. "  GMB765 ,Group Modifier Bit 765" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB764 ,Group Modifier Bit 764" "0,1"
bitfld.long 0x00 27. "  GMB763 ,Group Modifier Bit 763" "0,1"
bitfld.long 0x00 26. "  GMB762 ,Group Modifier Bit 762" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB761 ,Group Modifier Bit 761" "0,1"
bitfld.long 0x00 24. "  GMB760 ,Group Modifier Bit 760" "0,1"
bitfld.long 0x00 23. "  GMB759 ,Group Modifier Bit 759" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB758 ,Group Modifier Bit 758" "0,1"
bitfld.long 0x00 21. "  GMB757 ,Group Modifier Bit 757" "0,1"
bitfld.long 0x00 20. "  GMB756 ,Group Modifier Bit 756" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB755 ,Group Modifier Bit 755" "0,1"
bitfld.long 0x00 18. "  GMB754 ,Group Modifier Bit 754" "0,1"
bitfld.long 0x00 17. "  GMB753 ,Group Modifier Bit 753" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB752 ,Group Modifier Bit 752" "0,1"
bitfld.long 0x00 15. "  GMB751 ,Group Modifier Bit 751" "0,1"
bitfld.long 0x00 14. "  GMB750 ,Group Modifier Bit 750" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB749 ,Group Modifier Bit 749" "0,1"
bitfld.long 0x00 12. "  GMB748 ,Group Modifier Bit 748" "0,1"
bitfld.long 0x00 11. "  GMB747 ,Group Modifier Bit 747" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB746 ,Group Modifier Bit 746" "0,1"
bitfld.long 0x00 9. "  GMB745 ,Group Modifier Bit 745" "0,1"
bitfld.long 0x00 8. "  GMB744 ,Group Modifier Bit 744" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB743 ,Group Modifier Bit 743" "0,1"
bitfld.long 0x00 6. "  GMB742 ,Group Modifier Bit 742" "0,1"
bitfld.long 0x00 5. "  GMB741 ,Group Modifier Bit 741" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB740 ,Group Modifier Bit 740" "0,1"
bitfld.long 0x00 3. "  GMB739 ,Group Modifier Bit 739" "0,1"
bitfld.long 0x00 2. "  GMB738 ,Group Modifier Bit 738" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB737 ,Group Modifier Bit 737" "0,1"
bitfld.long 0x00 0. "  GMB736 ,Group Modifier Bit 736" "0,1"
else
hgroup.long 0x0D5C++0x03
hide.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D60))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x0D60++0x03
line.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24"
bitfld.long 0x00 31. " GMB799 ,Group Modifier Bit 799" "0,1"
bitfld.long 0x00 30. "  GMB798 ,Group Modifier Bit 798" "0,1"
bitfld.long 0x00 29. "  GMB797 ,Group Modifier Bit 797" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB796 ,Group Modifier Bit 796" "0,1"
bitfld.long 0x00 27. "  GMB795 ,Group Modifier Bit 795" "0,1"
bitfld.long 0x00 26. "  GMB794 ,Group Modifier Bit 794" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB793 ,Group Modifier Bit 793" "0,1"
bitfld.long 0x00 24. "  GMB792 ,Group Modifier Bit 792" "0,1"
bitfld.long 0x00 23. "  GMB791 ,Group Modifier Bit 791" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB790 ,Group Modifier Bit 790" "0,1"
bitfld.long 0x00 21. "  GMB789 ,Group Modifier Bit 789" "0,1"
bitfld.long 0x00 20. "  GMB788 ,Group Modifier Bit 788" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB787 ,Group Modifier Bit 787" "0,1"
bitfld.long 0x00 18. "  GMB786 ,Group Modifier Bit 786" "0,1"
bitfld.long 0x00 17. "  GMB785 ,Group Modifier Bit 785" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB784 ,Group Modifier Bit 784" "0,1"
bitfld.long 0x00 15. "  GMB783 ,Group Modifier Bit 783" "0,1"
bitfld.long 0x00 14. "  GMB782 ,Group Modifier Bit 782" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB781 ,Group Modifier Bit 781" "0,1"
bitfld.long 0x00 12. "  GMB780 ,Group Modifier Bit 780" "0,1"
bitfld.long 0x00 11. "  GMB779 ,Group Modifier Bit 779" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB778 ,Group Modifier Bit 778" "0,1"
bitfld.long 0x00 9. "  GMB777 ,Group Modifier Bit 777" "0,1"
bitfld.long 0x00 8. "  GMB776 ,Group Modifier Bit 776" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB775 ,Group Modifier Bit 775" "0,1"
bitfld.long 0x00 6. "  GMB774 ,Group Modifier Bit 774" "0,1"
bitfld.long 0x00 5. "  GMB773 ,Group Modifier Bit 773" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB772 ,Group Modifier Bit 772" "0,1"
bitfld.long 0x00 3. "  GMB771 ,Group Modifier Bit 771" "0,1"
bitfld.long 0x00 2. "  GMB770 ,Group Modifier Bit 770" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB769 ,Group Modifier Bit 769" "0,1"
bitfld.long 0x00 0. "  GMB768 ,Group Modifier Bit 768" "0,1"
else
hgroup.long 0x0D60++0x03
hide.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D64))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x0D64++0x03
line.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25"
bitfld.long 0x00 31. " GMB831 ,Group Modifier Bit 831" "0,1"
bitfld.long 0x00 30. "  GMB830 ,Group Modifier Bit 830" "0,1"
bitfld.long 0x00 29. "  GMB829 ,Group Modifier Bit 829" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB828 ,Group Modifier Bit 828" "0,1"
bitfld.long 0x00 27. "  GMB827 ,Group Modifier Bit 827" "0,1"
bitfld.long 0x00 26. "  GMB826 ,Group Modifier Bit 826" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB825 ,Group Modifier Bit 825" "0,1"
bitfld.long 0x00 24. "  GMB824 ,Group Modifier Bit 824" "0,1"
bitfld.long 0x00 23. "  GMB823 ,Group Modifier Bit 823" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB822 ,Group Modifier Bit 822" "0,1"
bitfld.long 0x00 21. "  GMB821 ,Group Modifier Bit 821" "0,1"
bitfld.long 0x00 20. "  GMB820 ,Group Modifier Bit 820" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB819 ,Group Modifier Bit 819" "0,1"
bitfld.long 0x00 18. "  GMB818 ,Group Modifier Bit 818" "0,1"
bitfld.long 0x00 17. "  GMB817 ,Group Modifier Bit 817" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB816 ,Group Modifier Bit 816" "0,1"
bitfld.long 0x00 15. "  GMB815 ,Group Modifier Bit 815" "0,1"
bitfld.long 0x00 14. "  GMB814 ,Group Modifier Bit 814" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB813 ,Group Modifier Bit 813" "0,1"
bitfld.long 0x00 12. "  GMB812 ,Group Modifier Bit 812" "0,1"
bitfld.long 0x00 11. "  GMB811 ,Group Modifier Bit 811" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB810 ,Group Modifier Bit 810" "0,1"
bitfld.long 0x00 9. "  GMB809 ,Group Modifier Bit 809" "0,1"
bitfld.long 0x00 8. "  GMB808 ,Group Modifier Bit 808" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB807 ,Group Modifier Bit 807" "0,1"
bitfld.long 0x00 6. "  GMB806 ,Group Modifier Bit 806" "0,1"
bitfld.long 0x00 5. "  GMB805 ,Group Modifier Bit 805" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB804 ,Group Modifier Bit 804" "0,1"
bitfld.long 0x00 3. "  GMB803 ,Group Modifier Bit 803" "0,1"
bitfld.long 0x00 2. "  GMB802 ,Group Modifier Bit 802" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB801 ,Group Modifier Bit 801" "0,1"
bitfld.long 0x00 0. "  GMB800 ,Group Modifier Bit 800" "0,1"
else
hgroup.long 0x0D64++0x03
hide.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D68))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01A))
group.long 0x0D68++0x03
line.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26"
bitfld.long 0x00 31. " GMB863 ,Group Modifier Bit 863" "0,1"
bitfld.long 0x00 30. "  GMB862 ,Group Modifier Bit 862" "0,1"
bitfld.long 0x00 29. "  GMB861 ,Group Modifier Bit 861" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB860 ,Group Modifier Bit 860" "0,1"
bitfld.long 0x00 27. "  GMB859 ,Group Modifier Bit 859" "0,1"
bitfld.long 0x00 26. "  GMB858 ,Group Modifier Bit 858" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB857 ,Group Modifier Bit 857" "0,1"
bitfld.long 0x00 24. "  GMB856 ,Group Modifier Bit 856" "0,1"
bitfld.long 0x00 23. "  GMB855 ,Group Modifier Bit 855" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB854 ,Group Modifier Bit 854" "0,1"
bitfld.long 0x00 21. "  GMB853 ,Group Modifier Bit 853" "0,1"
bitfld.long 0x00 20. "  GMB852 ,Group Modifier Bit 852" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB851 ,Group Modifier Bit 851" "0,1"
bitfld.long 0x00 18. "  GMB850 ,Group Modifier Bit 850" "0,1"
bitfld.long 0x00 17. "  GMB849 ,Group Modifier Bit 849" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB848 ,Group Modifier Bit 848" "0,1"
bitfld.long 0x00 15. "  GMB847 ,Group Modifier Bit 847" "0,1"
bitfld.long 0x00 14. "  GMB846 ,Group Modifier Bit 846" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB845 ,Group Modifier Bit 845" "0,1"
bitfld.long 0x00 12. "  GMB844 ,Group Modifier Bit 844" "0,1"
bitfld.long 0x00 11. "  GMB843 ,Group Modifier Bit 843" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB842 ,Group Modifier Bit 842" "0,1"
bitfld.long 0x00 9. "  GMB841 ,Group Modifier Bit 841" "0,1"
bitfld.long 0x00 8. "  GMB840 ,Group Modifier Bit 840" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB839 ,Group Modifier Bit 839" "0,1"
bitfld.long 0x00 6. "  GMB838 ,Group Modifier Bit 838" "0,1"
bitfld.long 0x00 5. "  GMB837 ,Group Modifier Bit 837" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB836 ,Group Modifier Bit 836" "0,1"
bitfld.long 0x00 3. "  GMB835 ,Group Modifier Bit 835" "0,1"
bitfld.long 0x00 2. "  GMB834 ,Group Modifier Bit 834" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB833 ,Group Modifier Bit 833" "0,1"
bitfld.long 0x00 0. "  GMB832 ,Group Modifier Bit 832" "0,1"
else
hgroup.long 0x0D68++0x03
hide.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D6C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x0D6C++0x03
line.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27"
bitfld.long 0x00 31. " GMB895 ,Group Modifier Bit 895" "0,1"
bitfld.long 0x00 30. "  GMB894 ,Group Modifier Bit 894" "0,1"
bitfld.long 0x00 29. "  GMB893 ,Group Modifier Bit 893" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB892 ,Group Modifier Bit 892" "0,1"
bitfld.long 0x00 27. "  GMB891 ,Group Modifier Bit 891" "0,1"
bitfld.long 0x00 26. "  GMB890 ,Group Modifier Bit 890" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB889 ,Group Modifier Bit 889" "0,1"
bitfld.long 0x00 24. "  GMB888 ,Group Modifier Bit 888" "0,1"
bitfld.long 0x00 23. "  GMB887 ,Group Modifier Bit 887" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB886 ,Group Modifier Bit 886" "0,1"
bitfld.long 0x00 21. "  GMB885 ,Group Modifier Bit 885" "0,1"
bitfld.long 0x00 20. "  GMB884 ,Group Modifier Bit 884" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB883 ,Group Modifier Bit 883" "0,1"
bitfld.long 0x00 18. "  GMB882 ,Group Modifier Bit 882" "0,1"
bitfld.long 0x00 17. "  GMB881 ,Group Modifier Bit 881" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB880 ,Group Modifier Bit 880" "0,1"
bitfld.long 0x00 15. "  GMB879 ,Group Modifier Bit 879" "0,1"
bitfld.long 0x00 14. "  GMB878 ,Group Modifier Bit 878" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB877 ,Group Modifier Bit 877" "0,1"
bitfld.long 0x00 12. "  GMB876 ,Group Modifier Bit 876" "0,1"
bitfld.long 0x00 11. "  GMB875 ,Group Modifier Bit 875" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB874 ,Group Modifier Bit 874" "0,1"
bitfld.long 0x00 9. "  GMB873 ,Group Modifier Bit 873" "0,1"
bitfld.long 0x00 8. "  GMB872 ,Group Modifier Bit 872" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB871 ,Group Modifier Bit 871" "0,1"
bitfld.long 0x00 6. "  GMB870 ,Group Modifier Bit 870" "0,1"
bitfld.long 0x00 5. "  GMB869 ,Group Modifier Bit 869" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB868 ,Group Modifier Bit 868" "0,1"
bitfld.long 0x00 3. "  GMB867 ,Group Modifier Bit 867" "0,1"
bitfld.long 0x00 2. "  GMB866 ,Group Modifier Bit 866" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB865 ,Group Modifier Bit 865" "0,1"
bitfld.long 0x00 0. "  GMB864 ,Group Modifier Bit 864" "0,1"
else
hgroup.long 0x0D6C++0x03
hide.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D70))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x0D70++0x03
line.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28"
bitfld.long 0x00 31. " GMB927 ,Group Modifier Bit 927" "0,1"
bitfld.long 0x00 30. "  GMB926 ,Group Modifier Bit 926" "0,1"
bitfld.long 0x00 29. "  GMB925 ,Group Modifier Bit 925" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB924 ,Group Modifier Bit 924" "0,1"
bitfld.long 0x00 27. "  GMB923 ,Group Modifier Bit 923" "0,1"
bitfld.long 0x00 26. "  GMB922 ,Group Modifier Bit 922" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB921 ,Group Modifier Bit 921" "0,1"
bitfld.long 0x00 24. "  GMB920 ,Group Modifier Bit 920" "0,1"
bitfld.long 0x00 23. "  GMB919 ,Group Modifier Bit 919" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB918 ,Group Modifier Bit 918" "0,1"
bitfld.long 0x00 21. "  GMB917 ,Group Modifier Bit 917" "0,1"
bitfld.long 0x00 20. "  GMB916 ,Group Modifier Bit 916" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB915 ,Group Modifier Bit 915" "0,1"
bitfld.long 0x00 18. "  GMB914 ,Group Modifier Bit 914" "0,1"
bitfld.long 0x00 17. "  GMB913 ,Group Modifier Bit 913" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB912 ,Group Modifier Bit 912" "0,1"
bitfld.long 0x00 15. "  GMB911 ,Group Modifier Bit 911" "0,1"
bitfld.long 0x00 14. "  GMB910 ,Group Modifier Bit 910" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB909 ,Group Modifier Bit 909" "0,1"
bitfld.long 0x00 12. "  GMB908 ,Group Modifier Bit 908" "0,1"
bitfld.long 0x00 11. "  GMB907 ,Group Modifier Bit 907" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB906 ,Group Modifier Bit 906" "0,1"
bitfld.long 0x00 9. "  GMB905 ,Group Modifier Bit 905" "0,1"
bitfld.long 0x00 8. "  GMB904 ,Group Modifier Bit 904" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB903 ,Group Modifier Bit 903" "0,1"
bitfld.long 0x00 6. "  GMB902 ,Group Modifier Bit 902" "0,1"
bitfld.long 0x00 5. "  GMB901 ,Group Modifier Bit 901" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB900 ,Group Modifier Bit 900" "0,1"
bitfld.long 0x00 3. "  GMB899 ,Group Modifier Bit 899" "0,1"
bitfld.long 0x00 2. "  GMB898 ,Group Modifier Bit 898" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB897 ,Group Modifier Bit 897" "0,1"
bitfld.long 0x00 0. "  GMB896 ,Group Modifier Bit 896" "0,1"
else
hgroup.long 0x0D70++0x03
hide.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D74))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x0D74++0x03
line.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29"
bitfld.long 0x00 31. " GMB959 ,Group Modifier Bit 959" "0,1"
bitfld.long 0x00 30. "  GMB958 ,Group Modifier Bit 958" "0,1"
bitfld.long 0x00 29. "  GMB957 ,Group Modifier Bit 957" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB956 ,Group Modifier Bit 956" "0,1"
bitfld.long 0x00 27. "  GMB955 ,Group Modifier Bit 955" "0,1"
bitfld.long 0x00 26. "  GMB954 ,Group Modifier Bit 954" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB953 ,Group Modifier Bit 953" "0,1"
bitfld.long 0x00 24. "  GMB952 ,Group Modifier Bit 952" "0,1"
bitfld.long 0x00 23. "  GMB951 ,Group Modifier Bit 951" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB950 ,Group Modifier Bit 950" "0,1"
bitfld.long 0x00 21. "  GMB949 ,Group Modifier Bit 949" "0,1"
bitfld.long 0x00 20. "  GMB948 ,Group Modifier Bit 948" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB947 ,Group Modifier Bit 947" "0,1"
bitfld.long 0x00 18. "  GMB946 ,Group Modifier Bit 946" "0,1"
bitfld.long 0x00 17. "  GMB945 ,Group Modifier Bit 945" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB944 ,Group Modifier Bit 944" "0,1"
bitfld.long 0x00 15. "  GMB943 ,Group Modifier Bit 943" "0,1"
bitfld.long 0x00 14. "  GMB942 ,Group Modifier Bit 942" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB941 ,Group Modifier Bit 941" "0,1"
bitfld.long 0x00 12. "  GMB940 ,Group Modifier Bit 940" "0,1"
bitfld.long 0x00 11. "  GMB939 ,Group Modifier Bit 939" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB938 ,Group Modifier Bit 938" "0,1"
bitfld.long 0x00 9. "  GMB937 ,Group Modifier Bit 937" "0,1"
bitfld.long 0x00 8. "  GMB936 ,Group Modifier Bit 936" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB935 ,Group Modifier Bit 935" "0,1"
bitfld.long 0x00 6. "  GMB934 ,Group Modifier Bit 934" "0,1"
bitfld.long 0x00 5. "  GMB933 ,Group Modifier Bit 933" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB932 ,Group Modifier Bit 932" "0,1"
bitfld.long 0x00 3. "  GMB931 ,Group Modifier Bit 931" "0,1"
bitfld.long 0x00 2. "  GMB930 ,Group Modifier Bit 930" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB929 ,Group Modifier Bit 929" "0,1"
bitfld.long 0x00 0. "  GMB928 ,Group Modifier Bit 928" "0,1"
else
hgroup.long 0x0D74++0x03
hide.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D78))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x0D78++0x03
line.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30"
bitfld.long 0x00 31. " GMB991 ,Group Modifier Bit 991" "0,1"
bitfld.long 0x00 30. "  GMB990 ,Group Modifier Bit 990" "0,1"
bitfld.long 0x00 29. "  GMB989 ,Group Modifier Bit 989" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB988 ,Group Modifier Bit 988" "0,1"
bitfld.long 0x00 27. "  GMB987 ,Group Modifier Bit 987" "0,1"
bitfld.long 0x00 26. "  GMB986 ,Group Modifier Bit 986" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB985 ,Group Modifier Bit 985" "0,1"
bitfld.long 0x00 24. "  GMB984 ,Group Modifier Bit 984" "0,1"
bitfld.long 0x00 23. "  GMB983 ,Group Modifier Bit 983" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB982 ,Group Modifier Bit 982" "0,1"
bitfld.long 0x00 21. "  GMB981 ,Group Modifier Bit 981" "0,1"
bitfld.long 0x00 20. "  GMB980 ,Group Modifier Bit 980" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB979 ,Group Modifier Bit 979" "0,1"
bitfld.long 0x00 18. "  GMB978 ,Group Modifier Bit 978" "0,1"
bitfld.long 0x00 17. "  GMB977 ,Group Modifier Bit 977" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB976 ,Group Modifier Bit 976" "0,1"
bitfld.long 0x00 15. "  GMB975 ,Group Modifier Bit 975" "0,1"
bitfld.long 0x00 14. "  GMB974 ,Group Modifier Bit 974" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB973 ,Group Modifier Bit 973" "0,1"
bitfld.long 0x00 12. "  GMB972 ,Group Modifier Bit 972" "0,1"
bitfld.long 0x00 11. "  GMB971 ,Group Modifier Bit 971" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB970 ,Group Modifier Bit 970" "0,1"
bitfld.long 0x00 9. "  GMB969 ,Group Modifier Bit 969" "0,1"
bitfld.long 0x00 8. "  GMB968 ,Group Modifier Bit 968" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB967 ,Group Modifier Bit 967" "0,1"
bitfld.long 0x00 6. "  GMB966 ,Group Modifier Bit 966" "0,1"
bitfld.long 0x00 5. "  GMB965 ,Group Modifier Bit 965" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB964 ,Group Modifier Bit 964" "0,1"
bitfld.long 0x00 3. "  GMB963 ,Group Modifier Bit 963" "0,1"
bitfld.long 0x00 2. "  GMB962 ,Group Modifier Bit 962" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB961 ,Group Modifier Bit 961" "0,1"
bitfld.long 0x00 0. "  GMB960 ,Group Modifier Bit 960" "0,1"
else
hgroup.long 0x0D78++0x03
hide.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30"
endif
tree.end
width 14.
tree "Non-secure Access Control Registers"
hgroup.long 0x0E00++0x03
hide.long 0x00 "GICD_NSACR0,Non-secure Access Control Register 0"
hgroup.long 0xE04++0x03
hide.long 0x00 "GICD_NSACR1,Non-secure Access Control Register 1"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE08)))
group.long 0xE08++0x03
line.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2"
bitfld.long 0x00 30.--31. " NS_ACCESS47  ,Controls Non-secure access of the interrupt with ID47 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS46  ,Controls Non-secure access of the interrupt with ID46 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS45  ,Controls Non-secure access of the interrupt with ID45 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS44  ,Controls Non-secure access of the interrupt with ID44 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS43  ,Controls Non-secure access of the interrupt with ID43 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS42  ,Controls Non-secure access of the interrupt with ID42 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS41  ,Controls Non-secure access of the interrupt with ID41 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS40  ,Controls Non-secure access of the interrupt with ID40 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS39  ,Controls Non-secure access of the interrupt with ID39 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS38  ,Controls Non-secure access of the interrupt with ID38 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS37  ,Controls Non-secure access of the interrupt with ID37 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS36  ,Controls Non-secure access of the interrupt with ID36 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS35  ,Controls Non-secure access of the interrupt with ID35 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS34  ,Controls Non-secure access of the interrupt with ID34 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS33  ,Controls Non-secure access of the interrupt with ID33 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS32  ,Controls Non-secure access of the interrupt with ID32 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE08++0x03
hide.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0C)))
group.long 0xE0C++0x03
line.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3"
bitfld.long 0x00 30.--31. " NS_ACCESS63  ,Controls Non-secure access of the interrupt with ID63 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS62  ,Controls Non-secure access of the interrupt with ID62 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS61  ,Controls Non-secure access of the interrupt with ID61 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS60  ,Controls Non-secure access of the interrupt with ID60 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS59  ,Controls Non-secure access of the interrupt with ID59 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS58  ,Controls Non-secure access of the interrupt with ID58 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS57  ,Controls Non-secure access of the interrupt with ID57 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS56  ,Controls Non-secure access of the interrupt with ID56 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS55  ,Controls Non-secure access of the interrupt with ID55 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS54  ,Controls Non-secure access of the interrupt with ID54 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS53  ,Controls Non-secure access of the interrupt with ID53 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS52  ,Controls Non-secure access of the interrupt with ID52 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS51  ,Controls Non-secure access of the interrupt with ID51 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS50  ,Controls Non-secure access of the interrupt with ID50 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS49  ,Controls Non-secure access of the interrupt with ID49 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS48  ,Controls Non-secure access of the interrupt with ID48 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE0C++0x03
hide.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE10)))
group.long 0xE10++0x03
line.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4"
bitfld.long 0x00 30.--31. " NS_ACCESS79  ,Controls Non-secure access of the interrupt with ID79 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS78  ,Controls Non-secure access of the interrupt with ID78 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS77  ,Controls Non-secure access of the interrupt with ID77 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS76  ,Controls Non-secure access of the interrupt with ID76 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS75  ,Controls Non-secure access of the interrupt with ID75 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS74  ,Controls Non-secure access of the interrupt with ID74 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS73  ,Controls Non-secure access of the interrupt with ID73 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS72  ,Controls Non-secure access of the interrupt with ID72 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS71  ,Controls Non-secure access of the interrupt with ID71 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS70  ,Controls Non-secure access of the interrupt with ID70 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS69  ,Controls Non-secure access of the interrupt with ID69 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS68  ,Controls Non-secure access of the interrupt with ID68 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS67  ,Controls Non-secure access of the interrupt with ID67 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS66  ,Controls Non-secure access of the interrupt with ID66 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS65  ,Controls Non-secure access of the interrupt with ID65 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS64  ,Controls Non-secure access of the interrupt with ID64 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE10++0x03
hide.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE14)))
group.long 0xE14++0x03
line.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5"
bitfld.long 0x00 30.--31. " NS_ACCESS95  ,Controls Non-secure access of the interrupt with ID95 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS94  ,Controls Non-secure access of the interrupt with ID94 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS93  ,Controls Non-secure access of the interrupt with ID93 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS92  ,Controls Non-secure access of the interrupt with ID92 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS91  ,Controls Non-secure access of the interrupt with ID91 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS90  ,Controls Non-secure access of the interrupt with ID90 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS89  ,Controls Non-secure access of the interrupt with ID89 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS88  ,Controls Non-secure access of the interrupt with ID88 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS87  ,Controls Non-secure access of the interrupt with ID87 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS86  ,Controls Non-secure access of the interrupt with ID86 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS85  ,Controls Non-secure access of the interrupt with ID85 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS84  ,Controls Non-secure access of the interrupt with ID84 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS83  ,Controls Non-secure access of the interrupt with ID83 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS82  ,Controls Non-secure access of the interrupt with ID82 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS81  ,Controls Non-secure access of the interrupt with ID81 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS80  ,Controls Non-secure access of the interrupt with ID80 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE14++0x03
hide.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE18)))
group.long 0xE18++0x03
line.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6"
bitfld.long 0x00 30.--31. " NS_ACCESS111 ,Controls Non-secure access of the interrupt with ID111" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS110 ,Controls Non-secure access of the interrupt with ID110" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS109 ,Controls Non-secure access of the interrupt with ID109" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS108 ,Controls Non-secure access of the interrupt with ID108" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS107 ,Controls Non-secure access of the interrupt with ID107" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS106 ,Controls Non-secure access of the interrupt with ID106" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS105 ,Controls Non-secure access of the interrupt with ID105" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS104 ,Controls Non-secure access of the interrupt with ID104" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS103 ,Controls Non-secure access of the interrupt with ID103" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS102 ,Controls Non-secure access of the interrupt with ID102" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS101 ,Controls Non-secure access of the interrupt with ID101" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS100 ,Controls Non-secure access of the interrupt with ID100" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS99  ,Controls Non-secure access of the interrupt with ID99 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS98  ,Controls Non-secure access of the interrupt with ID98 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS97  ,Controls Non-secure access of the interrupt with ID97 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS96  ,Controls Non-secure access of the interrupt with ID96 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE18++0x03
hide.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE1C)))
group.long 0xE1C++0x03
line.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7"
bitfld.long 0x00 30.--31. " NS_ACCESS127 ,Controls Non-secure access of the interrupt with ID127" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS126 ,Controls Non-secure access of the interrupt with ID126" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS125 ,Controls Non-secure access of the interrupt with ID125" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS124 ,Controls Non-secure access of the interrupt with ID124" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS123 ,Controls Non-secure access of the interrupt with ID123" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS122 ,Controls Non-secure access of the interrupt with ID122" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS121 ,Controls Non-secure access of the interrupt with ID121" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS120 ,Controls Non-secure access of the interrupt with ID120" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS119 ,Controls Non-secure access of the interrupt with ID119" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS118 ,Controls Non-secure access of the interrupt with ID118" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS117 ,Controls Non-secure access of the interrupt with ID117" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS116 ,Controls Non-secure access of the interrupt with ID116" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS115 ,Controls Non-secure access of the interrupt with ID115" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS114 ,Controls Non-secure access of the interrupt with ID114" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS113 ,Controls Non-secure access of the interrupt with ID113" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS112 ,Controls Non-secure access of the interrupt with ID112" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE1C++0x03
hide.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE20)))
group.long 0xE20++0x03
line.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8"
bitfld.long 0x00 30.--31. " NS_ACCESS143 ,Controls Non-secure access of the interrupt with ID143" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS142 ,Controls Non-secure access of the interrupt with ID142" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS141 ,Controls Non-secure access of the interrupt with ID141" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS140 ,Controls Non-secure access of the interrupt with ID140" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS139 ,Controls Non-secure access of the interrupt with ID139" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS138 ,Controls Non-secure access of the interrupt with ID138" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS137 ,Controls Non-secure access of the interrupt with ID137" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS136 ,Controls Non-secure access of the interrupt with ID136" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS135 ,Controls Non-secure access of the interrupt with ID135" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS134 ,Controls Non-secure access of the interrupt with ID134" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS133 ,Controls Non-secure access of the interrupt with ID133" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS132 ,Controls Non-secure access of the interrupt with ID132" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS131 ,Controls Non-secure access of the interrupt with ID131" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS130 ,Controls Non-secure access of the interrupt with ID130" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS129 ,Controls Non-secure access of the interrupt with ID129" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS128 ,Controls Non-secure access of the interrupt with ID128" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE20++0x03
hide.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE24)))
group.long 0xE24++0x03
line.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9"
bitfld.long 0x00 30.--31. " NS_ACCESS159 ,Controls Non-secure access of the interrupt with ID159" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS158 ,Controls Non-secure access of the interrupt with ID158" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS157 ,Controls Non-secure access of the interrupt with ID157" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS156 ,Controls Non-secure access of the interrupt with ID156" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS155 ,Controls Non-secure access of the interrupt with ID155" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS154 ,Controls Non-secure access of the interrupt with ID154" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS153 ,Controls Non-secure access of the interrupt with ID153" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS152 ,Controls Non-secure access of the interrupt with ID152" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS151 ,Controls Non-secure access of the interrupt with ID151" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS150 ,Controls Non-secure access of the interrupt with ID150" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS149 ,Controls Non-secure access of the interrupt with ID149" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS148 ,Controls Non-secure access of the interrupt with ID148" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS147 ,Controls Non-secure access of the interrupt with ID147" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS146 ,Controls Non-secure access of the interrupt with ID146" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS145 ,Controls Non-secure access of the interrupt with ID145" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS144 ,Controls Non-secure access of the interrupt with ID144" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE24++0x03
hide.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE28)))
group.long 0xE28++0x03
line.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10"
bitfld.long 0x00 30.--31. " NS_ACCESS175 ,Controls Non-secure access of the interrupt with ID175" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS174 ,Controls Non-secure access of the interrupt with ID174" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS173 ,Controls Non-secure access of the interrupt with ID173" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS172 ,Controls Non-secure access of the interrupt with ID172" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS171 ,Controls Non-secure access of the interrupt with ID171" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS170 ,Controls Non-secure access of the interrupt with ID170" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS169 ,Controls Non-secure access of the interrupt with ID169" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS168 ,Controls Non-secure access of the interrupt with ID168" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS167 ,Controls Non-secure access of the interrupt with ID167" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS166 ,Controls Non-secure access of the interrupt with ID166" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS165 ,Controls Non-secure access of the interrupt with ID165" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS164 ,Controls Non-secure access of the interrupt with ID164" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS163 ,Controls Non-secure access of the interrupt with ID163" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS162 ,Controls Non-secure access of the interrupt with ID162" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS161 ,Controls Non-secure access of the interrupt with ID161" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS160 ,Controls Non-secure access of the interrupt with ID160" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE28++0x03
hide.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE2C)))
group.long 0xE2C++0x03
line.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11"
bitfld.long 0x00 30.--31. " NS_ACCESS191 ,Controls Non-secure access of the interrupt with ID191" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS190 ,Controls Non-secure access of the interrupt with ID190" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS189 ,Controls Non-secure access of the interrupt with ID189" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS188 ,Controls Non-secure access of the interrupt with ID188" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS187 ,Controls Non-secure access of the interrupt with ID187" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS186 ,Controls Non-secure access of the interrupt with ID186" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS185 ,Controls Non-secure access of the interrupt with ID185" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS184 ,Controls Non-secure access of the interrupt with ID184" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS183 ,Controls Non-secure access of the interrupt with ID183" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS182 ,Controls Non-secure access of the interrupt with ID182" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS181 ,Controls Non-secure access of the interrupt with ID181" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS180 ,Controls Non-secure access of the interrupt with ID180" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS179 ,Controls Non-secure access of the interrupt with ID179" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS178 ,Controls Non-secure access of the interrupt with ID178" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS177 ,Controls Non-secure access of the interrupt with ID177" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS176 ,Controls Non-secure access of the interrupt with ID176" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE2C++0x03
hide.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE30)))
group.long 0xE30++0x03
line.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12"
bitfld.long 0x00 30.--31. " NS_ACCESS207 ,Controls Non-secure access of the interrupt with ID207" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS206 ,Controls Non-secure access of the interrupt with ID206" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS205 ,Controls Non-secure access of the interrupt with ID205" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS204 ,Controls Non-secure access of the interrupt with ID204" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS203 ,Controls Non-secure access of the interrupt with ID203" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS202 ,Controls Non-secure access of the interrupt with ID202" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS201 ,Controls Non-secure access of the interrupt with ID201" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS200 ,Controls Non-secure access of the interrupt with ID200" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS199 ,Controls Non-secure access of the interrupt with ID199" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS198 ,Controls Non-secure access of the interrupt with ID198" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS197 ,Controls Non-secure access of the interrupt with ID197" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS196 ,Controls Non-secure access of the interrupt with ID196" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS195 ,Controls Non-secure access of the interrupt with ID195" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS194 ,Controls Non-secure access of the interrupt with ID194" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS193 ,Controls Non-secure access of the interrupt with ID193" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS192 ,Controls Non-secure access of the interrupt with ID192" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE30++0x03
hide.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE34)))
group.long 0xE34++0x03
line.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13"
bitfld.long 0x00 30.--31. " NS_ACCESS223 ,Controls Non-secure access of the interrupt with ID223" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS222 ,Controls Non-secure access of the interrupt with ID222" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS221 ,Controls Non-secure access of the interrupt with ID221" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS220 ,Controls Non-secure access of the interrupt with ID220" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS219 ,Controls Non-secure access of the interrupt with ID219" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS218 ,Controls Non-secure access of the interrupt with ID218" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS217 ,Controls Non-secure access of the interrupt with ID217" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS216 ,Controls Non-secure access of the interrupt with ID216" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS215 ,Controls Non-secure access of the interrupt with ID215" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS214 ,Controls Non-secure access of the interrupt with ID214" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS213 ,Controls Non-secure access of the interrupt with ID213" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS212 ,Controls Non-secure access of the interrupt with ID212" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS211 ,Controls Non-secure access of the interrupt with ID211" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS210 ,Controls Non-secure access of the interrupt with ID210" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS209 ,Controls Non-secure access of the interrupt with ID209" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS208 ,Controls Non-secure access of the interrupt with ID208" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE34++0x03
hide.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE38)))
group.long 0xE38++0x03
line.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14"
bitfld.long 0x00 30.--31. " NS_ACCESS239 ,Controls Non-secure access of the interrupt with ID239" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS238 ,Controls Non-secure access of the interrupt with ID238" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS237 ,Controls Non-secure access of the interrupt with ID237" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS236 ,Controls Non-secure access of the interrupt with ID236" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS235 ,Controls Non-secure access of the interrupt with ID235" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS234 ,Controls Non-secure access of the interrupt with ID234" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS233 ,Controls Non-secure access of the interrupt with ID233" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS232 ,Controls Non-secure access of the interrupt with ID232" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS231 ,Controls Non-secure access of the interrupt with ID231" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS230 ,Controls Non-secure access of the interrupt with ID230" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS229 ,Controls Non-secure access of the interrupt with ID229" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS228 ,Controls Non-secure access of the interrupt with ID228" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS227 ,Controls Non-secure access of the interrupt with ID227" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS226 ,Controls Non-secure access of the interrupt with ID226" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS225 ,Controls Non-secure access of the interrupt with ID225" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS224 ,Controls Non-secure access of the interrupt with ID224" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE38++0x03
hide.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE3C)))
group.long 0xE3C++0x03
line.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15"
bitfld.long 0x00 30.--31. " NS_ACCESS255 ,Controls Non-secure access of the interrupt with ID255" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS254 ,Controls Non-secure access of the interrupt with ID254" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS253 ,Controls Non-secure access of the interrupt with ID253" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS252 ,Controls Non-secure access of the interrupt with ID252" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS251 ,Controls Non-secure access of the interrupt with ID251" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS250 ,Controls Non-secure access of the interrupt with ID250" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS249 ,Controls Non-secure access of the interrupt with ID249" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS248 ,Controls Non-secure access of the interrupt with ID248" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS247 ,Controls Non-secure access of the interrupt with ID247" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS246 ,Controls Non-secure access of the interrupt with ID246" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS245 ,Controls Non-secure access of the interrupt with ID245" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS244 ,Controls Non-secure access of the interrupt with ID244" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS243 ,Controls Non-secure access of the interrupt with ID243" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS242 ,Controls Non-secure access of the interrupt with ID242" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS241 ,Controls Non-secure access of the interrupt with ID241" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS240 ,Controls Non-secure access of the interrupt with ID240" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE3C++0x03
hide.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE40)))
group.long 0xE40++0x03
line.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16"
bitfld.long 0x00 30.--31. " NS_ACCESS271 ,Controls Non-secure access of the interrupt with ID271" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS270 ,Controls Non-secure access of the interrupt with ID270" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS269 ,Controls Non-secure access of the interrupt with ID269" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS268 ,Controls Non-secure access of the interrupt with ID268" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS267 ,Controls Non-secure access of the interrupt with ID267" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS266 ,Controls Non-secure access of the interrupt with ID266" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS265 ,Controls Non-secure access of the interrupt with ID265" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS264 ,Controls Non-secure access of the interrupt with ID264" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS263 ,Controls Non-secure access of the interrupt with ID263" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS262 ,Controls Non-secure access of the interrupt with ID262" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS261 ,Controls Non-secure access of the interrupt with ID261" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS260 ,Controls Non-secure access of the interrupt with ID260" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS259 ,Controls Non-secure access of the interrupt with ID259" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS258 ,Controls Non-secure access of the interrupt with ID258" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS257 ,Controls Non-secure access of the interrupt with ID257" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS256 ,Controls Non-secure access of the interrupt with ID256" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE40++0x03
hide.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE44)))
group.long 0xE44++0x03
line.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17"
bitfld.long 0x00 30.--31. " NS_ACCESS287 ,Controls Non-secure access of the interrupt with ID287" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS286 ,Controls Non-secure access of the interrupt with ID286" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS285 ,Controls Non-secure access of the interrupt with ID285" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS284 ,Controls Non-secure access of the interrupt with ID284" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS283 ,Controls Non-secure access of the interrupt with ID283" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS282 ,Controls Non-secure access of the interrupt with ID282" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS281 ,Controls Non-secure access of the interrupt with ID281" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS280 ,Controls Non-secure access of the interrupt with ID280" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS279 ,Controls Non-secure access of the interrupt with ID279" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS278 ,Controls Non-secure access of the interrupt with ID278" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS277 ,Controls Non-secure access of the interrupt with ID277" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS276 ,Controls Non-secure access of the interrupt with ID276" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS275 ,Controls Non-secure access of the interrupt with ID275" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS274 ,Controls Non-secure access of the interrupt with ID274" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS273 ,Controls Non-secure access of the interrupt with ID273" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS272 ,Controls Non-secure access of the interrupt with ID272" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE44++0x03
hide.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE48)))
group.long 0xE48++0x03
line.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18"
bitfld.long 0x00 30.--31. " NS_ACCESS303 ,Controls Non-secure access of the interrupt with ID303" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS302 ,Controls Non-secure access of the interrupt with ID302" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS301 ,Controls Non-secure access of the interrupt with ID301" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS300 ,Controls Non-secure access of the interrupt with ID300" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS299 ,Controls Non-secure access of the interrupt with ID299" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS298 ,Controls Non-secure access of the interrupt with ID298" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS297 ,Controls Non-secure access of the interrupt with ID297" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS296 ,Controls Non-secure access of the interrupt with ID296" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS295 ,Controls Non-secure access of the interrupt with ID295" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS294 ,Controls Non-secure access of the interrupt with ID294" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS293 ,Controls Non-secure access of the interrupt with ID293" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS292 ,Controls Non-secure access of the interrupt with ID292" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS291 ,Controls Non-secure access of the interrupt with ID291" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS290 ,Controls Non-secure access of the interrupt with ID290" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS289 ,Controls Non-secure access of the interrupt with ID289" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS288 ,Controls Non-secure access of the interrupt with ID288" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE48++0x03
hide.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4C)))
group.long 0xE4C++0x03
line.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19"
bitfld.long 0x00 30.--31. " NS_ACCESS319 ,Controls Non-secure access of the interrupt with ID319" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS318 ,Controls Non-secure access of the interrupt with ID318" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS317 ,Controls Non-secure access of the interrupt with ID317" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS316 ,Controls Non-secure access of the interrupt with ID316" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS315 ,Controls Non-secure access of the interrupt with ID315" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS314 ,Controls Non-secure access of the interrupt with ID314" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS313 ,Controls Non-secure access of the interrupt with ID313" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS312 ,Controls Non-secure access of the interrupt with ID312" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS311 ,Controls Non-secure access of the interrupt with ID311" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS310 ,Controls Non-secure access of the interrupt with ID310" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS309 ,Controls Non-secure access of the interrupt with ID309" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS308 ,Controls Non-secure access of the interrupt with ID308" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS307 ,Controls Non-secure access of the interrupt with ID307" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS306 ,Controls Non-secure access of the interrupt with ID306" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS305 ,Controls Non-secure access of the interrupt with ID305" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS304 ,Controls Non-secure access of the interrupt with ID304" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE4C++0x03
hide.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE50)))
group.long 0xE50++0x03
line.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20"
bitfld.long 0x00 30.--31. " NS_ACCESS335 ,Controls Non-secure access of the interrupt with ID335" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS334 ,Controls Non-secure access of the interrupt with ID334" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS333 ,Controls Non-secure access of the interrupt with ID333" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS332 ,Controls Non-secure access of the interrupt with ID332" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS331 ,Controls Non-secure access of the interrupt with ID331" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS330 ,Controls Non-secure access of the interrupt with ID330" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS329 ,Controls Non-secure access of the interrupt with ID329" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS328 ,Controls Non-secure access of the interrupt with ID328" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS327 ,Controls Non-secure access of the interrupt with ID327" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS326 ,Controls Non-secure access of the interrupt with ID326" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS325 ,Controls Non-secure access of the interrupt with ID325" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS324 ,Controls Non-secure access of the interrupt with ID324" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS323 ,Controls Non-secure access of the interrupt with ID323" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS322 ,Controls Non-secure access of the interrupt with ID322" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS321 ,Controls Non-secure access of the interrupt with ID321" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS320 ,Controls Non-secure access of the interrupt with ID320" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE50++0x03
hide.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE54)))
group.long 0xE54++0x03
line.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21"
bitfld.long 0x00 30.--31. " NS_ACCESS351 ,Controls Non-secure access of the interrupt with ID351" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS350 ,Controls Non-secure access of the interrupt with ID350" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS349 ,Controls Non-secure access of the interrupt with ID349" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS348 ,Controls Non-secure access of the interrupt with ID348" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS347 ,Controls Non-secure access of the interrupt with ID347" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS346 ,Controls Non-secure access of the interrupt with ID346" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS345 ,Controls Non-secure access of the interrupt with ID345" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS344 ,Controls Non-secure access of the interrupt with ID344" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS343 ,Controls Non-secure access of the interrupt with ID343" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS342 ,Controls Non-secure access of the interrupt with ID342" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS341 ,Controls Non-secure access of the interrupt with ID341" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS340 ,Controls Non-secure access of the interrupt with ID340" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS339 ,Controls Non-secure access of the interrupt with ID339" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS338 ,Controls Non-secure access of the interrupt with ID338" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS337 ,Controls Non-secure access of the interrupt with ID337" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS336 ,Controls Non-secure access of the interrupt with ID336" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE54++0x03
hide.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE58)))
group.long 0xE58++0x03
line.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22"
bitfld.long 0x00 30.--31. " NS_ACCESS367 ,Controls Non-secure access of the interrupt with ID367" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS366 ,Controls Non-secure access of the interrupt with ID366" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS365 ,Controls Non-secure access of the interrupt with ID365" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS364 ,Controls Non-secure access of the interrupt with ID364" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS363 ,Controls Non-secure access of the interrupt with ID363" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS362 ,Controls Non-secure access of the interrupt with ID362" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS361 ,Controls Non-secure access of the interrupt with ID361" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS360 ,Controls Non-secure access of the interrupt with ID360" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS359 ,Controls Non-secure access of the interrupt with ID359" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS358 ,Controls Non-secure access of the interrupt with ID358" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS357 ,Controls Non-secure access of the interrupt with ID357" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS356 ,Controls Non-secure access of the interrupt with ID356" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS355 ,Controls Non-secure access of the interrupt with ID355" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS354 ,Controls Non-secure access of the interrupt with ID354" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS353 ,Controls Non-secure access of the interrupt with ID353" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS352 ,Controls Non-secure access of the interrupt with ID352" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE58++0x03
hide.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE5C)))
group.long 0xE5C++0x03
line.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23"
bitfld.long 0x00 30.--31. " NS_ACCESS383 ,Controls Non-secure access of the interrupt with ID383" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS382 ,Controls Non-secure access of the interrupt with ID382" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS381 ,Controls Non-secure access of the interrupt with ID381" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS380 ,Controls Non-secure access of the interrupt with ID380" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS379 ,Controls Non-secure access of the interrupt with ID379" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS378 ,Controls Non-secure access of the interrupt with ID378" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS377 ,Controls Non-secure access of the interrupt with ID377" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS376 ,Controls Non-secure access of the interrupt with ID376" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS375 ,Controls Non-secure access of the interrupt with ID375" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS374 ,Controls Non-secure access of the interrupt with ID374" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS373 ,Controls Non-secure access of the interrupt with ID373" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS372 ,Controls Non-secure access of the interrupt with ID372" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS371 ,Controls Non-secure access of the interrupt with ID371" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS370 ,Controls Non-secure access of the interrupt with ID370" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS369 ,Controls Non-secure access of the interrupt with ID369" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS368 ,Controls Non-secure access of the interrupt with ID368" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE5C++0x03
hide.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE60)))
group.long 0xE60++0x03
line.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24"
bitfld.long 0x00 30.--31. " NS_ACCESS399 ,Controls Non-secure access of the interrupt with ID399" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS398 ,Controls Non-secure access of the interrupt with ID398" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS397 ,Controls Non-secure access of the interrupt with ID397" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS396 ,Controls Non-secure access of the interrupt with ID396" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS395 ,Controls Non-secure access of the interrupt with ID395" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS394 ,Controls Non-secure access of the interrupt with ID394" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS393 ,Controls Non-secure access of the interrupt with ID393" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS392 ,Controls Non-secure access of the interrupt with ID392" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS391 ,Controls Non-secure access of the interrupt with ID391" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS390 ,Controls Non-secure access of the interrupt with ID390" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS389 ,Controls Non-secure access of the interrupt with ID389" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS388 ,Controls Non-secure access of the interrupt with ID388" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS387 ,Controls Non-secure access of the interrupt with ID387" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS386 ,Controls Non-secure access of the interrupt with ID386" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS385 ,Controls Non-secure access of the interrupt with ID385" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS384 ,Controls Non-secure access of the interrupt with ID384" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE60++0x03
hide.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE64)))
group.long 0xE64++0x03
line.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25"
bitfld.long 0x00 30.--31. " NS_ACCESS415 ,Controls Non-secure access of the interrupt with ID415" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS414 ,Controls Non-secure access of the interrupt with ID414" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS413 ,Controls Non-secure access of the interrupt with ID413" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS412 ,Controls Non-secure access of the interrupt with ID412" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS411 ,Controls Non-secure access of the interrupt with ID411" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS410 ,Controls Non-secure access of the interrupt with ID410" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS409 ,Controls Non-secure access of the interrupt with ID409" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS408 ,Controls Non-secure access of the interrupt with ID408" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS407 ,Controls Non-secure access of the interrupt with ID407" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS406 ,Controls Non-secure access of the interrupt with ID406" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS405 ,Controls Non-secure access of the interrupt with ID405" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS404 ,Controls Non-secure access of the interrupt with ID404" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS403 ,Controls Non-secure access of the interrupt with ID403" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS402 ,Controls Non-secure access of the interrupt with ID402" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS401 ,Controls Non-secure access of the interrupt with ID401" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS400 ,Controls Non-secure access of the interrupt with ID400" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE64++0x03
hide.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE68)))
group.long 0xE68++0x03
line.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26"
bitfld.long 0x00 30.--31. " NS_ACCESS431 ,Controls Non-secure access of the interrupt with ID431" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS430 ,Controls Non-secure access of the interrupt with ID430" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS429 ,Controls Non-secure access of the interrupt with ID429" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS428 ,Controls Non-secure access of the interrupt with ID428" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS427 ,Controls Non-secure access of the interrupt with ID427" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS426 ,Controls Non-secure access of the interrupt with ID426" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS425 ,Controls Non-secure access of the interrupt with ID425" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS424 ,Controls Non-secure access of the interrupt with ID424" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS423 ,Controls Non-secure access of the interrupt with ID423" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS422 ,Controls Non-secure access of the interrupt with ID422" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS421 ,Controls Non-secure access of the interrupt with ID421" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS420 ,Controls Non-secure access of the interrupt with ID420" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS419 ,Controls Non-secure access of the interrupt with ID419" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS418 ,Controls Non-secure access of the interrupt with ID418" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS417 ,Controls Non-secure access of the interrupt with ID417" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS416 ,Controls Non-secure access of the interrupt with ID416" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE68++0x03
hide.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE6C)))
group.long 0xE6C++0x03
line.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27"
bitfld.long 0x00 30.--31. " NS_ACCESS447 ,Controls Non-secure access of the interrupt with ID447" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS446 ,Controls Non-secure access of the interrupt with ID446" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS445 ,Controls Non-secure access of the interrupt with ID445" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS444 ,Controls Non-secure access of the interrupt with ID444" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS443 ,Controls Non-secure access of the interrupt with ID443" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS442 ,Controls Non-secure access of the interrupt with ID442" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS441 ,Controls Non-secure access of the interrupt with ID441" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS440 ,Controls Non-secure access of the interrupt with ID440" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS439 ,Controls Non-secure access of the interrupt with ID439" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS438 ,Controls Non-secure access of the interrupt with ID438" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS437 ,Controls Non-secure access of the interrupt with ID437" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS436 ,Controls Non-secure access of the interrupt with ID436" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS435 ,Controls Non-secure access of the interrupt with ID435" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS434 ,Controls Non-secure access of the interrupt with ID434" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS433 ,Controls Non-secure access of the interrupt with ID433" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS432 ,Controls Non-secure access of the interrupt with ID432" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE6C++0x03
hide.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE70)))
group.long 0xE70++0x03
line.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28"
bitfld.long 0x00 30.--31. " NS_ACCESS463 ,Controls Non-secure access of the interrupt with ID463" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS462 ,Controls Non-secure access of the interrupt with ID462" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS461 ,Controls Non-secure access of the interrupt with ID461" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS460 ,Controls Non-secure access of the interrupt with ID460" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS459 ,Controls Non-secure access of the interrupt with ID459" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS458 ,Controls Non-secure access of the interrupt with ID458" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS457 ,Controls Non-secure access of the interrupt with ID457" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS456 ,Controls Non-secure access of the interrupt with ID456" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS455 ,Controls Non-secure access of the interrupt with ID455" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS454 ,Controls Non-secure access of the interrupt with ID454" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS453 ,Controls Non-secure access of the interrupt with ID453" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS452 ,Controls Non-secure access of the interrupt with ID452" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS451 ,Controls Non-secure access of the interrupt with ID451" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS450 ,Controls Non-secure access of the interrupt with ID450" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS449 ,Controls Non-secure access of the interrupt with ID449" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS448 ,Controls Non-secure access of the interrupt with ID448" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE70++0x03
hide.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE74)))
group.long 0xE74++0x03
line.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29"
bitfld.long 0x00 30.--31. " NS_ACCESS479 ,Controls Non-secure access of the interrupt with ID479" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS478 ,Controls Non-secure access of the interrupt with ID478" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS477 ,Controls Non-secure access of the interrupt with ID477" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS476 ,Controls Non-secure access of the interrupt with ID476" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS475 ,Controls Non-secure access of the interrupt with ID475" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS474 ,Controls Non-secure access of the interrupt with ID474" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS473 ,Controls Non-secure access of the interrupt with ID473" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS472 ,Controls Non-secure access of the interrupt with ID472" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS471 ,Controls Non-secure access of the interrupt with ID471" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS470 ,Controls Non-secure access of the interrupt with ID470" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS469 ,Controls Non-secure access of the interrupt with ID469" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS468 ,Controls Non-secure access of the interrupt with ID468" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS467 ,Controls Non-secure access of the interrupt with ID467" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS466 ,Controls Non-secure access of the interrupt with ID466" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS465 ,Controls Non-secure access of the interrupt with ID465" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS464 ,Controls Non-secure access of the interrupt with ID464" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE74++0x03
hide.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE78)))
group.long 0xE78++0x03
line.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30"
bitfld.long 0x00 30.--31. " NS_ACCESS495 ,Controls Non-secure access of the interrupt with ID495" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS494 ,Controls Non-secure access of the interrupt with ID494" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS493 ,Controls Non-secure access of the interrupt with ID493" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS492 ,Controls Non-secure access of the interrupt with ID492" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS491 ,Controls Non-secure access of the interrupt with ID491" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS490 ,Controls Non-secure access of the interrupt with ID490" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS489 ,Controls Non-secure access of the interrupt with ID489" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS488 ,Controls Non-secure access of the interrupt with ID488" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS487 ,Controls Non-secure access of the interrupt with ID487" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS486 ,Controls Non-secure access of the interrupt with ID486" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS485 ,Controls Non-secure access of the interrupt with ID485" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS484 ,Controls Non-secure access of the interrupt with ID484" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS483 ,Controls Non-secure access of the interrupt with ID483" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS482 ,Controls Non-secure access of the interrupt with ID482" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS481 ,Controls Non-secure access of the interrupt with ID481" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS480 ,Controls Non-secure access of the interrupt with ID480" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE78++0x03
hide.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE7C)))
group.long 0xE7C++0x03
line.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31"
bitfld.long 0x00 30.--31. " NS_ACCESS511 ,Controls Non-secure access of the interrupt with ID511" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS510 ,Controls Non-secure access of the interrupt with ID510" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS509 ,Controls Non-secure access of the interrupt with ID509" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS508 ,Controls Non-secure access of the interrupt with ID508" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS507 ,Controls Non-secure access of the interrupt with ID507" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS506 ,Controls Non-secure access of the interrupt with ID506" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS505 ,Controls Non-secure access of the interrupt with ID505" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS504 ,Controls Non-secure access of the interrupt with ID504" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS503 ,Controls Non-secure access of the interrupt with ID503" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS502 ,Controls Non-secure access of the interrupt with ID502" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS501 ,Controls Non-secure access of the interrupt with ID501" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS500 ,Controls Non-secure access of the interrupt with ID500" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS499 ,Controls Non-secure access of the interrupt with ID499" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS498 ,Controls Non-secure access of the interrupt with ID498" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS497 ,Controls Non-secure access of the interrupt with ID497" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS496 ,Controls Non-secure access of the interrupt with ID496" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE7C++0x03
hide.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE80)))
group.long 0xE80++0x03
line.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32"
bitfld.long 0x00 30.--31. " NS_ACCESS527 ,Controls Non-secure access of the interrupt with ID527" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS526 ,Controls Non-secure access of the interrupt with ID526" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS525 ,Controls Non-secure access of the interrupt with ID525" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS524 ,Controls Non-secure access of the interrupt with ID524" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS523 ,Controls Non-secure access of the interrupt with ID523" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS522 ,Controls Non-secure access of the interrupt with ID522" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS521 ,Controls Non-secure access of the interrupt with ID521" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS520 ,Controls Non-secure access of the interrupt with ID520" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS519 ,Controls Non-secure access of the interrupt with ID519" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS518 ,Controls Non-secure access of the interrupt with ID518" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS517 ,Controls Non-secure access of the interrupt with ID517" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS516 ,Controls Non-secure access of the interrupt with ID516" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS515 ,Controls Non-secure access of the interrupt with ID515" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS514 ,Controls Non-secure access of the interrupt with ID514" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS513 ,Controls Non-secure access of the interrupt with ID513" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS512 ,Controls Non-secure access of the interrupt with ID512" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE80++0x03
hide.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE84)))
group.long 0xE84++0x03
line.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33"
bitfld.long 0x00 30.--31. " NS_ACCESS543 ,Controls Non-secure access of the interrupt with ID543" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS542 ,Controls Non-secure access of the interrupt with ID542" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS541 ,Controls Non-secure access of the interrupt with ID541" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS540 ,Controls Non-secure access of the interrupt with ID540" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS539 ,Controls Non-secure access of the interrupt with ID539" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS538 ,Controls Non-secure access of the interrupt with ID538" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS537 ,Controls Non-secure access of the interrupt with ID537" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS536 ,Controls Non-secure access of the interrupt with ID536" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS535 ,Controls Non-secure access of the interrupt with ID535" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS534 ,Controls Non-secure access of the interrupt with ID534" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS533 ,Controls Non-secure access of the interrupt with ID533" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS532 ,Controls Non-secure access of the interrupt with ID532" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS531 ,Controls Non-secure access of the interrupt with ID531" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS530 ,Controls Non-secure access of the interrupt with ID530" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS529 ,Controls Non-secure access of the interrupt with ID529" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS528 ,Controls Non-secure access of the interrupt with ID528" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE84++0x03
hide.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE88)))
group.long 0xE88++0x03
line.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34"
bitfld.long 0x00 30.--31. " NS_ACCESS559 ,Controls Non-secure access of the interrupt with ID559" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS558 ,Controls Non-secure access of the interrupt with ID558" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS557 ,Controls Non-secure access of the interrupt with ID557" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS556 ,Controls Non-secure access of the interrupt with ID556" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS555 ,Controls Non-secure access of the interrupt with ID555" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS554 ,Controls Non-secure access of the interrupt with ID554" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS553 ,Controls Non-secure access of the interrupt with ID553" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS552 ,Controls Non-secure access of the interrupt with ID552" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS551 ,Controls Non-secure access of the interrupt with ID551" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS550 ,Controls Non-secure access of the interrupt with ID550" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS549 ,Controls Non-secure access of the interrupt with ID549" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS548 ,Controls Non-secure access of the interrupt with ID548" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS547 ,Controls Non-secure access of the interrupt with ID547" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS546 ,Controls Non-secure access of the interrupt with ID546" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS545 ,Controls Non-secure access of the interrupt with ID545" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS544 ,Controls Non-secure access of the interrupt with ID544" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE88++0x03
hide.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8C)))
group.long 0xE8C++0x03
line.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35"
bitfld.long 0x00 30.--31. " NS_ACCESS575 ,Controls Non-secure access of the interrupt with ID575" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS574 ,Controls Non-secure access of the interrupt with ID574" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS573 ,Controls Non-secure access of the interrupt with ID573" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS572 ,Controls Non-secure access of the interrupt with ID572" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS571 ,Controls Non-secure access of the interrupt with ID571" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS570 ,Controls Non-secure access of the interrupt with ID570" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS569 ,Controls Non-secure access of the interrupt with ID569" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS568 ,Controls Non-secure access of the interrupt with ID568" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS567 ,Controls Non-secure access of the interrupt with ID567" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS566 ,Controls Non-secure access of the interrupt with ID566" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS565 ,Controls Non-secure access of the interrupt with ID565" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS564 ,Controls Non-secure access of the interrupt with ID564" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS563 ,Controls Non-secure access of the interrupt with ID563" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS562 ,Controls Non-secure access of the interrupt with ID562" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS561 ,Controls Non-secure access of the interrupt with ID561" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS560 ,Controls Non-secure access of the interrupt with ID560" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE8C++0x03
hide.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE90)))
group.long 0xE90++0x03
line.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36"
bitfld.long 0x00 30.--31. " NS_ACCESS591 ,Controls Non-secure access of the interrupt with ID591" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS590 ,Controls Non-secure access of the interrupt with ID590" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS589 ,Controls Non-secure access of the interrupt with ID589" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS588 ,Controls Non-secure access of the interrupt with ID588" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS587 ,Controls Non-secure access of the interrupt with ID587" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS586 ,Controls Non-secure access of the interrupt with ID586" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS585 ,Controls Non-secure access of the interrupt with ID585" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS584 ,Controls Non-secure access of the interrupt with ID584" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS583 ,Controls Non-secure access of the interrupt with ID583" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS582 ,Controls Non-secure access of the interrupt with ID582" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS581 ,Controls Non-secure access of the interrupt with ID581" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS580 ,Controls Non-secure access of the interrupt with ID580" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS579 ,Controls Non-secure access of the interrupt with ID579" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS578 ,Controls Non-secure access of the interrupt with ID578" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS577 ,Controls Non-secure access of the interrupt with ID577" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS576 ,Controls Non-secure access of the interrupt with ID576" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE90++0x03
hide.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE94)))
group.long 0xE94++0x03
line.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37"
bitfld.long 0x00 30.--31. " NS_ACCESS607 ,Controls Non-secure access of the interrupt with ID607" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS606 ,Controls Non-secure access of the interrupt with ID606" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS605 ,Controls Non-secure access of the interrupt with ID605" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS604 ,Controls Non-secure access of the interrupt with ID604" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS603 ,Controls Non-secure access of the interrupt with ID603" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS602 ,Controls Non-secure access of the interrupt with ID602" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS601 ,Controls Non-secure access of the interrupt with ID601" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS600 ,Controls Non-secure access of the interrupt with ID600" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS599 ,Controls Non-secure access of the interrupt with ID599" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS598 ,Controls Non-secure access of the interrupt with ID598" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS597 ,Controls Non-secure access of the interrupt with ID597" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS596 ,Controls Non-secure access of the interrupt with ID596" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS595 ,Controls Non-secure access of the interrupt with ID595" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS594 ,Controls Non-secure access of the interrupt with ID594" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS593 ,Controls Non-secure access of the interrupt with ID593" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS592 ,Controls Non-secure access of the interrupt with ID592" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE94++0x03
hide.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE98)))
group.long 0xE98++0x03
line.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38"
bitfld.long 0x00 30.--31. " NS_ACCESS623 ,Controls Non-secure access of the interrupt with ID623" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS622 ,Controls Non-secure access of the interrupt with ID622" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS621 ,Controls Non-secure access of the interrupt with ID621" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS620 ,Controls Non-secure access of the interrupt with ID620" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS619 ,Controls Non-secure access of the interrupt with ID619" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS618 ,Controls Non-secure access of the interrupt with ID618" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS617 ,Controls Non-secure access of the interrupt with ID617" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS616 ,Controls Non-secure access of the interrupt with ID616" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS615 ,Controls Non-secure access of the interrupt with ID615" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS614 ,Controls Non-secure access of the interrupt with ID614" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS613 ,Controls Non-secure access of the interrupt with ID613" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS612 ,Controls Non-secure access of the interrupt with ID612" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS611 ,Controls Non-secure access of the interrupt with ID611" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS610 ,Controls Non-secure access of the interrupt with ID610" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS609 ,Controls Non-secure access of the interrupt with ID609" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS608 ,Controls Non-secure access of the interrupt with ID608" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE98++0x03
hide.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE9C)))
group.long 0xE9C++0x03
line.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39"
bitfld.long 0x00 30.--31. " NS_ACCESS639 ,Controls Non-secure access of the interrupt with ID639" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS638 ,Controls Non-secure access of the interrupt with ID638" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS637 ,Controls Non-secure access of the interrupt with ID637" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS636 ,Controls Non-secure access of the interrupt with ID636" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS635 ,Controls Non-secure access of the interrupt with ID635" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS634 ,Controls Non-secure access of the interrupt with ID634" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS633 ,Controls Non-secure access of the interrupt with ID633" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS632 ,Controls Non-secure access of the interrupt with ID632" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS631 ,Controls Non-secure access of the interrupt with ID631" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS630 ,Controls Non-secure access of the interrupt with ID630" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS629 ,Controls Non-secure access of the interrupt with ID629" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS628 ,Controls Non-secure access of the interrupt with ID628" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS627 ,Controls Non-secure access of the interrupt with ID627" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS626 ,Controls Non-secure access of the interrupt with ID626" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS625 ,Controls Non-secure access of the interrupt with ID625" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS624 ,Controls Non-secure access of the interrupt with ID624" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE9C++0x03
hide.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA0)))
group.long 0xEA0++0x03
line.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40"
bitfld.long 0x00 30.--31. " NS_ACCESS655 ,Controls Non-secure access of the interrupt with ID655" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS654 ,Controls Non-secure access of the interrupt with ID654" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS653 ,Controls Non-secure access of the interrupt with ID653" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS652 ,Controls Non-secure access of the interrupt with ID652" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS651 ,Controls Non-secure access of the interrupt with ID651" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS650 ,Controls Non-secure access of the interrupt with ID650" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS649 ,Controls Non-secure access of the interrupt with ID649" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS648 ,Controls Non-secure access of the interrupt with ID648" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS647 ,Controls Non-secure access of the interrupt with ID647" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS646 ,Controls Non-secure access of the interrupt with ID646" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS645 ,Controls Non-secure access of the interrupt with ID645" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS644 ,Controls Non-secure access of the interrupt with ID644" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS643 ,Controls Non-secure access of the interrupt with ID643" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS642 ,Controls Non-secure access of the interrupt with ID642" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS641 ,Controls Non-secure access of the interrupt with ID641" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS640 ,Controls Non-secure access of the interrupt with ID640" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA0++0x03
hide.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA4)))
group.long 0xEA4++0x03
line.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41"
bitfld.long 0x00 30.--31. " NS_ACCESS671 ,Controls Non-secure access of the interrupt with ID671" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS670 ,Controls Non-secure access of the interrupt with ID670" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS669 ,Controls Non-secure access of the interrupt with ID669" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS668 ,Controls Non-secure access of the interrupt with ID668" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS667 ,Controls Non-secure access of the interrupt with ID667" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS666 ,Controls Non-secure access of the interrupt with ID666" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS665 ,Controls Non-secure access of the interrupt with ID665" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS664 ,Controls Non-secure access of the interrupt with ID664" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS663 ,Controls Non-secure access of the interrupt with ID663" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS662 ,Controls Non-secure access of the interrupt with ID662" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS661 ,Controls Non-secure access of the interrupt with ID661" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS660 ,Controls Non-secure access of the interrupt with ID660" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS659 ,Controls Non-secure access of the interrupt with ID659" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS658 ,Controls Non-secure access of the interrupt with ID658" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS657 ,Controls Non-secure access of the interrupt with ID657" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS656 ,Controls Non-secure access of the interrupt with ID656" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA4++0x03
hide.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA8)))
group.long 0xEA8++0x03
line.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42"
bitfld.long 0x00 30.--31. " NS_ACCESS687 ,Controls Non-secure access of the interrupt with ID687" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS686 ,Controls Non-secure access of the interrupt with ID686" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS685 ,Controls Non-secure access of the interrupt with ID685" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS684 ,Controls Non-secure access of the interrupt with ID684" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS683 ,Controls Non-secure access of the interrupt with ID683" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS682 ,Controls Non-secure access of the interrupt with ID682" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS681 ,Controls Non-secure access of the interrupt with ID681" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS680 ,Controls Non-secure access of the interrupt with ID680" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS679 ,Controls Non-secure access of the interrupt with ID679" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS678 ,Controls Non-secure access of the interrupt with ID678" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS677 ,Controls Non-secure access of the interrupt with ID677" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS676 ,Controls Non-secure access of the interrupt with ID676" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS675 ,Controls Non-secure access of the interrupt with ID675" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS674 ,Controls Non-secure access of the interrupt with ID674" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS673 ,Controls Non-secure access of the interrupt with ID673" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS672 ,Controls Non-secure access of the interrupt with ID672" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA8++0x03
hide.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEAC)))
group.long 0xEAC++0x03
line.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43"
bitfld.long 0x00 30.--31. " NS_ACCESS703 ,Controls Non-secure access of the interrupt with ID703" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS702 ,Controls Non-secure access of the interrupt with ID702" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS701 ,Controls Non-secure access of the interrupt with ID701" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS700 ,Controls Non-secure access of the interrupt with ID700" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS699 ,Controls Non-secure access of the interrupt with ID699" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS698 ,Controls Non-secure access of the interrupt with ID698" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS697 ,Controls Non-secure access of the interrupt with ID697" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS696 ,Controls Non-secure access of the interrupt with ID696" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS695 ,Controls Non-secure access of the interrupt with ID695" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS694 ,Controls Non-secure access of the interrupt with ID694" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS693 ,Controls Non-secure access of the interrupt with ID693" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS692 ,Controls Non-secure access of the interrupt with ID692" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS691 ,Controls Non-secure access of the interrupt with ID691" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS690 ,Controls Non-secure access of the interrupt with ID690" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS689 ,Controls Non-secure access of the interrupt with ID689" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS688 ,Controls Non-secure access of the interrupt with ID688" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEAC++0x03
hide.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB0)))
group.long 0xEB0++0x03
line.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44"
bitfld.long 0x00 30.--31. " NS_ACCESS719 ,Controls Non-secure access of the interrupt with ID719" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS718 ,Controls Non-secure access of the interrupt with ID718" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS717 ,Controls Non-secure access of the interrupt with ID717" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS716 ,Controls Non-secure access of the interrupt with ID716" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS715 ,Controls Non-secure access of the interrupt with ID715" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS714 ,Controls Non-secure access of the interrupt with ID714" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS713 ,Controls Non-secure access of the interrupt with ID713" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS712 ,Controls Non-secure access of the interrupt with ID712" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS711 ,Controls Non-secure access of the interrupt with ID711" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS710 ,Controls Non-secure access of the interrupt with ID710" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS709 ,Controls Non-secure access of the interrupt with ID709" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS708 ,Controls Non-secure access of the interrupt with ID708" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS707 ,Controls Non-secure access of the interrupt with ID707" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS706 ,Controls Non-secure access of the interrupt with ID706" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS705 ,Controls Non-secure access of the interrupt with ID705" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS704 ,Controls Non-secure access of the interrupt with ID704" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB0++0x03
hide.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB4)))
group.long 0xEB4++0x03
line.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45"
bitfld.long 0x00 30.--31. " NS_ACCESS735 ,Controls Non-secure access of the interrupt with ID735" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS734 ,Controls Non-secure access of the interrupt with ID734" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS733 ,Controls Non-secure access of the interrupt with ID733" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS732 ,Controls Non-secure access of the interrupt with ID732" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS731 ,Controls Non-secure access of the interrupt with ID731" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS730 ,Controls Non-secure access of the interrupt with ID730" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS729 ,Controls Non-secure access of the interrupt with ID729" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS728 ,Controls Non-secure access of the interrupt with ID728" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS727 ,Controls Non-secure access of the interrupt with ID727" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS726 ,Controls Non-secure access of the interrupt with ID726" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS725 ,Controls Non-secure access of the interrupt with ID725" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS724 ,Controls Non-secure access of the interrupt with ID724" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS723 ,Controls Non-secure access of the interrupt with ID723" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS722 ,Controls Non-secure access of the interrupt with ID722" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS721 ,Controls Non-secure access of the interrupt with ID721" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS720 ,Controls Non-secure access of the interrupt with ID720" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB4++0x03
hide.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB8)))
group.long 0xEB8++0x03
line.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46"
bitfld.long 0x00 30.--31. " NS_ACCESS751 ,Controls Non-secure access of the interrupt with ID751" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS750 ,Controls Non-secure access of the interrupt with ID750" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS749 ,Controls Non-secure access of the interrupt with ID749" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS748 ,Controls Non-secure access of the interrupt with ID748" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS747 ,Controls Non-secure access of the interrupt with ID747" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS746 ,Controls Non-secure access of the interrupt with ID746" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS745 ,Controls Non-secure access of the interrupt with ID745" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS744 ,Controls Non-secure access of the interrupt with ID744" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS743 ,Controls Non-secure access of the interrupt with ID743" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS742 ,Controls Non-secure access of the interrupt with ID742" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS741 ,Controls Non-secure access of the interrupt with ID741" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS740 ,Controls Non-secure access of the interrupt with ID740" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS739 ,Controls Non-secure access of the interrupt with ID739" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS738 ,Controls Non-secure access of the interrupt with ID738" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS737 ,Controls Non-secure access of the interrupt with ID737" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS736 ,Controls Non-secure access of the interrupt with ID736" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB8++0x03
hide.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEBC)))
group.long 0xEBC++0x03
line.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47"
bitfld.long 0x00 30.--31. " NS_ACCESS767 ,Controls Non-secure access of the interrupt with ID767" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS766 ,Controls Non-secure access of the interrupt with ID766" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS765 ,Controls Non-secure access of the interrupt with ID765" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS764 ,Controls Non-secure access of the interrupt with ID764" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS763 ,Controls Non-secure access of the interrupt with ID763" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS762 ,Controls Non-secure access of the interrupt with ID762" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS761 ,Controls Non-secure access of the interrupt with ID761" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS760 ,Controls Non-secure access of the interrupt with ID760" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS759 ,Controls Non-secure access of the interrupt with ID759" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS758 ,Controls Non-secure access of the interrupt with ID758" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS757 ,Controls Non-secure access of the interrupt with ID757" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS756 ,Controls Non-secure access of the interrupt with ID756" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS755 ,Controls Non-secure access of the interrupt with ID755" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS754 ,Controls Non-secure access of the interrupt with ID754" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS753 ,Controls Non-secure access of the interrupt with ID753" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS752 ,Controls Non-secure access of the interrupt with ID752" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEBC++0x03
hide.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC0)))
group.long 0xEC0++0x03
line.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48"
bitfld.long 0x00 30.--31. " NS_ACCESS783 ,Controls Non-secure access of the interrupt with ID783" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS782 ,Controls Non-secure access of the interrupt with ID782" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS781 ,Controls Non-secure access of the interrupt with ID781" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS780 ,Controls Non-secure access of the interrupt with ID780" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS779 ,Controls Non-secure access of the interrupt with ID779" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS778 ,Controls Non-secure access of the interrupt with ID778" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS777 ,Controls Non-secure access of the interrupt with ID777" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS776 ,Controls Non-secure access of the interrupt with ID776" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS775 ,Controls Non-secure access of the interrupt with ID775" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS774 ,Controls Non-secure access of the interrupt with ID774" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS773 ,Controls Non-secure access of the interrupt with ID773" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS772 ,Controls Non-secure access of the interrupt with ID772" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS771 ,Controls Non-secure access of the interrupt with ID771" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS770 ,Controls Non-secure access of the interrupt with ID770" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS769 ,Controls Non-secure access of the interrupt with ID769" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS768 ,Controls Non-secure access of the interrupt with ID768" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC0++0x03
hide.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC4)))
group.long 0xEC4++0x03
line.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49"
bitfld.long 0x00 30.--31. " NS_ACCESS799 ,Controls Non-secure access of the interrupt with ID799" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS798 ,Controls Non-secure access of the interrupt with ID798" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS797 ,Controls Non-secure access of the interrupt with ID797" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS796 ,Controls Non-secure access of the interrupt with ID796" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS795 ,Controls Non-secure access of the interrupt with ID795" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS794 ,Controls Non-secure access of the interrupt with ID794" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS793 ,Controls Non-secure access of the interrupt with ID793" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS792 ,Controls Non-secure access of the interrupt with ID792" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS791 ,Controls Non-secure access of the interrupt with ID791" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS790 ,Controls Non-secure access of the interrupt with ID790" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS789 ,Controls Non-secure access of the interrupt with ID789" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS788 ,Controls Non-secure access of the interrupt with ID788" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS787 ,Controls Non-secure access of the interrupt with ID787" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS786 ,Controls Non-secure access of the interrupt with ID786" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS785 ,Controls Non-secure access of the interrupt with ID785" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS784 ,Controls Non-secure access of the interrupt with ID784" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC4++0x03
hide.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC8)))
group.long 0xEC8++0x03
line.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50"
bitfld.long 0x00 30.--31. " NS_ACCESS815 ,Controls Non-secure access of the interrupt with ID815" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS814 ,Controls Non-secure access of the interrupt with ID814" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS813 ,Controls Non-secure access of the interrupt with ID813" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS812 ,Controls Non-secure access of the interrupt with ID812" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS811 ,Controls Non-secure access of the interrupt with ID811" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS810 ,Controls Non-secure access of the interrupt with ID810" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS809 ,Controls Non-secure access of the interrupt with ID809" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS808 ,Controls Non-secure access of the interrupt with ID808" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS807 ,Controls Non-secure access of the interrupt with ID807" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS806 ,Controls Non-secure access of the interrupt with ID806" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS805 ,Controls Non-secure access of the interrupt with ID805" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS804 ,Controls Non-secure access of the interrupt with ID804" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS803 ,Controls Non-secure access of the interrupt with ID803" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS802 ,Controls Non-secure access of the interrupt with ID802" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS801 ,Controls Non-secure access of the interrupt with ID801" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS800 ,Controls Non-secure access of the interrupt with ID800" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC8++0x03
hide.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xECC)))
group.long 0xECC++0x03
line.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51"
bitfld.long 0x00 30.--31. " NS_ACCESS831 ,Controls Non-secure access of the interrupt with ID831" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS830 ,Controls Non-secure access of the interrupt with ID830" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS829 ,Controls Non-secure access of the interrupt with ID829" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS828 ,Controls Non-secure access of the interrupt with ID828" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS827 ,Controls Non-secure access of the interrupt with ID827" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS826 ,Controls Non-secure access of the interrupt with ID826" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS825 ,Controls Non-secure access of the interrupt with ID825" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS824 ,Controls Non-secure access of the interrupt with ID824" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS823 ,Controls Non-secure access of the interrupt with ID823" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS822 ,Controls Non-secure access of the interrupt with ID822" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS821 ,Controls Non-secure access of the interrupt with ID821" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS820 ,Controls Non-secure access of the interrupt with ID820" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS819 ,Controls Non-secure access of the interrupt with ID819" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS818 ,Controls Non-secure access of the interrupt with ID818" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS817 ,Controls Non-secure access of the interrupt with ID817" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS816 ,Controls Non-secure access of the interrupt with ID816" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xECC++0x03
hide.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED0)))
group.long 0xED0++0x03
line.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52"
bitfld.long 0x00 30.--31. " NS_ACCESS847 ,Controls Non-secure access of the interrupt with ID847" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS846 ,Controls Non-secure access of the interrupt with ID846" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS845 ,Controls Non-secure access of the interrupt with ID845" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS844 ,Controls Non-secure access of the interrupt with ID844" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS843 ,Controls Non-secure access of the interrupt with ID843" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS842 ,Controls Non-secure access of the interrupt with ID842" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS841 ,Controls Non-secure access of the interrupt with ID841" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS840 ,Controls Non-secure access of the interrupt with ID840" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS839 ,Controls Non-secure access of the interrupt with ID839" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS838 ,Controls Non-secure access of the interrupt with ID838" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS837 ,Controls Non-secure access of the interrupt with ID837" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS836 ,Controls Non-secure access of the interrupt with ID836" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS835 ,Controls Non-secure access of the interrupt with ID835" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS834 ,Controls Non-secure access of the interrupt with ID834" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS833 ,Controls Non-secure access of the interrupt with ID833" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS832 ,Controls Non-secure access of the interrupt with ID832" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED0++0x03
hide.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED4)))
group.long 0xED4++0x03
line.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53"
bitfld.long 0x00 30.--31. " NS_ACCESS863 ,Controls Non-secure access of the interrupt with ID863" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS862 ,Controls Non-secure access of the interrupt with ID862" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS861 ,Controls Non-secure access of the interrupt with ID861" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS860 ,Controls Non-secure access of the interrupt with ID860" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS859 ,Controls Non-secure access of the interrupt with ID859" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS858 ,Controls Non-secure access of the interrupt with ID858" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS857 ,Controls Non-secure access of the interrupt with ID857" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS856 ,Controls Non-secure access of the interrupt with ID856" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS855 ,Controls Non-secure access of the interrupt with ID855" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS854 ,Controls Non-secure access of the interrupt with ID854" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS853 ,Controls Non-secure access of the interrupt with ID853" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS852 ,Controls Non-secure access of the interrupt with ID852" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS851 ,Controls Non-secure access of the interrupt with ID851" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS850 ,Controls Non-secure access of the interrupt with ID850" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS849 ,Controls Non-secure access of the interrupt with ID849" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS848 ,Controls Non-secure access of the interrupt with ID848" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED4++0x03
hide.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED8)))
group.long 0xED8++0x03
line.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54"
bitfld.long 0x00 30.--31. " NS_ACCESS879 ,Controls Non-secure access of the interrupt with ID879" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS878 ,Controls Non-secure access of the interrupt with ID878" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS877 ,Controls Non-secure access of the interrupt with ID877" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS876 ,Controls Non-secure access of the interrupt with ID876" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS875 ,Controls Non-secure access of the interrupt with ID875" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS874 ,Controls Non-secure access of the interrupt with ID874" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS873 ,Controls Non-secure access of the interrupt with ID873" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS872 ,Controls Non-secure access of the interrupt with ID872" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS871 ,Controls Non-secure access of the interrupt with ID871" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS870 ,Controls Non-secure access of the interrupt with ID870" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS869 ,Controls Non-secure access of the interrupt with ID869" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS868 ,Controls Non-secure access of the interrupt with ID868" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS867 ,Controls Non-secure access of the interrupt with ID867" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS866 ,Controls Non-secure access of the interrupt with ID866" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS865 ,Controls Non-secure access of the interrupt with ID865" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS864 ,Controls Non-secure access of the interrupt with ID864" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED8++0x03
hide.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEDC)))
group.long 0xEDC++0x03
line.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55"
bitfld.long 0x00 30.--31. " NS_ACCESS895 ,Controls Non-secure access of the interrupt with ID895" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS894 ,Controls Non-secure access of the interrupt with ID894" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS893 ,Controls Non-secure access of the interrupt with ID893" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS892 ,Controls Non-secure access of the interrupt with ID892" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS891 ,Controls Non-secure access of the interrupt with ID891" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS890 ,Controls Non-secure access of the interrupt with ID890" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS889 ,Controls Non-secure access of the interrupt with ID889" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS888 ,Controls Non-secure access of the interrupt with ID888" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS887 ,Controls Non-secure access of the interrupt with ID887" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS886 ,Controls Non-secure access of the interrupt with ID886" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS885 ,Controls Non-secure access of the interrupt with ID885" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS884 ,Controls Non-secure access of the interrupt with ID884" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS883 ,Controls Non-secure access of the interrupt with ID883" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS882 ,Controls Non-secure access of the interrupt with ID882" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS881 ,Controls Non-secure access of the interrupt with ID881" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS880 ,Controls Non-secure access of the interrupt with ID880" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEDC++0x03
hide.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE0)))
group.long 0xEE0++0x03
line.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56"
bitfld.long 0x00 30.--31. " NS_ACCESS911 ,Controls Non-secure access of the interrupt with ID911" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS910 ,Controls Non-secure access of the interrupt with ID910" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS909 ,Controls Non-secure access of the interrupt with ID909" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS908 ,Controls Non-secure access of the interrupt with ID908" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS907 ,Controls Non-secure access of the interrupt with ID907" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS906 ,Controls Non-secure access of the interrupt with ID906" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS905 ,Controls Non-secure access of the interrupt with ID905" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS904 ,Controls Non-secure access of the interrupt with ID904" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS903 ,Controls Non-secure access of the interrupt with ID903" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS902 ,Controls Non-secure access of the interrupt with ID902" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS901 ,Controls Non-secure access of the interrupt with ID901" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS900 ,Controls Non-secure access of the interrupt with ID900" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS899 ,Controls Non-secure access of the interrupt with ID899" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS898 ,Controls Non-secure access of the interrupt with ID898" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS897 ,Controls Non-secure access of the interrupt with ID897" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS896 ,Controls Non-secure access of the interrupt with ID896" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE0++0x03
hide.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE4)))
group.long 0xEE4++0x03
line.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57"
bitfld.long 0x00 30.--31. " NS_ACCESS927 ,Controls Non-secure access of the interrupt with ID927" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS926 ,Controls Non-secure access of the interrupt with ID926" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS925 ,Controls Non-secure access of the interrupt with ID925" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS924 ,Controls Non-secure access of the interrupt with ID924" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS923 ,Controls Non-secure access of the interrupt with ID923" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS922 ,Controls Non-secure access of the interrupt with ID922" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS921 ,Controls Non-secure access of the interrupt with ID921" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS920 ,Controls Non-secure access of the interrupt with ID920" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS919 ,Controls Non-secure access of the interrupt with ID919" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS918 ,Controls Non-secure access of the interrupt with ID918" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS917 ,Controls Non-secure access of the interrupt with ID917" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS916 ,Controls Non-secure access of the interrupt with ID916" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS915 ,Controls Non-secure access of the interrupt with ID915" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS914 ,Controls Non-secure access of the interrupt with ID914" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS913 ,Controls Non-secure access of the interrupt with ID913" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS912 ,Controls Non-secure access of the interrupt with ID912" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE4++0x03
hide.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE8)))
group.long 0xEE8++0x03
line.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58"
bitfld.long 0x00 30.--31. " NS_ACCESS943 ,Controls Non-secure access of the interrupt with ID943" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS942 ,Controls Non-secure access of the interrupt with ID942" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS941 ,Controls Non-secure access of the interrupt with ID941" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS940 ,Controls Non-secure access of the interrupt with ID940" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS939 ,Controls Non-secure access of the interrupt with ID939" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS938 ,Controls Non-secure access of the interrupt with ID938" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS937 ,Controls Non-secure access of the interrupt with ID937" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS936 ,Controls Non-secure access of the interrupt with ID936" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS935 ,Controls Non-secure access of the interrupt with ID935" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS934 ,Controls Non-secure access of the interrupt with ID934" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS933 ,Controls Non-secure access of the interrupt with ID933" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS932 ,Controls Non-secure access of the interrupt with ID932" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS931 ,Controls Non-secure access of the interrupt with ID931" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS930 ,Controls Non-secure access of the interrupt with ID930" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS929 ,Controls Non-secure access of the interrupt with ID929" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS928 ,Controls Non-secure access of the interrupt with ID928" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE8++0x03
hide.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEEC)))
group.long 0xEEC++0x03
line.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59"
bitfld.long 0x00 30.--31. " NS_ACCESS959 ,Controls Non-secure access of the interrupt with ID959" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS958 ,Controls Non-secure access of the interrupt with ID958" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS957 ,Controls Non-secure access of the interrupt with ID957" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS956 ,Controls Non-secure access of the interrupt with ID956" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS955 ,Controls Non-secure access of the interrupt with ID955" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS954 ,Controls Non-secure access of the interrupt with ID954" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS953 ,Controls Non-secure access of the interrupt with ID953" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS952 ,Controls Non-secure access of the interrupt with ID952" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS951 ,Controls Non-secure access of the interrupt with ID951" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS950 ,Controls Non-secure access of the interrupt with ID950" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS949 ,Controls Non-secure access of the interrupt with ID949" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS948 ,Controls Non-secure access of the interrupt with ID948" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS947 ,Controls Non-secure access of the interrupt with ID947" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS946 ,Controls Non-secure access of the interrupt with ID946" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS945 ,Controls Non-secure access of the interrupt with ID945" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS944 ,Controls Non-secure access of the interrupt with ID944" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEEC++0x03
hide.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF0)))
group.long 0xEF0++0x03
line.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60"
bitfld.long 0x00 30.--31. " NS_ACCESS975 ,Controls Non-secure access of the interrupt with ID975" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS974 ,Controls Non-secure access of the interrupt with ID974" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS973 ,Controls Non-secure access of the interrupt with ID973" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS972 ,Controls Non-secure access of the interrupt with ID972" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS971 ,Controls Non-secure access of the interrupt with ID971" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS970 ,Controls Non-secure access of the interrupt with ID970" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS969 ,Controls Non-secure access of the interrupt with ID969" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS968 ,Controls Non-secure access of the interrupt with ID968" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS967 ,Controls Non-secure access of the interrupt with ID967" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS966 ,Controls Non-secure access of the interrupt with ID966" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS965 ,Controls Non-secure access of the interrupt with ID965" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS964 ,Controls Non-secure access of the interrupt with ID964" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS963 ,Controls Non-secure access of the interrupt with ID963" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS962 ,Controls Non-secure access of the interrupt with ID962" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS961 ,Controls Non-secure access of the interrupt with ID961" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS960 ,Controls Non-secure access of the interrupt with ID960" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEF0++0x03
hide.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF4)))
group.long 0xEF4++0x03
line.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61"
bitfld.long 0x00 30.--31. " NS_ACCESS991 ,Controls Non-secure access of the interrupt with ID991" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS990 ,Controls Non-secure access of the interrupt with ID990" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS989 ,Controls Non-secure access of the interrupt with ID989" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS988 ,Controls Non-secure access of the interrupt with ID988" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS987 ,Controls Non-secure access of the interrupt with ID987" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS986 ,Controls Non-secure access of the interrupt with ID986" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS985 ,Controls Non-secure access of the interrupt with ID985" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS984 ,Controls Non-secure access of the interrupt with ID984" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS983 ,Controls Non-secure access of the interrupt with ID983" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS982 ,Controls Non-secure access of the interrupt with ID982" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS981 ,Controls Non-secure access of the interrupt with ID981" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS980 ,Controls Non-secure access of the interrupt with ID980" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS979 ,Controls Non-secure access of the interrupt with ID979" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS978 ,Controls Non-secure access of the interrupt with ID978" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS977 ,Controls Non-secure access of the interrupt with ID977" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS976 ,Controls Non-secure access of the interrupt with ID976" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEF4++0x03
hide.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61"
endif
tree.end
width 25.
tree "Software Generated Interrupt"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0F00++0x03
hide.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
hgroup.long 0xF10++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0"
hgroup.long 0xF14++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1"
hgroup.long 0xF18++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2"
hgroup.long 0xF1C++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3"
hgroup.long 0xF20++0x03
hide.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0"
hgroup.long 0xF24++0x03
hide.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1"
hgroup.long 0xF28++0x03
hide.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2"
hgroup.long 0xF2C++0x03
hide.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3"
else
wgroup.long 0x0F00++0x03
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
group.long 0xF10++0x03
line.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0"
group.long 0xF14++0x03
line.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1"
group.long 0xF18++0x03
line.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2"
group.long 0xF1C++0x03
line.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3"
group.long 0xF20++0x03
line.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0"
group.long 0xF24++0x03
line.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1"
group.long 0xF28++0x03
line.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2"
group.long 0xF2C++0x03
line.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3"
endif
tree.end
width 24.
tree "Interrupt Routing Registers"
group.quad 0x6100++0x07
line.quad 0x00 "GICD_IROUTER32 ,Interrupt Routing Register 32 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6108++0x07
line.quad 0x00 "GICD_IROUTER33 ,Interrupt Routing Register 33 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6110++0x07
line.quad 0x00 "GICD_IROUTER34 ,Interrupt Routing Register 34 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6118++0x07
line.quad 0x00 "GICD_IROUTER35 ,Interrupt Routing Register 35 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6120++0x07
line.quad 0x00 "GICD_IROUTER36 ,Interrupt Routing Register 36 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6128++0x07
line.quad 0x00 "GICD_IROUTER37 ,Interrupt Routing Register 37 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6130++0x07
line.quad 0x00 "GICD_IROUTER38 ,Interrupt Routing Register 38 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6138++0x07
line.quad 0x00 "GICD_IROUTER39 ,Interrupt Routing Register 39 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6140++0x07
line.quad 0x00 "GICD_IROUTER40 ,Interrupt Routing Register 40 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6148++0x07
line.quad 0x00 "GICD_IROUTER41 ,Interrupt Routing Register 41 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6150++0x07
line.quad 0x00 "GICD_IROUTER42 ,Interrupt Routing Register 42 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6158++0x07
line.quad 0x00 "GICD_IROUTER43 ,Interrupt Routing Register 43 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6160++0x07
line.quad 0x00 "GICD_IROUTER44 ,Interrupt Routing Register 44 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6168++0x07
line.quad 0x00 "GICD_IROUTER45 ,Interrupt Routing Register 45 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6170++0x07
line.quad 0x00 "GICD_IROUTER46 ,Interrupt Routing Register 46 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6178++0x07
line.quad 0x00 "GICD_IROUTER47 ,Interrupt Routing Register 47 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6180++0x07
line.quad 0x00 "GICD_IROUTER48 ,Interrupt Routing Register 48 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6188++0x07
line.quad 0x00 "GICD_IROUTER49 ,Interrupt Routing Register 49 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6190++0x07
line.quad 0x00 "GICD_IROUTER50 ,Interrupt Routing Register 50 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6198++0x07
line.quad 0x00 "GICD_IROUTER51 ,Interrupt Routing Register 51 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61A0++0x07
line.quad 0x00 "GICD_IROUTER52 ,Interrupt Routing Register 52 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61A8++0x07
line.quad 0x00 "GICD_IROUTER53 ,Interrupt Routing Register 53 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61B0++0x07
line.quad 0x00 "GICD_IROUTER54 ,Interrupt Routing Register 54 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61B8++0x07
line.quad 0x00 "GICD_IROUTER55 ,Interrupt Routing Register 55 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61C0++0x07
line.quad 0x00 "GICD_IROUTER56 ,Interrupt Routing Register 56 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61C8++0x07
line.quad 0x00 "GICD_IROUTER57 ,Interrupt Routing Register 57 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61D0++0x07
line.quad 0x00 "GICD_IROUTER58 ,Interrupt Routing Register 58 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61D8++0x07
line.quad 0x00 "GICD_IROUTER59 ,Interrupt Routing Register 59 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61E0++0x07
line.quad 0x00 "GICD_IROUTER60 ,Interrupt Routing Register 60 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61E8++0x07
line.quad 0x00 "GICD_IROUTER61 ,Interrupt Routing Register 61 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61F0++0x07
line.quad 0x00 "GICD_IROUTER62 ,Interrupt Routing Register 62 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61F8++0x07
line.quad 0x00 "GICD_IROUTER63 ,Interrupt Routing Register 63 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6200++0x07
line.quad 0x00 "GICD_IROUTER64 ,Interrupt Routing Register 64 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6208++0x07
line.quad 0x00 "GICD_IROUTER65 ,Interrupt Routing Register 65 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6210++0x07
line.quad 0x00 "GICD_IROUTER66 ,Interrupt Routing Register 66 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6218++0x07
line.quad 0x00 "GICD_IROUTER67 ,Interrupt Routing Register 67 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6220++0x07
line.quad 0x00 "GICD_IROUTER68 ,Interrupt Routing Register 68 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6228++0x07
line.quad 0x00 "GICD_IROUTER69 ,Interrupt Routing Register 69 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6230++0x07
line.quad 0x00 "GICD_IROUTER70 ,Interrupt Routing Register 70 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6238++0x07
line.quad 0x00 "GICD_IROUTER71 ,Interrupt Routing Register 71 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6240++0x07
line.quad 0x00 "GICD_IROUTER72 ,Interrupt Routing Register 72 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6248++0x07
line.quad 0x00 "GICD_IROUTER73 ,Interrupt Routing Register 73 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6250++0x07
line.quad 0x00 "GICD_IROUTER74 ,Interrupt Routing Register 74 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6258++0x07
line.quad 0x00 "GICD_IROUTER75 ,Interrupt Routing Register 75 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6260++0x07
line.quad 0x00 "GICD_IROUTER76 ,Interrupt Routing Register 76 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6268++0x07
line.quad 0x00 "GICD_IROUTER77 ,Interrupt Routing Register 77 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6270++0x07
line.quad 0x00 "GICD_IROUTER78 ,Interrupt Routing Register 78 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6278++0x07
line.quad 0x00 "GICD_IROUTER79 ,Interrupt Routing Register 79 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6280++0x07
line.quad 0x00 "GICD_IROUTER80 ,Interrupt Routing Register 80 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6288++0x07
line.quad 0x00 "GICD_IROUTER81 ,Interrupt Routing Register 81 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6290++0x07
line.quad 0x00 "GICD_IROUTER82 ,Interrupt Routing Register 82 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6298++0x07
line.quad 0x00 "GICD_IROUTER83 ,Interrupt Routing Register 83 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62A0++0x07
line.quad 0x00 "GICD_IROUTER84 ,Interrupt Routing Register 84 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62A8++0x07
line.quad 0x00 "GICD_IROUTER85 ,Interrupt Routing Register 85 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62B0++0x07
line.quad 0x00 "GICD_IROUTER86 ,Interrupt Routing Register 86 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62B8++0x07
line.quad 0x00 "GICD_IROUTER87 ,Interrupt Routing Register 87 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62C0++0x07
line.quad 0x00 "GICD_IROUTER88 ,Interrupt Routing Register 88 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62C8++0x07
line.quad 0x00 "GICD_IROUTER89 ,Interrupt Routing Register 89 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62D0++0x07
line.quad 0x00 "GICD_IROUTER90 ,Interrupt Routing Register 90 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62D8++0x07
line.quad 0x00 "GICD_IROUTER91 ,Interrupt Routing Register 91 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62E0++0x07
line.quad 0x00 "GICD_IROUTER92 ,Interrupt Routing Register 92 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62E8++0x07
line.quad 0x00 "GICD_IROUTER93 ,Interrupt Routing Register 93 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62F0++0x07
line.quad 0x00 "GICD_IROUTER94 ,Interrupt Routing Register 94 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62F8++0x07
line.quad 0x00 "GICD_IROUTER95 ,Interrupt Routing Register 95 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6300++0x07
line.quad 0x00 "GICD_IROUTER96 ,Interrupt Routing Register 96 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6308++0x07
line.quad 0x00 "GICD_IROUTER97 ,Interrupt Routing Register 97 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6310++0x07
line.quad 0x00 "GICD_IROUTER98 ,Interrupt Routing Register 98 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6318++0x07
line.quad 0x00 "GICD_IROUTER99 ,Interrupt Routing Register 99 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6320++0x07
line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6328++0x07
line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6330++0x07
line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6338++0x07
line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6340++0x07
line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6348++0x07
line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6350++0x07
line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6358++0x07
line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6360++0x07
line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6368++0x07
line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6370++0x07
line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6378++0x07
line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6380++0x07
line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6388++0x07
line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6390++0x07
line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6398++0x07
line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63A0++0x07
line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63A8++0x07
line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63B0++0x07
line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63B8++0x07
line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63C0++0x07
line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63C8++0x07
line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63D0++0x07
line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63D8++0x07
line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63E0++0x07
line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63E8++0x07
line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63F0++0x07
line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63F8++0x07
line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6400++0x07
line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6408++0x07
line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6410++0x07
line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6418++0x07
line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6420++0x07
line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6428++0x07
line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6430++0x07
line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6438++0x07
line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6440++0x07
line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6448++0x07
line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6450++0x07
line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6458++0x07
line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6460++0x07
line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6468++0x07
line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6470++0x07
line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6478++0x07
line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6480++0x07
line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6488++0x07
line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6490++0x07
line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6498++0x07
line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64A0++0x07
line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64A8++0x07
line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64B0++0x07
line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64B8++0x07
line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64C0++0x07
line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64C8++0x07
line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64D0++0x07
line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64D8++0x07
line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64E0++0x07
line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64E8++0x07
line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64F0++0x07
line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64F8++0x07
line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6500++0x07
line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6508++0x07
line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6510++0x07
line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6518++0x07
line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6520++0x07
line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6528++0x07
line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6530++0x07
line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6538++0x07
line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6540++0x07
line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6548++0x07
line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6550++0x07
line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6558++0x07
line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6560++0x07
line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6568++0x07
line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6570++0x07
line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6578++0x07
line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6580++0x07
line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6588++0x07
line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6590++0x07
line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6598++0x07
line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65A0++0x07
line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65A8++0x07
line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65B0++0x07
line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65B8++0x07
line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65C0++0x07
line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65C8++0x07
line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65D0++0x07
line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65D8++0x07
line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65E0++0x07
line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65E8++0x07
line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65F0++0x07
line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65F8++0x07
line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6600++0x07
line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6608++0x07
line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6610++0x07
line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6618++0x07
line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6620++0x07
line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6628++0x07
line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6630++0x07
line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6638++0x07
line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6640++0x07
line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6648++0x07
line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6650++0x07
line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6658++0x07
line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6660++0x07
line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6668++0x07
line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6670++0x07
line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6678++0x07
line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6680++0x07
line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6688++0x07
line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6690++0x07
line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6698++0x07
line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66A0++0x07
line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66A8++0x07
line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66B0++0x07
line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66B8++0x07
line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66C0++0x07
line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66C8++0x07
line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66D0++0x07
line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66D8++0x07
line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66E0++0x07
line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66E8++0x07
line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66F0++0x07
line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66F8++0x07
line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6700++0x07
line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6708++0x07
line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6710++0x07
line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6718++0x07
line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6720++0x07
line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6728++0x07
line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6730++0x07
line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6738++0x07
line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6740++0x07
line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6748++0x07
line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6750++0x07
line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6758++0x07
line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6760++0x07
line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6768++0x07
line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6770++0x07
line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6778++0x07
line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6780++0x07
line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6788++0x07
line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6790++0x07
line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6798++0x07
line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67A0++0x07
line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67A8++0x07
line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67B0++0x07
line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67B8++0x07
line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67C0++0x07
line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67C8++0x07
line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67D0++0x07
line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67D8++0x07
line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67E0++0x07
line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67E8++0x07
line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67F0++0x07
line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67F8++0x07
line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6800++0x07
line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6808++0x07
line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6810++0x07
line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6818++0x07
line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6820++0x07
line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6828++0x07
line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6830++0x07
line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6838++0x07
line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6840++0x07
line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6848++0x07
line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6850++0x07
line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6858++0x07
line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6860++0x07
line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6868++0x07
line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6870++0x07
line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6878++0x07
line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6880++0x07
line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6888++0x07
line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6890++0x07
line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6898++0x07
line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68A0++0x07
line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68A8++0x07
line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68B0++0x07
line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68B8++0x07
line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68C0++0x07
line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68C8++0x07
line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68D0++0x07
line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68D8++0x07
line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68E0++0x07
line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68E8++0x07
line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68F0++0x07
line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68F8++0x07
line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6900++0x07
line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6908++0x07
line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6910++0x07
line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6918++0x07
line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6920++0x07
line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6928++0x07
line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6930++0x07
line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6938++0x07
line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6940++0x07
line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6948++0x07
line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6950++0x07
line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6958++0x07
line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6960++0x07
line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6968++0x07
line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6970++0x07
line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6978++0x07
line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6980++0x07
line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6988++0x07
line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6990++0x07
line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6998++0x07
line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69A0++0x07
line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69A8++0x07
line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69B0++0x07
line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69B8++0x07
line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69C0++0x07
line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69C8++0x07
line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69D0++0x07
line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69D8++0x07
line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69E0++0x07
line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69E8++0x07
line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69F0++0x07
line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69F8++0x07
line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A00++0x07
line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A08++0x07
line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A10++0x07
line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A18++0x07
line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A20++0x07
line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A28++0x07
line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A30++0x07
line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A38++0x07
line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A40++0x07
line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A48++0x07
line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A50++0x07
line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A58++0x07
line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A60++0x07
line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A68++0x07
line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A70++0x07
line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A78++0x07
line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A80++0x07
line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A88++0x07
line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A90++0x07
line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A98++0x07
line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AA0++0x07
line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AA8++0x07
line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AB0++0x07
line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AB8++0x07
line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AC0++0x07
line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AC8++0x07
line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AD0++0x07
line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AD8++0x07
line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AE0++0x07
line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AE8++0x07
line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AF0++0x07
line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AF8++0x07
line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B00++0x07
line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B08++0x07
line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B10++0x07
line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B18++0x07
line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B20++0x07
line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B28++0x07
line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B30++0x07
line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B38++0x07
line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B40++0x07
line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B48++0x07
line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B50++0x07
line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B58++0x07
line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B60++0x07
line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B68++0x07
line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B70++0x07
line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B78++0x07
line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B80++0x07
line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B88++0x07
line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B90++0x07
line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B98++0x07
line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BA0++0x07
line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BA8++0x07
line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BB0++0x07
line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BB8++0x07
line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BC0++0x07
line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BC8++0x07
line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BD0++0x07
line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BD8++0x07
line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BE0++0x07
line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BE8++0x07
line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BF0++0x07
line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BF8++0x07
line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C00++0x07
line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C08++0x07
line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C10++0x07
line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C18++0x07
line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C20++0x07
line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C28++0x07
line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C30++0x07
line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C38++0x07
line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C40++0x07
line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C48++0x07
line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C50++0x07
line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C58++0x07
line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C60++0x07
line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C68++0x07
line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C70++0x07
line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C78++0x07
line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C80++0x07
line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C88++0x07
line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C90++0x07
line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C98++0x07
line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CA0++0x07
line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CA8++0x07
line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CB0++0x07
line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CB8++0x07
line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CC0++0x07
line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CC8++0x07
line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CD0++0x07
line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CD8++0x07
line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CE0++0x07
line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CE8++0x07
line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CF0++0x07
line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CF8++0x07
line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D00++0x07
line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D08++0x07
line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D10++0x07
line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D18++0x07
line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D20++0x07
line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D28++0x07
line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D30++0x07
line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D38++0x07
line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D40++0x07
line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D48++0x07
line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D50++0x07
line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D58++0x07
line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D60++0x07
line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D68++0x07
line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D70++0x07
line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D78++0x07
line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D80++0x07
line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D88++0x07
line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D90++0x07
line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D98++0x07
line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DA0++0x07
line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DA8++0x07
line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DB0++0x07
line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DB8++0x07
line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DC0++0x07
line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DC8++0x07
line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DD0++0x07
line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DD8++0x07
line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DE0++0x07
line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DE8++0x07
line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DF0++0x07
line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DF8++0x07
line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E00++0x07
line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E08++0x07
line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E10++0x07
line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E18++0x07
line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E20++0x07
line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E28++0x07
line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E30++0x07
line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E38++0x07
line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E40++0x07
line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E48++0x07
line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E50++0x07
line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E58++0x07
line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E60++0x07
line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E68++0x07
line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E70++0x07
line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E78++0x07
line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E80++0x07
line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E88++0x07
line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E90++0x07
line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E98++0x07
line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EA0++0x07
line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EA8++0x07
line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EB0++0x07
line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EB8++0x07
line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EC0++0x07
line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EC8++0x07
line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6ED0++0x07
line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6ED8++0x07
line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EE0++0x07
line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EE8++0x07
line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EF0++0x07
line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EF8++0x07
line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F00++0x07
line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F08++0x07
line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F10++0x07
line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F18++0x07
line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F20++0x07
line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F28++0x07
line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F30++0x07
line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F38++0x07
line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F40++0x07
line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F48++0x07
line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F50++0x07
line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F58++0x07
line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F60++0x07
line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F68++0x07
line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F70++0x07
line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F78++0x07
line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F80++0x07
line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F88++0x07
line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F90++0x07
line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F98++0x07
line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FA0++0x07
line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FA8++0x07
line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FB0++0x07
line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FB8++0x07
line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FC0++0x07
line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FC8++0x07
line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FD0++0x07
line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FD8++0x07
line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FE0++0x07
line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FE8++0x07
line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FF0++0x07
line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FF8++0x07
line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7000++0x07
line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7008++0x07
line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7010++0x07
line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7018++0x07
line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7020++0x07
line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7028++0x07
line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7030++0x07
line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7038++0x07
line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7040++0x07
line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7048++0x07
line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7050++0x07
line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7058++0x07
line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7060++0x07
line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7068++0x07
line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7070++0x07
line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7078++0x07
line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7080++0x07
line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7088++0x07
line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7090++0x07
line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7098++0x07
line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70A0++0x07
line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70A8++0x07
line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70B0++0x07
line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70B8++0x07
line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70C0++0x07
line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70C8++0x07
line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70D0++0x07
line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70D8++0x07
line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70E0++0x07
line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70E8++0x07
line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70F0++0x07
line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70F8++0x07
line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7100++0x07
line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7108++0x07
line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7110++0x07
line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7118++0x07
line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7120++0x07
line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7128++0x07
line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7130++0x07
line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7138++0x07
line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7140++0x07
line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7148++0x07
line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7150++0x07
line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7158++0x07
line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7160++0x07
line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7168++0x07
line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7170++0x07
line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7178++0x07
line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7180++0x07
line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7188++0x07
line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7190++0x07
line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7198++0x07
line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71A0++0x07
line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71A8++0x07
line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71B0++0x07
line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71B8++0x07
line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71C0++0x07
line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71C8++0x07
line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71D0++0x07
line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71D8++0x07
line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71E0++0x07
line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71E8++0x07
line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71F0++0x07
line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71F8++0x07
line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7200++0x07
line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7208++0x07
line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7210++0x07
line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7218++0x07
line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7220++0x07
line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7228++0x07
line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7230++0x07
line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7238++0x07
line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7240++0x07
line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7248++0x07
line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7250++0x07
line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7258++0x07
line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7260++0x07
line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7268++0x07
line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7270++0x07
line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7278++0x07
line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7280++0x07
line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7288++0x07
line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7290++0x07
line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7298++0x07
line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72A0++0x07
line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72A8++0x07
line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72B0++0x07
line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72B8++0x07
line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72C0++0x07
line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72C8++0x07
line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72D0++0x07
line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72D8++0x07
line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72E0++0x07
line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72E8++0x07
line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72F0++0x07
line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72F8++0x07
line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7300++0x07
line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7308++0x07
line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7310++0x07
line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7318++0x07
line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7320++0x07
line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7328++0x07
line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7330++0x07
line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7338++0x07
line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7340++0x07
line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7348++0x07
line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7350++0x07
line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7358++0x07
line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7360++0x07
line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7368++0x07
line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7370++0x07
line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7378++0x07
line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7380++0x07
line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7388++0x07
line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7390++0x07
line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7398++0x07
line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73A0++0x07
line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73A8++0x07
line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73B0++0x07
line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73B8++0x07
line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73C0++0x07
line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73C8++0x07
line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73D0++0x07
line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73D8++0x07
line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73E0++0x07
line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73E8++0x07
line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73F0++0x07
line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73F8++0x07
line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7400++0x07
line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7408++0x07
line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7410++0x07
line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7418++0x07
line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7420++0x07
line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7428++0x07
line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7430++0x07
line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7438++0x07
line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7440++0x07
line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7448++0x07
line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7450++0x07
line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7458++0x07
line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7460++0x07
line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7468++0x07
line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7470++0x07
line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7478++0x07
line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7480++0x07
line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7488++0x07
line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7490++0x07
line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7498++0x07
line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74A0++0x07
line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74A8++0x07
line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74B0++0x07
line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74B8++0x07
line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74C0++0x07
line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74C8++0x07
line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74D0++0x07
line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74D8++0x07
line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74E0++0x07
line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74E8++0x07
line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74F0++0x07
line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74F8++0x07
line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7500++0x07
line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7508++0x07
line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7510++0x07
line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7518++0x07
line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7520++0x07
line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7528++0x07
line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7530++0x07
line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7538++0x07
line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7540++0x07
line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7548++0x07
line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7550++0x07
line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7558++0x07
line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7560++0x07
line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7568++0x07
line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7570++0x07
line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7578++0x07
line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7580++0x07
line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7588++0x07
line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7590++0x07
line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7598++0x07
line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75A0++0x07
line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75A8++0x07
line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75B0++0x07
line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75B8++0x07
line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75C0++0x07
line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75C8++0x07
line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75D0++0x07
line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75D8++0x07
line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75E0++0x07
line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75E8++0x07
line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75F0++0x07
line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75F8++0x07
line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7600++0x07
line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7608++0x07
line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7610++0x07
line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7618++0x07
line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7620++0x07
line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7628++0x07
line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7630++0x07
line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7638++0x07
line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7640++0x07
line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7648++0x07
line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7650++0x07
line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7658++0x07
line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7660++0x07
line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7668++0x07
line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7670++0x07
line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7678++0x07
line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7680++0x07
line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7688++0x07
line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7690++0x07
line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7698++0x07
line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76A0++0x07
line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76A8++0x07
line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76B0++0x07
line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76B8++0x07
line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76C0++0x07
line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76C8++0x07
line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76D0++0x07
line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76D8++0x07
line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76E0++0x07
line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76E8++0x07
line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76F0++0x07
line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76F8++0x07
line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7700++0x07
line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7708++0x07
line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7710++0x07
line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7718++0x07
line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7720++0x07
line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7728++0x07
line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7730++0x07
line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7738++0x07
line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7740++0x07
line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7748++0x07
line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7750++0x07
line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7758++0x07
line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7760++0x07
line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7768++0x07
line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7770++0x07
line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7778++0x07
line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7780++0x07
line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7788++0x07
line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7790++0x07
line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7798++0x07
line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77A0++0x07
line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77A8++0x07
line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77B0++0x07
line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77B8++0x07
line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77C0++0x07
line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77C8++0x07
line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77D0++0x07
line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77D8++0x07
line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77E0++0x07
line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77E8++0x07
line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77F0++0x07
line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77F8++0x07
line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7800++0x07
line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7808++0x07
line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7810++0x07
line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7818++0x07
line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7820++0x07
line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7828++0x07
line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7830++0x07
line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7838++0x07
line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7840++0x07
line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7848++0x07
line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7850++0x07
line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7858++0x07
line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7860++0x07
line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7868++0x07
line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7870++0x07
line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7878++0x07
line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7880++0x07
line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7888++0x07
line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7890++0x07
line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7898++0x07
line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78A0++0x07
line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78A8++0x07
line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78B0++0x07
line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78B8++0x07
line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78C0++0x07
line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78C8++0x07
line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78D0++0x07
line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78D8++0x07
line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78E0++0x07
line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78E8++0x07
line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78F0++0x07
line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78F8++0x07
line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7900++0x07
line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7908++0x07
line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7910++0x07
line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7918++0x07
line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7920++0x07
line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7928++0x07
line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7930++0x07
line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7938++0x07
line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7940++0x07
line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7948++0x07
line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7950++0x07
line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7958++0x07
line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7960++0x07
line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7968++0x07
line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7970++0x07
line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7978++0x07
line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7980++0x07
line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7988++0x07
line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7990++0x07
line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7998++0x07
line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79A0++0x07
line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79A8++0x07
line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79B0++0x07
line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79B8++0x07
line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79C0++0x07
line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79C8++0x07
line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79D0++0x07
line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79D8++0x07
line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79E0++0x07
line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79E8++0x07
line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79F0++0x07
line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79F8++0x07
line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A00++0x07
line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A08++0x07
line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A10++0x07
line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A18++0x07
line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A20++0x07
line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A28++0x07
line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A30++0x07
line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A38++0x07
line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A40++0x07
line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A48++0x07
line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A50++0x07
line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A58++0x07
line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A60++0x07
line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A68++0x07
line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A70++0x07
line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A78++0x07
line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A80++0x07
line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A88++0x07
line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A90++0x07
line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A98++0x07
line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AA0++0x07
line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AA8++0x07
line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AB0++0x07
line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AB8++0x07
line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AC0++0x07
line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AC8++0x07
line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AD0++0x07
line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AD8++0x07
line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AE0++0x07
line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AE8++0x07
line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AF0++0x07
line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AF8++0x07
line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B00++0x07
line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B08++0x07
line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B10++0x07
line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B18++0x07
line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B20++0x07
line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B28++0x07
line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B30++0x07
line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B38++0x07
line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B40++0x07
line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B48++0x07
line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B50++0x07
line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B58++0x07
line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B60++0x07
line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B68++0x07
line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B70++0x07
line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B78++0x07
line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B80++0x07
line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B88++0x07
line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B90++0x07
line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B98++0x07
line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BA0++0x07
line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BA8++0x07
line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BB0++0x07
line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BB8++0x07
line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BC0++0x07
line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BC8++0x07
line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BD0++0x07
line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BD8++0x07
line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BE0++0x07
line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BE8++0x07
line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BF0++0x07
line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BF8++0x07
line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C00++0x07
line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C08++0x07
line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C10++0x07
line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C18++0x07
line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C20++0x07
line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C28++0x07
line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C30++0x07
line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C38++0x07
line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C40++0x07
line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C48++0x07
line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C50++0x07
line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C58++0x07
line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C60++0x07
line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C68++0x07
line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C70++0x07
line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C78++0x07
line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C80++0x07
line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C88++0x07
line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C90++0x07
line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C98++0x07
line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CA0++0x07
line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CA8++0x07
line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CB0++0x07
line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CB8++0x07
line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CC0++0x07
line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CC8++0x07
line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CD0++0x07
line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CD8++0x07
line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CE0++0x07
line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CE8++0x07
line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CF0++0x07
line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CF8++0x07
line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D00++0x07
line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D08++0x07
line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D10++0x07
line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D18++0x07
line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D20++0x07
line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D28++0x07
line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D30++0x07
line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D38++0x07
line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D40++0x07
line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D48++0x07
line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D50++0x07
line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D58++0x07
line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D60++0x07
line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D68++0x07
line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D70++0x07
line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D78++0x07
line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D80++0x07
line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D88++0x07
line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D90++0x07
line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D98++0x07
line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DA0++0x07
line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DA8++0x07
line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DB0++0x07
line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DB8++0x07
line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DC0++0x07
line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DC8++0x07
line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DD0++0x07
line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DD8++0x07
line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DE0++0x07
line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DE8++0x07
line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DF0++0x07
line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DF8++0x07
line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E00++0x07
line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E08++0x07
line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E10++0x07
line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E18++0x07
line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E20++0x07
line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E28++0x07
line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E30++0x07
line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E38++0x07
line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E40++0x07
line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E48++0x07
line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E50++0x07
line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E58++0x07
line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E60++0x07
line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E68++0x07
line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E70++0x07
line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E78++0x07
line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E80++0x07
line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E88++0x07
line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E90++0x07
line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E98++0x07
line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EA0++0x07
line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EA8++0x07
line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EB0++0x07
line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EB8++0x07
line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EC0++0x07
line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EC8++0x07
line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7ED0++0x07
line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7ED8++0x07
line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EE0++0x07
line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EE8++0x07
line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EF0++0x07
line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EF8++0x07
line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
tree.end
width 22.
tree "Implementation Defined Test Registers"
rgroup.long 0xC000++0x03
line.long 0x00 "GICD_ESTATUSR,GICD_ESTATUSR"
bitfld.long 0x00 31. " SRWP     ,Super Register Write Pending" "Not pending,Pending"
wgroup.long 0xC004++0x03
line.long 0x00 "GICD_ERRTESTR,Error Test Register"
bitfld.long 0x00 1. " AXIM_ERR ,Drives the axim_err pin to 0b1 for 1 cycle" "Low,High"
bitfld.long 0x00 0. "         ECC_FATAL ,Drives the ecc_fatal pin to 0b1 for 1 cycle" "Low,High"
textline "                               "
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
rgroup.long 0xC084++0x03
line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
bitfld.long 0x00 31. " SPIS63  ,SPI Status Bit 63" "Low,High"
bitfld.long 0x00 30. "  SPIS62  ,SPI Status Bit 62" "Low,High"
bitfld.long 0x00 29. "  SPIS61  ,SPI Status Bit 61" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS60  ,SPI Status Bit 60" "Low,High"
bitfld.long 0x00 27. "  SPIS59  ,SPI Status Bit 59" "Low,High"
bitfld.long 0x00 26. "  SPIS58  ,SPI Status Bit 58" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS57  ,SPI Status Bit 57" "Low,High"
bitfld.long 0x00 24. "  SPIS56  ,SPI Status Bit 56" "Low,High"
bitfld.long 0x00 23. "  SPIS55  ,SPI Status Bit 55" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS54  ,SPI Status Bit 54" "Low,High"
bitfld.long 0x00 21. "  SPIS53  ,SPI Status Bit 53" "Low,High"
bitfld.long 0x00 20. "  SPIS52  ,SPI Status Bit 52" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS51  ,SPI Status Bit 51" "Low,High"
bitfld.long 0x00 18. "  SPIS50  ,SPI Status Bit 50" "Low,High"
bitfld.long 0x00 17. "  SPIS49  ,SPI Status Bit 49" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS48  ,SPI Status Bit 48" "Low,High"
bitfld.long 0x00 15. "  SPIS47  ,SPI Status Bit 47" "Low,High"
bitfld.long 0x00 14. "  SPIS46  ,SPI Status Bit 46" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS45  ,SPI Status Bit 45" "Low,High"
bitfld.long 0x00 12. "  SPIS44  ,SPI Status Bit 44" "Low,High"
bitfld.long 0x00 11. "  SPIS43  ,SPI Status Bit 43" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS42  ,SPI Status Bit 42" "Low,High"
bitfld.long 0x00 9. "  SPIS41  ,SPI Status Bit 41" "Low,High"
bitfld.long 0x00 8. "  SPIS40  ,SPI Status Bit 40" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS39  ,SPI Status Bit 39" "Low,High"
bitfld.long 0x00 6. "  SPIS38  ,SPI Status Bit 38" "Low,High"
bitfld.long 0x00 5. "  SPIS37  ,SPI Status Bit 37" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS36  ,SPI Status Bit 36" "Low,High"
bitfld.long 0x00 3. "  SPIS35  ,SPI Status Bit 35" "Low,High"
bitfld.long 0x00 2. "  SPIS34  ,SPI Status Bit 34" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS33  ,SPI Status Bit 33" "Low,High"
bitfld.long 0x00 0. "  SPIS32  ,SPI Status Bit 32" "Low,High"
else
hgroup.long 0xC084++0x03
hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
rgroup.long 0xC088++0x03
line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
bitfld.long 0x00 31. " SPIS95  ,SPI Status Bit 95" "Low,High"
bitfld.long 0x00 30. "  SPIS94  ,SPI Status Bit 94" "Low,High"
bitfld.long 0x00 29. "  SPIS93  ,SPI Status Bit 93" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS92  ,SPI Status Bit 92" "Low,High"
bitfld.long 0x00 27. "  SPIS91  ,SPI Status Bit 91" "Low,High"
bitfld.long 0x00 26. "  SPIS90  ,SPI Status Bit 90" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS89  ,SPI Status Bit 89" "Low,High"
bitfld.long 0x00 24. "  SPIS88  ,SPI Status Bit 88" "Low,High"
bitfld.long 0x00 23. "  SPIS87  ,SPI Status Bit 87" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS86  ,SPI Status Bit 86" "Low,High"
bitfld.long 0x00 21. "  SPIS85  ,SPI Status Bit 85" "Low,High"
bitfld.long 0x00 20. "  SPIS84  ,SPI Status Bit 84" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS83  ,SPI Status Bit 83" "Low,High"
bitfld.long 0x00 18. "  SPIS82  ,SPI Status Bit 82" "Low,High"
bitfld.long 0x00 17. "  SPIS81  ,SPI Status Bit 81" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS80  ,SPI Status Bit 80" "Low,High"
bitfld.long 0x00 15. "  SPIS79  ,SPI Status Bit 79" "Low,High"
bitfld.long 0x00 14. "  SPIS78  ,SPI Status Bit 78" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS77  ,SPI Status Bit 77" "Low,High"
bitfld.long 0x00 12. "  SPIS76  ,SPI Status Bit 76" "Low,High"
bitfld.long 0x00 11. "  SPIS75  ,SPI Status Bit 75" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS74  ,SPI Status Bit 74" "Low,High"
bitfld.long 0x00 9. "  SPIS73  ,SPI Status Bit 73" "Low,High"
bitfld.long 0x00 8. "  SPIS72  ,SPI Status Bit 72" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS71  ,SPI Status Bit 71" "Low,High"
bitfld.long 0x00 6. "  SPIS70  ,SPI Status Bit 70" "Low,High"
bitfld.long 0x00 5. "  SPIS69  ,SPI Status Bit 69" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS68  ,SPI Status Bit 68" "Low,High"
bitfld.long 0x00 3. "  SPIS67  ,SPI Status Bit 67" "Low,High"
bitfld.long 0x00 2. "  SPIS66  ,SPI Status Bit 66" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS65  ,SPI Status Bit 65" "Low,High"
bitfld.long 0x00 0. "  SPIS64  ,SPI Status Bit 64" "Low,High"
else
hgroup.long 0xC088++0x03
hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
rgroup.long 0xC08C++0x03
line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
bitfld.long 0x00 31. " SPIS127 ,SPI Status Bit 127" "Low,High"
bitfld.long 0x00 30. "  SPIS126 ,SPI Status Bit 126" "Low,High"
bitfld.long 0x00 29. "  SPIS125 ,SPI Status Bit 125" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS124 ,SPI Status Bit 124" "Low,High"
bitfld.long 0x00 27. "  SPIS123 ,SPI Status Bit 123" "Low,High"
bitfld.long 0x00 26. "  SPIS122 ,SPI Status Bit 122" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS121 ,SPI Status Bit 121" "Low,High"
bitfld.long 0x00 24. "  SPIS120 ,SPI Status Bit 120" "Low,High"
bitfld.long 0x00 23. "  SPIS119 ,SPI Status Bit 119" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS118 ,SPI Status Bit 118" "Low,High"
bitfld.long 0x00 21. "  SPIS117 ,SPI Status Bit 117" "Low,High"
bitfld.long 0x00 20. "  SPIS116 ,SPI Status Bit 116" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS115 ,SPI Status Bit 115" "Low,High"
bitfld.long 0x00 18. "  SPIS114 ,SPI Status Bit 114" "Low,High"
bitfld.long 0x00 17. "  SPIS113 ,SPI Status Bit 113" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS112 ,SPI Status Bit 112" "Low,High"
bitfld.long 0x00 15. "  SPIS111 ,SPI Status Bit 111" "Low,High"
bitfld.long 0x00 14. "  SPIS110 ,SPI Status Bit 110" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS109 ,SPI Status Bit 109" "Low,High"
bitfld.long 0x00 12. "  SPIS108 ,SPI Status Bit 108" "Low,High"
bitfld.long 0x00 11. "  SPIS107 ,SPI Status Bit 107" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS106 ,SPI Status Bit 106" "Low,High"
bitfld.long 0x00 9. "  SPIS105 ,SPI Status Bit 105" "Low,High"
bitfld.long 0x00 8. "  SPIS104 ,SPI Status Bit 104" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS103 ,SPI Status Bit 103" "Low,High"
bitfld.long 0x00 6. "  SPIS102 ,SPI Status Bit 102" "Low,High"
bitfld.long 0x00 5. "  SPIS101 ,SPI Status Bit 101" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS100 ,SPI Status Bit 100" "Low,High"
bitfld.long 0x00 3. "  SPIS99  ,SPI Status Bit 99" "Low,High"
bitfld.long 0x00 2. "  SPIS98  ,SPI Status Bit 98" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS97  ,SPI Status Bit 97" "Low,High"
bitfld.long 0x00 0. "  SPIS96  ,SPI Status Bit 96" "Low,High"
else
hgroup.long 0xC08C++0x03
hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
rgroup.long 0xC090++0x03
line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
bitfld.long 0x00 31. " SPIS159 ,SPI Status Bit 159" "Low,High"
bitfld.long 0x00 30. "  SPIS158 ,SPI Status Bit 158" "Low,High"
bitfld.long 0x00 29. "  SPIS157 ,SPI Status Bit 157" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS156 ,SPI Status Bit 156" "Low,High"
bitfld.long 0x00 27. "  SPIS155 ,SPI Status Bit 155" "Low,High"
bitfld.long 0x00 26. "  SPIS154 ,SPI Status Bit 154" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS153 ,SPI Status Bit 153" "Low,High"
bitfld.long 0x00 24. "  SPIS152 ,SPI Status Bit 152" "Low,High"
bitfld.long 0x00 23. "  SPIS151 ,SPI Status Bit 151" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS150 ,SPI Status Bit 150" "Low,High"
bitfld.long 0x00 21. "  SPIS149 ,SPI Status Bit 149" "Low,High"
bitfld.long 0x00 20. "  SPIS148 ,SPI Status Bit 148" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS147 ,SPI Status Bit 147" "Low,High"
bitfld.long 0x00 18. "  SPIS146 ,SPI Status Bit 146" "Low,High"
bitfld.long 0x00 17. "  SPIS145 ,SPI Status Bit 145" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS144 ,SPI Status Bit 144" "Low,High"
bitfld.long 0x00 15. "  SPIS143 ,SPI Status Bit 143" "Low,High"
bitfld.long 0x00 14. "  SPIS142 ,SPI Status Bit 142" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS141 ,SPI Status Bit 141" "Low,High"
bitfld.long 0x00 12. "  SPIS140 ,SPI Status Bit 140" "Low,High"
bitfld.long 0x00 11. "  SPIS139 ,SPI Status Bit 139" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS138 ,SPI Status Bit 138" "Low,High"
bitfld.long 0x00 9. "  SPIS137 ,SPI Status Bit 137" "Low,High"
bitfld.long 0x00 8. "  SPIS136 ,SPI Status Bit 136" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS135 ,SPI Status Bit 135" "Low,High"
bitfld.long 0x00 6. "  SPIS134 ,SPI Status Bit 134" "Low,High"
bitfld.long 0x00 5. "  SPIS133 ,SPI Status Bit 133" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS132 ,SPI Status Bit 132" "Low,High"
bitfld.long 0x00 3. "  SPIS131 ,SPI Status Bit 131" "Low,High"
bitfld.long 0x00 2. "  SPIS130 ,SPI Status Bit 130" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS129 ,SPI Status Bit 129" "Low,High"
bitfld.long 0x00 0. "  SPIS128 ,SPI Status Bit 128" "Low,High"
else
hgroup.long 0xC090++0x03
hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
rgroup.long 0xC094++0x03
line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
bitfld.long 0x00 31. " SPIS191 ,SPI Status Bit 191" "Low,High"
bitfld.long 0x00 30. "  SPIS190 ,SPI Status Bit 190" "Low,High"
bitfld.long 0x00 29. "  SPIS189 ,SPI Status Bit 189" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS188 ,SPI Status Bit 188" "Low,High"
bitfld.long 0x00 27. "  SPIS187 ,SPI Status Bit 187" "Low,High"
bitfld.long 0x00 26. "  SPIS186 ,SPI Status Bit 186" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS185 ,SPI Status Bit 185" "Low,High"
bitfld.long 0x00 24. "  SPIS184 ,SPI Status Bit 184" "Low,High"
bitfld.long 0x00 23. "  SPIS183 ,SPI Status Bit 183" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS182 ,SPI Status Bit 182" "Low,High"
bitfld.long 0x00 21. "  SPIS181 ,SPI Status Bit 181" "Low,High"
bitfld.long 0x00 20. "  SPIS180 ,SPI Status Bit 180" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS179 ,SPI Status Bit 179" "Low,High"
bitfld.long 0x00 18. "  SPIS178 ,SPI Status Bit 178" "Low,High"
bitfld.long 0x00 17. "  SPIS177 ,SPI Status Bit 177" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS176 ,SPI Status Bit 176" "Low,High"
bitfld.long 0x00 15. "  SPIS175 ,SPI Status Bit 175" "Low,High"
bitfld.long 0x00 14. "  SPIS174 ,SPI Status Bit 174" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS173 ,SPI Status Bit 173" "Low,High"
bitfld.long 0x00 12. "  SPIS172 ,SPI Status Bit 172" "Low,High"
bitfld.long 0x00 11. "  SPIS171 ,SPI Status Bit 171" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS170 ,SPI Status Bit 170" "Low,High"
bitfld.long 0x00 9. "  SPIS169 ,SPI Status Bit 169" "Low,High"
bitfld.long 0x00 8. "  SPIS168 ,SPI Status Bit 168" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS167 ,SPI Status Bit 167" "Low,High"
bitfld.long 0x00 6. "  SPIS166 ,SPI Status Bit 166" "Low,High"
bitfld.long 0x00 5. "  SPIS165 ,SPI Status Bit 165" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS164 ,SPI Status Bit 164" "Low,High"
bitfld.long 0x00 3. "  SPIS163 ,SPI Status Bit 163" "Low,High"
bitfld.long 0x00 2. "  SPIS162 ,SPI Status Bit 162" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS161 ,SPI Status Bit 161" "Low,High"
bitfld.long 0x00 0. "  SPIS160 ,SPI Status Bit 160" "Low,High"
else
hgroup.long 0xC094++0x03
hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
rgroup.long 0xC098++0x03
line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
bitfld.long 0x00 31. " SPIS223 ,SPI Status Bit 223" "Low,High"
bitfld.long 0x00 30. "  SPIS222 ,SPI Status Bit 222" "Low,High"
bitfld.long 0x00 29. "  SPIS221 ,SPI Status Bit 221" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS220 ,SPI Status Bit 220" "Low,High"
bitfld.long 0x00 27. "  SPIS219 ,SPI Status Bit 219" "Low,High"
bitfld.long 0x00 26. "  SPIS218 ,SPI Status Bit 218" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS217 ,SPI Status Bit 217" "Low,High"
bitfld.long 0x00 24. "  SPIS216 ,SPI Status Bit 216" "Low,High"
bitfld.long 0x00 23. "  SPIS215 ,SPI Status Bit 215" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS214 ,SPI Status Bit 214" "Low,High"
bitfld.long 0x00 21. "  SPIS213 ,SPI Status Bit 213" "Low,High"
bitfld.long 0x00 20. "  SPIS212 ,SPI Status Bit 212" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS211 ,SPI Status Bit 211" "Low,High"
bitfld.long 0x00 18. "  SPIS210 ,SPI Status Bit 210" "Low,High"
bitfld.long 0x00 17. "  SPIS209 ,SPI Status Bit 209" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS208 ,SPI Status Bit 208" "Low,High"
bitfld.long 0x00 15. "  SPIS207 ,SPI Status Bit 207" "Low,High"
bitfld.long 0x00 14. "  SPIS206 ,SPI Status Bit 206" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS205 ,SPI Status Bit 205" "Low,High"
bitfld.long 0x00 12. "  SPIS204 ,SPI Status Bit 204" "Low,High"
bitfld.long 0x00 11. "  SPIS203 ,SPI Status Bit 203" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS202 ,SPI Status Bit 202" "Low,High"
bitfld.long 0x00 9. "  SPIS201 ,SPI Status Bit 201" "Low,High"
bitfld.long 0x00 8. "  SPIS200 ,SPI Status Bit 200" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS199 ,SPI Status Bit 199" "Low,High"
bitfld.long 0x00 6. "  SPIS198 ,SPI Status Bit 198" "Low,High"
bitfld.long 0x00 5. "  SPIS197 ,SPI Status Bit 197" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS196 ,SPI Status Bit 196" "Low,High"
bitfld.long 0x00 3. "  SPIS195 ,SPI Status Bit 195" "Low,High"
bitfld.long 0x00 2. "  SPIS194 ,SPI Status Bit 194" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS193 ,SPI Status Bit 193" "Low,High"
bitfld.long 0x00 0. "  SPIS192 ,SPI Status Bit 192" "Low,High"
else
hgroup.long 0xC098++0x03
hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
rgroup.long 0xC09C++0x03
line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
bitfld.long 0x00 31. " SPIS255 ,SPI Status Bit 255" "Low,High"
bitfld.long 0x00 30. "  SPIS254 ,SPI Status Bit 254" "Low,High"
bitfld.long 0x00 29. "  SPIS253 ,SPI Status Bit 253" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS252 ,SPI Status Bit 252" "Low,High"
bitfld.long 0x00 27. "  SPIS251 ,SPI Status Bit 251" "Low,High"
bitfld.long 0x00 26. "  SPIS250 ,SPI Status Bit 250" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS249 ,SPI Status Bit 249" "Low,High"
bitfld.long 0x00 24. "  SPIS248 ,SPI Status Bit 248" "Low,High"
bitfld.long 0x00 23. "  SPIS247 ,SPI Status Bit 247" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS246 ,SPI Status Bit 246" "Low,High"
bitfld.long 0x00 21. "  SPIS245 ,SPI Status Bit 245" "Low,High"
bitfld.long 0x00 20. "  SPIS244 ,SPI Status Bit 244" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS243 ,SPI Status Bit 243" "Low,High"
bitfld.long 0x00 18. "  SPIS242 ,SPI Status Bit 242" "Low,High"
bitfld.long 0x00 17. "  SPIS241 ,SPI Status Bit 241" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS240 ,SPI Status Bit 240" "Low,High"
bitfld.long 0x00 15. "  SPIS239 ,SPI Status Bit 239" "Low,High"
bitfld.long 0x00 14. "  SPIS238 ,SPI Status Bit 238" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS237 ,SPI Status Bit 237" "Low,High"
bitfld.long 0x00 12. "  SPIS236 ,SPI Status Bit 236" "Low,High"
bitfld.long 0x00 11. "  SPIS235 ,SPI Status Bit 235" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS234 ,SPI Status Bit 234" "Low,High"
bitfld.long 0x00 9. "  SPIS233 ,SPI Status Bit 233" "Low,High"
bitfld.long 0x00 8. "  SPIS232 ,SPI Status Bit 232" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS231 ,SPI Status Bit 231" "Low,High"
bitfld.long 0x00 6. "  SPIS230 ,SPI Status Bit 230" "Low,High"
bitfld.long 0x00 5. "  SPIS229 ,SPI Status Bit 229" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS228 ,SPI Status Bit 228" "Low,High"
bitfld.long 0x00 3. "  SPIS227 ,SPI Status Bit 227" "Low,High"
bitfld.long 0x00 2. "  SPIS226 ,SPI Status Bit 226" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS225 ,SPI Status Bit 225" "Low,High"
bitfld.long 0x00 0. "  SPIS224 ,SPI Status Bit 224" "Low,High"
else
hgroup.long 0xC09C++0x03
hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
rgroup.long 0xC0A0++0x03
line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
bitfld.long 0x00 31. " SPIS287 ,SPI Status Bit 287" "Low,High"
bitfld.long 0x00 30. "  SPIS286 ,SPI Status Bit 286" "Low,High"
bitfld.long 0x00 29. "  SPIS285 ,SPI Status Bit 285" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS284 ,SPI Status Bit 284" "Low,High"
bitfld.long 0x00 27. "  SPIS283 ,SPI Status Bit 283" "Low,High"
bitfld.long 0x00 26. "  SPIS282 ,SPI Status Bit 282" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS281 ,SPI Status Bit 281" "Low,High"
bitfld.long 0x00 24. "  SPIS280 ,SPI Status Bit 280" "Low,High"
bitfld.long 0x00 23. "  SPIS279 ,SPI Status Bit 279" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS278 ,SPI Status Bit 278" "Low,High"
bitfld.long 0x00 21. "  SPIS277 ,SPI Status Bit 277" "Low,High"
bitfld.long 0x00 20. "  SPIS276 ,SPI Status Bit 276" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS275 ,SPI Status Bit 275" "Low,High"
bitfld.long 0x00 18. "  SPIS274 ,SPI Status Bit 274" "Low,High"
bitfld.long 0x00 17. "  SPIS273 ,SPI Status Bit 273" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS272 ,SPI Status Bit 272" "Low,High"
bitfld.long 0x00 15. "  SPIS271 ,SPI Status Bit 271" "Low,High"
bitfld.long 0x00 14. "  SPIS270 ,SPI Status Bit 270" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS269 ,SPI Status Bit 269" "Low,High"
bitfld.long 0x00 12. "  SPIS268 ,SPI Status Bit 268" "Low,High"
bitfld.long 0x00 11. "  SPIS267 ,SPI Status Bit 267" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS266 ,SPI Status Bit 266" "Low,High"
bitfld.long 0x00 9. "  SPIS265 ,SPI Status Bit 265" "Low,High"
bitfld.long 0x00 8. "  SPIS264 ,SPI Status Bit 264" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS263 ,SPI Status Bit 263" "Low,High"
bitfld.long 0x00 6. "  SPIS262 ,SPI Status Bit 262" "Low,High"
bitfld.long 0x00 5. "  SPIS261 ,SPI Status Bit 261" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS260 ,SPI Status Bit 260" "Low,High"
bitfld.long 0x00 3. "  SPIS259 ,SPI Status Bit 259" "Low,High"
bitfld.long 0x00 2. "  SPIS258 ,SPI Status Bit 258" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS257 ,SPI Status Bit 257" "Low,High"
bitfld.long 0x00 0. "  SPIS256 ,SPI Status Bit 256" "Low,High"
else
hgroup.long 0xC0A0++0x03
hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
rgroup.long 0xC0A4++0x03
line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
bitfld.long 0x00 31. " SPIS319 ,SPI Status Bit 319" "Low,High"
bitfld.long 0x00 30. "  SPIS318 ,SPI Status Bit 318" "Low,High"
bitfld.long 0x00 29. "  SPIS317 ,SPI Status Bit 317" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS316 ,SPI Status Bit 316" "Low,High"
bitfld.long 0x00 27. "  SPIS315 ,SPI Status Bit 315" "Low,High"
bitfld.long 0x00 26. "  SPIS314 ,SPI Status Bit 314" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS313 ,SPI Status Bit 313" "Low,High"
bitfld.long 0x00 24. "  SPIS312 ,SPI Status Bit 312" "Low,High"
bitfld.long 0x00 23. "  SPIS311 ,SPI Status Bit 311" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS310 ,SPI Status Bit 310" "Low,High"
bitfld.long 0x00 21. "  SPIS309 ,SPI Status Bit 309" "Low,High"
bitfld.long 0x00 20. "  SPIS308 ,SPI Status Bit 308" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS307 ,SPI Status Bit 307" "Low,High"
bitfld.long 0x00 18. "  SPIS306 ,SPI Status Bit 306" "Low,High"
bitfld.long 0x00 17. "  SPIS305 ,SPI Status Bit 305" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS304 ,SPI Status Bit 304" "Low,High"
bitfld.long 0x00 15. "  SPIS303 ,SPI Status Bit 303" "Low,High"
bitfld.long 0x00 14. "  SPIS302 ,SPI Status Bit 302" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS301 ,SPI Status Bit 301" "Low,High"
bitfld.long 0x00 12. "  SPIS300 ,SPI Status Bit 300" "Low,High"
bitfld.long 0x00 11. "  SPIS299 ,SPI Status Bit 299" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS298 ,SPI Status Bit 298" "Low,High"
bitfld.long 0x00 9. "  SPIS297 ,SPI Status Bit 297" "Low,High"
bitfld.long 0x00 8. "  SPIS296 ,SPI Status Bit 296" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS295 ,SPI Status Bit 295" "Low,High"
bitfld.long 0x00 6. "  SPIS294 ,SPI Status Bit 294" "Low,High"
bitfld.long 0x00 5. "  SPIS293 ,SPI Status Bit 293" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS292 ,SPI Status Bit 292" "Low,High"
bitfld.long 0x00 3. "  SPIS291 ,SPI Status Bit 291" "Low,High"
bitfld.long 0x00 2. "  SPIS290 ,SPI Status Bit 290" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS289 ,SPI Status Bit 289" "Low,High"
bitfld.long 0x00 0. "  SPIS288 ,SPI Status Bit 288" "Low,High"
else
hgroup.long 0xC0A4++0x03
hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
rgroup.long 0xC0A8++0x03
line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
bitfld.long 0x00 31. " SPIS351 ,SPI Status Bit 351" "Low,High"
bitfld.long 0x00 30. "  SPIS350 ,SPI Status Bit 350" "Low,High"
bitfld.long 0x00 29. "  SPIS349 ,SPI Status Bit 349" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS348 ,SPI Status Bit 348" "Low,High"
bitfld.long 0x00 27. "  SPIS347 ,SPI Status Bit 347" "Low,High"
bitfld.long 0x00 26. "  SPIS346 ,SPI Status Bit 346" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS345 ,SPI Status Bit 345" "Low,High"
bitfld.long 0x00 24. "  SPIS344 ,SPI Status Bit 344" "Low,High"
bitfld.long 0x00 23. "  SPIS343 ,SPI Status Bit 343" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS342 ,SPI Status Bit 342" "Low,High"
bitfld.long 0x00 21. "  SPIS341 ,SPI Status Bit 341" "Low,High"
bitfld.long 0x00 20. "  SPIS340 ,SPI Status Bit 340" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS339 ,SPI Status Bit 339" "Low,High"
bitfld.long 0x00 18. "  SPIS338 ,SPI Status Bit 338" "Low,High"
bitfld.long 0x00 17. "  SPIS337 ,SPI Status Bit 337" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS336 ,SPI Status Bit 336" "Low,High"
bitfld.long 0x00 15. "  SPIS335 ,SPI Status Bit 335" "Low,High"
bitfld.long 0x00 14. "  SPIS334 ,SPI Status Bit 334" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS333 ,SPI Status Bit 333" "Low,High"
bitfld.long 0x00 12. "  SPIS332 ,SPI Status Bit 332" "Low,High"
bitfld.long 0x00 11. "  SPIS331 ,SPI Status Bit 331" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS330 ,SPI Status Bit 330" "Low,High"
bitfld.long 0x00 9. "  SPIS329 ,SPI Status Bit 329" "Low,High"
bitfld.long 0x00 8. "  SPIS328 ,SPI Status Bit 328" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS327 ,SPI Status Bit 327" "Low,High"
bitfld.long 0x00 6. "  SPIS326 ,SPI Status Bit 326" "Low,High"
bitfld.long 0x00 5. "  SPIS325 ,SPI Status Bit 325" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS324 ,SPI Status Bit 324" "Low,High"
bitfld.long 0x00 3. "  SPIS323 ,SPI Status Bit 323" "Low,High"
bitfld.long 0x00 2. "  SPIS322 ,SPI Status Bit 322" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS321 ,SPI Status Bit 321" "Low,High"
bitfld.long 0x00 0. "  SPIS320 ,SPI Status Bit 320" "Low,High"
else
hgroup.long 0xC0A8++0x03
hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
rgroup.long 0xC0AC++0x03
line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
bitfld.long 0x00 31. " SPIS383 ,SPI Status Bit 383" "Low,High"
bitfld.long 0x00 30. "  SPIS382 ,SPI Status Bit 382" "Low,High"
bitfld.long 0x00 29. "  SPIS381 ,SPI Status Bit 381" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS380 ,SPI Status Bit 380" "Low,High"
bitfld.long 0x00 27. "  SPIS379 ,SPI Status Bit 379" "Low,High"
bitfld.long 0x00 26. "  SPIS378 ,SPI Status Bit 378" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS377 ,SPI Status Bit 377" "Low,High"
bitfld.long 0x00 24. "  SPIS376 ,SPI Status Bit 376" "Low,High"
bitfld.long 0x00 23. "  SPIS375 ,SPI Status Bit 375" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS374 ,SPI Status Bit 374" "Low,High"
bitfld.long 0x00 21. "  SPIS373 ,SPI Status Bit 373" "Low,High"
bitfld.long 0x00 20. "  SPIS372 ,SPI Status Bit 372" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS371 ,SPI Status Bit 371" "Low,High"
bitfld.long 0x00 18. "  SPIS370 ,SPI Status Bit 370" "Low,High"
bitfld.long 0x00 17. "  SPIS369 ,SPI Status Bit 369" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS368 ,SPI Status Bit 368" "Low,High"
bitfld.long 0x00 15. "  SPIS367 ,SPI Status Bit 367" "Low,High"
bitfld.long 0x00 14. "  SPIS366 ,SPI Status Bit 366" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS365 ,SPI Status Bit 365" "Low,High"
bitfld.long 0x00 12. "  SPIS364 ,SPI Status Bit 364" "Low,High"
bitfld.long 0x00 11. "  SPIS363 ,SPI Status Bit 363" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS362 ,SPI Status Bit 362" "Low,High"
bitfld.long 0x00 9. "  SPIS361 ,SPI Status Bit 361" "Low,High"
bitfld.long 0x00 8. "  SPIS360 ,SPI Status Bit 360" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS359 ,SPI Status Bit 359" "Low,High"
bitfld.long 0x00 6. "  SPIS358 ,SPI Status Bit 358" "Low,High"
bitfld.long 0x00 5. "  SPIS357 ,SPI Status Bit 357" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS356 ,SPI Status Bit 356" "Low,High"
bitfld.long 0x00 3. "  SPIS355 ,SPI Status Bit 355" "Low,High"
bitfld.long 0x00 2. "  SPIS354 ,SPI Status Bit 354" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS353 ,SPI Status Bit 353" "Low,High"
bitfld.long 0x00 0. "  SPIS352 ,SPI Status Bit 352" "Low,High"
else
hgroup.long 0xC0AC++0x03
hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
rgroup.long 0xC0B0++0x03
line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
bitfld.long 0x00 31. " SPIS415 ,SPI Status Bit 415" "Low,High"
bitfld.long 0x00 30. "  SPIS414 ,SPI Status Bit 414" "Low,High"
bitfld.long 0x00 29. "  SPIS413 ,SPI Status Bit 413" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS412 ,SPI Status Bit 412" "Low,High"
bitfld.long 0x00 27. "  SPIS411 ,SPI Status Bit 411" "Low,High"
bitfld.long 0x00 26. "  SPIS410 ,SPI Status Bit 410" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS409 ,SPI Status Bit 409" "Low,High"
bitfld.long 0x00 24. "  SPIS408 ,SPI Status Bit 408" "Low,High"
bitfld.long 0x00 23. "  SPIS407 ,SPI Status Bit 407" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS406 ,SPI Status Bit 406" "Low,High"
bitfld.long 0x00 21. "  SPIS405 ,SPI Status Bit 405" "Low,High"
bitfld.long 0x00 20. "  SPIS404 ,SPI Status Bit 404" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS403 ,SPI Status Bit 403" "Low,High"
bitfld.long 0x00 18. "  SPIS402 ,SPI Status Bit 402" "Low,High"
bitfld.long 0x00 17. "  SPIS401 ,SPI Status Bit 401" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS400 ,SPI Status Bit 400" "Low,High"
bitfld.long 0x00 15. "  SPIS399 ,SPI Status Bit 399" "Low,High"
bitfld.long 0x00 14. "  SPIS398 ,SPI Status Bit 398" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS397 ,SPI Status Bit 397" "Low,High"
bitfld.long 0x00 12. "  SPIS396 ,SPI Status Bit 396" "Low,High"
bitfld.long 0x00 11. "  SPIS395 ,SPI Status Bit 395" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS394 ,SPI Status Bit 394" "Low,High"
bitfld.long 0x00 9. "  SPIS393 ,SPI Status Bit 393" "Low,High"
bitfld.long 0x00 8. "  SPIS392 ,SPI Status Bit 392" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS391 ,SPI Status Bit 391" "Low,High"
bitfld.long 0x00 6. "  SPIS390 ,SPI Status Bit 390" "Low,High"
bitfld.long 0x00 5. "  SPIS389 ,SPI Status Bit 389" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS388 ,SPI Status Bit 388" "Low,High"
bitfld.long 0x00 3. "  SPIS387 ,SPI Status Bit 387" "Low,High"
bitfld.long 0x00 2. "  SPIS386 ,SPI Status Bit 386" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS385 ,SPI Status Bit 385" "Low,High"
bitfld.long 0x00 0. "  SPIS384 ,SPI Status Bit 384" "Low,High"
else
hgroup.long 0xC0B0++0x03
hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
rgroup.long 0xC0B4++0x03
line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
bitfld.long 0x00 31. " SPIS447 ,SPI Status Bit 447" "Low,High"
bitfld.long 0x00 30. "  SPIS446 ,SPI Status Bit 446" "Low,High"
bitfld.long 0x00 29. "  SPIS445 ,SPI Status Bit 445" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS444 ,SPI Status Bit 444" "Low,High"
bitfld.long 0x00 27. "  SPIS443 ,SPI Status Bit 443" "Low,High"
bitfld.long 0x00 26. "  SPIS442 ,SPI Status Bit 442" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS441 ,SPI Status Bit 441" "Low,High"
bitfld.long 0x00 24. "  SPIS440 ,SPI Status Bit 440" "Low,High"
bitfld.long 0x00 23. "  SPIS439 ,SPI Status Bit 439" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS438 ,SPI Status Bit 438" "Low,High"
bitfld.long 0x00 21. "  SPIS437 ,SPI Status Bit 437" "Low,High"
bitfld.long 0x00 20. "  SPIS436 ,SPI Status Bit 436" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS435 ,SPI Status Bit 435" "Low,High"
bitfld.long 0x00 18. "  SPIS434 ,SPI Status Bit 434" "Low,High"
bitfld.long 0x00 17. "  SPIS433 ,SPI Status Bit 433" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS432 ,SPI Status Bit 432" "Low,High"
bitfld.long 0x00 15. "  SPIS431 ,SPI Status Bit 431" "Low,High"
bitfld.long 0x00 14. "  SPIS430 ,SPI Status Bit 430" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS429 ,SPI Status Bit 429" "Low,High"
bitfld.long 0x00 12. "  SPIS428 ,SPI Status Bit 428" "Low,High"
bitfld.long 0x00 11. "  SPIS427 ,SPI Status Bit 427" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS426 ,SPI Status Bit 426" "Low,High"
bitfld.long 0x00 9. "  SPIS425 ,SPI Status Bit 425" "Low,High"
bitfld.long 0x00 8. "  SPIS424 ,SPI Status Bit 424" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS423 ,SPI Status Bit 423" "Low,High"
bitfld.long 0x00 6. "  SPIS422 ,SPI Status Bit 422" "Low,High"
bitfld.long 0x00 5. "  SPIS421 ,SPI Status Bit 421" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS420 ,SPI Status Bit 420" "Low,High"
bitfld.long 0x00 3. "  SPIS419 ,SPI Status Bit 419" "Low,High"
bitfld.long 0x00 2. "  SPIS418 ,SPI Status Bit 418" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS417 ,SPI Status Bit 417" "Low,High"
bitfld.long 0x00 0. "  SPIS416 ,SPI Status Bit 416" "Low,High"
else
hgroup.long 0xC0B4++0x03
hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
rgroup.long 0xC0B8++0x03
line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
bitfld.long 0x00 31. " SPIS479 ,SPI Status Bit 479" "Low,High"
bitfld.long 0x00 30. "  SPIS478 ,SPI Status Bit 478" "Low,High"
bitfld.long 0x00 29. "  SPIS477 ,SPI Status Bit 477" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS476 ,SPI Status Bit 476" "Low,High"
bitfld.long 0x00 27. "  SPIS475 ,SPI Status Bit 475" "Low,High"
bitfld.long 0x00 26. "  SPIS474 ,SPI Status Bit 474" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS473 ,SPI Status Bit 473" "Low,High"
bitfld.long 0x00 24. "  SPIS472 ,SPI Status Bit 472" "Low,High"
bitfld.long 0x00 23. "  SPIS471 ,SPI Status Bit 471" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS470 ,SPI Status Bit 470" "Low,High"
bitfld.long 0x00 21. "  SPIS469 ,SPI Status Bit 469" "Low,High"
bitfld.long 0x00 20. "  SPIS468 ,SPI Status Bit 468" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS467 ,SPI Status Bit 467" "Low,High"
bitfld.long 0x00 18. "  SPIS466 ,SPI Status Bit 466" "Low,High"
bitfld.long 0x00 17. "  SPIS465 ,SPI Status Bit 465" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS464 ,SPI Status Bit 464" "Low,High"
bitfld.long 0x00 15. "  SPIS463 ,SPI Status Bit 463" "Low,High"
bitfld.long 0x00 14. "  SPIS462 ,SPI Status Bit 462" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS461 ,SPI Status Bit 461" "Low,High"
bitfld.long 0x00 12. "  SPIS460 ,SPI Status Bit 460" "Low,High"
bitfld.long 0x00 11. "  SPIS459 ,SPI Status Bit 459" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS458 ,SPI Status Bit 458" "Low,High"
bitfld.long 0x00 9. "  SPIS457 ,SPI Status Bit 457" "Low,High"
bitfld.long 0x00 8. "  SPIS456 ,SPI Status Bit 456" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS455 ,SPI Status Bit 455" "Low,High"
bitfld.long 0x00 6. "  SPIS454 ,SPI Status Bit 454" "Low,High"
bitfld.long 0x00 5. "  SPIS453 ,SPI Status Bit 453" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS452 ,SPI Status Bit 452" "Low,High"
bitfld.long 0x00 3. "  SPIS451 ,SPI Status Bit 451" "Low,High"
bitfld.long 0x00 2. "  SPIS450 ,SPI Status Bit 450" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS449 ,SPI Status Bit 449" "Low,High"
bitfld.long 0x00 0. "  SPIS448 ,SPI Status Bit 448" "Low,High"
else
hgroup.long 0xC0B8++0x03
hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
rgroup.long 0xC0BC++0x03
line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
bitfld.long 0x00 31. " SPIS511 ,SPI Status Bit 511" "Low,High"
bitfld.long 0x00 30. "  SPIS510 ,SPI Status Bit 510" "Low,High"
bitfld.long 0x00 29. "  SPIS509 ,SPI Status Bit 509" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS508 ,SPI Status Bit 508" "Low,High"
bitfld.long 0x00 27. "  SPIS507 ,SPI Status Bit 507" "Low,High"
bitfld.long 0x00 26. "  SPIS506 ,SPI Status Bit 506" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS505 ,SPI Status Bit 505" "Low,High"
bitfld.long 0x00 24. "  SPIS504 ,SPI Status Bit 504" "Low,High"
bitfld.long 0x00 23. "  SPIS503 ,SPI Status Bit 503" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS502 ,SPI Status Bit 502" "Low,High"
bitfld.long 0x00 21. "  SPIS501 ,SPI Status Bit 501" "Low,High"
bitfld.long 0x00 20. "  SPIS500 ,SPI Status Bit 500" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS499 ,SPI Status Bit 499" "Low,High"
bitfld.long 0x00 18. "  SPIS498 ,SPI Status Bit 498" "Low,High"
bitfld.long 0x00 17. "  SPIS497 ,SPI Status Bit 497" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS496 ,SPI Status Bit 496" "Low,High"
bitfld.long 0x00 15. "  SPIS495 ,SPI Status Bit 495" "Low,High"
bitfld.long 0x00 14. "  SPIS494 ,SPI Status Bit 494" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS493 ,SPI Status Bit 493" "Low,High"
bitfld.long 0x00 12. "  SPIS492 ,SPI Status Bit 492" "Low,High"
bitfld.long 0x00 11. "  SPIS491 ,SPI Status Bit 491" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS490 ,SPI Status Bit 490" "Low,High"
bitfld.long 0x00 9. "  SPIS489 ,SPI Status Bit 489" "Low,High"
bitfld.long 0x00 8. "  SPIS488 ,SPI Status Bit 488" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS487 ,SPI Status Bit 487" "Low,High"
bitfld.long 0x00 6. "  SPIS486 ,SPI Status Bit 486" "Low,High"
bitfld.long 0x00 5. "  SPIS485 ,SPI Status Bit 485" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS484 ,SPI Status Bit 484" "Low,High"
bitfld.long 0x00 3. "  SPIS483 ,SPI Status Bit 483" "Low,High"
bitfld.long 0x00 2. "  SPIS482 ,SPI Status Bit 482" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS481 ,SPI Status Bit 481" "Low,High"
bitfld.long 0x00 0. "  SPIS480 ,SPI Status Bit 480" "Low,High"
else
hgroup.long 0xC0BC++0x03
hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
rgroup.long 0xC0C0++0x03
line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
bitfld.long 0x00 31. " SPIS543 ,SPI Status Bit 543" "Low,High"
bitfld.long 0x00 30. "  SPIS542 ,SPI Status Bit 542" "Low,High"
bitfld.long 0x00 29. "  SPIS541 ,SPI Status Bit 541" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS540 ,SPI Status Bit 540" "Low,High"
bitfld.long 0x00 27. "  SPIS539 ,SPI Status Bit 539" "Low,High"
bitfld.long 0x00 26. "  SPIS538 ,SPI Status Bit 538" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS537 ,SPI Status Bit 537" "Low,High"
bitfld.long 0x00 24. "  SPIS536 ,SPI Status Bit 536" "Low,High"
bitfld.long 0x00 23. "  SPIS535 ,SPI Status Bit 535" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS534 ,SPI Status Bit 534" "Low,High"
bitfld.long 0x00 21. "  SPIS533 ,SPI Status Bit 533" "Low,High"
bitfld.long 0x00 20. "  SPIS532 ,SPI Status Bit 532" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS531 ,SPI Status Bit 531" "Low,High"
bitfld.long 0x00 18. "  SPIS530 ,SPI Status Bit 530" "Low,High"
bitfld.long 0x00 17. "  SPIS529 ,SPI Status Bit 529" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS528 ,SPI Status Bit 528" "Low,High"
bitfld.long 0x00 15. "  SPIS527 ,SPI Status Bit 527" "Low,High"
bitfld.long 0x00 14. "  SPIS526 ,SPI Status Bit 526" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS525 ,SPI Status Bit 525" "Low,High"
bitfld.long 0x00 12. "  SPIS524 ,SPI Status Bit 524" "Low,High"
bitfld.long 0x00 11. "  SPIS523 ,SPI Status Bit 523" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS522 ,SPI Status Bit 522" "Low,High"
bitfld.long 0x00 9. "  SPIS521 ,SPI Status Bit 521" "Low,High"
bitfld.long 0x00 8. "  SPIS520 ,SPI Status Bit 520" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS519 ,SPI Status Bit 519" "Low,High"
bitfld.long 0x00 6. "  SPIS518 ,SPI Status Bit 518" "Low,High"
bitfld.long 0x00 5. "  SPIS517 ,SPI Status Bit 517" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS516 ,SPI Status Bit 516" "Low,High"
bitfld.long 0x00 3. "  SPIS515 ,SPI Status Bit 515" "Low,High"
bitfld.long 0x00 2. "  SPIS514 ,SPI Status Bit 514" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS513 ,SPI Status Bit 513" "Low,High"
bitfld.long 0x00 0. "  SPIS512 ,SPI Status Bit 512" "Low,High"
else
hgroup.long 0xC0C0++0x03
hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
rgroup.long 0xC0C4++0x03
line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
bitfld.long 0x00 31. " SPIS575 ,SPI Status Bit 575" "Low,High"
bitfld.long 0x00 30. "  SPIS574 ,SPI Status Bit 574" "Low,High"
bitfld.long 0x00 29. "  SPIS573 ,SPI Status Bit 573" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS572 ,SPI Status Bit 572" "Low,High"
bitfld.long 0x00 27. "  SPIS571 ,SPI Status Bit 571" "Low,High"
bitfld.long 0x00 26. "  SPIS570 ,SPI Status Bit 570" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS569 ,SPI Status Bit 569" "Low,High"
bitfld.long 0x00 24. "  SPIS568 ,SPI Status Bit 568" "Low,High"
bitfld.long 0x00 23. "  SPIS567 ,SPI Status Bit 567" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS566 ,SPI Status Bit 566" "Low,High"
bitfld.long 0x00 21. "  SPIS565 ,SPI Status Bit 565" "Low,High"
bitfld.long 0x00 20. "  SPIS564 ,SPI Status Bit 564" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS563 ,SPI Status Bit 563" "Low,High"
bitfld.long 0x00 18. "  SPIS562 ,SPI Status Bit 562" "Low,High"
bitfld.long 0x00 17. "  SPIS561 ,SPI Status Bit 561" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS560 ,SPI Status Bit 560" "Low,High"
bitfld.long 0x00 15. "  SPIS559 ,SPI Status Bit 559" "Low,High"
bitfld.long 0x00 14. "  SPIS558 ,SPI Status Bit 558" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS557 ,SPI Status Bit 557" "Low,High"
bitfld.long 0x00 12. "  SPIS556 ,SPI Status Bit 556" "Low,High"
bitfld.long 0x00 11. "  SPIS555 ,SPI Status Bit 555" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS554 ,SPI Status Bit 554" "Low,High"
bitfld.long 0x00 9. "  SPIS553 ,SPI Status Bit 553" "Low,High"
bitfld.long 0x00 8. "  SPIS552 ,SPI Status Bit 552" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS551 ,SPI Status Bit 551" "Low,High"
bitfld.long 0x00 6. "  SPIS550 ,SPI Status Bit 550" "Low,High"
bitfld.long 0x00 5. "  SPIS549 ,SPI Status Bit 549" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS548 ,SPI Status Bit 548" "Low,High"
bitfld.long 0x00 3. "  SPIS547 ,SPI Status Bit 547" "Low,High"
bitfld.long 0x00 2. "  SPIS546 ,SPI Status Bit 546" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS545 ,SPI Status Bit 545" "Low,High"
bitfld.long 0x00 0. "  SPIS544 ,SPI Status Bit 544" "Low,High"
else
hgroup.long 0xC0C4++0x03
hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
rgroup.long 0xC0C8++0x03
line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
bitfld.long 0x00 31. " SPIS607 ,SPI Status Bit 607" "Low,High"
bitfld.long 0x00 30. "  SPIS606 ,SPI Status Bit 606" "Low,High"
bitfld.long 0x00 29. "  SPIS605 ,SPI Status Bit 605" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS604 ,SPI Status Bit 604" "Low,High"
bitfld.long 0x00 27. "  SPIS603 ,SPI Status Bit 603" "Low,High"
bitfld.long 0x00 26. "  SPIS602 ,SPI Status Bit 602" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS601 ,SPI Status Bit 601" "Low,High"
bitfld.long 0x00 24. "  SPIS600 ,SPI Status Bit 600" "Low,High"
bitfld.long 0x00 23. "  SPIS599 ,SPI Status Bit 599" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS598 ,SPI Status Bit 598" "Low,High"
bitfld.long 0x00 21. "  SPIS597 ,SPI Status Bit 597" "Low,High"
bitfld.long 0x00 20. "  SPIS596 ,SPI Status Bit 596" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS595 ,SPI Status Bit 595" "Low,High"
bitfld.long 0x00 18. "  SPIS594 ,SPI Status Bit 594" "Low,High"
bitfld.long 0x00 17. "  SPIS593 ,SPI Status Bit 593" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS592 ,SPI Status Bit 592" "Low,High"
bitfld.long 0x00 15. "  SPIS591 ,SPI Status Bit 591" "Low,High"
bitfld.long 0x00 14. "  SPIS590 ,SPI Status Bit 590" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS589 ,SPI Status Bit 589" "Low,High"
bitfld.long 0x00 12. "  SPIS588 ,SPI Status Bit 588" "Low,High"
bitfld.long 0x00 11. "  SPIS587 ,SPI Status Bit 587" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS586 ,SPI Status Bit 586" "Low,High"
bitfld.long 0x00 9. "  SPIS585 ,SPI Status Bit 585" "Low,High"
bitfld.long 0x00 8. "  SPIS584 ,SPI Status Bit 584" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS583 ,SPI Status Bit 583" "Low,High"
bitfld.long 0x00 6. "  SPIS582 ,SPI Status Bit 582" "Low,High"
bitfld.long 0x00 5. "  SPIS581 ,SPI Status Bit 581" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS580 ,SPI Status Bit 580" "Low,High"
bitfld.long 0x00 3. "  SPIS579 ,SPI Status Bit 579" "Low,High"
bitfld.long 0x00 2. "  SPIS578 ,SPI Status Bit 578" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS577 ,SPI Status Bit 577" "Low,High"
bitfld.long 0x00 0. "  SPIS576 ,SPI Status Bit 576" "Low,High"
else
hgroup.long 0xC0C8++0x03
hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
rgroup.long 0xC0CC++0x03
line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
bitfld.long 0x00 31. " SPIS639 ,SPI Status Bit 639" "Low,High"
bitfld.long 0x00 30. "  SPIS638 ,SPI Status Bit 638" "Low,High"
bitfld.long 0x00 29. "  SPIS637 ,SPI Status Bit 637" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS636 ,SPI Status Bit 636" "Low,High"
bitfld.long 0x00 27. "  SPIS635 ,SPI Status Bit 635" "Low,High"
bitfld.long 0x00 26. "  SPIS634 ,SPI Status Bit 634" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS633 ,SPI Status Bit 633" "Low,High"
bitfld.long 0x00 24. "  SPIS632 ,SPI Status Bit 632" "Low,High"
bitfld.long 0x00 23. "  SPIS631 ,SPI Status Bit 631" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS630 ,SPI Status Bit 630" "Low,High"
bitfld.long 0x00 21. "  SPIS629 ,SPI Status Bit 629" "Low,High"
bitfld.long 0x00 20. "  SPIS628 ,SPI Status Bit 628" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS627 ,SPI Status Bit 627" "Low,High"
bitfld.long 0x00 18. "  SPIS626 ,SPI Status Bit 626" "Low,High"
bitfld.long 0x00 17. "  SPIS625 ,SPI Status Bit 625" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS624 ,SPI Status Bit 624" "Low,High"
bitfld.long 0x00 15. "  SPIS623 ,SPI Status Bit 623" "Low,High"
bitfld.long 0x00 14. "  SPIS622 ,SPI Status Bit 622" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS621 ,SPI Status Bit 621" "Low,High"
bitfld.long 0x00 12. "  SPIS620 ,SPI Status Bit 620" "Low,High"
bitfld.long 0x00 11. "  SPIS619 ,SPI Status Bit 619" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS618 ,SPI Status Bit 618" "Low,High"
bitfld.long 0x00 9. "  SPIS617 ,SPI Status Bit 617" "Low,High"
bitfld.long 0x00 8. "  SPIS616 ,SPI Status Bit 616" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS615 ,SPI Status Bit 615" "Low,High"
bitfld.long 0x00 6. "  SPIS614 ,SPI Status Bit 614" "Low,High"
bitfld.long 0x00 5. "  SPIS613 ,SPI Status Bit 613" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS612 ,SPI Status Bit 612" "Low,High"
bitfld.long 0x00 3. "  SPIS611 ,SPI Status Bit 611" "Low,High"
bitfld.long 0x00 2. "  SPIS610 ,SPI Status Bit 610" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS609 ,SPI Status Bit 609" "Low,High"
bitfld.long 0x00 0. "  SPIS608 ,SPI Status Bit 608" "Low,High"
else
hgroup.long 0xC0CC++0x03
hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
rgroup.long 0xC0D0++0x03
line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
bitfld.long 0x00 31. " SPIS671 ,SPI Status Bit 671" "Low,High"
bitfld.long 0x00 30. "  SPIS670 ,SPI Status Bit 670" "Low,High"
bitfld.long 0x00 29. "  SPIS669 ,SPI Status Bit 669" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS668 ,SPI Status Bit 668" "Low,High"
bitfld.long 0x00 27. "  SPIS667 ,SPI Status Bit 667" "Low,High"
bitfld.long 0x00 26. "  SPIS666 ,SPI Status Bit 666" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS665 ,SPI Status Bit 665" "Low,High"
bitfld.long 0x00 24. "  SPIS664 ,SPI Status Bit 664" "Low,High"
bitfld.long 0x00 23. "  SPIS663 ,SPI Status Bit 663" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS662 ,SPI Status Bit 662" "Low,High"
bitfld.long 0x00 21. "  SPIS661 ,SPI Status Bit 661" "Low,High"
bitfld.long 0x00 20. "  SPIS660 ,SPI Status Bit 660" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS659 ,SPI Status Bit 659" "Low,High"
bitfld.long 0x00 18. "  SPIS658 ,SPI Status Bit 658" "Low,High"
bitfld.long 0x00 17. "  SPIS657 ,SPI Status Bit 657" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS656 ,SPI Status Bit 656" "Low,High"
bitfld.long 0x00 15. "  SPIS655 ,SPI Status Bit 655" "Low,High"
bitfld.long 0x00 14. "  SPIS654 ,SPI Status Bit 654" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS653 ,SPI Status Bit 653" "Low,High"
bitfld.long 0x00 12. "  SPIS652 ,SPI Status Bit 652" "Low,High"
bitfld.long 0x00 11. "  SPIS651 ,SPI Status Bit 651" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS650 ,SPI Status Bit 650" "Low,High"
bitfld.long 0x00 9. "  SPIS649 ,SPI Status Bit 649" "Low,High"
bitfld.long 0x00 8. "  SPIS648 ,SPI Status Bit 648" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS647 ,SPI Status Bit 647" "Low,High"
bitfld.long 0x00 6. "  SPIS646 ,SPI Status Bit 646" "Low,High"
bitfld.long 0x00 5. "  SPIS645 ,SPI Status Bit 645" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS644 ,SPI Status Bit 644" "Low,High"
bitfld.long 0x00 3. "  SPIS643 ,SPI Status Bit 643" "Low,High"
bitfld.long 0x00 2. "  SPIS642 ,SPI Status Bit 642" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS641 ,SPI Status Bit 641" "Low,High"
bitfld.long 0x00 0. "  SPIS640 ,SPI Status Bit 640" "Low,High"
else
hgroup.long 0xC0D0++0x03
hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
rgroup.long 0xC0D4++0x03
line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
bitfld.long 0x00 31. " SPIS703 ,SPI Status Bit 703" "Low,High"
bitfld.long 0x00 30. "  SPIS702 ,SPI Status Bit 702" "Low,High"
bitfld.long 0x00 29. "  SPIS701 ,SPI Status Bit 701" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS700 ,SPI Status Bit 700" "Low,High"
bitfld.long 0x00 27. "  SPIS699 ,SPI Status Bit 699" "Low,High"
bitfld.long 0x00 26. "  SPIS698 ,SPI Status Bit 698" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS697 ,SPI Status Bit 697" "Low,High"
bitfld.long 0x00 24. "  SPIS696 ,SPI Status Bit 696" "Low,High"
bitfld.long 0x00 23. "  SPIS695 ,SPI Status Bit 695" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS694 ,SPI Status Bit 694" "Low,High"
bitfld.long 0x00 21. "  SPIS693 ,SPI Status Bit 693" "Low,High"
bitfld.long 0x00 20. "  SPIS692 ,SPI Status Bit 692" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS691 ,SPI Status Bit 691" "Low,High"
bitfld.long 0x00 18. "  SPIS690 ,SPI Status Bit 690" "Low,High"
bitfld.long 0x00 17. "  SPIS689 ,SPI Status Bit 689" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS688 ,SPI Status Bit 688" "Low,High"
bitfld.long 0x00 15. "  SPIS687 ,SPI Status Bit 687" "Low,High"
bitfld.long 0x00 14. "  SPIS686 ,SPI Status Bit 686" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS685 ,SPI Status Bit 685" "Low,High"
bitfld.long 0x00 12. "  SPIS684 ,SPI Status Bit 684" "Low,High"
bitfld.long 0x00 11. "  SPIS683 ,SPI Status Bit 683" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS682 ,SPI Status Bit 682" "Low,High"
bitfld.long 0x00 9. "  SPIS681 ,SPI Status Bit 681" "Low,High"
bitfld.long 0x00 8. "  SPIS680 ,SPI Status Bit 680" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS679 ,SPI Status Bit 679" "Low,High"
bitfld.long 0x00 6. "  SPIS678 ,SPI Status Bit 678" "Low,High"
bitfld.long 0x00 5. "  SPIS677 ,SPI Status Bit 677" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS676 ,SPI Status Bit 676" "Low,High"
bitfld.long 0x00 3. "  SPIS675 ,SPI Status Bit 675" "Low,High"
bitfld.long 0x00 2. "  SPIS674 ,SPI Status Bit 674" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS673 ,SPI Status Bit 673" "Low,High"
bitfld.long 0x00 0. "  SPIS672 ,SPI Status Bit 672" "Low,High"
else
hgroup.long 0xC0D4++0x03
hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
rgroup.long 0xC0D8++0x03
line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
bitfld.long 0x00 31. " SPIS735 ,SPI Status Bit 735" "Low,High"
bitfld.long 0x00 30. "  SPIS734 ,SPI Status Bit 734" "Low,High"
bitfld.long 0x00 29. "  SPIS733 ,SPI Status Bit 733" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS732 ,SPI Status Bit 732" "Low,High"
bitfld.long 0x00 27. "  SPIS731 ,SPI Status Bit 731" "Low,High"
bitfld.long 0x00 26. "  SPIS730 ,SPI Status Bit 730" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS729 ,SPI Status Bit 729" "Low,High"
bitfld.long 0x00 24. "  SPIS728 ,SPI Status Bit 728" "Low,High"
bitfld.long 0x00 23. "  SPIS727 ,SPI Status Bit 727" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS726 ,SPI Status Bit 726" "Low,High"
bitfld.long 0x00 21. "  SPIS725 ,SPI Status Bit 725" "Low,High"
bitfld.long 0x00 20. "  SPIS724 ,SPI Status Bit 724" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS723 ,SPI Status Bit 723" "Low,High"
bitfld.long 0x00 18. "  SPIS722 ,SPI Status Bit 722" "Low,High"
bitfld.long 0x00 17. "  SPIS721 ,SPI Status Bit 721" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS720 ,SPI Status Bit 720" "Low,High"
bitfld.long 0x00 15. "  SPIS719 ,SPI Status Bit 719" "Low,High"
bitfld.long 0x00 14. "  SPIS718 ,SPI Status Bit 718" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS717 ,SPI Status Bit 717" "Low,High"
bitfld.long 0x00 12. "  SPIS716 ,SPI Status Bit 716" "Low,High"
bitfld.long 0x00 11. "  SPIS715 ,SPI Status Bit 715" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS714 ,SPI Status Bit 714" "Low,High"
bitfld.long 0x00 9. "  SPIS713 ,SPI Status Bit 713" "Low,High"
bitfld.long 0x00 8. "  SPIS712 ,SPI Status Bit 712" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS711 ,SPI Status Bit 711" "Low,High"
bitfld.long 0x00 6. "  SPIS710 ,SPI Status Bit 710" "Low,High"
bitfld.long 0x00 5. "  SPIS709 ,SPI Status Bit 709" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS708 ,SPI Status Bit 708" "Low,High"
bitfld.long 0x00 3. "  SPIS707 ,SPI Status Bit 707" "Low,High"
bitfld.long 0x00 2. "  SPIS706 ,SPI Status Bit 706" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS705 ,SPI Status Bit 705" "Low,High"
bitfld.long 0x00 0. "  SPIS704 ,SPI Status Bit 704" "Low,High"
else
hgroup.long 0xC0D8++0x03
hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
rgroup.long 0xC0DC++0x03
line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
bitfld.long 0x00 31. " SPIS767 ,SPI Status Bit 767" "Low,High"
bitfld.long 0x00 30. "  SPIS766 ,SPI Status Bit 766" "Low,High"
bitfld.long 0x00 29. "  SPIS765 ,SPI Status Bit 765" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS764 ,SPI Status Bit 764" "Low,High"
bitfld.long 0x00 27. "  SPIS763 ,SPI Status Bit 763" "Low,High"
bitfld.long 0x00 26. "  SPIS762 ,SPI Status Bit 762" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS761 ,SPI Status Bit 761" "Low,High"
bitfld.long 0x00 24. "  SPIS760 ,SPI Status Bit 760" "Low,High"
bitfld.long 0x00 23. "  SPIS759 ,SPI Status Bit 759" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS758 ,SPI Status Bit 758" "Low,High"
bitfld.long 0x00 21. "  SPIS757 ,SPI Status Bit 757" "Low,High"
bitfld.long 0x00 20. "  SPIS756 ,SPI Status Bit 756" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS755 ,SPI Status Bit 755" "Low,High"
bitfld.long 0x00 18. "  SPIS754 ,SPI Status Bit 754" "Low,High"
bitfld.long 0x00 17. "  SPIS753 ,SPI Status Bit 753" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS752 ,SPI Status Bit 752" "Low,High"
bitfld.long 0x00 15. "  SPIS751 ,SPI Status Bit 751" "Low,High"
bitfld.long 0x00 14. "  SPIS750 ,SPI Status Bit 750" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS749 ,SPI Status Bit 749" "Low,High"
bitfld.long 0x00 12. "  SPIS748 ,SPI Status Bit 748" "Low,High"
bitfld.long 0x00 11. "  SPIS747 ,SPI Status Bit 747" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS746 ,SPI Status Bit 746" "Low,High"
bitfld.long 0x00 9. "  SPIS745 ,SPI Status Bit 745" "Low,High"
bitfld.long 0x00 8. "  SPIS744 ,SPI Status Bit 744" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS743 ,SPI Status Bit 743" "Low,High"
bitfld.long 0x00 6. "  SPIS742 ,SPI Status Bit 742" "Low,High"
bitfld.long 0x00 5. "  SPIS741 ,SPI Status Bit 741" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS740 ,SPI Status Bit 740" "Low,High"
bitfld.long 0x00 3. "  SPIS739 ,SPI Status Bit 739" "Low,High"
bitfld.long 0x00 2. "  SPIS738 ,SPI Status Bit 738" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS737 ,SPI Status Bit 737" "Low,High"
bitfld.long 0x00 0. "  SPIS736 ,SPI Status Bit 736" "Low,High"
else
hgroup.long 0xC0DC++0x03
hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
rgroup.long 0xC0E0++0x03
line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
bitfld.long 0x00 31. " SPIS799 ,SPI Status Bit 799" "Low,High"
bitfld.long 0x00 30. "  SPIS798 ,SPI Status Bit 798" "Low,High"
bitfld.long 0x00 29. "  SPIS797 ,SPI Status Bit 797" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS796 ,SPI Status Bit 796" "Low,High"
bitfld.long 0x00 27. "  SPIS795 ,SPI Status Bit 795" "Low,High"
bitfld.long 0x00 26. "  SPIS794 ,SPI Status Bit 794" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS793 ,SPI Status Bit 793" "Low,High"
bitfld.long 0x00 24. "  SPIS792 ,SPI Status Bit 792" "Low,High"
bitfld.long 0x00 23. "  SPIS791 ,SPI Status Bit 791" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS790 ,SPI Status Bit 790" "Low,High"
bitfld.long 0x00 21. "  SPIS789 ,SPI Status Bit 789" "Low,High"
bitfld.long 0x00 20. "  SPIS788 ,SPI Status Bit 788" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS787 ,SPI Status Bit 787" "Low,High"
bitfld.long 0x00 18. "  SPIS786 ,SPI Status Bit 786" "Low,High"
bitfld.long 0x00 17. "  SPIS785 ,SPI Status Bit 785" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS784 ,SPI Status Bit 784" "Low,High"
bitfld.long 0x00 15. "  SPIS783 ,SPI Status Bit 783" "Low,High"
bitfld.long 0x00 14. "  SPIS782 ,SPI Status Bit 782" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS781 ,SPI Status Bit 781" "Low,High"
bitfld.long 0x00 12. "  SPIS780 ,SPI Status Bit 780" "Low,High"
bitfld.long 0x00 11. "  SPIS779 ,SPI Status Bit 779" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS778 ,SPI Status Bit 778" "Low,High"
bitfld.long 0x00 9. "  SPIS777 ,SPI Status Bit 777" "Low,High"
bitfld.long 0x00 8. "  SPIS776 ,SPI Status Bit 776" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS775 ,SPI Status Bit 775" "Low,High"
bitfld.long 0x00 6. "  SPIS774 ,SPI Status Bit 774" "Low,High"
bitfld.long 0x00 5. "  SPIS773 ,SPI Status Bit 773" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS772 ,SPI Status Bit 772" "Low,High"
bitfld.long 0x00 3. "  SPIS771 ,SPI Status Bit 771" "Low,High"
bitfld.long 0x00 2. "  SPIS770 ,SPI Status Bit 770" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS769 ,SPI Status Bit 769" "Low,High"
bitfld.long 0x00 0. "  SPIS768 ,SPI Status Bit 768" "Low,High"
else
hgroup.long 0xC0E0++0x03
hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
rgroup.long 0xC0E4++0x03
line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
bitfld.long 0x00 31. " SPIS831 ,SPI Status Bit 831" "Low,High"
bitfld.long 0x00 30. "  SPIS830 ,SPI Status Bit 830" "Low,High"
bitfld.long 0x00 29. "  SPIS829 ,SPI Status Bit 829" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS828 ,SPI Status Bit 828" "Low,High"
bitfld.long 0x00 27. "  SPIS827 ,SPI Status Bit 827" "Low,High"
bitfld.long 0x00 26. "  SPIS826 ,SPI Status Bit 826" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS825 ,SPI Status Bit 825" "Low,High"
bitfld.long 0x00 24. "  SPIS824 ,SPI Status Bit 824" "Low,High"
bitfld.long 0x00 23. "  SPIS823 ,SPI Status Bit 823" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS822 ,SPI Status Bit 822" "Low,High"
bitfld.long 0x00 21. "  SPIS821 ,SPI Status Bit 821" "Low,High"
bitfld.long 0x00 20. "  SPIS820 ,SPI Status Bit 820" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS819 ,SPI Status Bit 819" "Low,High"
bitfld.long 0x00 18. "  SPIS818 ,SPI Status Bit 818" "Low,High"
bitfld.long 0x00 17. "  SPIS817 ,SPI Status Bit 817" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS816 ,SPI Status Bit 816" "Low,High"
bitfld.long 0x00 15. "  SPIS815 ,SPI Status Bit 815" "Low,High"
bitfld.long 0x00 14. "  SPIS814 ,SPI Status Bit 814" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS813 ,SPI Status Bit 813" "Low,High"
bitfld.long 0x00 12. "  SPIS812 ,SPI Status Bit 812" "Low,High"
bitfld.long 0x00 11. "  SPIS811 ,SPI Status Bit 811" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS810 ,SPI Status Bit 810" "Low,High"
bitfld.long 0x00 9. "  SPIS809 ,SPI Status Bit 809" "Low,High"
bitfld.long 0x00 8. "  SPIS808 ,SPI Status Bit 808" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS807 ,SPI Status Bit 807" "Low,High"
bitfld.long 0x00 6. "  SPIS806 ,SPI Status Bit 806" "Low,High"
bitfld.long 0x00 5. "  SPIS805 ,SPI Status Bit 805" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS804 ,SPI Status Bit 804" "Low,High"
bitfld.long 0x00 3. "  SPIS803 ,SPI Status Bit 803" "Low,High"
bitfld.long 0x00 2. "  SPIS802 ,SPI Status Bit 802" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS801 ,SPI Status Bit 801" "Low,High"
bitfld.long 0x00 0. "  SPIS800 ,SPI Status Bit 800" "Low,High"
else
hgroup.long 0xC0E4++0x03
hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
rgroup.long 0xC0E8++0x03
line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
bitfld.long 0x00 31. " SPIS863 ,SPI Status Bit 863" "Low,High"
bitfld.long 0x00 30. "  SPIS862 ,SPI Status Bit 862" "Low,High"
bitfld.long 0x00 29. "  SPIS861 ,SPI Status Bit 861" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS860 ,SPI Status Bit 860" "Low,High"
bitfld.long 0x00 27. "  SPIS859 ,SPI Status Bit 859" "Low,High"
bitfld.long 0x00 26. "  SPIS858 ,SPI Status Bit 858" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS857 ,SPI Status Bit 857" "Low,High"
bitfld.long 0x00 24. "  SPIS856 ,SPI Status Bit 856" "Low,High"
bitfld.long 0x00 23. "  SPIS855 ,SPI Status Bit 855" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS854 ,SPI Status Bit 854" "Low,High"
bitfld.long 0x00 21. "  SPIS853 ,SPI Status Bit 853" "Low,High"
bitfld.long 0x00 20. "  SPIS852 ,SPI Status Bit 852" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS851 ,SPI Status Bit 851" "Low,High"
bitfld.long 0x00 18. "  SPIS850 ,SPI Status Bit 850" "Low,High"
bitfld.long 0x00 17. "  SPIS849 ,SPI Status Bit 849" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS848 ,SPI Status Bit 848" "Low,High"
bitfld.long 0x00 15. "  SPIS847 ,SPI Status Bit 847" "Low,High"
bitfld.long 0x00 14. "  SPIS846 ,SPI Status Bit 846" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS845 ,SPI Status Bit 845" "Low,High"
bitfld.long 0x00 12. "  SPIS844 ,SPI Status Bit 844" "Low,High"
bitfld.long 0x00 11. "  SPIS843 ,SPI Status Bit 843" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS842 ,SPI Status Bit 842" "Low,High"
bitfld.long 0x00 9. "  SPIS841 ,SPI Status Bit 841" "Low,High"
bitfld.long 0x00 8. "  SPIS840 ,SPI Status Bit 840" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS839 ,SPI Status Bit 839" "Low,High"
bitfld.long 0x00 6. "  SPIS838 ,SPI Status Bit 838" "Low,High"
bitfld.long 0x00 5. "  SPIS837 ,SPI Status Bit 837" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS836 ,SPI Status Bit 836" "Low,High"
bitfld.long 0x00 3. "  SPIS835 ,SPI Status Bit 835" "Low,High"
bitfld.long 0x00 2. "  SPIS834 ,SPI Status Bit 834" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS833 ,SPI Status Bit 833" "Low,High"
bitfld.long 0x00 0. "  SPIS832 ,SPI Status Bit 832" "Low,High"
else
hgroup.long 0xC0E8++0x03
hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
rgroup.long 0xC0EC++0x03
line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
bitfld.long 0x00 31. " SPIS895 ,SPI Status Bit 895" "Low,High"
bitfld.long 0x00 30. "  SPIS894 ,SPI Status Bit 894" "Low,High"
bitfld.long 0x00 29. "  SPIS893 ,SPI Status Bit 893" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS892 ,SPI Status Bit 892" "Low,High"
bitfld.long 0x00 27. "  SPIS891 ,SPI Status Bit 891" "Low,High"
bitfld.long 0x00 26. "  SPIS890 ,SPI Status Bit 890" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS889 ,SPI Status Bit 889" "Low,High"
bitfld.long 0x00 24. "  SPIS888 ,SPI Status Bit 888" "Low,High"
bitfld.long 0x00 23. "  SPIS887 ,SPI Status Bit 887" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS886 ,SPI Status Bit 886" "Low,High"
bitfld.long 0x00 21. "  SPIS885 ,SPI Status Bit 885" "Low,High"
bitfld.long 0x00 20. "  SPIS884 ,SPI Status Bit 884" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS883 ,SPI Status Bit 883" "Low,High"
bitfld.long 0x00 18. "  SPIS882 ,SPI Status Bit 882" "Low,High"
bitfld.long 0x00 17. "  SPIS881 ,SPI Status Bit 881" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS880 ,SPI Status Bit 880" "Low,High"
bitfld.long 0x00 15. "  SPIS879 ,SPI Status Bit 879" "Low,High"
bitfld.long 0x00 14. "  SPIS878 ,SPI Status Bit 878" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS877 ,SPI Status Bit 877" "Low,High"
bitfld.long 0x00 12. "  SPIS876 ,SPI Status Bit 876" "Low,High"
bitfld.long 0x00 11. "  SPIS875 ,SPI Status Bit 875" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS874 ,SPI Status Bit 874" "Low,High"
bitfld.long 0x00 9. "  SPIS873 ,SPI Status Bit 873" "Low,High"
bitfld.long 0x00 8. "  SPIS872 ,SPI Status Bit 872" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS871 ,SPI Status Bit 871" "Low,High"
bitfld.long 0x00 6. "  SPIS870 ,SPI Status Bit 870" "Low,High"
bitfld.long 0x00 5. "  SPIS869 ,SPI Status Bit 869" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS868 ,SPI Status Bit 868" "Low,High"
bitfld.long 0x00 3. "  SPIS867 ,SPI Status Bit 867" "Low,High"
bitfld.long 0x00 2. "  SPIS866 ,SPI Status Bit 866" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS865 ,SPI Status Bit 865" "Low,High"
bitfld.long 0x00 0. "  SPIS864 ,SPI Status Bit 864" "Low,High"
else
hgroup.long 0xC0EC++0x03
hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
rgroup.long 0xC0F0++0x03
line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
bitfld.long 0x00 31. " SPIS927 ,SPI Status Bit 927" "Low,High"
bitfld.long 0x00 30. "  SPIS926 ,SPI Status Bit 926" "Low,High"
bitfld.long 0x00 29. "  SPIS925 ,SPI Status Bit 925" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS924 ,SPI Status Bit 924" "Low,High"
bitfld.long 0x00 27. "  SPIS923 ,SPI Status Bit 923" "Low,High"
bitfld.long 0x00 26. "  SPIS922 ,SPI Status Bit 922" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS921 ,SPI Status Bit 921" "Low,High"
bitfld.long 0x00 24. "  SPIS920 ,SPI Status Bit 920" "Low,High"
bitfld.long 0x00 23. "  SPIS919 ,SPI Status Bit 919" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS918 ,SPI Status Bit 918" "Low,High"
bitfld.long 0x00 21. "  SPIS917 ,SPI Status Bit 917" "Low,High"
bitfld.long 0x00 20. "  SPIS916 ,SPI Status Bit 916" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS915 ,SPI Status Bit 915" "Low,High"
bitfld.long 0x00 18. "  SPIS914 ,SPI Status Bit 914" "Low,High"
bitfld.long 0x00 17. "  SPIS913 ,SPI Status Bit 913" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS912 ,SPI Status Bit 912" "Low,High"
bitfld.long 0x00 15. "  SPIS911 ,SPI Status Bit 911" "Low,High"
bitfld.long 0x00 14. "  SPIS910 ,SPI Status Bit 910" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS909 ,SPI Status Bit 909" "Low,High"
bitfld.long 0x00 12. "  SPIS908 ,SPI Status Bit 908" "Low,High"
bitfld.long 0x00 11. "  SPIS907 ,SPI Status Bit 907" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS906 ,SPI Status Bit 906" "Low,High"
bitfld.long 0x00 9. "  SPIS905 ,SPI Status Bit 905" "Low,High"
bitfld.long 0x00 8. "  SPIS904 ,SPI Status Bit 904" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS903 ,SPI Status Bit 903" "Low,High"
bitfld.long 0x00 6. "  SPIS902 ,SPI Status Bit 902" "Low,High"
bitfld.long 0x00 5. "  SPIS901 ,SPI Status Bit 901" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS900 ,SPI Status Bit 900" "Low,High"
bitfld.long 0x00 3. "  SPIS899 ,SPI Status Bit 899" "Low,High"
bitfld.long 0x00 2. "  SPIS898 ,SPI Status Bit 898" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS897 ,SPI Status Bit 897" "Low,High"
bitfld.long 0x00 0. "  SPIS896 ,SPI Status Bit 896" "Low,High"
else
hgroup.long 0xC0F0++0x03
hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
rgroup.long 0xC0F4++0x03
line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
bitfld.long 0x00 31. " SPIS959 ,SPI Status Bit 959" "Low,High"
bitfld.long 0x00 30. "  SPIS958 ,SPI Status Bit 958" "Low,High"
bitfld.long 0x00 29. "  SPIS957 ,SPI Status Bit 957" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS956 ,SPI Status Bit 956" "Low,High"
bitfld.long 0x00 27. "  SPIS955 ,SPI Status Bit 955" "Low,High"
bitfld.long 0x00 26. "  SPIS954 ,SPI Status Bit 954" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS953 ,SPI Status Bit 953" "Low,High"
bitfld.long 0x00 24. "  SPIS952 ,SPI Status Bit 952" "Low,High"
bitfld.long 0x00 23. "  SPIS951 ,SPI Status Bit 951" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS950 ,SPI Status Bit 950" "Low,High"
bitfld.long 0x00 21. "  SPIS949 ,SPI Status Bit 949" "Low,High"
bitfld.long 0x00 20. "  SPIS948 ,SPI Status Bit 948" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS947 ,SPI Status Bit 947" "Low,High"
bitfld.long 0x00 18. "  SPIS946 ,SPI Status Bit 946" "Low,High"
bitfld.long 0x00 17. "  SPIS945 ,SPI Status Bit 945" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS944 ,SPI Status Bit 944" "Low,High"
bitfld.long 0x00 15. "  SPIS943 ,SPI Status Bit 943" "Low,High"
bitfld.long 0x00 14. "  SPIS942 ,SPI Status Bit 942" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS941 ,SPI Status Bit 941" "Low,High"
bitfld.long 0x00 12. "  SPIS940 ,SPI Status Bit 940" "Low,High"
bitfld.long 0x00 11. "  SPIS939 ,SPI Status Bit 939" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS938 ,SPI Status Bit 938" "Low,High"
bitfld.long 0x00 9. "  SPIS937 ,SPI Status Bit 937" "Low,High"
bitfld.long 0x00 8. "  SPIS936 ,SPI Status Bit 936" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS935 ,SPI Status Bit 935" "Low,High"
bitfld.long 0x00 6. "  SPIS934 ,SPI Status Bit 934" "Low,High"
bitfld.long 0x00 5. "  SPIS933 ,SPI Status Bit 933" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS932 ,SPI Status Bit 932" "Low,High"
bitfld.long 0x00 3. "  SPIS931 ,SPI Status Bit 931" "Low,High"
bitfld.long 0x00 2. "  SPIS930 ,SPI Status Bit 930" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS929 ,SPI Status Bit 929" "Low,High"
bitfld.long 0x00 0. "  SPIS928 ,SPI Status Bit 928" "Low,High"
else
hgroup.long 0xC0F4++0x03
hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
rgroup.long 0xC0F8++0x03
line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
bitfld.long 0x00 31. " SPIS991 ,SPI Status Bit 991" "Low,High"
bitfld.long 0x00 30. "  SPIS990 ,SPI Status Bit 990" "Low,High"
bitfld.long 0x00 29. "  SPIS989 ,SPI Status Bit 989" "Low,High"
textline "                               "
bitfld.long 0x00 28. " SPIS988 ,SPI Status Bit 988" "Low,High"
bitfld.long 0x00 27. "  SPIS987 ,SPI Status Bit 987" "Low,High"
bitfld.long 0x00 26. "  SPIS986 ,SPI Status Bit 986" "Low,High"
textline "                               "
bitfld.long 0x00 25. " SPIS985 ,SPI Status Bit 985" "Low,High"
bitfld.long 0x00 24. "  SPIS984 ,SPI Status Bit 984" "Low,High"
bitfld.long 0x00 23. "  SPIS983 ,SPI Status Bit 983" "Low,High"
textline "                               "
bitfld.long 0x00 22. " SPIS982 ,SPI Status Bit 982" "Low,High"
bitfld.long 0x00 21. "  SPIS981 ,SPI Status Bit 981" "Low,High"
bitfld.long 0x00 20. "  SPIS980 ,SPI Status Bit 980" "Low,High"
textline "                               "
bitfld.long 0x00 19. " SPIS979 ,SPI Status Bit 979" "Low,High"
bitfld.long 0x00 18. "  SPIS978 ,SPI Status Bit 978" "Low,High"
bitfld.long 0x00 17. "  SPIS977 ,SPI Status Bit 977" "Low,High"
textline "                               "
bitfld.long 0x00 16. " SPIS976 ,SPI Status Bit 976" "Low,High"
bitfld.long 0x00 15. "  SPIS975 ,SPI Status Bit 975" "Low,High"
bitfld.long 0x00 14. "  SPIS974 ,SPI Status Bit 974" "Low,High"
textline "                               "
bitfld.long 0x00 13. " SPIS973 ,SPI Status Bit 973" "Low,High"
bitfld.long 0x00 12. "  SPIS972 ,SPI Status Bit 972" "Low,High"
bitfld.long 0x00 11. "  SPIS971 ,SPI Status Bit 971" "Low,High"
textline "                               "
bitfld.long 0x00 10. " SPIS970 ,SPI Status Bit 970" "Low,High"
bitfld.long 0x00 9. "  SPIS969 ,SPI Status Bit 969" "Low,High"
bitfld.long 0x00 8. "  SPIS968 ,SPI Status Bit 968" "Low,High"
textline "                               "
bitfld.long 0x00 7. " SPIS967 ,SPI Status Bit 967" "Low,High"
bitfld.long 0x00 6. "  SPIS966 ,SPI Status Bit 966" "Low,High"
bitfld.long 0x00 5. "  SPIS965 ,SPI Status Bit 965" "Low,High"
textline "                               "
bitfld.long 0x00 4. " SPIS964 ,SPI Status Bit 964" "Low,High"
bitfld.long 0x00 3. "  SPIS963 ,SPI Status Bit 963" "Low,High"
bitfld.long 0x00 2. "  SPIS962 ,SPI Status Bit 962" "Low,High"
textline "                               "
bitfld.long 0x00 1. " SPIS961 ,SPI Status Bit 961" "Low,High"
bitfld.long 0x00 0. "  SPIS960 ,SPI Status Bit 960" "Low,High"
else
hgroup.long 0xC0F8++0x03
hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
endif
tree.end
width 12.
tree "Peripheral/Component ID Registers"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " PART_0  ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. " DES_1   ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PART_1 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "  JEDEC  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Not Used,Used"
bitfld.long 0x00 0.--2. "  DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. " REVAND  ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        CMOD   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. " SIZE    ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DES_2  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GICD_CIDR0,Component ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GICD_CIDR1,Component ID1 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GICD_CIDR2,Component ID2 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GICD_CIDR3,Component ID3 Register"
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
tree.end
tree.end
width 0x0B
base (COMP.BASE("GICD",-1.)+0x20000)
width 24.
tree "Interrupt Translation Service"
group.long 0x00++0x03
line.long 0x00 "GITS_CTLR,ITS Control Register"
rbitfld.long 0x00 31. "         QUIESCENT              ,Indicates completion of all ITS operations" "Not quiescent,Quiescent"
bitfld.long 0x00 0. "                      ENABLED                ,Controls whether the ITS is enabled" "Disabled,Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "GITS_IIDR,ITS Implementer Identification Register"
bitfld.long 0x00 24.--31. "         PRODID                 ,Indicates the product ID" "GIC-500,?..."
bitfld.long 0x00 16.--19. "                            VAR                    ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.long 0x00 12.--15. " REV                    ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "                                 IMP                    ,Implementer"
if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)&&(((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
bitfld.quad 0x00 32.--35. " CIDBITS                ,Number of Collection ID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 24.--31. 1. "                                 HCC                    ,Hardware Collection Count"
textline "                                         "
bitfld.quad 0x00 19. " PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
bitfld.quad 0x00 18. "  SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
textline "                                         "
bitfld.quad 0x00 13.--17. " DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--12. "                                 ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 2. "                                 CCT                    ,Cumulative Collection Tables" "0,1"
elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
bitfld.quad 0x00 32.--35. " CIDBITS                ,Number of Collection ID bits minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 24.--31. 1. "                                 HCC                    ,Hardware Collection Count"
textline "                                         "
bitfld.quad 0x00 19. " PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
bitfld.quad 0x00 18. "  SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
textline "                                         "
bitfld.quad 0x00 13.--17. " DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--12. "                                 ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
hexmask.quad.byte 0x00 24.--31. 1. " HCC                    ,Hardware Collection Count"
bitfld.quad 0x00 19. "                                 PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
textline "                                         "
bitfld.quad 0x00 18. " SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
bitfld.quad 0x00 13.--17. "                     DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.quad 0x00 8.--12. " ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.quad 0x00 4.--7. "                                 ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                         "
bitfld.quad 0x00 2. " CCT                    ,Cumulative Collection Tables" "0,1"
else
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. " VMOVP                  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "                           CIL                    ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value"
textline "                                         "
hexmask.quad.byte 0x00 24.--31. 1. " HCC                    ,Hardware Collection Count"
bitfld.quad 0x00 19. "                                 PTA                    ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address"
textline "                                         "
bitfld.quad 0x00 18. " SEIS                   ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
bitfld.quad 0x00 13.--17. "                     DEVBITS                ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
bitfld.quad 0x00 8.--12. " ID_BITS                ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.quad 0x00 4.--7. "                                 ITT_ENTRY_SIZE         ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.quad 0x80++0x07
line.quad 0x00 "GITS_CBASER,The command queue control register"
bitfld.quad 0x00 63. " VALID                  ,Indicates whether software has allocated memory for the command queue" "Not allocated,Allocated"
bitfld.quad 0x00 59.--61. "                      INNERCACHE             ,Indicates the Inner Cacheability attributes of accesses to the command queue" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
textline "                                         "
bitfld.quad 0x00 53.--55. " OUTERCACHE             ,Indicates the Outer Cacheability attributes of accesses to the command queue" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
hexmask.quad 0x00 12.--51. 0x10 "    PHYSICAL_ADDRESS       ,Bits [51:12] of the base physical address of the command queue"
textline "                                         "
bitfld.quad 0x00 10.--11. " SHAREABILITY           ,Indicates the Shareability attributes of accesses to the command queue" "Non-shareable,Inner Shareable,Outer Shareable,?..."
hexmask.quad.byte 0x00 0.--7. 1. "                    SIZE                   ,The number of 4KB pages of physical memory allocated to the command queue minus one"
group.quad 0x88++0x7
line.quad 0x00 "GITS_CWRITER,The command queue write pointer"
hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET                 ,Bits [19:5] of the offset from GITS_CBASER"
bitfld.quad 0x00 0. "                               RETRY                  ,Restarts the processing of commands by the ITS if it stalled because of a command error" "No effect,Restarted"
group.quad 0x90++0x07
line.quad 0x00 "GITS_CREADR,The command queue read pointer"
hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET                 ,Bits [19:5] of the offset from GITS_CBASER"
bitfld.quad 0x00 0. "                               STALLED                ,Reports whether the processing of commands is stalled because of a command error" "Not stalled,Stalled"
if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0100))&0x700000000000000)==0x00)
group.quad 0x100++0x07
line.quad 0x00 "GITS_BASER0,ITS table control register"
bitfld.quad 0x00 63. " VALID                  ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
bitfld.quad 0x00 62. "                      INDIRECT               ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
textline "                                         "
bitfld.quad 0x00 59.--61. " INNERCACHE             ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
rbitfld.quad 0x00 56.--58. "    TYPE                   ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
textline "                                         "
bitfld.quad 0x00 53.--55. " OUTERCACHE             ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
rbitfld.quad 0x00 48.--52. "    ENTRY_SIZE             ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.quad 0x00 12.--47. 1. " PHYSICAL_ADDRESS       ,Physical Address"
bitfld.quad 0x00 10.--11. "                   SHAREABILITY           ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
textline "                                         "
bitfld.quad 0x00 8.--9. " PAGE_SIZE              ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
else
group.quad 0x100++0x07
line.quad 0x00 "GITS_BASER0,ITS table control register"
bitfld.quad 0x00 63. " VALID                  ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
bitfld.quad 0x00 62. "                      INDIRECT               ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
textline "                                         "
bitfld.quad 0x00 59.--61. " INNERCACHE             ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
rbitfld.quad 0x00 56.--58. "    TYPE                   ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
textline "                                         "
bitfld.quad 0x00 53.--55. " OUTERCACHE             ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
rbitfld.quad 0x00 48.--52. "    ENTRY_SIZE             ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline "                                         "
hexmask.quad 0x00 12.--47. 0x10 " PHYSICAL_ADDRESS       ,Physical Address"
bitfld.quad 0x00 10.--11. "                   SHAREABILITY           ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
textline "                                         "
bitfld.quad 0x00 8.--9. " PAGE_SIZE              ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
hexmask.quad.byte 0x00 0.--7. 1. "                               SIZE                   ,The number of pages of physical memory allocated to the table minus one"
endif
textline "                                         "
wgroup.long 0xC000++0x03
line.long 0x00 "GITS_TRKCTLR,Tracking Control Register"
bitfld.long 0x00 1. "         LPI_TRACK              ,Write 0b1 to capture information about the next interrupt that the ITS generated or failed to generate because of misprogramming" "No effect,Capture"
bitfld.long 0x00 0. "  CACHE_COUNT_RESET      ,Write 0b1 to reset the cache hit and miss counters in GITS_TRKICR and GITS_TRKLCR" "No effect,Reset"
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x1F)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 6. "         PID_OUT_OF_RANGE       ,Indicates that the LPI PID is larger than that allowed by the IDbits field in the GICR_PROPBASER" "0,1"
bitfld.long 0x00 5. "          TARGET_OUT_OF_RANGE    ,Indicates that target collection has not been successfully mapped using MAPC or that the target core does not have LPIs enabled in GICR_CTLR" "0,1"
textline "                                 "
bitfld.long 0x00 4. "         NO_TRANSLATION         ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1"
bitfld.long 0x00 3. "          INPUT_ID_OUT_OF_RANGE  ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
textline "                                 "
bitfld.long 0x00 2. "         DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
bitfld.long 0x00 1. "          DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
textline "                                 "
bitfld.long 0x00 0. "         LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0xF)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 4. "         NO_TRANSLATION         ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1"
bitfld.long 0x00 3. "          INPUT_ID_OUT_OF_RANGE  ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
textline "                                 "
bitfld.long 0x00 2. "         DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
bitfld.long 0x00 1. "          DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
textline "                                 "
bitfld.long 0x00 0. "         LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 3. "         INPUT_ID_OUT_OF_RANGE  ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1"
bitfld.long 0x00 2. "          DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
textline "                                 "
bitfld.long 0x00 1. "         DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
bitfld.long 0x00 0. "          LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x3)==0x01)
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 2. "         DEVICE_ID_UNMAPPED     ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1"
bitfld.long 0x00 1. "          DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
textline "                                 "
bitfld.long 0x00 0. "         LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
else
rgroup.long 0xC004++0x03
line.long 0x00 "GITS_TRKR,Tracking Status Register"
bitfld.long 0x00 1. "         DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1"
bitfld.long 0x00 0. "          LPI_TRACKED            ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01)
rgroup.long 0xC008++0x03
line.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register"
hexmask.long.tbyte 0x00 0.--19. 1. "         LPI_DID                ,The Device ID for the interrupt that was tracked"
else
hgroup.long 0xC008++0x03
hide.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01)
rgroup.long 0xC00C++0x03
line.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register"
hexmask.long.word 0x00 0.--15. 1. "         LPI_PID                ,The ID after translation for an interrupt that was tracked and generated an LPI successfully"
else
hgroup.long 0xC00C++0x03
hide.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01)
rgroup.long 0xC010++0x03
line.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register"
hexmask.long.word 0x00 0.--15. 1. "         LPI_ID                 ,The ID before translation of the interrupt that was tracked"
else
hgroup.long 0xC010++0x03
hide.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register"
endif
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01)
rgroup.long 0xC014++0x03
line.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register"
hexmask.long.byte 0x00 0.--6. 1. "         LPI_TARGET_CORE        ,The target core for an interrupt that was tracked and generated an LPI successfully"
else
hgroup.long 0xC014++0x03
hide.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register"
endif
rgroup.long 0xC018++0x03
line.long 0x00 "GITS_TRKICR,Debug ITE Cache Statistics"
hexmask.long.word 0x00 16.--31. 1. "         ITE_CACHE_HITS         ,Number of hits in the ITE cache"
hexmask.long.word 0x00 0.--15. 1. "       ITE_CACHE_MISSES       ,Number of misses in the ITE cache"
rgroup.long 0xC01C++0x03
line.long 0x00 "GITS_TRKLCR,Debug LPI Cache Statistics"
hexmask.long.word 0x00 16.--31. 1. "         LPI_CACHE_HITS         ,Number of hits in the LPI cache"
hexmask.long.word 0x00 0.--15. 1. "       LPI_CACHE_MISSES       ,Number of misses in the LPI cache"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GITS_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. "         PART_0                 ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GITS_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. "         DES_1                  ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "         PART_1                 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GITS_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. "         ARCHREV                ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "   JEDEC                  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High"
textline "                                 "
bitfld.long 0x00 0.--2. "         DES_1                  ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GITS_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. "         REVAND                 ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "         CMOD                   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GITS_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. "         SIZE                   ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "         DES_2                  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GITS_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GITS_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GITS_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GITS_CIDR0,Component ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GITS_CIDR1,Component ID1 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GITS_CIDR2,Component ID2 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GITS_CIDR3,Component ID3 Register"
hexmask.long.byte 0x00 0.--7. 1. "         FIXVAL                 ,ARM-defined fixed values for the preamble for component discovery"
textline "                                 "
base (COMP.BASE("GICD",-1.)+0x20000)+0x10000
if (((per.l((COMP.BASE("GICD",-1.)+0x20000)))&0x01)==0x01)
wgroup.long 0x40++0x03
line.long 0x00 "GITS_TRANSLATER,ITS Translation Register"
else
hgroup.long 0x40++0x03
hide.long 0x00 "GITS_TRANSLATER,ITS Translation Register"
endif
tree.end
width 0x0B
base COMP.BASE("GICR",-1.)
width 17.
tree "Redistributor Interface"
tree "Control Registers"
if (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x21)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 26. "       DPG1S          ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes"
bitfld.long 0x00 25. "             DPG1NS           ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes"
textline "                                  "
bitfld.long 0x00 24. " DPG0      ,Disable Processor selection for Group 0 interrupts" "No,Yes"
bitfld.long 0x00 3. "               RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
bitfld.long 0x00 0. "     ENABLE_LPIS      ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled"
elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x20)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 26. "       DPG1S          ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes"
bitfld.long 0x00 25. "             DPG1NS           ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes"
textline "                                  "
bitfld.long 0x00 24. " DPG0      ,Disable Processor selection for Group 0 interrupts" "No,Yes"
bitfld.long 0x00 3. "               RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x01)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 3. "       RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
bitfld.long 0x00 0. "     ENABLE_LPIS      ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled"
else
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 3. "       RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
endif
rgroup.long 0x0004++0x03
line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register"
bitfld.long 0x00 24.--31. "         PRODID    ,Indicates the product ID" "GIC-500,?..."
bitfld.long 0x00 16.--19. "           VAR            ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                                  "
bitfld.long 0x00 12.--15. " REV       ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "                IMP            ,Implementer"
rgroup.quad 0x0008++0x07
line.quad 0x00 "GICR_TYPER,Interrupt Controller Type Register"
hexmask.quad.byte 0x00 56.--63. 1. " AFF3      ,Affinity level 3 value for the Redistributor"
hexmask.quad.byte 0x00 48.--55. 1. "                AFF2           ,Affinity level 2 value for the Redistributor"
hexmask.quad.byte 0x00 40.--47. 1. "              AFF1             ,Affinity level 1 value for the Redistributor"
textline "                                  "
hexmask.quad.byte 0x00 32.--39. 1. " AFF0      ,Affinity level 0 value for the Redistributor"
bitfld.quad 0x00 24.--25. "                COMMONLPIAFF   ,The affinity level at which Redistributors share a LPI Configuration table" "All levels,AFF3,AFF3/AFF2,AFF3/AFF2/AFF1"
hexmask.quad.word 0x00 8.--23. 1. "  PROCESSOR_NUMBER ,A unique identifier for the PE"
textline "                                  "
bitfld.quad 0x00 5. " DPGS      ,Sets support for GICR_CTLR.DPG* bits" "Not supported,Supported"
bitfld.quad 0x00 4. "     LAST           ,Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages" "Not highest,Highest"
bitfld.quad 0x00 3. "     DIRECTLPI        ,Indicates whether this Redistributor supports direct injection of LPIs" "Not supported,Supported"
textline "                                  "
bitfld.quad 0x00 0. " PLPIS     ,Indicates whether the GIC implementation supports physical LPIs" "Not supported,Supported"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x0014))))
group.long 0x0014++0x03
line.long 0x00 "GICR_WAKER,Power Management Control Register"
bitfld.long 0x00 31. "         QUIESCENT ,This bit shows that the GIC-500 is idle and can be powered down if required" "Not quiescent,Quiescent"
bitfld.long 0x00 2. "     CHILDRENASLEEP ,Indicates the bus between the CPU interface and this Redistributor is quiescent" "Not quiescent,Quiescent"
bitfld.long 0x00 1. "   PROCESSORASLEEP  ,Indicates if this Redistributor must assert a WakeRequest if there is a pending interrupt targeted at the connected core" "No,Yes"
textline "                                  "
bitfld.long 0x00 0. " SLEEP     ,Indicates if GIC-500 ensures that all the caches are consistent with external memory and that it is safe to power off" "No,Yes"
textline "                                  "
else
hgroup.long 0x0014++0x03
hide.long 0x00 "GICR_WAKER,Power Management Control Register"
endif
group.quad 0x070++0x07
line.quad 0x00 "GICR_PROPBASER,Common LPI configuration table base register"
bitfld.quad 0x00 56.--58. " OUTERCACHE       ,Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
hexmask.quad 0x00 12.--51. 0x10 "  PHYSICAL_ADDRESS ,Bits [51:12] of the physical address containing the LPI Configuration table"
textline "                                  "
bitfld.quad 0x00 10.--11. " SHAREABILITY     ,Indicates the Shareability attributes of accesses to the LPI Configuration table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
bitfld.quad 0x00 7.--9. "                  INNERCACHE       ,Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
textline "                                  "
bitfld.quad 0x00 0.--4. " IDBITS           ,The number of bits of LPI INTID supported minus one by the LPI Configuration table starting at Physical_Address"
group.quad 0x78++0x07
line.quad 0x00 "GICR_PENDBASER,LPI pending table base register"
bitfld.quad 0x00 62. "         PTZ              ,Pending Table Zero" "Not zero,Zero" 
bitfld.quad 0x00 56.--58. "                         OUTERCACHE       ,Indicates the Outer Cacheability attributes of accesses to the LPI Pending table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
textline "                                  "
hexmask.quad 0x00 16.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:16] of the physical address containing the LPI Pending table"
bitfld.quad 0x00 10.--11. "                 SHAREABILITY     ,Indicates the Shareability attributes of accesses to the LPI Pending table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
textline "                                  "
bitfld.quad 0x00 7.--9. " INNERCACHE       ,Indicates the Inner Cacheability attributes of accesses to the LPI Pending table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
textline "                                 "
tree.end
tree "SGI and PPI Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10080))
group.long 0x10080++0x03
line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. "         GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. "         GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. "         GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. "         GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. "         GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. "         GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. "         GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. "         GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB9  ,Group Status Bit 9" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB8  ,Group Status Bit 8" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. "         GSB7  ,Group Status Bit 7" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB6  ,Group Status Bit 6" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB5  ,Group Status Bit 5" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. "         GSB4  ,Group Status Bit 4" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB3  ,Group Status Bit 3" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB2  ,Group Status Bit 2" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. "         GSB1  ,Group Status Bit 1" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB0  ,Group Status Bit 0" "Secure,Non-secure Group 1"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x000)
group.long 0x10080++0x03
line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. "         GSB31 ,Group Status Bit 31" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB30 ,Group Status Bit 30" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB29 ,Group Status Bit 29" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. "         GSB28 ,Group Status Bit 28" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB27 ,Group Status Bit 27" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB26 ,Group Status Bit 26" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. "         GSB25 ,Group Status Bit 25" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB24 ,Group Status Bit 24" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB23 ,Group Status Bit 23" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. "         GSB22 ,Group Status Bit 22" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB21 ,Group Status Bit 21" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB20 ,Group Status Bit 20" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. "         GSB19 ,Group Status Bit 19" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB18 ,Group Status Bit 18" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB17 ,Group Status Bit 17" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. "         GSB16 ,Group Status Bit 16" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB15 ,Group Status Bit 15" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB14 ,Group Status Bit 14" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. "         GSB13 ,Group Status Bit 13" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB12 ,Group Status Bit 12" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB11 ,Group Status Bit 11" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. "         GSB10 ,Group Status Bit 10" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB9  ,Group Status Bit 9" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB8  ,Group Status Bit 8" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. "         GSB7  ,Group Status Bit 7" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB6  ,Group Status Bit 6" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB5  ,Group Status Bit 5" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. "         GSB4  ,Group Status Bit 4" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB3  ,Group Status Bit 3" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB2  ,Group Status Bit 2" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. "         GSB1  ,Group Status Bit 1" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB0  ,Group Status Bit 0" "Group 0,Group 1"
else
hgroup.long 0x10080++0x03
hide.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
textline "                          "
width 24.
group.long 0x10100++0x03
line.long 0x0 "GICR_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRENB31    ,Set/Clear Enable Bit 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRENB30    ,Set/Clear Enable Bit 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRENB29    ,Set/Clear Enable Bit 29" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRENB28    ,Set/Clear Enable Bit 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRENB27    ,Set/Clear Enable Bit 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRENB26    ,Set/Clear Enable Bit 26" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRENB25    ,Set/Clear Enable Bit 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRENB24    ,Set/Clear Enable Bit 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRENB23    ,Set/Clear Enable Bit 23" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRENB22    ,Set/Clear Enable Bit 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRENB21    ,Set/Clear Enable Bit 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRENB20    ,Set/Clear Enable Bit 20" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRENB19    ,Set/Clear Enable Bit 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRENB18    ,Set/Clear Enable Bit 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRENB17    ,Set/Clear Enable Bit 17" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRENB16    ,Set/Clear Enable Bit 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRENB15    ,Set/Clear Enable Bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRENB14    ,Set/Clear Enable Bit 14" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRENB13    ,Set/Clear Enable Bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRENB12    ,Set/Clear Enable Bit 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRENB11    ,Set/Clear Enable Bit 11" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRENB10    ,Set/Clear Enable Bit 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRENB9     ,Set/Clear Enable Bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRENB8     ,Set/Clear Enable Bit 8" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRENB7     ,Set/Clear Enable Bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRENB6     ,Set/Clear Enable Bit 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRENB5     ,Set/Clear Enable Bit 5" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRENB4     ,Set/Clear Enable Bit 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRENB3     ,Set/Clear Enable Bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRENB2     ,Set/Clear Enable Bit 2" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRENB1     ,Set/Clear Enable Bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRENB0     ,Set/Clear Enable Bit 0" "Disabled,Enabled"
group.long 0x10200++0x03
line.long 0x0 "GICR_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRPEND31   ,Set/Clear Pending Bit 31" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRPEND30   ,Set/Clear Pending Bit 30" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRPEND29   ,Set/Clear Pending Bit 29" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRPEND28   ,Set/Clear Pending Bit 28" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRPEND27   ,Set/Clear Pending Bit 27" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRPEND26   ,Set/Clear Pending Bit 26" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRPEND25   ,Set/Clear Pending Bit 25" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRPEND24   ,Set/Clear Pending Bit 24" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRPEND23   ,Set/Clear Pending Bit 23" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRPEND22   ,Set/Clear Pending Bit 22" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRPEND21   ,Set/Clear Pending Bit 21" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRPEND20   ,Set/Clear Pending Bit 20" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRPEND19   ,Set/Clear Pending Bit 19" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRPEND18   ,Set/Clear Pending Bit 18" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRPEND17   ,Set/Clear Pending Bit 17" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRPEND16   ,Set/Clear Pending Bit 16" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRPEND15   ,Set/Clear Pending Bit 15" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRPEND14   ,Set/Clear Pending Bit 14" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRPEND13   ,Set/Clear Pending Bit 13" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRPEND12   ,Set/Clear Pending Bit 12" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRPEND11   ,Set/Clear Pending Bit 11" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRPEND10   ,Set/Clear Pending Bit 10" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRPEND9    ,Set/Clear Pending Bit 9" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRPEND8    ,Set/Clear Pending Bit 8" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRPEND7    ,Set/Clear Pending Bit 7" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRPEND6    ,Set/Clear Pending Bit 6" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRPEND5    ,Set/Clear Pending Bit 5" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRPEND4    ,Set/Clear Pending Bit 4" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRPEND3    ,Set/Clear Pending Bit 3" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRPEND2    ,Set/Clear Pending Bit 2" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRPEND1    ,Set/Clear Pending Bit 1" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRPEND0    ,Set/Clear Pending Bit 0" "Not pending,Pending"
group.long 0x10300++0x03
line.long 0x0 "GICR_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE9  ,Set/Clear Active Bit 9" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE8  ,Set/Clear Active Bit 8" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRACTIVE7  ,Set/Clear Active Bit 7" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE6  ,Set/Clear Active Bit 6" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE5  ,Set/Clear Active Bit 5" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRACTIVE4  ,Set/Clear Active Bit 4" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE3  ,Set/Clear Active Bit 3" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE2  ,Set/Clear Active Bit 2" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRACTIVE1  ,Set/Clear Active Bit 1" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE0  ,Set/Clear Active Bit 0" "Not active,Active"
textline "                                 "
width 18.
group.long 0x10400++0x03
line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0"
hexmask.long.byte 0x00 24.--31. 1. " INTID3    ,Interrupt ID3    Priority/Priority Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "     INTID2    ,Interrupt ID2    Priority/Priority Byte Offset 2   "
hexmask.long.byte 0x00 8.--15. 1. "     INTID1    ,Interrupt ID1    Priority/Priority Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID0    ,Interrupt ID0    Priority/Priority Byte Offset 0   "
group.long 0x10404++0x03
line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " INTID7    ,Interrupt ID7    Priority/Priority Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "     INTID6    ,Interrupt ID6    Priority/Priority Byte Offset 6   "
hexmask.long.byte 0x00 8.--15. 1. "     INTID5    ,Interrupt ID5    Priority/Priority Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID4    ,Interrupt ID4    Priority/Priority Byte Offset 4   "
group.long 0x10408++0x03
line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2"
hexmask.long.byte 0x00 24.--31. 1. " INTID11   ,Interrupt ID11   Priority/Priority Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID10   ,Interrupt ID10   Priority/Priority Byte Offset 10  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID9    ,Interrupt ID9    Priority/Priority Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID8    ,Interrupt ID8    Priority/Priority Byte Offset 8   "
group.long 0x1040C++0x03
line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3"
hexmask.long.byte 0x00 24.--31. 1. " INTID15   ,Interrupt ID15   Priority/Priority Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID14   ,Interrupt ID14   Priority/Priority Byte Offset 14  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID13   ,Interrupt ID13   Priority/Priority Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID12   ,Interrupt ID12   Priority/Priority Byte Offset 12  "
group.long 0x10410++0x03
line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4"
hexmask.long.byte 0x00 24.--31. 1. " INTID19   ,Interrupt ID19   Priority/Priority Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID18   ,Interrupt ID18   Priority/Priority Byte Offset 18  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID17   ,Interrupt ID17   Priority/Priority Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID16   ,Interrupt ID16   Priority/Priority Byte Offset 16  "
group.long 0x10414++0x03
line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5"
hexmask.long.byte 0x00 24.--31. 1. " INTID23   ,Interrupt ID23   Priority/Priority Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID22   ,Interrupt ID22   Priority/Priority Byte Offset 22  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID21   ,Interrupt ID21   Priority/Priority Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID20   ,Interrupt ID20   Priority/Priority Byte Offset 20  "
group.long 0x10418++0x03
line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6"
hexmask.long.byte 0x00 24.--31. 1. " INTID27   ,Interrupt ID27   Priority/Priority Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID26   ,Interrupt ID26   Priority/Priority Byte Offset 26  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID25   ,Interrupt ID25   Priority/Priority Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID24   ,Interrupt ID24   Priority/Priority Byte Offset 24  "
group.long 0x1041C++0x03
line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7"
hexmask.long.byte 0x00 24.--31. 1. " INTID31   ,Interrupt ID31   Priority/Priority Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID30   ,Interrupt ID30   Priority/Priority Byte Offset 30  "
hexmask.long.byte 0x00 8.--15. 1. "     INTID29   ,Interrupt ID29   Priority/Priority Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID28   ,Interrupt ID28   Priority/Priority Byte Offset 28  "
textline "                                 "
rgroup.long 0x10C00++0x03
line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15   ,Interrupt Configuration 15 (SGI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14   ,Interrupt Configuration 14 (SGI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13   ,Interrupt Configuration 13 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 25. " ICF12   ,Interrupt Configuration 12 (SGI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11   ,Interrupt Configuration 11 (SGI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10   ,Interrupt Configuration 10 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 19. " ICF9    ,Interrupt Configuration 9 (SGI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8    ,Interrupt Configuration 8 (SGI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7    ,Interrupt Configuration 7 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 13. " ICF6    ,Interrupt Configuration 6 (SGI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5    ,Interrupt Configuration 5 (SGI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4    ,Interrupt Configuration 4 (SGI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 7. " ICF3    ,Interrupt Configuration 3 (SGI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2    ,Interrupt Configuration 2 (SGI)" "Level,Edge"
group.long 0x10C04++0x03
line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15   ,Interrupt Configuration 15 (PPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14   ,Interrupt Configuration 14 (PPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13   ,Interrupt Configuration 13 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 25. " ICF12   ,Interrupt Configuration 12 (PPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11   ,Interrupt Configuration 11 (PPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10   ,Interrupt Configuration 10 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 19. " ICF9    ,Interrupt Configuration 9 (PPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8    ,Interrupt Configuration 8 (PPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7    ,Interrupt Configuration 7 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 13. " ICF6    ,Interrupt Configuration 6 (PPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5    ,Interrupt Configuration 5 (PPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4    ,Interrupt Configuration 4 (PPI)" "Level,Edge"
textline "                           "
bitfld.long 0x00 7. " ICF3    ,Interrupt Configuration 3 (PPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2    ,Interrupt Configuration 2 (PPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1    ,Interrupt Configuration 1 (PPI)" "Level,Edge"
textline "                           "
width 18.
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10D00))
group.long 0x10D00++0x03
line.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0"
bitfld.long 0x00 31. " GMB31 ,Group Modifier Bit 31" "0,1"
bitfld.long 0x00 30. "  GMB30 ,Group Modifier Bit 30" "0,1"
bitfld.long 0x00 29. "  GMB29 ,Group Modifier Bit 29" "0,1"
textline "                           "
bitfld.long 0x00 28. " GMB28 ,Group Modifier Bit 28" "0,1"
bitfld.long 0x00 27. "  GMB27 ,Group Modifier Bit 27" "0,1"
bitfld.long 0x00 26. "  GMB26 ,Group Modifier Bit 26" "0,1"
textline "                           "
bitfld.long 0x00 25. " GMB25 ,Group Modifier Bit 25" "0,1"
bitfld.long 0x00 24. "  GMB24 ,Group Modifier Bit 24" "0,1"
bitfld.long 0x00 23. "  GMB23 ,Group Modifier Bit 23" "0,1"
textline "                           "
bitfld.long 0x00 22. " GMB22 ,Group Modifier Bit 22" "0,1"
bitfld.long 0x00 21. "  GMB21 ,Group Modifier Bit 21" "0,1"
bitfld.long 0x00 20. "  GMB20 ,Group Modifier Bit 20" "0,1"
textline "                           "
bitfld.long 0x00 19. " GMB19 ,Group Modifier Bit 19" "0,1"
bitfld.long 0x00 18. "  GMB18 ,Group Modifier Bit 18" "0,1"
bitfld.long 0x00 17. "  GMB17 ,Group Modifier Bit 17" "0,1"
textline "                           "
bitfld.long 0x00 16. " GMB16 ,Group Modifier Bit 16" "0,1"
bitfld.long 0x00 15. "  GMB15 ,Group Modifier Bit 15" "0,1"
bitfld.long 0x00 14. "  GMB14 ,Group Modifier Bit 14" "0,1"
textline "                           "
bitfld.long 0x00 13. " GMB13 ,Group Modifier Bit 13" "0,1"
bitfld.long 0x00 12. "  GMB12 ,Group Modifier Bit 12" "0,1"
bitfld.long 0x00 11. "  GMB11 ,Group Modifier Bit 11" "0,1"
textline "                           "
bitfld.long 0x00 10. " GMB10 ,Group Modifier Bit 10" "0,1"
bitfld.long 0x00 9. "  GMB9  ,Group Modifier Bit 9" "0,1"
bitfld.long 0x00 8. "  GMB8  ,Group Modifier Bit 8" "0,1"
textline "                           "
bitfld.long 0x00 7. " GMB7  ,Group Modifier Bit 7" "0,1"
bitfld.long 0x00 6. "  GMB6  ,Group Modifier Bit 6" "0,1"
bitfld.long 0x00 5. "  GMB5  ,Group Modifier Bit 5" "0,1"
textline "                           "
bitfld.long 0x00 4. " GMB4  ,Group Modifier Bit 4" "0,1"
bitfld.long 0x00 3. "  GMB3  ,Group Modifier Bit 3" "0,1"
bitfld.long 0x00 2. "  GMB2  ,Group Modifier Bit 2" "0,1"
textline "                           "
bitfld.long 0x00 1. " GMB1  ,Group Modifier Bit 1" "0,1"
bitfld.long 0x00 0. "  GMB0  ,Group Modifier Bit 0" "0,1"
textline "                           "
else
hgroup.long 0x10D00++0x03
hide.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10E00))
group.long 0x10E00++0x03
line.long 0x00 "GICR_NSACR,Non-secure Access Control Register"
bitfld.long 0x00 30.--31. " NS_ACCESS15 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID15" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 28.--29. "  NS_ACCESS14 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID14" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 26.--27. "  NS_ACCESS13 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID13" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 24.--25. " NS_ACCESS12 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID12" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 22.--23. "  NS_ACCESS11 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID11" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 20.--21. "  NS_ACCESS10 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID10" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 18.--19. " NS_ACCESS9  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID9" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 16.--17. "  NS_ACCESS8  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID8" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 14.--15. "  NS_ACCESS7  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID7" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 12.--13. " NS_ACCESS6  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID6" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 10.--11. "  NS_ACCESS5  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID5" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 8.--9. "  NS_ACCESS4  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID4" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 6.--7. " NS_ACCESS3  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID3" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 4.--5. "  NS_ACCESS2  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID2" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 2.--3. "  NS_ACCESS1  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID1" "No access,G0S,G0S/G1S,?..."
textline "                           "
bitfld.long 0x00 0.--1. " NS_ACCESS0  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID0" "No access,G0S,G0S/G1S,?..."
textline "                           "
else
hgroup.long 0x10E00++0x03
hide.long 0x00 "GICR_NSACR,Non-secure Access Control Register"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
rgroup.long 0x1C000++0x03
line.long 0x00 "GICR_MISCSTATUSR,Miscellaneous Status Register"
bitfld.long 0x00 31. " CPU_AS     ,CPU active state. This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read" "Low,High"
bitfld.long 0x00 2. "  ENABLEGRP1_S ,EnableGrp1 Secure" "0,1"
bitfld.long 0x00 1. "     ENABLEGRP1_NS ,EnableGrp1 Non-secure" "0,1"
textline "                           "
bitfld.long 0x00 0. " ENABLEGRP0 ,EnableGrp0" "0,1"
rgroup.long 0x1C080++0x03
line.long 0x00 "GICR_PPISR,Private Peripheral Interrupt Status Register"
bitfld.long 0x00 31. " PPI31S     ,Actual status of the PPI31 input signal" "Low,High"
bitfld.long 0x00 30. "  PPI30S       ,Actual status of the PPI30 input signal" "Low,High"
bitfld.long 0x00 29. "  PPI29S        ,Actual status of the PPI29 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 28. " PPI28S     ,Actual status of the PPI28 input signal" "Low,High"
bitfld.long 0x00 27. "  PPI27S       ,Actual status of the PPI27 input signal" "Low,High"
bitfld.long 0x00 26. "  PPI26S        ,Actual status of the PPI26 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 25. " PPI25S     ,Actual status of the PPI25 input signal" "Low,High"
bitfld.long 0x00 24. "  PPI24S       ,Actual status of the PPI24 input signal" "Low,High"
bitfld.long 0x00 23. "  PPI23S        ,Actual status of the PPI23 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 22. " PPI22S     ,Actual status of the PPI22 input signal" "Low,High"
bitfld.long 0x00 21. "  PPI21S       ,Actual status of the PPI21 input signal" "Low,High"
bitfld.long 0x00 20. "  PPI20S        ,Actual status of the PPI20 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 19. " PPI19S     ,Actual status of the PPI19 input signal" "Low,High"
bitfld.long 0x00 18. "  PPI18S       ,Actual status of the PPI18 input signal" "Low,High"
bitfld.long 0x00 17. "  PPI17S        ,Actual status of the PPI17 input signal" "Low,High"
textline "                           "
bitfld.long 0x00 16. " PPI16S     ,Actual status of the PPI16 input signal" "Low,High"
tree.end
width 12.
tree "Peripheral/Component ID Registers"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GICR_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " PART_0  ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GICR_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. " DES_1   ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PART_1 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GICR_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "  JEDEC  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High"
bitfld.long 0x00 0.--2. "  DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GICR_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. " REVAND  ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        CMOD   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GICR_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. " SIZE    ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DES_2  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GICR_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GICR_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GICR_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GICR_CIDR0,Component ID0 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GICR_CIDR1,Component ID1 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GICR_CIDR2,Component ID2 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GICR_CIDR3,Component ID3 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
tree.end
tree.end
width 0x0B
sif COMP.AVAILABLE("GICC")
base COMP.BASE("GICC",-1.)
width 14.
tree "CPU Interface"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICC",-1.)))
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 10. " EOIMODENS     ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 9. "  EOIMODES      ,Controls the behavior of Secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 8. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 6. "          IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 4. " CBPR          ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both"
bitfld.long 0x00 3. "               FIQEN         ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ"
bitfld.long 0x00 1. "                   ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLEGRP0    ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 9. " EOIMODENS     ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 6. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 0. " ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
else
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 9. " EOIMODE       ,Controls the behavior of accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 8. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 7. "          FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 4. "          CBPR          ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both"
textline "                       "
bitfld.long 0x00 3. " FIQEN         ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ"
bitfld.long 0x00 1. "                   ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
bitfld.long 0x00 0. "              ENABLEGRP0    ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
endif
textline "                       "
group.long 0x04++0x03
line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface"
group.long 0x08++0x03
line.long 0x00 "GICC_BPR,Binary Point Register"
bitfld.long 0x00 0.--2. " BP       ,Binary point" "0,1,2,3,4,5,6,7"
hgroup.long 0x0C++0x03
hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register"
in
wgroup.long 0x10++0x03
line.long 0x00 "GICC_EOIR,End Of Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x14++0x03
line.long 0x00 "GICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt"
rgroup.long 0x18++0x03
line.long 0x00 "GICC_HPPIR,Highest Priority Pending Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
group.long 0x1C++0x03
line.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
bitfld.long 0x00 0.--2. " BP       ,Binary point" "0,1,2,3,4,5,6,7"
hgroup.long 0x20++0x03
hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register"
in
wgroup.long 0x24++0x03
line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x28++0x03
line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x2C++0x03
line.long 0x00 "GICC_STATUSR,CPU Interface Status Register"
bitfld.long 0x00 4. " ASV      ,Attempted security violation" "Not detected,Detected"
bitfld.long 0x00 3. "  WROD    ,Write to an RO location" "Not detected,Detected"
bitfld.long 0x00 2. "  RWOD ,Read of a WO location" "Not detected,Detected"
textline "                       "
bitfld.long 0x00 1. " WRD      ,Write to a reserved location" "Not detected,Detected"
bitfld.long 0x00 0. "  RRD     ,Read of a reserved location" "Not detected,Detected"
group.long 0xD0++0x03
line.long 0x00 "GICC_APR0,Active Priorities Register 0"
group.long 0xD4++0x03
line.long 0x00 "GICC_APR1,Active Priorities Register 1"
group.long 0xD8++0x03
line.long 0x00 "GICC_APR2,Active Priorities Register 2"
group.long 0xDC++0x03
line.long 0x00 "GICC_APR3,Active Priorities Register 3"
group.long 0xE0++0x03
line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register 0"
group.long 0xE4++0x03
line.long 0x00 "GICC_NSAPR1,Non-Secure Active Priorities Register 1"
group.long 0xE8++0x03
line.long 0x00 "GICC_NSAPR2,Non-Secure Active Priorities Register 2"
group.long 0xEC++0x03
line.long 0x00 "GICC_NSAPR3,Non-Secure Active Priorities Register 3"
rgroup.long 0xFC++0x03
line.long 0x00 "GICC_IIDR,CPU Interface Identification Register"
hexmask.long.word 0x00 20.--31. 1. " PRODID   ,Product ID"
bitfld.long 0x00 16.--19. "          ARCHVER ,The version of the GIC architecture that is implemented" ",,,GICv3,?..."
bitfld.long 0x00 12.--15. "         REV  ,Revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "            IMP ,Implementer"
wgroup.long 0x1000++0x03
line.long 0x00 "GICC_DIR,Deactivate Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
tree.end
width 0x0b
endif
sif COMP.AVAILABLE("GICH")
base COMP.BASE("GICH",-1.)
width 13.
tree "Virtual CPU Control Interface"
group.long 0x00++0x03
line.long 0x00 "GICH_HCR,Hypervisor Control Register"
bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 7. "             VGRP1DIE ,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "      VGRP1EIE ,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "             VGRP0DIE ,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 4. " VGRP0EIE ,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "       NPIE     ,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      LRENPIE  ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "             UIE      ,Underflow Interrupt Enable" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 0. " EN       ,Virtual CPU interface Enable" "Disabled,Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "GICH_VTR,Virtual Type Register"
bitfld.long 0x00 29.--31. " PRIBITS  ,Number of priority bits" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 26.--28. "              PREBITS  ,Number of pre-emption bits" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 23.--25. "             IDBITS   ,The number of virtual interrupt identifier bits supported" "16 bits,24 bits,?..."
textline "                      "
bitfld.long 0x00 22. " SEIS     ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "  A3V      ,Affinity 3 valid" "Invalid,Valid"
bitfld.long 0x00 0.--4. "       LISTREGS ,List regs number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
group.long 0x08++0x03
line.long 0x00 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. " VPMR     ,Virtual priority mask"
bitfld.long 0x00 21.--23. "             VBPR0    ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 0)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "             VBPR1    ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 1)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "                    VEOIM    ,Virtual EOImode. DP - Drop the priority / ID - interrupt deactivate" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
textline "                      "
bitfld.long 0x00 4. " VCBPR    ,Virtual Common Binary Point Register" "ABPR,BPR"
bitfld.long 0x00 3. "           VFIQEN   ,Virtual FIQ enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      VACKCTL  ,Virtual AckCtl" "INTID=1022,INTID=corresponding"
bitfld.long 0x00 1. "  VENG1    ,Virtual interrupt enable for group 1" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 0. " VENG0    ,Virtual interrupt enable for group 0" "Disabled,Enabled"
rgroup.long 0x10++0x03
line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register"
bitfld.long 0x00 7. " VGRP1D   ,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 6. "   VGRP1E   ,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 5. "  VGRP0D   ,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 4. "         VGRP0E   ,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
textline "                      "
bitfld.long 0x00 3. " NP       ,No Pending maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 2. "   LRENP    ,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 1. "  U        ,Underflow maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 0. "         EOI      ,End Of Interrupt maintenance interrupt assertion" "Not asserted,Asserted"
rgroup.long 0x20++0x03
line.long 0x00 "GICH_EISR0,End of Interrupt Status Register"
bitfld.long 0x00 15. " STATUS15 ,EOI maintenance interrupt status for List register 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "   STATUS14 ,EOI maintenance interrupt status for List register 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "  STATUS13 ,EOI maintenance interrupt status for List register 13" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 12. " STATUS12 ,EOI maintenance interrupt status for List register 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "   STATUS11 ,EOI maintenance interrupt status for List register 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "  STATUS10 ,EOI maintenance interrupt status for List register 10" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 9. " STATUS9  ,EOI maintenance interrupt status for List register 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "   STATUS8  ,EOI maintenance interrupt status for List register 8" "No interrupt,Interrupt"
bitfld.long 0x00 7. "  STATUS7  ,EOI maintenance interrupt status for List register 7" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 6. " STATUS6  ,EOI maintenance interrupt status for List register 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "   STATUS5  ,EOI maintenance interrupt status for List register 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "  STATUS4  ,EOI maintenance interrupt status for List register 4" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 3. " STATUS3  ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "   STATUS2  ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "  STATUS1  ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 0. " STATUS0  ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt"
rgroup.long 0x30++0x03
line.long 0x00 "GICH_ELRSR0,Empty List register Status Register"
bitfld.long 0x00 15. " STATUS15 ,Status bit for List register 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "   STATUS14 ,Status bit for List register 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "  STATUS13 ,Status bit for List register 13" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 12. " STATUS12 ,Status bit for List register 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "   STATUS11 ,Status bit for List register 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "  STATUS10 ,Status bit for List register 10" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 9. " STATUS9  ,Status bit for List register 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "   STATUS8  ,Status bit for List register 8" "No interrupt,Interrupt"
bitfld.long 0x00 7. "  STATUS7  ,Status bit for List register 7" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 6. " STATUS6  ,Status bit for List register 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "   STATUS5  ,Status bit for List register 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "  STATUS4  ,Status bit for List register 4" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 3. " STATUS3  ,Status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "   STATUS2  ,Status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "  STATUS1  ,Status bit for List register 1" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 0. " STATUS0  ,Status bit for List register 0" "No interrupt,Interrupt"
textline "                      "
group.long 0xF0++0x03
line.long 0x00 "GICH_APR0,Active Priorities Register 0"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xF4++0x03
line.long 0x00 "GICH_APR1,Active Priorities Register 1"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xF8++0x03
line.long 0x00 "GICH_APR2,Active Priorities Register 2"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xFC++0x03
line.long 0x00 "GICH_APR3,Active Priorities Register 3"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
textline "                       "
group.long 0x100++0x03
line.long 0x00 "GICH_LR0,List Register 0"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x104++0x03
line.long 0x00 "GICH_LR1,List Register 1"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x108++0x03
line.long 0x00 "GICH_LR2,List Register 2"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x10C++0x03
line.long 0x00 "GICH_LR3,List Register 3"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x110++0x03
line.long 0x00 "GICH_LR4,List Register 4"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x114++0x03
line.long 0x00 "GICH_LR5,List Register 5"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x118++0x03
line.long 0x00 "GICH_LR6,List Register 6"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x11C++0x03
line.long 0x00 "GICH_LR7,List Register 7"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x120++0x03
line.long 0x00 "GICH_LR8,List Register 8"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x124++0x03
line.long 0x00 "GICH_LR9,List Register 9"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x128++0x03
line.long 0x00 "GICH_LR10,List Register 10"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x12C++0x03
line.long 0x00 "GICH_LR11,List Register 11"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x130++0x03
line.long 0x00 "GICH_LR12,List Register 12"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x134++0x03
line.long 0x00 "GICH_LR13,List Register 13"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x138++0x03
line.long 0x00 "GICH_LR14,List Register 14"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
tree.end
width 0x0b
endif
sif COMP.AVAILABLE("GICV")
base COMP.BASE("GICV",-1.)
width 14.
tree "Virtual CPU Interface"
group.long 0x00++0x03
line.long 0x00 "GICV_CTLR,VM Control Register"
bitfld.long 0x00 9. " EOIMODE    ,Controls the behaviour of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 4. "  CBPR       ,Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts" "Group 0,Both"
bitfld.long 0x00 3. "       FIQEN ,FIQ Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      ACKCTL ,Acknowledge control. Return ID of the corresponding interrupt" "1022,Corresponding"
textline "                      "
bitfld.long 0x00 1. "  ENABLEGRP1 ,Enables the signalling of Group 1 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled"
bitfld.long 0x00 0. "              ENABLEGRP0 ,Enables the signalling of Group 0 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled"
group.long 0x04++0x03
line.long 0x00 "GICV_PMR,VM Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY   ,Priority mask level for the virtual CPU interface"
group.long 0x08++0x03
line.long 0x00 "GICV_BPR,VM Binary Point Register"
bitfld.long 0x00 0.--2. " BP         ,Binary point" "0,1,2,3,4,5,6,7"
rgroup.long 0x0C++0x03
line.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
wgroup.long 0x10++0x03
line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
rgroup.long 0x14++0x03
line.long 0x00 "GICV_RPR,VM Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY   ,Priority value of highest priority interrupt"
rgroup.long 0x18++0x03
line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
group.long 0x1C++0x03
line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register"
bitfld.long 0x00 0.--2. " BP         ,Binary point" "0,1,2,3,4,5,6,7"
rgroup.long 0x20++0x03
line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
wgroup.long 0x24++0x03
line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
rgroup.long 0x28++0x03
line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
textline ""
group.long 0xD0++0x03
line.long 0x00 "GICV_APR0,VM Active Priority Register 0"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xD4++0x03
line.long 0x00 "GICV_APR1,VM Active Priority Register 1"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xD8++0x03
line.long 0x00 "GICV_APR2,VM Active Priority Register 2"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xDC++0x03
line.long 0x00 "GICV_APR3,VM Active Priority Register 3"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
textline "                      "
rgroup.long 0xFC++0x03
line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register"
hexmask.long.word 0x00 20.--31. 1. " PRODID     ,Product ID"
bitfld.long 0x00 16.--19. "    ARCHVER ,The version of the GIC architecture that is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "  REV ,Revision number for the CPU interface" ",,,GICv3,?..."
hexmask.long.word 0x00 0.--11. 1. "  IMP ,Implementer"
wgroup.long 0x1000++0x03
line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
tree.end
width 0x0b
endif
width 0x0B
tree.end
tree.end
else
tree.close "Core Registers (Cortex-M7F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 28. " DISFPUISSOPT   ,DISFPUISSOPT" "No,Yes"
bitfld.long 0x00 27. "                   DISCRITAXIRUW  ,Disables critical AXI read-under-write" "No,Yes"
bitfld.long 0x00 26. "                  DISDYNADD      ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes"
textline "                     "
bitfld.long 0x00 21.--25. " DISISSCH1      ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
bitfld.long 0x00 16.--20. "   DISDI          ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
bitfld.long 0x00 15. "  DISCRITAXIRUR  ,Disables critical AXI read-under-read" "No,Yes"
textline "                     "
bitfld.long 0x00 14. " DISBTACALLOC   ,DISBTACALLOC" "No,Yes"
bitfld.long 0x00 13. "                   DISBTACREAD    ,DISBTACREAD" "No,Yes"
bitfld.long 0x00 12. "                  DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
textline "                     "
bitfld.long 0x00 11. " DISRAMODE      ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes"
bitfld.long 0x00 10. "                   FPEXCODIS      ,Disables FPU exception outputs" "No,Yes"
bitfld.long 0x00 2. "                  DISFOLD        ,Disables dual-issue functionality" "No,Yes"
textline ""
group.long 0x10++0x03
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x00 16. " COUNTFLAG      ,Counter Flag" "Not counted,Counted"
bitfld.long 0x00 2. "           CLKSOURCE      ,SysTick clock source" "External,Core"
bitfld.long 0x00 1. "        TICKINT        ,SysTick Handler" "No SysTick,SysTick"
textline "                     "
bitfld.long 0x00 0. " ENABLE         ,Counter Enable" "Disabled,Enabled"
group.long 0x14++0x07
line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD         ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x04 "SYST_CVR,SysTick Current Value Register"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
bitfld.long 0x00 31. " NOREF          ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "       SKEW           ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "         TENMS          ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER    ,Indicates implementer"
bitfld.long 0x00 20.--23. "                    VARIANT        ,Indicates processor revision" "Revision 0,Revision 1,?..."
bitfld.long 0x00 16.--19. "      ARCHITECTURE   ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
hexmask.long.word 0x00 4.--15. 1. " PARTNO         ,Indicates part number"
bitfld.long 0x00 0.--3. "                  REVISION       ,Indicates patch release" "Patch 0,Patch 1,Patch 2,?..."
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control and State Register"
bitfld.long 0x00 31. " NMIPENDSET     ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active"
setclrfld.long 0x00 28. 0x00 28. 0x00 27. "              PENDSVSET      ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x00 25. "     PENDSTSET      ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
textline "                     "
rbitfld.long 0x00 23. " ISRPREEMPT     ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
rbitfld.long 0x00 22. "              ISRPENDING     ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
hexmask.long.word 0x00 12.--20. 1. "     VECTPENDING    ,The exception number of the highest priority pending and enabled interrupt"
textline "                     "
rbitfld.long 0x00 11. " RETTOBASE      ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
hexmask.long.word 0x00 0.--8. 1. "               VECTACTIVE     ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF         ,Bits[31:7] of the vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT    ,Vector Key"
rbitfld.long 0x08 15. "                  ENDIANNESS     ,Indicates the memory system endianness" "Little endian,Big endian"
bitfld.long 0x08 8.--10. "   PRIGROUP       ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
textline "                     "
bitfld.long 0x08 2. " SYSRESETREQ    ,System Reset Request" "Not requested,Requested"
bitfld.long 0x08 1. "         VECTCLRACTIVE  ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
bitfld.long 0x08 0. "       VECTRESET      ,Writing 1 to this bit causes a local system reset" "No effect,Reset"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND      ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 2. "            SLEEPDEEP      ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
bitfld.long 0x0C 1. "  SLEEPONEXIT    ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration and Control Register"
bitfld.long 0x10 18. " BP             ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. "              IC             ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. "        DC             ,Cache enable bit" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 9. " STKALIGN       ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment"
bitfld.long 0x10 8. "  BFHFNMIGN      ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored"
bitfld.long 0x10 4. "         DIV_0_TRP      ,Controls the trap on divide by 0" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 3. " UNALIGN_TRP    ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
bitfld.long 0x10 1. "              USERSETMPEND   ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
bitfld.long 0x10 0. "        NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled"
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7          ,Priority of System Handler 7"
hexmask.long.byte 0x14 16.--23. 1. "                    PRI_6          ,Priority of system handler 6(UsageFault)"
hexmask.long.byte 0x14 8.--15. 1. "              PRI_5          ,Priority of system handler 5(BusFault)"
textline "                     "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4          ,Priority of system handler 4(MemManage)"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11         ,Priority of system handler 11(SVCall)"
hexmask.long.byte 0x18 16.--23. 1. "                    PRI_10         ,Priority of System Handler 10"
hexmask.long.byte 0x18 8.--15. 1. "              PRI_9          ,Priority of System Handler 9"
textline "                     "
hexmask.long.byte 0x18 0.--7. 1. " PRI_8          ,Priority of System Handler 8"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15         ,Priority of System Handler 15(SysTick)"
hexmask.long.byte 0x1C 16.--23. 1. "                    PRI_14         ,Priority of System Handler 14(PendSV)"
hexmask.long.byte 0x1C 8.--15. 1. "              PRI_13         ,Priority of System Handler 13"
textline "                     "
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12         ,Priority of System Handler 12(DebugMonitor)"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 18. " USGFAULTENA    ,UsageFault" "Disabled,Enabled"
bitfld.long 0x20 17. "              BUSFAULTENA    ,BusFault" "Disabled,Enabled"
bitfld.long 0x20 16. "        MEMFAULTENA    ,MemManage" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 15. " SVCALLPENDED   ,SVCall status" "Not pending,Pending"
bitfld.long 0x20 14. "           BUSFAULTPENDED ,BusFault status" "Not pending,Pending"
bitfld.long 0x20 13. "     MEMFAULTPENDED ,MemManage status" "Not pending,Pending"
textline "                     "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending"
bitfld.long 0x20 11. "           SYSTICKACT     ,SysTick status" "Not active,Active"
bitfld.long 0x20 10. "      PENDSVACT      ,PendSV status" "Not active,Active"
textline "                     "
bitfld.long 0x20 8. " MONITORACT     ,Monitor status" "Not active,Active"
bitfld.long 0x20 7. "            SVCALLACT      ,SVCall status" "Not active,Active"
bitfld.long 0x20 3. "      USGFAULTACT    ,UsageFault status" "Not active,Active"
textline "                     "
bitfld.long 0x20 1. " BUSFAULTACT    ,BusFault status" "Not active,Active"
bitfld.long 0x20 0. "            MEMFAULTACT    ,MemManage status" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. "       MMARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. "             MLSPERR        ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. "    MSTKERR        ,tacking Access Violations" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x00 3. " MUNSTKERR      ,Unstack Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. "          DACCVIOL       ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. "    IACCVIOL       ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. "             LSPERR         ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. "    STKERR         ,Derived bus fault(exception entry)" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 3. " UNSTKERR       ,Derived bus fault(exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. "          IMPRECISERR    ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. "    PRECISERR      ,Precise data access error" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 0. " IBUSERR        ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "USAFAULT,Usage Fault Status Register"
bitfld.word 0x00 9. "     DIVBYZERO      ,Divide by zero error" "No error,Error"
bitfld.word 0x00 8. "              UNALIGNED      ,Unaligned access error" "No error,Error"
bitfld.word 0x00 3. "        NOCP           ,A coprocessor access error" "No error,Error"
textline "                     "
bitfld.word 0x00 2. " INVPC          ,An integrity check error" "No error,Error"
bitfld.word 0x00 1. "              INVSTATE       ,Invalid Combination of EPSR and Instruction" "No error,Error"
bitfld.word 0x00 0. "        UNDEFINSTR     ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x13
line.long 0x00 "HFSR,HardFault Status Register"
eventfld.long 0x00 31. " DEBUGEVT       ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
eventfld.long 0x00 30. "          FORCED         ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
eventfld.long 0x00 1. "    VECTTBL        ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
line.long 0x04 "DFSR,Debug Fault Status Register"
eventfld.long 0x04 4. " EXTERNAL       ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred"
eventfld.long 0x04 3. "          VCATCH         ,Indicates triggering of a Vector catch" "Not occurred,Occurred"
eventfld.long 0x04 2. "    DWTTRAP        ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
textline "                     "
eventfld.long 0x04 1. " BKPT           ,Indicates a debug event generated by  BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred"
eventfld.long 0x04 0. "          HALTED         ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred"
line.long 0x08 "MMFAR,MemManage Fault Address Register"
line.long 0x0C "BFAR,BusFault Address Register"
line.long 0x10 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 22.--23. " CP11           ,Access privileges for coprocessor 11" "Denied,Privileged,,Full"
bitfld.long 0x00 20.--21. "            CP10           ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
bitfld.long 0x00 14.--15. "      CP7            ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 12.--13. " CP6            ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
bitfld.long 0x00 10.--11. "            CP5            ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
bitfld.long 0x00 8.--9. "      CP4            ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 6.--7. " CP3            ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
bitfld.long 0x00 4.--5. "            CP2            ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
bitfld.long 0x00 2.--3. "      CP1            ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 0.--1. " CP0            ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Triggered Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID          ,Indicates the interrupt to be triggered"
tree "Memory System"
width 10.
rgroup.long 0xD78++0x0B
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. " LOU       ,Level of Unification" "Level 1,level 2,?..."
bitfld.long 0x00 24.--26. "          LOC      ,Level of Coherency" "Level 1,level 2,?..."
bitfld.long 0x00 18.--20. "          CL7           ,Cache type field level 7" "No cache,?..."
textline "                   "
bitfld.long 0x00 15.--17. " CL6       ,Cache type field level 6" "No cache,?..."
bitfld.long 0x00 12.--14. "         CL5      ,Cache type field level 5" "No cache,?..."
bitfld.long 0x00 9.--11. "         CL4           ,Cache type field level 4" "No cache,?..."
textline "                   "
bitfld.long 0x00 6.--8. " CL3       ,Cache type field level 3" "No cache,?..."
bitfld.long 0x00 3.--5. "         CL2      ,Cache type field level 2" "No cache,?..."
bitfld.long 0x00 0.--2. "         CL1           ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
line.long 0x04 "CTR,Cache Type Register"
bitfld.long 0x04 29.--31. " FORMAT    ,Indicates the implemented CTR format" ",,,,ARMv7,?..."
bitfld.long 0x04 24.--27. "            CWG      ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
bitfld.long 0x04 20.--23. "                ERG           ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
textline "                   "
bitfld.long 0x04 16.--19. " DMINLINE  ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "               IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CCSIDR,Cache Size ID Register"
bitfld.long 0x08 31. " WT        ,Indicates support available for Write-Through" "Not supported,Supported"
bitfld.long 0x08 30. "    WB       ,Indicates support available for Write-Back" "Not supported,Supported"
bitfld.long 0x08 29. "    RA            ,Indicates support available for read allocation" "Not supported,Supported"
textline "                   "
bitfld.long 0x08 28. " WA        ,Indicates support available for write allocation" "Not supported,Supported"
hexmask.long.word 0x08 13.--27. 1. "    NUMSETS  ,Indicates the number of sets as (number of sets) - 1"
hexmask.long.word 0x08 3.--12. 1. "             ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
textline "                   "
bitfld.long 0x08 0.--2. " LINESIZE  ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
group.long 0xD84++0x03
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL     ,Identifies which cache level to select" "Level 1,?..."
bitfld.long 0x00 0. "          IND      ,Identifies instruction or data cache to use" "Data,Instruction"
wgroup.long 0xF50++0x03
line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification"
wgroup.long 0xF58++0x1F
line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU"
line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)"
line.long 0x08 "DCISW,Data cache invalidate by set/way"
line.long 0x0C "DCCMVAU,Data cache by address to PoU"
line.long 0x10 "DCCMVAC,Data cache clean by address to PoC"
line.long 0x14 "DCCSW,Data cache clean by set/way"
line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC"
line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way"
group.long 0xF90++0x13
line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register"
bitfld.long 0x00 3.--6. " SZ        ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
bitfld.long 0x00 2. "  RETEN    ,Retry phase enable" "Disabled,Enabled"
bitfld.long 0x00 1. "         RMW           ,Read-Modify-Write enable" "Disabled,Enabled"
textline "                   "
bitfld.long 0x00 0. " EN        ,TCM enable" "Disabled,Enabled"
line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register"
bitfld.long 0x04 3.--6. " SZ        ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
bitfld.long 0x04 2. "  RETEN    ,Retry phase enable" "Disabled,Enabled"
bitfld.long 0x04 1. "         RMW           ,Read-Modify-Write enable" "Disabled,Enabled"
textline "                   "
bitfld.long 0x04 0. " EN        ,TCM enable" "Disabled,Enabled"
line.long 0x08 "AHBPCR,AHBP control register"
bitfld.long 0x08 1.--3. " SZ        ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..."
bitfld.long 0x08 0. "    EN       ,AHBP enable" "Disabled,Enabled"
line.long 0x0C "CACR,L1 Cache Control Register"
bitfld.long 0x0C 2. " FORCEWT   ,Enables Force Write-through in the data cache" "Disabled,Enabled"
bitfld.long 0x0C 1. "         ECCDIS   ,Disables ECC in the instruction and data cache" "No,Yes"
bitfld.long 0x0C 0. "              SIWT          ,Enables limited cache coherency usage" "Disabled,Enabled"
line.long 0x10 "AHBSCR,AHB Slave Control Register"
bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x10 2.--10. 1. "               TPRI     ,Threshold execution priority for AHBS traffic demotion"
bitfld.long 0x10 0.--1. "             CTL           ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI"
group.long 0xFA8++0x03
line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register"
bitfld.long 0x00 8.--9. " AXIMTYPE  ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR"
bitfld.long 0x00 4. "           EPPB     ,Asynchronous fault on EPPB interface" "Not occurred,Occurred"
bitfld.long 0x00 3. "     AXIM          ,Asynchronous fault on AXIM interface" "Not occurred,Occurred"
textline "                   "
bitfld.long 0x00 2. " AHBP      ,Asynchronous fault on AHBP interface" "Not occurred,Occurred"
bitfld.long 0x00 1. "     DTCM     ,Asynchronous fault on DTCM interface" "Not occurred,Occurred"
bitfld.long 0x00 0. "     ITCM          ,Asynchronous fault on ITCM interface" "Not occurred,Occurred"
group.long 0xFB0++0x03
line.long 0x00 "IEBR0,Instruction Error bank Register 0"
bitfld.long 0x00 30.--31. " UD        ,User-defined" "0,1,2,3"
bitfld.long 0x00 17. "                TOE      ,Indicates the error type" "Correctable,Non-correctable"
bitfld.long 0x00 16. "  RB            ,Indicates which RAM bank to use" "Tag,Data"
textline "                   "
hexmask.long.word 0x00 2.--15. 0x4 " RL        ,Indicates the location in instruction cache RAM"
bitfld.long 0x00 1. "             LOCKED   ,Indicates whether the location is locked or not locked" "Not locked,Locked"
bitfld.long 0x00 0. "       VALID         ,Indicates whether the entry is valid or not" "Not valid,Valid"
group.long 0xFB4++0x03
line.long 0x00 "IEBR1,Instruction Error bank Register 1"
bitfld.long 0x00 30.--31. " UD        ,User-defined" "0,1,2,3"
bitfld.long 0x00 17. "                TOE      ,Indicates the error type" "Correctable,Non-correctable"
bitfld.long 0x00 16. "  RB            ,Indicates which RAM bank to use" "Tag,Data"
textline "                   "
hexmask.long.word 0x00 2.--15. 0x4 " RL        ,Indicates the location in instruction cache RAM"
bitfld.long 0x00 1. "             LOCKED   ,Indicates whether the location is locked or not locked" "Not locked,Locked"
bitfld.long 0x00 0. "       VALID         ,Indicates whether the entry is valid or not" "Not valid,Valid"
group.long 0xFB8++0x03
line.long 0x00 "DEBR0,Data Error bank Register 0"
bitfld.long 0x00 30.--31. " UD        ,User-defined" "0,1,2,3"
bitfld.long 0x00 17. "                TOE      ,Indicates the error type" "Correctable,Non-correctable"
bitfld.long 0x00 16. "  RB            ,Indicates which RAM bank to use" "Tag,Data"
textline "                   "
hexmask.long.word 0x00 2.--15. 0x4 " RL        ,Indicates the location in instruction cache RAM"
bitfld.long 0x00 1. "             LOCKED   ,Indicates whether the location is locked or not locked" "Not locked,Locked"
bitfld.long 0x00 0. "       VALID         ,Indicates whether the entry is valid or not" "Not valid,Valid"
group.long 0xFBC++0x03
line.long 0x00 "DEBR1,Data Error bank Register 1"
bitfld.long 0x00 30.--31. " UD        ,User-defined" "0,1,2,3"
bitfld.long 0x00 17. "                TOE      ,Indicates the error type" "Correctable,Non-correctable"
bitfld.long 0x00 16. "  RB            ,Indicates which RAM bank to use" "Tag,Data"
textline "                   "
hexmask.long.word 0x00 2.--15. 0x4 " RL        ,Indicates the location in instruction cache RAM"
bitfld.long 0x00 1. "             LOCKED   ,Indicates whether the location is locked or not locked" "Not locked,Locked"
bitfld.long 0x00 0. "       VALID         ,Indicates whether the entry is valid or not" "Not valid,Valid"
tree.end
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,Thumb instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "              STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " DBGMOD    ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
hgroup.long 0xD4C++0x03
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
bitfld.long 0x00 16.--19. "          TCMSUP         ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "Level 1,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "          PMSASUP        ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
hgroup.long 0xD54++0x03
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD60++0x13
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "          DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "          BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x04 20.--23. "          IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x04 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x04 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x08 24.--27. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x08 20.--23. "   MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x08 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
textline "                   "
bitfld.long 0x08 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
bitfld.long 0x08 8.--11. "          MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x08 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x0C 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x0C 20.--23. "          THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x0C 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x0C 8.--11. "          SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x0C 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
textline "                   "
bitfld.long 0x0C 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x10 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
bitfld.long 0x10 20.--23. "          SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x10 16.--19. "        BARRIER   ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x10 4.--7. "          WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
bitfld.long 0x10 0.--3. "        UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
tree.end
tree "CoreSight Identification Registers"
width 6.
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0C "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 16.--23. " IREGION    ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 8.--15. "               DREGION   ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "                    SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
textline "                        "
textline "                        "
endif
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
rgroup.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
tree "Interrupt Enable Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x100++0x7
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x100++0x0B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x100++0x0F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x100++0x13
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x100++0x17
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x100++0x1B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x100++0x1F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x100++0x1F
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
tree "Interrupt Pending Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x200++0x07
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x200++0x0B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x200++0x0F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x200++0x13
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x200++0x17
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x200++0x1B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x200++0x1F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x200++0x1F
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
tree "Interrupt Active Bit Registers"
width 9.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
rgroup.long 0x300++0x07
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
rgroup.long 0x300++0x0B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
rgroup.long 0x300++0x0F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
rgroup.long 0x300++0x13
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
rgroup.long 0x300++0x17
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
rgroup.long 0x300++0x1B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
rgroup.long 0x300++0x1F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
line.long 0x1c "ACTIVE8,Active Bit Register 8"
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 13. "  ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 7. "  ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 1. "  ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x300++0x1F
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
endif
tree.end
tree "Interrupt Priority Registers"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x400++0x3F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x400++0x5F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x400++0x7F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x400++0x9F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x400++0xBF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x400++0xDF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x400++0xEF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28 ,Interrupt 28 Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32 ,Interrupt 32 Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36 ,Interrupt 36 Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40 ,Interrupt 40 Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44 ,Interrupt 44 Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48 ,Interrupt 48 Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52 ,Interrupt 52 Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56 ,Interrupt 56 Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60 ,Interrupt 60 Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64 ,Interrupt 64 Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68 ,Interrupt 68 Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72 ,Interrupt 72 Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76 ,Interrupt 76 Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80 ,Interrupt 80 Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84 ,Interrupt 84 Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88 ,Interrupt 88 Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92 ,Interrupt 92 Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96 ,Interrupt 96 Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
line.long 0xE0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0xE0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0xE0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0xE0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0xE4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0xE4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0xE4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0xE4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0xE8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0xE8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0xE8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0xE8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xEC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xEC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xEC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xEC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
else
hgroup.long 0x400++0xEF
hide.long 0x0 "IPR0,Interrupt Priority Register"
hide.long 0x4 "IPR1,Interrupt Priority Register"
hide.long 0x8 "IPR2,Interrupt Priority Register"
hide.long 0xC "IPR3,Interrupt Priority Register"
hide.long 0x10 "IPR4,Interrupt Priority Register"
hide.long 0x14 "IPR5,Interrupt Priority Register"
hide.long 0x18 "IPR6,Interrupt Priority Register"
hide.long 0x1C "IPR7,Interrupt Priority Register"
hide.long 0x20 "IPR8,Interrupt Priority Register"
hide.long 0x24 "IPR9,Interrupt Priority Register"
hide.long 0x28 "IPR10,Interrupt Priority Register"
hide.long 0x2C "IPR11,Interrupt Priority Register"
hide.long 0x30 "IPR12,Interrupt Priority Register"
hide.long 0x34 "IPR13,Interrupt Priority Register"
hide.long 0x38 "IPR14,Interrupt Priority Register"
hide.long 0x3C "IPR15,Interrupt Priority Register"
hide.long 0x40 "IPR16,Interrupt Priority Register"
hide.long 0x44 "IPR17,Interrupt Priority Register"
hide.long 0x48 "IPR18,Interrupt Priority Register"
hide.long 0x4C "IPR19,Interrupt Priority Register"
hide.long 0x50 "IPR20,Interrupt Priority Register"
hide.long 0x54 "IPR21,Interrupt Priority Register"
hide.long 0x58 "IPR22,Interrupt Priority Register"
hide.long 0x5C "IPR23,Interrupt Priority Register"
hide.long 0x60 "IPR24,Interrupt Priority Register"
hide.long 0x64 "IPR25,Interrupt Priority Register"
hide.long 0x68 "IPR26,Interrupt Priority Register"
hide.long 0x6C "IPR27,Interrupt Priority Register"
hide.long 0x70 "IPR28,Interrupt Priority Register"
hide.long 0x74 "IPR29,Interrupt Priority Register"
hide.long 0x78 "IPR30,Interrupt Priority Register"
hide.long 0x7C "IPR31,Interrupt Priority Register"
hide.long 0x80 "IPR32,Interrupt Priority Register"
hide.long 0x84 "IPR33,Interrupt Priority Register"
hide.long 0x88 "IPR34,Interrupt Priority Register"
hide.long 0x8C "IPR35,Interrupt Priority Register"
hide.long 0x90 "IPR36,Interrupt Priority Register"
hide.long 0x94 "IPR37,Interrupt Priority Register"
hide.long 0x98 "IPR38,Interrupt Priority Register"
hide.long 0x9C "IPR39,Interrupt Priority Register"
hide.long 0xA0 "IPR40,Interrupt Priority Register"
hide.long 0xA4 "IPR41,Interrupt Priority Register"
hide.long 0xA8 "IPR42,Interrupt Priority Register"
hide.long 0xAC "IPR43,Interrupt Priority Register"
hide.long 0xB0 "IPR44,Interrupt Priority Register"
hide.long 0xB4 "IPR45,Interrupt Priority Register"
hide.long 0xB8 "IPR46,Interrupt Priority Register"
hide.long 0xBC "IPR47,Interrupt Priority Register"
hide.long 0xC0 "IPR48,Interrupt Priority Register"
hide.long 0xC4 "IPR49,Interrupt Priority Register"
hide.long 0xC8 "IPR50,Interrupt Priority Register"
hide.long 0xCC "IPR51,Interrupt Priority Register"
hide.long 0xD0 "IPR52,Interrupt Priority Register"
hide.long 0xD4 "IPR53,Interrupt Priority Register"
hide.long 0xD8 "IPR54,Interrupt Priority Register"
hide.long 0xDC "IPR55,Interrupt Priority Register"
hide.long 0xE0 "IPR56,Interrupt Priority Register"
hide.long 0xE4 "IPR57,Interrupt Priority Register"
hide.long 0xE8 "IPR58,Interrupt Priority Register"
hide.long 0xEC "IPR59,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif CORENAME()=="CORTEXM7F"
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN        ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. "                      LSPEN    ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 8. "       MONRDY  ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
newline
bitfld.long 0x00 6. " BFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. "                      MMRDY    ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
bitfld.long 0x00 4. "       HFRDY   ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
newline
bitfld.long 0x00 3. " THREAD       ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 1. "                       USER     ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. "   LSPACT  ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS      ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP          ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. "                 DN       ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. "  FZ      ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
newline
bitfld.long 0x08 22.--23. " RMODE        ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x0B
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD     ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 24.--27. "                 SRTERR   ,Indicates the hardware support for FP short vectors" "Not supported,?..."
bitfld.long 0x00 20.--23. "  SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
newline
bitfld.long 0x00 16.--19. " DIV          ,Indicates the hardware support for FP divide operations" ",Supported,?..."
bitfld.long 0x00 12.--15. "                     FPEXTRP  ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
bitfld.long 0x00 8.--11. "  DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
newline
bitfld.long 0x00 4.--7. " SNGLPREC     ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. "                     A_SIMD   ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. "                     FP_HPFP  ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
newline
bitfld.long 0x04 4.--7. " D_NAN        ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. "               FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
bitfld.long 0x08 4.--7. " VFP_MISC     ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 7.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL     ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. "  VCATCH     ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. "  DWTTRAP    ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT         ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. "  HALTED     ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR       ,Specifies the access type for the transfer" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. "          REGSEL     ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "              MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 10.
group.long 0x00++0x03
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV     ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. "     NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
bitfld.long 0x00 1. "  KEY ,Key Field" "Low,High"
bitfld.long 0x00 0. "  ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
newline
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE  ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0C "CID3,Component ID3"
tree.end
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 15.
group.long 0x00++0x1B
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP     ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 27. "             NOTRCPKT   ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 26. "  NOEXTTRIG   ,Shows whether the implementation includes external match signals" "Supported,Not supported"
newline
rbitfld.long 0x00 25. " NOCYCCNT    ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
rbitfld.long 0x00 24. "  NOPRFCNT   ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 22. "  CYCEVTENA   ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
newline
bitfld.long 0x00 21. " FOLDEVTENA  ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. "       LSUEVTENA  ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. "       SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
newline
bitfld.long 0x00 18. " EXCEVTENA   ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. "       CPIEVTENA  ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. "       EXCTRCENA   ,Enables generation of exception trace" "Disabled,Enabled"
newline
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "       SYNCTAP    ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. "     CYCTAP      ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
newline
bitfld.long 0x00 5.--8. " POSTINIT    ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "             POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "             CYCCNTENA   ,Enables CYCCNT" "Disabled,Enabled"
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
line.long 0x08 "DWT_CPICNT,CPI Count register"
hexmask.long.byte 0x08 0.--7. 1. " CPICNT      ,The base CPI counter"
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT      ,The exception overhead counter"
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT    ,Sleep Counter"
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT      ,Load-store counter"
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT     ,Folded-instruction counter"
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
newline
group.long 0x20++0x07
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
else
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x30)++0x07
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x40)++0x07
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x50)++0x07
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "     DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0  ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "       LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH  ,Data value compare" "Disabled,Enabled"
newline
textfld "                     "
bitfld.long 0x00 5. "       EMITRANGE  ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION    ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
endif
tree "IVT Table (QSPI)"
base ad:0x00
width 58.
group.long 0x00++0x03
line.long 0x00 "IVT header,Header Showing The Start Of The IVT"
hexmask.long.byte 0x00 24.--31. 1. " TAG         ,Tag"
newline
hexmask.long.word 0x00 8.--23. 1. " LEN         ,Length"
newline
hexmask.long.byte 0x00 0.--7. 1. " VER         ,Version"
group.long 0x08++0x27
line.long 0x00 "Self-Test DCD pointer,Pointer to the start of the configuration data used for BIST"
line.long 0x04 "Self-Test DCD pointer (backup),Pointer to the start of the backup configuration data used for BIST"
line.long 0x08 "DCD_pointer,Pointer to the start of DCD configuration data"
line.long 0x0C "DCD_pointer (backup),Pointer to the start of backup DCD configuration data"
line.long 0x10 "HSE_H firmware flash memory start pointer,Pointer to the start of the HSE_H firmware in flash memory"
line.long 0x14 "HSE_H firmware flash memory start pointer (backup),Pointer to the start of the backup HSE_H firmware in flash memory"
line.long 0x18 "Application_boot code flash memory start pointer,Pointer to the start of the application boot code in flash memory"
line.long 0x1C "Application_boot code flash memory start pointer (backup),Pointer to the start of the backup application boot code in flash memory"
line.long 0x20 "Boot_configuration word,Configuration data used to select the boot configuration"
bitfld.long 0x20 3. " BOOT_SEQ    ,Secure boot mode" "Non-secure,Secure"
newline
bitfld.long 0x20 2. " SWT         ,Boot target watchdog" "Disabled,Enabled"
newline
bitfld.long 0x20 0.--1. " BOOT_TARGET ,Boot target" "Cortex-M7_0,Cortex-A53_0,?..."
line.long 0x24 "Life cycle configuration word,Configuration data used for advancing life cycle"
bitfld.long 0x24 1. " IN_FIELD    ,Advances life cycle state to IN_FIELD" "Disabled,Enabled"
newline
bitfld.long 0x24 0. " OEM_PROD    ,Advances life cycle state to OEM_PROD" "Disabled,Enabled"
repeat 8. (increment 0x34 0x04) (increment 0. 1.)
group.long $1++0x03
line.long 0x00 "HSE_H firmware $2,Defined by the HSE_H firmware specification"
repeat.end
newline
repeat 4. (increment 0xF0 0x04) (increment 0. 1.)
group.long $1++0x03
line.long 0x00 "GMAC$2,Galois Message Authentication Code of first 240 bytes of IVT image structure"
repeat.end
tree "DCD Registers"
base ad:((per.l(ad:0x00+0x10))&0xFFFFFFFF)
width 26.
group.long 0x00++0x03
line.long 0x00 "DCD header,Header to signify start of DCD data"
hexmask.long.byte 0x00 24.--31. 1. " TAG      ,Tag"
hexmask.long.word 0x00 8.--23. 1. "               LEN       ,Length"
hexmask.long.byte 0x00 0.--7. 1. "           VER   ,Version"
group.byte 0x04++0x01 "DCD data"
line.byte 0x00 "Write Data Parameters,Write data command parameters"
bitfld.byte 0x00 4. "     Data Set ,Status bit showing whether bits at target were successfully overwritten" "Not overwritten,Overwritten"
bitfld.byte 0x00 3. "  Data Mask ,Enables overwriting of bits at target address" "All bits,Specific bits"
bitfld.byte 0x00 0.--2. "  Bytes ,Width of target location(s) in bytes" ",1 byte,2 bytes,,4 bytes,?..."
line.byte 0x01 "Check Data Parameters,Check data command parameters"
bitfld.byte 0x01 4. "     Data Set ,Enables bit checking at target address" "Ignored,Checked"
bitfld.byte 0x01 3. "          Data Mask ,Enables partial/complete checking of bits when the Data Set field is set to 1" "All bits,Specific bits"
bitfld.byte 0x01 0.--2. "  Bytes ,Size of target locations in bytes." ",1 byte,2 bytes,,4 bytes,?..."
base ad:(((per.l(ad:((per.l(ad:0x00+0x10))&0xFFFFFFFF))>>8)&0xFFFF)+0x04)
group.long 0x000++0x03
line.long 0x00 "GMAC,Cryptographic hash for DCD header and complete DCD data using IVTDCD key"
width 0x0B
tree.end
tree "DCD Self-Test Registers"
base ad:((per.l(ad:0x00+0x08))&0xFFFFFFFF)
width 26.
group.long 0x00++0x03
line.long 0x00 "DCD SelfTest header,Header to signify start of DCD SelfTest data"
hexmask.long.byte 0x00 24.--31. 1. " TAG      ,Tag"
hexmask.long.word 0x00 8.--23. 1. "               LEN       ,Length"
hexmask.long.byte 0x00 0.--7. 1. "           VER   ,Version"
group.byte 0x04++0x01 "DCD data"
line.byte 0x00 "Write Data Parameters,Write data command parameters"
bitfld.byte 0x00 4. "     Data Set ,Status bit showing whether bits at target were successfully overwritten" "Not overwritten,Overwritten"
bitfld.byte 0x00 3. "  Data Mask ,Enables overwriting of bits at target address" "All bits,Specific bits"
bitfld.byte 0x00 0.--2. "  Bytes ,Width of target location(s) in bytes" ",1 byte,2 bytes,,4 bytes,?..."
line.byte 0x01 "Check Data Parameters,Check data command parameters"
bitfld.byte 0x01 4. "     Data Set ,Enables bit checking at target address" "Ignored,Checked"
bitfld.byte 0x01 3. "          Data Mask ,Enables partial/complete checking of bits when the Data Set field is set to 1" "All bits,Specific bits"
bitfld.byte 0x01 0.--2. "  Bytes ,Size of target locations in bytes." ",1 byte,2 bytes,,4 bytes,?..."
base ad:(((per.l(ad:((per.l(ad:0x00)+0x08)&0xFFFFFFFF))>>8)&0xFFFF)+0x04)
group.long 0x00++0x03
line.long 0x00 "GMAC,Cryptographic hash for DCD header and complete DCD data using IVTDCD key"
width 0x0B
tree.end
tree "BOOT Registers"
base ad:((per.l(ad:0x00+0x20))&0xFFFFFFFF)
width 24.
if (((per.l(ad:0x00+0x28)&0x08)==0))
group.long 0x00++0x0F "Application boot"
line.long 0x00 "Image header,Marks start of application image"
hexmask.long.byte 0x00 24.--31. 1. " TAG                    ,Tag"
newline
hexmask.long.byte 0x00 0.--7. 1. " Version                ,Version"
line.long 0x04 "RAM start pointer,Pointer to the first RAM address to which BootROM must load application boot code"
line.long 0x08 "RAM entry pointer,Pointer to out of RESET start of boot target core. For Cortex-M7 it corresponds to VTOR. For A53 it corresponds to start of code execution"
line.long 0x0C "Code length word,Length of code section of the image"
group.long 0x40++0x03
line.long 0x00 "Code,Code can be any size up to the maximum size of system SRAM"
sif cpuis("Cortex-M7")
group.long 0x00++0x0B "Serial boot"
line.long 0x00 "Image header,Marks start of serial boot code image"
hexmask.long.byte 0x00 24.--31. 1. " TAG                    ,Tag"
hexmask.long.byte 0x00 0.--7. 1. "        Version                 ,Version"
line.long 0x04 "RAM start pointer,Pointer to the first RAM address to which BootROM must load serial boot code"
line.long 0x08 "RAM entry pointer,Pointer to out of RESET start of boot target core. For Cortex-M7 it corresponds to VTOR"
group.long 0x40++0x03
line.long 0x00 "Code,Code can be any size up to the maximum size of system SRAM"
endif
else
sif cpuis("CortexM7")
group.long 0x00++0x17 "Serial boot"
line.long 0x00 "Image header,Marks start of serial boot code image"
hexmask.long.byte 0x00 24.--31. 1. " TAG                    ,Tag"
hexmask.long.byte 0x00 0.--7. 1. "        Version                 ,Version"
line.long 0x04 "RAM start pointer,Pointer to the first RAM address to which BootROM must load serial boot code"
line.long 0x08 "RAM entry pointer,Pointer to out of RESET start of boot target core. For Cortex-M7 it corresponds to VTOR"
line.long 0x0C "Code length word,Length of code section of the image."
line.long 0x10 "Auth mode,Authentication mode"
line.long 0x14 "NSKPUB Key Selector,NSK public key selector"
group.long 0x40++0x03
line.long 0x00 "Code,Code can be any size up to the maximum size of system SRAM."
repeat 64. (increment 0x1040 0x04)(increment 0. 1.)
group.long $1++0x03
line.long 0x00 "CSKPUB$2,Customer Public key for RSA authentication $2"
repeat.end
repeat 64. (increment 0x1140 0x04) (increment 0. 1.)
group.long $1++0x03
line.long 0x00 "CSK Signature $2,RSA signature for CSKPUB authentication $2"
repeat.end
group.long 0x1240++0x03
line.long 0x00 "Code,Code can be any size up to the maximum size of SRAM"
base ad:per.l(ad:((per.l(ad:0x00+0x20))&0xFFFFFFFF)+0x0C)
repeat 64. (increment 0x1240 0x04) (increment 0. 1.)
group.long ($1+0x0C)++0x03
line.long 0x00 "Public key Signature $2,Public key signature for image authentication $2"
repeat.end
endif
endif
width 0x0B
tree.end
width 0x0B
tree.end
autoindent.on center tree
tree "A53_GPR"
base ad:0x440D0000
group.long 0x00++0x03
line.long 0x00 "GPR00,GPR00"
bitfld.long 0x00 24.--26. "CA53_COUNTER_CLK_DIV_VAL,Cortex-A53 System Counter Clock Divide Value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18. "CA53_0_CORE0_VINITHI,VINITHI Of Cortex-A53 Core 0 Cluster 0" "0,1"
newline
bitfld.long 0x00 12. "CA53_0_CORE0_CFGTE,CFGTE Of Cortex-A53 Core 0 Cluster 0" "0,1"
bitfld.long 0x00 10. "CA53_0_CORE0_CFGEND,CFGEND Of Cortex-A53 Core 0 Cluster 0" "0,1"
newline
bitfld.long 0x00 6. "CA53_0_BROADCASTOUTER,BROADCASTOUTER Of Cortex-A53 Cluster 0" "0,1"
bitfld.long 0x00 5. "CA53_0_BROADCASTINNER,BROADCASTINNER Of Cortex-A53 Cluster 0" "0,1"
newline
bitfld.long 0x00 4. "CA53_0_BROADCASTCACHEMAINT,BROADCASTCACHEMAINT Of Cortex-A53 Cluster 0" "0,1"
bitfld.long 0x00 0. "CA53_0_CORE0_AA64nAA32,AA64nAA32 Of Cortex-A53 Core 0 Cluster 0" "0,1"
group.long 0x04++0x03
line.long 0x00 "GPR01,GPR01"
bitfld.long 0x00 24. "CA53_0_CORE0_CP15SDISABLE,CP15SDISABLE Of Cortex-A53 Core 0 Cluster 0" "0,1"
bitfld.long 0x00 8. "CLUSTER0_CG_EN,Cortex-A53 Cluster 0 Clock Gating Enable" "0: CLUSTER0_CG_EN_0,1: CLUSTER0_CG_EN_1"
newline
bitfld.long 0x00 0. "WFE_EVT_CA53_CLUSTER0,WFE Event For Cortex-A53 Cluster 0" "0,1"
group.long 0x1C++0x03
line.long 0x00 "GPR07,GPR07"
hexmask.long.byte 0x00 8.--15. 1. "CA53_0_CLUSTERIDAFF2,Cluster ID Affinity Level 2 For Cortex-A53 Cluster 0"
hexmask.long.byte 0x00 0.--7. 1. "CA53_0_CLUSTERIDAFF1,Cluster ID Affinity Level 1 For Cortex-A53 Cluster 0"
rgroup.long 0x20++0x03
line.long 0x00 "GPR08,GPR08"
bitfld.long 0x00 24. "CA53_0_CORE0_STANDBYWFI_STATUS,STANDBYWFI Status Of Cortex-A53 Core 0 Cluster 0" "0: CA53_0_CORE0_STANDBYWFI_STATUS_0,1: CA53_0_CORE0_STANDBYWFI_STATUS_1"
bitfld.long 0x00 16. "CA53_0_CORE0_STANDBYWFE_STATUS,STANDBYWFE Status Of Cortex-A53 Core 0 Cluster 0" "0: CA53_0_CORE0_STANDBYWFE_STATUS_0,1: CA53_0_CORE0_STANDBYWFE_STATUS_1"
newline
bitfld.long 0x00 8. "CLUSTER0_STANDBYWFIL2_STATUS,STANDBYWFIL2 Status Of Cortex-A53 Cluster 0" "0: CLUSTER0_STANDBYWFIL2_STATUS_0,1: CLUSTER0_STANDBYWFIL2_STATUS_1"
bitfld.long 0x00 0. "CA53_0_CORE0_WARM_RESET_STATUS,Warm Reset Status Of Cortex-A53 Core 0 Cluster 0" "0: CA53_0_CORE0_WARM_RESET_STATUS_0,1: CA53_0_CORE0_WARM_RESET_STATUS_1"
group.long 0x24++0x03
line.long 0x00 "GPR09,GPR09"
hexmask.long.byte 0x00 0.--7. 1. "CA53_0_CORE0_RVBARADDR_39_32,Cortex-A53 Core 0 Reset Vector Base Address"
tree.end
tree "ADC (SAR_ADC)"
base ad:0x402CC000
group.long 0x00++0x03
line.long 0x00 "MCR,Main Configuration"
bitfld.long 0x00 31. "OWREN,Overwrite enable" "0: Older valid conversion data is not..,1: Newer conversion result is always overwritten.."
bitfld.long 0x00 30. "WLSIDE,Selects whether conversion data is left or right aligned" "0: Write right-aligned conversion data (from 11..,1: Write left-aligned conversion data (from 15.."
newline
bitfld.long 0x00 29. "MODE,Normal scan mode select" "0: One-Shot Operation mode,1: Scan Operation mode"
bitfld.long 0x00 27. "TRGEN,External trigger enable" "0: External trigger is disabled,1: Enables the external trigger to start a.."
newline
bitfld.long 0x00 26. "EDGE,Trigger edge select" "0: Falling edge is trigger,1: Rising edge is trigger"
bitfld.long 0x00 24. "NSTART,Normal conversion start" "0,1"
newline
bitfld.long 0x00 22. "JTRGEN,Injection external trigger enable" "0: Injected conversion not started by external..,1: Injected conversion started by external trigger"
bitfld.long 0x00 21. "JEDGE,Injection trigger edge selection" "0: Falling edge is trigger,1: Rising edge is trigger"
newline
bitfld.long 0x00 20. "JSTART,Start injection conversion" "0,1"
bitfld.long 0x00 17. "CTUEN,Cross trigger unit enable" "0: The CTU is disabled and the triggered..,1: The CTU is enabled and the triggered injected.."
newline
bitfld.long 0x00 16. "CTU_MODE,Cross trigger unit mode" "0: CTU control mode is selected,1: CTU trigger mode is selected"
bitfld.long 0x00 15. "STCL,Self-testing configuration lock" "0: Self-test registers are not locked,1: The self-test configuration is locked (STCR1.."
newline
bitfld.long 0x00 14. "CALSTART,Calibration start" "0: No effect (default return value),1: CALSTART_START_CAL"
bitfld.long 0x00 13. "AVGEN,Average enable" "0: AVGEN_DISABLE,1: Enable (default)"
newline
bitfld.long 0x00 11.--12. "NRSMPL,Number of averaging samples" "0: NMRSMPL_SAMPLES_16,1: NMRSMPL_SAMPLES_32,2: NMRSMPL_SAMPLES_128,3: NMRSMPL_SAMPLES_512"
bitfld.long 0x00 9.--10. "TSAMP,Sample period of calibration conversions" "0: 22 cycles of AD_CLK (default),1: TSAMP_PERIOD_8_CYC,2: TSAMP_PERIOD_16_CYC,3: TSAMP_PERIOD_32_CYC"
newline
bitfld.long 0x00 8. "ADCLKSE,Analog clock frequency select" "0: AD_CLK frequency is half,1: AD_CLK frequency is equal to bus clock.."
bitfld.long 0x00 7. "ABORTCHAIN,Abort conversion chain" "0: Chain conversion has been aborted or chain..,1: Abort current chain conversion"
newline
bitfld.long 0x00 6. "ABORT,Abort conversion" "0,1"
bitfld.long 0x00 5. "ACKO,Auto-Clock-Off mode enable" "0: Auto-Clock-Off feature is disabled,1: Auto-Clock-Off feature is enabled"
newline
bitfld.long 0x00 0. "PWDN,Power-down enable" "0: When ADC status is in Power-down mode..,1: Request to enter Power-down mode"
group.long 0x04++0x03
line.long 0x00 "MSR,Main Status"
rbitfld.long 0x00 31. "CALIBRTD,Calibration status" "0: Uncalibrated or calibration unsuccessful,1: Calibrated or calibration successful"
eventfld.long 0x00 30. "CALFAIL,Calibration failed" "0: Calibration passed (must be checked with..,1: Calibration failed"
newline
rbitfld.long 0x00 29. "CALBUSY,Calibration busy" "0: ADC is ready for use,1: ADC is busy in a calibration process"
rbitfld.long 0x00 24. "NSTART,Normal conversion status" "0: Normal conversion is not in process,1: Normal conversion is in process"
newline
rbitfld.long 0x00 23. "JABORT,Injected conversion abort status" "0: Injected conversion has not been aborted,1: Injected conversion has been aborted"
rbitfld.long 0x00 20. "JSTART,Injected conversion status" "0: Injected conversion is not in process,1: Injected conversion is in process"
newline
rbitfld.long 0x00 18. "SELF_TEST_S,SELF_TEST_S signals that a self-test conversion is in process" "0: Self-test conversion is not in process,1: Self-test conversion is in process"
rbitfld.long 0x00 16. "CTUSTART,CTUSTART is used to show that a CTU conversion is in process" "0,1"
newline
hexmask.long.byte 0x00 9.--15. 1. "CHADDR,Channel address"
rbitfld.long 0x00 5. "ACKO,Auto-Clock-Off enable" "0: Auto-Clock-Off feature is not enabled,1: Auto-Clock-Off feature is enabled"
newline
rbitfld.long 0x00 0.--2. "ADCSTATUS,ADC status" "0,1,2,3,4,5,6,7"
group.long 0x10++0x03
line.long 0x00 "ISR,Interrupt Status"
eventfld.long 0x00 4. "EOCTU,End of CTU conversion" "0: CTU end of conversion has not occurred,1: CTU end of conversion has occurred"
eventfld.long 0x00 3. "JEOC,Injected channel end of conversion" "0: Injected channel end of conversion has not..,1: Injected channel end of conversion has occurred"
newline
eventfld.long 0x00 2. "JECH,Injected end of conversion chain" "0: Injected channel end of conversion chain has..,1: Injected channel end of conversion chain has.."
eventfld.long 0x00 1. "EOC,End of channel conversion" "0: Channel end of conversion has not occurred,1: Channel end of conversion has occurred"
newline
eventfld.long 0x00 0. "ECH,End of conversion chain" "0: End of conversion chain has not occurred,1: End of conversion chain has occurred"
group.long 0x14++0x03
line.long 0x00 "CEOCFR0,Channel Pending 0"
eventfld.long 0x00 7. "EOC_CH7,Channel 7 conversion complete" "0: Conversion not complete,1: Conversion complete"
eventfld.long 0x00 6. "EOC_CH6,Channel 6 conversion complete" "0: Conversion not complete,1: Conversion complete"
newline
eventfld.long 0x00 5. "EOC_CH5,Channel 5 conversion complete" "0: Conversion not complete,1: Conversion complete"
eventfld.long 0x00 4. "EOC_CH4,Channel 4 conversion complete" "0: Conversion not complete,1: Conversion complete"
newline
eventfld.long 0x00 3. "EOC_CH3,Channel 3 conversion complete" "0: Conversion not complete,1: Conversion complete"
eventfld.long 0x00 2. "EOC_CH2,Channel 2 conversion complete" "0: Conversion not complete,1: Conversion complete"
newline
eventfld.long 0x00 1. "EOC_CH1,Channel 1 conversion complete" "0: Conversion not complete,1: Conversion complete"
eventfld.long 0x00 0. "EOC_CH0,EOC_CH0" "0: Conversion not complete,1: Conversion complete"
group.long 0x18++0x03
line.long 0x00 "CEOCFR1,Channel Pending 1"
eventfld.long 0x00 7. "EOC_CH39,Channel 39 conversion complete" "0: Conversion not complete,1: Conversion complete"
eventfld.long 0x00 6. "EOC_CH38,Channel 38 conversion complete" "0: Conversion not complete,1: Conversion complete"
newline
eventfld.long 0x00 5. "EOC_CH37,Channel 37 conversion complete" "0: Conversion not complete,1: Conversion complete"
eventfld.long 0x00 4. "EOC_CH36,Channel 36 conversion complete" "0: Conversion not complete,1: Conversion complete"
newline
eventfld.long 0x00 3. "EOC_CH35,Channel 35 conversion complete" "0: Conversion not complete,1: Conversion complete"
eventfld.long 0x00 2. "EOC_CH34,Channel 34 conversion complete" "0: Conversion not complete,1: Conversion complete"
newline
eventfld.long 0x00 1. "EOC_CH33,Channel 33 conversion complete" "0: Conversion not complete,1: Conversion complete"
eventfld.long 0x00 0. "EOC_CH32,Channel 32 conversion complete" "0: Conversion not complete,1: Conversion complete"
group.long 0x20++0x03
line.long 0x00 "IMR,Interrupt Mask"
bitfld.long 0x00 4. "MSKEOCTU,End of CTU conversion interrupt mask" "0: EOCTU interrupt disabled,1: EOCTU interrupt enabled"
bitfld.long 0x00 3. "MSKJEOC,End of injected conversion interrupt mask" "0: End of injected conversion interrupt disabled,1: End of injected conversion interrupt enabled"
newline
bitfld.long 0x00 2. "MSKJECH,End of injected chain conversion interrupt mask" "0: End of injected chain conversion interrupt..,1: End of injected chain conversion interrupt.."
bitfld.long 0x00 1. "MSKEOC,End of conversion interrupt mask" "0: End of conversion interrupt disabled,1: End of conversion interrupt enabled"
newline
bitfld.long 0x00 0. "MSKECH,End of chain conversion interrupt mask" "0: End of chain conversion interrupt disabled,1: End of chain conversion interrupt enabled"
group.long 0x24++0x03
line.long 0x00 "CIMR0,Channel Interrupt Mask 0"
bitfld.long 0x00 7. "CIM7,Channel 7 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
bitfld.long 0x00 6. "CIM6,Channel 6 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 5. "CIM5,Channel 5 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
bitfld.long 0x00 4. "CIM4,Channel 4 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 3. "CIM3,Channel 3 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
bitfld.long 0x00 2. "CIM2,Channel 2 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 1. "CIM1,Channel 1 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
bitfld.long 0x00 0. "CIM0,Channel 0 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
group.long 0x28++0x03
line.long 0x00 "CIMR1,Channel Interrupt Mask 1"
bitfld.long 0x00 7. "CIM39,Channel 39 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
bitfld.long 0x00 6. "CIM38,Channel 38 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 5. "CIM37,Channel 37 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
bitfld.long 0x00 4. "CIM36,Channel 36 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 3. "CIM35,Channel 35 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
bitfld.long 0x00 2. "CIM34,Channel 34 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 1. "CIM33,Channel 33 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
bitfld.long 0x00 0. "CIM32,Channel 32 interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
group.long 0x30++0x03
line.long 0x00 "WTISR,Watchdog Threshold Interrupt Status"
eventfld.long 0x00 15. "WDG7H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt not asserted,1: Interrupt asserted"
eventfld.long 0x00 14. "WDG7L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold" "0: Interrupt not asserted,1: Interrupt asserted"
newline
eventfld.long 0x00 13. "WDG6H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt not asserted,1: Interrupt asserted"
eventfld.long 0x00 12. "WDG6L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold" "0,1"
newline
eventfld.long 0x00 11. "WDG5H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt not asserted,1: Interrupt asserted"
eventfld.long 0x00 10. "WDG5L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold" "0: Interrupt not asserted,1: Interrupt asserted"
newline
eventfld.long 0x00 9. "WDG4H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt not asserted,1: Interrupt asserted"
eventfld.long 0x00 8. "WDG4L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold" "0,1"
newline
eventfld.long 0x00 7. "WDG3H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt not asserted,1: Interrupt asserted"
eventfld.long 0x00 6. "WDG3L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold" "0: Interrupt not asserted,1: Interrupt asserted"
newline
eventfld.long 0x00 5. "WDG2H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt not asserted,1: Interrupt asserted"
eventfld.long 0x00 4. "WDG2L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold" "0: Interrupt not asserted,1: Interrupt asserted"
newline
eventfld.long 0x00 3. "WDG1H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt not asserted,1: Interrupt asserted"
eventfld.long 0x00 2. "WDG1L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold" "0,1"
newline
eventfld.long 0x00 1. "WDG0H,This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt not asserted,1: Interrupt asserted"
eventfld.long 0x00 0. "WDG0L,This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold" "0: Interrupt not asserted,1: Interrupt asserted"
group.long 0x34++0x03
line.long 0x00 "WTIMR,Watchdog Threshold Interrupt Mask"
bitfld.long 0x00 15. "MSKWDG7H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 14. "MSKWDG7L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
bitfld.long 0x00 13. "MSKWDG6H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 12. "MSKWDG6L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
bitfld.long 0x00 11. "MSKWDG5H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 10. "MSKWDG5L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
bitfld.long 0x00 9. "MSKWDG4H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 8. "MSKWDG4L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
bitfld.long 0x00 7. "MSKWDG3H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 6. "MSKWDG3L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
bitfld.long 0x00 5. "MSKWDG2H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 4. "MSKWDG2L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
bitfld.long 0x00 3. "MSKWDG1H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 2. "MSKWDG1L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
newline
bitfld.long 0x00 1. "MSKWDG0H,This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
bitfld.long 0x00 0. "MSKWDG0L,This corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold" "0: Interrupt is disabled,1: Interrupt is enabled"
group.long 0x40++0x03
line.long 0x00 "DMAE,DMAE"
bitfld.long 0x00 1. "DCLR,DMA clear sequence enable" "0: DMA request cleared by acknowledge from DMA..,1: DMA request cleared on read of data registers"
bitfld.long 0x00 0. "DMAEN,DMA global enable" "0: DMA feature is disabled,1: DMA feature is enabled"
group.long 0x44++0x03
line.long 0x00 "DMAR0,DMA 0"
bitfld.long 0x00 7. "DMA7,Channel 7 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
bitfld.long 0x00 6. "DMA6,Channel 6 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
newline
bitfld.long 0x00 5. "DMA5,Channel 5 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
bitfld.long 0x00 4. "DMA4,Channel 4 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
newline
bitfld.long 0x00 3. "DMA3,Channel 3 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
bitfld.long 0x00 2. "DMA2,Channel 2 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
newline
bitfld.long 0x00 1. "DMA1,Channel 1 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
bitfld.long 0x00 0. "DMA0,Channel 0 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
group.long 0x48++0x03
line.long 0x00 "DMAR1,DMA 1"
bitfld.long 0x00 7. "DMA39,Channel 39 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
bitfld.long 0x00 6. "DMA38,Channel 38 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
newline
bitfld.long 0x00 5. "DMA37,Channel 37 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
bitfld.long 0x00 4. "DMA36,Channel 36 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
newline
bitfld.long 0x00 3. "DMA35,Channel 35 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
bitfld.long 0x00 2. "DMA34,Channel 34 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
newline
bitfld.long 0x00 1. "DMA33,Channel 33 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
bitfld.long 0x00 0. "DMA32,Channel 32 DMA enable" "0: Transfer of data in DMA mode is disabled,1: Transfer of data in DMA mode is enabled"
group.long 0x60++0x03
line.long 0x00 "THRHLR0,Analog Watchdog Threshold 0"
hexmask.long.word 0x00 16.--27. 1. "THRH,THRH"
hexmask.long.word 0x00 0.--11. 1. "THRL,Low threshold value for channel n"
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
group.long ($2+0x64)++0x03
line.long 0x00 "THRHLR$1,Analog Watchdog Threshold $1"
hexmask.long.word 0x00 16.--27. 1. "THRH,High threshold value for channel n"
hexmask.long.word 0x00 0.--11. 1. "THRL,Low threshold value for channel n"
repeat.end
group.long 0x80++0x03
line.long 0x00 "PSCR,Presampling Control"
bitfld.long 0x00 3.--4. "PREVAL1,Internal presampling voltage selection" "0,1,2,3"
bitfld.long 0x00 1.--2. "PREVAL0,Internal presampling voltage selection" "0,1,2,3"
newline
bitfld.long 0x00 0. "PRECONV,Convert presampled value If PRECONV is set presampling is followed by the conversion" "0,1"
group.long 0x84++0x03
line.long 0x00 "PSR0,Presampling 0"
bitfld.long 0x00 7. "PRES7,Presampling enable for channel 7" "0,1"
bitfld.long 0x00 6. "PRES6,Presampling enable for channel 6" "0,1"
newline
bitfld.long 0x00 5. "PRES5,Presampling enable for channel 5" "0,1"
bitfld.long 0x00 4. "PRES4,Presampling enable for channel 4" "0,1"
newline
bitfld.long 0x00 3. "PRES3,Presampling enable for channel 3" "0,1"
bitfld.long 0x00 2. "PRES2,Presampling enable for channel 2" "0,1"
newline
bitfld.long 0x00 1. "PRES1,Presampling enable for channel 1" "0,1"
bitfld.long 0x00 0. "PRES0,Presampling enable for channel 0" "0: Presampling is disabled,1: Presampling is enabled"
group.long 0x88++0x03
line.long 0x00 "PSR1,Presampling 1"
bitfld.long 0x00 7. "PRES39,Presampling enable for channel 39" "0,1"
bitfld.long 0x00 6. "PRES38,Presampling enable for channel 38" "0,1"
newline
bitfld.long 0x00 5. "PRES37,Presampling enable for channel 37" "0,1"
bitfld.long 0x00 4. "PRES36,Presampling enable for channel 36" "0,1"
newline
bitfld.long 0x00 3. "PRES35,Presampling enable for channel 35" "0,1"
bitfld.long 0x00 2. "PRES34,Presampling enable for channel 34" "0,1"
newline
bitfld.long 0x00 1. "PRES33,Presampling enable for channel 33" "0,1"
bitfld.long 0x00 0. "PRES32,Presampling enable for channel 32" "0: Presampling is disabled,1: Presampling is enabled"
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
group.long ($2+0x94)++0x03
line.long 0x00 "CTR$1,Conversion Timing $1"
hexmask.long.byte 0x00 0.--7. 1. "INPSAMP,Sampling phase duration"
repeat.end
group.long 0xA4++0x03
line.long 0x00 "NCMR0,Normal Conversion Mask 0"
bitfld.long 0x00 7. "CH7,Normal sampling enable for channel 7" "0,1"
bitfld.long 0x00 6. "CH6,Normal sampling enable for channel 6" "0,1"
newline
bitfld.long 0x00 5. "CH5,Normal sampling enable for channel 5" "0,1"
bitfld.long 0x00 4. "CH4,Normal sampling enable for channel 4" "0,1"
newline
bitfld.long 0x00 3. "CH3,Normal sampling enable for channel 3" "0,1"
bitfld.long 0x00 2. "CH2,Normal sampling enable for channel 2" "0,1"
newline
bitfld.long 0x00 1. "CH1,Normal sampling enable for channel 1" "0,1"
bitfld.long 0x00 0. "CH0,Normal sampling enable for channel 0" "0: Normal sampling is disabled,1: Normal sampling is enabled"
group.long 0xA8++0x03
line.long 0x00 "NCMR1,Normal Conversion Mask 1"
bitfld.long 0x00 7. "CH39,Normal sampling enable for channel 39" "0,1"
bitfld.long 0x00 6. "CH38,Normal sampling enable for channel 38" "0,1"
newline
bitfld.long 0x00 5. "CH37,Normal sampling enable for channel 37" "0,1"
bitfld.long 0x00 4. "CH36,Normal sampling enable for channel 36" "0,1"
newline
bitfld.long 0x00 3. "CH35,Normal sampling enable for channel 35" "0,1"
bitfld.long 0x00 2. "CH34,Normal sampling enable for channel 34" "0,1"
newline
bitfld.long 0x00 1. "CH33,Normal sampling enable for channel 33" "0,1"
bitfld.long 0x00 0. "CH32,Normal sampling enable for channel 32" "0: Normal sampling is disabled,1: Normal sampling is enabled"
group.long 0xB4++0x03
line.long 0x00 "JCMR0,Injected Conversion Mask 0"
bitfld.long 0x00 7. "CH7,Injected sampling enable for channel 7" "0,1"
bitfld.long 0x00 6. "CH6,Injected sampling enable for channel 6" "0,1"
newline
bitfld.long 0x00 5. "CH5,Injected sampling enable for channel 5" "0,1"
bitfld.long 0x00 4. "CH4,Injected sampling enable for channel 4" "0,1"
newline
bitfld.long 0x00 3. "CH3,Injected sampling enable for channel 3" "0,1"
bitfld.long 0x00 2. "CH2,Injected sampling enable for channel 2" "0,1"
newline
bitfld.long 0x00 1. "CH1,Injected sampling enable for channel 1" "0,1"
bitfld.long 0x00 0. "CH0,Injected sampling enable for channel 0" "0: Injected sampling is disabled,1: Injected sampling is enabled"
group.long 0xB8++0x03
line.long 0x00 "JCMR1,Injected Conversion Mask 1"
bitfld.long 0x00 7. "CH39,Injected sampling enable for channel 39" "0,1"
bitfld.long 0x00 6. "CH38,Injected sampling enable for channel 38" "0,1"
newline
bitfld.long 0x00 5. "CH37,Injected sampling enable for channel 37" "0,1"
bitfld.long 0x00 4. "CH36,Injected sampling enable for channel 36" "0,1"
newline
bitfld.long 0x00 3. "CH35,Injected sampling enable for channel 35" "0,1"
bitfld.long 0x00 2. "CH34,Injected sampling enable for channel 34" "0,1"
newline
bitfld.long 0x00 1. "CH33,Injected sampling enable for channel 33" "0,1"
bitfld.long 0x00 0. "CH32,Injected sampling enable for channel 32" "0: Injected sampling is disabled,1: Injected sampling is enabled"
group.long 0xC0++0x03
line.long 0x00 "USROFSGN,User OFFSET and Gain"
hexmask.long.word 0x00 16.--25. 1. "GAINUSER,User-defined gain value"
hexmask.long.byte 0x00 0.--7. 1. "OFFSUSER,User defined offset"
group.long 0xC8++0x03
line.long 0x00 "PDEDR,Power Down Exit Delay"
hexmask.long.byte 0x00 0.--7. 1. "PDED,The delay between the power-down bit reset and the start of conversion"
repeat 8. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x100)++0x03
line.long 0x00 "PCDR[$1],Precision Channel n Data $1"
bitfld.long 0x00 19. "VALID,Conversion data valid" "0,1"
bitfld.long 0x00 18. "OVERW,Data over" "0,1"
newline
bitfld.long 0x00 16.--17. "RESULT,This field reflects the mode of conversion for the corresponding channel" "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?..."
hexmask.long.word 0x00 0.--11. 1. "CDATA,Channel converted data"
repeat.end
repeat 8. (strings "32" "33" "34" "35" "36" "37" "38" "39" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x180)++0x03
line.long 0x00 "ICDR$1,Internal Channel n Data"
bitfld.long 0x00 19. "VALID,Conversion data valid" "0,1"
bitfld.long 0x00 18. "OVERW,Data over" "0,1"
newline
bitfld.long 0x00 16.--17. "RESULT,This field reflects the mode of conversion for the corresponding channel" "0: Data is a result of Normal conversion mode,1: Data is a result of Injected conversion mode,2: Data is a result of CTU conversion mode,?..."
hexmask.long.word 0x00 0.--11. 1. "CDATA,Channel converted data"
repeat.end
repeat 4. (strings "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x280)++0x03
line.long 0x00 "THRHLR$1,Analog Watchdog Threshold $1"
hexmask.long.word 0x00 16.--27. 1. "THRH,High threshold value for channel n"
hexmask.long.word 0x00 0.--11. 1. "THRL,Low threshold value for channel n"
repeat.end
group.long 0x2B0++0x03
line.long 0x00 "CWSELR0,Channel Watchdog Select 0"
bitfld.long 0x00 28.--30. "WSEL_CH7,Channel Watchdog select for channel 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "WSEL_CH6,Channel Watchdog select for channel 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. "WSEL_CH5,Channel Watchdog select for channel 5" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "WSEL_CH4,Channel Watchdog select for channel 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "WSEL_CH3,Channel Watchdog select for channel 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "WSEL_CH2,Channel Watchdog select for channel 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "WSEL_CH1,Channel Watchdog select for channel 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "WSEL_CH0,Channel Watchdog select for channel 0" "0,1,2,3,4,5,6,7"
group.long 0x2C0++0x03
line.long 0x00 "CWSELR4,Channel Watchdog Select 4"
bitfld.long 0x00 28.--30. "WSEL_CH39,Channel Watchdog select for channel 39" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "WSEL_CH38,Channel Watchdog select for channel 38" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. "WSEL_CH37,Channel Watchdog select for channel 37" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "WSEL_CH36,Channel Watchdog select for channel 36" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "WSEL_CH35,Channel Watchdog select for channel 35" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "WSEL_CH34,Channel Watchdog select for channel 34" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "WSEL_CH33,Channel Watchdog select for channel 33" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "WSEL_CH32,Channel Watchdog select for channel 32" "0,1,2,3,4,5,6,7"
group.long 0x2E0++0x03
line.long 0x00 "CWENR0,Channel Watchdog Enable 0"
bitfld.long 0x00 7. "CWEN7,Watchdog enable for channel 7" "0,1"
bitfld.long 0x00 6. "CWEN6,Watchdog enable for channel 6" "0,1"
newline
bitfld.long 0x00 5. "CWEN5,Watchdog enable for channel 5" "0,1"
bitfld.long 0x00 4. "CWEN4,Watchdog enable for channel 4" "0,1"
newline
bitfld.long 0x00 3. "CWEN3,Watchdog enable for channel 3" "0,1"
bitfld.long 0x00 2. "CWEN2,Watchdog enable for channel 2" "0,1"
newline
bitfld.long 0x00 1. "CWEN1,Watchdog enable for channel 1" "0,1"
bitfld.long 0x00 0. "CWEN0,Watchdog enable for channel 0" "0: CWENR0_CWEN0_DISABLED,1: CWENR0_CWEN0_ENABLED"
group.long 0x2E4++0x03
line.long 0x00 "CWENR1,Channel Watchdog Enable 1"
bitfld.long 0x00 7. "CWEN39,Watchdog enable for channel 39" "0,1"
bitfld.long 0x00 6. "CWEN38,Watchdog enable for channel 38" "0,1"
newline
bitfld.long 0x00 5. "CWEN37,Watchdog enable for channel 37" "0,1"
bitfld.long 0x00 4. "CWEN36,Watchdog enable for channel 36" "0,1"
newline
bitfld.long 0x00 3. "CWEN35,Watchdog enable for channel 35" "0,1"
bitfld.long 0x00 2. "CWEN34,Watchdog enable for channel 34" "0,1"
newline
bitfld.long 0x00 1. "CWEN33,Watchdog enable for channel 33" "0,1"
bitfld.long 0x00 0. "CWEN32,Watchdog enable for channel 32" "0: CWENR1_CWEN32_DISABLED,1: CWENR1_CWEN32_ENABLED"
group.long 0x2F0++0x03
line.long 0x00 "AWORR0,Analog Watchdog Out of Range 0"
eventfld.long 0x00 7. "AWOR_CH7,Indicates channel 7 converted data is out of range" "0,1"
eventfld.long 0x00 6. "AWOR_CH6,Indicates channel 6 converted data is out of range" "0,1"
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eventfld.long 0x00 5. "AWOR_CH5,Indicates channel 5 converted data is out of range" "0,1"
eventfld.long 0x00 4. "AWOR_CH4,Indicates channel 4 converted data is out of range" "0,1"
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eventfld.long 0x00 3. "AWOR_CH3,Indicates channel 3 converted data is out of range" "0,1"
eventfld.long 0x00 2. "AWOR_CH2,Indicates channel 2 converted data is out of range" "0,1"
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eventfld.long 0x00 1. "AWOR_CH1,Indicates channel 1 converted data is out of range" "0,1"
eventfld.long 0x00 0. "AWOR_CH0,Indicates channel 0 converted data is out of range" "0: Converted data is in range,1: Converted data is out of range"
group.long 0x2F4++0x03
line.long 0x00 "AWORR1,Analog Watchdog Out of Range 1"
eventfld.long 0x00 7. "AWOR_CH39,Indicates channel 39 converted data is out of range" "0,1"
eventfld.long 0x00 6. "AWOR_CH38,Indicates channel 38 converted data is out of range" "0,1"
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eventfld.long 0x00 5. "AWOR_CH37,Indicates channel 37 converted data is out of range" "0,1"
eventfld.long 0x00 4. "AWOR_CH36,Indicates channel 36 converted data is out of range" "0,1"
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eventfld.long 0x00 3. "AWOR_CH35,Indicates channel 35 converted data is out of range" "0,1"
eventfld.long 0x00 2. "AWOR_CH34,Indicates channel 34 converted data is out of range" "0,1"
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eventfld.long 0x00 1. "AWOR_CH33,Indicates channel 33 converted data is out of range" "0,1"
eventfld.long 0x00 0. "AWOR_CH32,Indicates channel 32 converted data is out of range" "0: Converted data is in range,1: Converted data is out of range"
group.long 0x340++0x03
line.long 0x00 "STCR1,Self-Test Configuration 1"
hexmask.long.byte 0x00 24.--31. 1. "INPSAMP_C,Sampling phase duration for the test conversions related to Algorithm C"
hexmask.long.byte 0x00 8.--15. 1. "INPSAMP_S,Sampling phase duration for the test conversions related to Algorithm S"
group.long 0x344++0x03
line.long 0x00 "STCR2,Self-Test Configuration 2"
bitfld.long 0x00 27. "MSKWDSERR,Watchdog sequence error interrupt mask" "0: STCR2_MSKWDSERR_DISABLED,1: STCR2_MSKWDSERR_ENABLED"
bitfld.long 0x00 26. "SERR,Error fault injection field (write-only)" "0,1"
newline
bitfld.long 0x00 25. "MSKWDTERR,Watchdog timer error interrupt mask" "0: STCR2_MSKWDTERR_DISABLED,1: STCR2_MSKWDTERR_ENABLED"
bitfld.long 0x00 23. "MSKST_EOC,Self-Test EOC interrupt mask" "0: STCR2_MSKST_EOC_DISABLED,1: STCR2_MSKST_EOC_ENABLED"
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bitfld.long 0x00 18. "MSKWDG_EOA_C,End of algorithm C interrupt mask" "0: STCR2_MSKWDG_EOAC_DISABLED,1: STCR2_MSKWDG_EOAC_ENABLED"
bitfld.long 0x00 16. "MSKWDG_EOA_S,End of algorithm S interrupt mask" "0: STCR2_MSKWDG_EOAS_DISABLED,1: STCR2_MSKWDG_EOAS_ENABLED"
newline
bitfld.long 0x00 15. "MSKERR_C,Error on algorithm C channel interrupt mask" "0: STCR2_MSKERRC_DISABLED,1: STCR2_MSKERRC_ENABLED"
bitfld.long 0x00 13. "MSKERR_S2,Error on algorithm S2 channel interrupt mask" "0: STCR2_MSKERRS2_DISABLED,1: STCR2_MSKERRS2_ENABLED"
newline
bitfld.long 0x00 12. "MSKERR_S1,Error on algorithm S1 channel interrupt mask" "0: STCR2_MSKERRS1_DISABLED,1: STCR2_MSKERRS1_ENABLED"
bitfld.long 0x00 11. "MSKERR_S0,Error on algorithm S0 channel interrupt mask" "0: STCR2_MSKERRS0_DISABLED,1: STCR2_MSKERRS0_ENABLED"
newline
bitfld.long 0x00 7. "EN,Self-testing channel enable" "0: STCR2_EN_OFF,1: STCR2_EN_ON"
bitfld.long 0x00 4. "FMA_WDSERR,Fault mapping for watchdog sequence error" "0: STCR2_FMAWDSERR_NCF,1: STCR2_FMAWDSERR_CF"
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bitfld.long 0x00 3. "FMA_WDTERR,Fault mapping for watchdog timer error" "0: STCR2_FMAWDTERR_NCF,1: STCR2_FMAWDTERR_CF"
bitfld.long 0x00 2. "FMA_C,Fault mapping for algorithm C" "0: STCR2_FMAC_NCF,1: STCR2_FMAC_CF"
newline
bitfld.long 0x00 0. "FMA_S,Fault mapping for BGAP algorithm" "0: Non-Critical Fault (NCF) mapping,1: Critical Fault (CF) mapping"
group.long 0x348++0x03
line.long 0x00 "STCR3,Self-Test Configuration 3"
bitfld.long 0x00 8.--9. "ALG,One-Shot Operation mode algorithm scheduling" "0: Algorithm S (single step=MSTEP),1: Reserved,2: Algorithm C (single step=MSTEP),3: Algorithm S (default) For test/debug purposes"
bitfld.long 0x00 0.--4. "MSTEP,For One-Shot Operation mode: Current step for Algorithm S//C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34C++0x03
line.long 0x00 "STBRR,Self-Test Baud Rate"
bitfld.long 0x00 16.--18. "WDT,The watchdog timer value is used to monitor the algorithm sequence to verify that it is correctly executing within the safe time period" "0: 0.1 ms ((0008h * Prescaler) cycles at 80 MHz),1: 0.5 ms ((0027h * Prescaler) cycles at 80 MHz),2: 1 ms ((004Eh * Prescaler) cycles at 80 MHz),3: 2 ms ((009Ch * Prescaler) cycles at 80 MHz),4: 5 ms ((0187h * Prescaler) cycles at 80 MHz),5: 10 ms ((030Dh * Prescaler) cycles at 80 MHz),6: 20 ms (061Ah * Prescaler) cycles at 80 MHz),7: 50 ms (0F42h *Prescaler) cycles at 80 MHz)"
hexmask.long.byte 0x00 0.--7. 1. "BR,Algorithm baud rate"
group.long 0x350++0x03
line.long 0x00 "STSR1,Self-Test Status 1"
eventfld.long 0x00 27. "WDSERR,Watchdog sequence errors" "0: STSR1_WDSERR_NO_FAIL,1: STSR1_WDSERR_FAIL"
eventfld.long 0x00 25. "WDTERR,Watchdog timer error" "0: STSR1_WDTERR_NO_FAIL,1: STSR1_WDTERR_FAIL"
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eventfld.long 0x00 24. "OVERWR,Overwrite error" "0: STSR1_OVERWR_NO_ERROR,1: Overwrite error occurred"
eventfld.long 0x00 23. "ST_EOC,Self-test EOC" "0: Self-test end of conversion is not complete,1: Self-test end of conversion is complete"
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eventfld.long 0x00 18. "WDG_EOA_C,Indicates that Algorithm C has completed" "0: Self-test end of Algorithm C conversion is..,1: Self-test end of Algorithm C conversion is.."
eventfld.long 0x00 16. "WDG_EOA_S,Indicates that Algorithm S has been completed" "0: Self-test end of Algorithm S conversion is..,1: Self-test end of Algorithm S conversion is.."
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eventfld.long 0x00 15. "ERR_C,Algorithm C error" "0: No Algorithm C error,1: Algorithm C error occurred"
eventfld.long 0x00 13. "ERR_S2,STSR1[ERR_S2] indicates an error on the self-test channel (Algorithm S (SUPPLY) step2)" "0: No error occurred on the sampled signal,1: Error occurred on the sampled signal"
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eventfld.long 0x00 12. "ERR_S1,STSR1[ERR_S1] indicates an error on the self-test channel (Algorithm S (SUPPLY) step1)" "0: STSR1_ERRS1_NO_VDDERR,1: STSR1_ERRS1_VDDERR"
eventfld.long 0x00 11. "ERR_S0,STSR1[ERR_S0] indicates an error on the self-test channel (Algorithm S (SUPPLY) step0)" "0: STSR1_ERRS0_NO_VREFERR,1: STSR1_ERRS0_VREFERR"
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eventfld.long 0x00 5.--9. "STEP_C,Algorithm C step number error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x354++0x03
line.long 0x00 "STSR2,Self-Test Status 2"
bitfld.long 0x00 31. "OVFL,Overflow bit Overflow bit is set when divisor is zero" "0,1"
hexmask.long.word 0x00 16.--27. 1. "DATA1,Test channel converted data when the ERR_S1 has occurred"
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hexmask.long.word 0x00 0.--11. 1. "DATA0,Test channel converted data when the ERR_S1 has occurred"
rgroup.long 0x358++0x03
line.long 0x00 "STSR3,Self-Test Status 3"
hexmask.long.word 0x00 16.--27. 1. "DATA1,Test channel converted data when the ERR_S2 has occurred"
hexmask.long.word 0x00 0.--11. 1. "DATA0,Test channel converted data when the ERR_S0 has occurred"
rgroup.long 0x35C++0x03
line.long 0x00 "STSR4,Self-Test Status 4"
hexmask.long.word 0x00 16.--27. 1. "DATA1,DATA1"
rgroup.long 0x370++0x03
line.long 0x00 "STDR1,Self-Test Data 1"
bitfld.long 0x00 19. "VALID,Valid data" "0,1"
bitfld.long 0x00 18. "OWERWR,Overwrite data" "0,1"
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hexmask.long.word 0x00 0.--11. 1. "TCDATA,Test channel converted data"
rgroup.long 0x374++0x03
line.long 0x00 "STDR2,Self-Test Data 2"
hexmask.long.word 0x00 20.--31. 1. "FDATA,Fractional data"
bitfld.long 0x00 19. "VALID,Valid data" "0,1"
newline
bitfld.long 0x00 18. "OVERWR,Overwrite data" "0,1"
hexmask.long.word 0x00 0.--11. 1. "IDATA,Integer data"
group.long 0x380++0x03
line.long 0x00 "STAW0R,Self-Test Analog Watchdog 0"
bitfld.long 0x00 31. "AWDE,Enables/disables the comparison of the conversion result from the ADC supply self-test step0 to the thresholds contained in this register (THRH and THRL)" "0: STAW0R_AWDE_DISABLED,1: STAW0R_AWDE_ENABLED"
bitfld.long 0x00 30. "WDTE,Watchdog timer enable (related to the Algorithm S)" "0: STAW0R_WDTE_DISABLED,1: STAW0R_WDTE_ENABLED"
newline
hexmask.long.word 0x00 16.--27. 1. "THRH,High threshold value for Algorithm S step0"
hexmask.long.word 0x00 0.--11. 1. "THRL,Low threshold value for Algorithm S step0"
group.long 0x384++0x03
line.long 0x00 "STAW1AR,Self-Test Analog Watchdog 1A"
bitfld.long 0x00 31. "AWDE,Analog watchdog enable related to Algorithm S (step1)" "0,1"
hexmask.long.word 0x00 16.--27. 1. "THRH,High threshold value (integer part) for Algorithm S (step1) test channel (unsigned coding)"
newline
hexmask.long.word 0x00 0.--11. 1. "THRL,Low threshold value (integer part) for Algorithm S (step1) test channel (unsigned coding)"
group.long 0x388++0x03
line.long 0x00 "STAW1BR,Self-Test Analog Watchdog 1B"
hexmask.long.word 0x00 16.--27. 1. "THRH,High threshold value (fractional part) for Algorithm S (step1) test channel (unsigned coding)"
hexmask.long.word 0x00 0.--11. 1. "THRL,Low threshold value (fractional part) for Algorithm S (step1) test channel (unsigned coding)"
group.long 0x38C++0x03
line.long 0x00 "STAW2R,Self-Test Analog Watchdog 2"
bitfld.long 0x00 31. "AWDE,Analog watchdog enable related to Algorithm S (step2)" "0,1"
hexmask.long.word 0x00 0.--11. 1. "THRL,Threshold level low"
rgroup.long 0x390++0x03
line.long 0x00 "STAW3R,Self-Test Analog Watchdog 3"
group.long 0x394++0x03
line.long 0x00 "STAW4R,Self-Test Analog Watchdog 4"
bitfld.long 0x00 31. "AWDE,Analog watchdog enable (related to Algorithm C)" "0: STAW4R_AWDE_DISABLED,1: STAW4R_AWDE_ENABLED"
bitfld.long 0x00 30. "WDTE,Watchdog timer enable (related to Algorithm C)" "0: STAW4R_WDTE_DISABLED,1: STAW4R_WDTE_ENABLED"
newline
hexmask.long.word 0x00 16.--27. 1. "THRH,High threshold value for step0 of Algorithm C"
hexmask.long.word 0x00 0.--11. 1. "THRL,Low threshold value for step0 of Algorithm C"
group.long 0x398++0x03
line.long 0x00 "STAW5R,Self-Test Analog Watchdog 5"
hexmask.long.word 0x00 16.--27. 1. "THRH,High threshold value for step N of Algorithm C (N = 1 to CS-1)"
hexmask.long.word 0x00 0.--11. 1. "THRL,Low threshold value for step0 of Algorithm C"
rgroup.long 0x39C++0x03
line.long 0x00 "CALSTAT,Calibration Status"
hexmask.long.word 0x00 16.--31. 1. "TEST_RESULT,TEST_RESULT"
bitfld.long 0x00 11. "STAT_12,Status of Calibration step 12" "0: CALSTAT_STAT12_PASSED,1: CALSTAT_STAT12_FAILED"
newline
bitfld.long 0x00 10. "STAT_11,Status of calibration step 11" "0: CALSTAT_STAT11_PASSED,1: CALSTAT_STAT11_FAILED"
bitfld.long 0x00 9. "STAT_10,Status of calibration step 10" "0: CALSTAT_STAT10_PASSED,1: CALSTAT_STAT10_FAILED"
newline
bitfld.long 0x00 8. "STAT_9,Status of calibration step 9" "0: CALSTAT_STAT9_PASSED,1: CALSTAT_STAT9_FAILED"
bitfld.long 0x00 7. "STAT_8,Status of calibration step 8" "0: CALSTAT_STAT8_PASSED,1: CALSTAT_STAT8_FAILED"
newline
bitfld.long 0x00 6. "STAT_7,Status of calibration step 7" "0: CALSTAT_STAT7_PASSED,1: CALSTAT_STAT7_FAILED"
bitfld.long 0x00 5. "STAT_6,Status of calibration step 6" "0: CALSTAT_STAT6_PASSED,1: CALSTAT_STAT6_FAILED"
newline
bitfld.long 0x00 4. "STAT_5,Status of calibration step 5" "0: CALSTAT_STAT5_PASSED,1: CALSTAT_STAT5_FAILED"
bitfld.long 0x00 3. "STAT_4,Status of calibration step 4" "0: CALSTAT_STAT4_PASSED,1: CALSTAT_STAT4_FAILED"
newline
bitfld.long 0x00 2. "STAT_3,Status of calibration step 3" "0: CALSTAT_STAT3_PASSED,1: CALSTAT_STAT3_FAILED"
bitfld.long 0x00 1. "STAT_2,Status of calibration step 2" "0: CALSTAT_STAT2_PASSED,1: CALSTAT_STAT2_FAILED"
newline
bitfld.long 0x00 0. "STAT_1,Status of calibration step 1" "0: CALSTAT_STAT1_PASSED,1: CALSTAT_STAT1_FAILED"
tree.end
tree "ATP"
base ad:0x51033000
group.long 0x00++0x03
line.long 0x00 "PLLC,PLL Control"
bitfld.long 0x00 31. "PLLPD,PLL Reset" "0: Analog PLL reset is deasserted,1: Analog PLL reset is asserted"
group.long 0x04++0x03
line.long 0x00 "PLLS,PLL Status"
eventfld.long 0x00 3. "LOL,PLL Loss of Lock Status" "0: No loss-of-lock detected,1: Loss-of-lock detected"
rbitfld.long 0x00 2. "LOCK,PLL Lock Status" "0: PLL unlocked,1: PLL locked"
group.long 0x08++0x03
line.long 0x00 "PLLDIV,PLL Divider"
bitfld.long 0x00 16.--21. "ODIV1,PLL Output Division Factor 1" "0: Divide by 1,1: Divide by 1,2: Divide by 2,3: Divide by 3,4: Divide by 4,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,63: Divide by 63"
bitfld.long 0x00 12.--14. "RDIV,PLL Input Clock Predivider" "0: Divide by 1,1: Divide by 1,2: Divide by 2,3: Divide by 3,4: Divide by 4,5: a00065987801,6: Divide by 6,7: Divide by 7"
newline
hexmask.long.byte 0x00 0.--7. 1. "MFID,PLL Multiplication Factor Integer Divider"
group.long 0x18++0x03
line.long 0x00 "PLLCAL_2,PLL Calibration 2"
bitfld.long 0x00 17.--18. "CALDPER,Calibration DAC Period" "0: Not allowed,1: a0442300012,2: 64 DAC settling time (in terms of number of..,3: Not allowed"
group.long 0x20++0x03
line.long 0x00 "PLLCKMUX,PLL Clock MUX"
bitfld.long 0x00 0.--1. "REFCLKSEL,Reference Clock Selection" "0: 100 MHz LVDS reference clock (AURORA_EXT_CLK),1: 40 MHz crystal oscillator clock (FXOSC_CLK),?..."
rgroup.long 0x300++0x03
line.long 0x00 "ALS,AL Status"
bitfld.long 0x00 10.--12. "TXCFG,TX Lane Configuration" "?,1: 2 TX lanes,?,3: 4 TX lanes,?..."
bitfld.long 0x00 9. "PRST,Channel Partner Reset" "0: No reset of channel partner,1: Channel partner has reset (causes AL to reset.."
newline
bitfld.long 0x00 2.--3. "TS,Training Status" "0: Training has not completed any stage,1: AL has successfully completed symbol lock and..,2: AL has successfully completed channel bonding,3: AL has successfully completed verification"
bitfld.long 0x00 1. "CS,Channel Status" "0: Aurora channel not ready,1: Aurora channel ready"
newline
bitfld.long 0x00 0. "AS,Aurora Status" "0: Aurora not enabled,1: Aurora enabled"
group.long 0x308++0x03
line.long 0x00 "ALGC,AL General Control"
bitfld.long 0x00 31. "RST,Aurora Channel Reset" "0,1"
bitfld.long 0x00 14. "PCRST,Protocol Converter Reset" "0,1"
newline
bitfld.long 0x00 3. "CRCEN,CRC Enable" "0: CRC generation is disabled for TX data,1: CRC is inserted for TX frames"
bitfld.long 0x00 2. "CCOEN,Clock Compensation Override Enable" "0: Clock compensation counter times out at 7427..,1: Clock compensation counter times out at 1280.."
group.long 0x30C++0x03
line.long 0x00 "ALTC,AL Training Control"
bitfld.long 0x00 31. "STE,Static Training Enable" "?,1: Static (timer based) training method is used.."
bitfld.long 0x00 30. "AHD,Hold in Align" "0: Follows Aurora training sequence,1: AL remains in align until this bit is cleared"
newline
bitfld.long 0x00 29. "BHD,Hold in Bond" "0: Follows Aurora training sequence,1: AL remains in bond until this bit is cleared"
bitfld.long 0x00 28. "VHD,Hold in Verify" "0: Follows Aurora training sequence,1: AL remains in verify until this bit is cleared"
newline
bitfld.long 0x00 19.--22. "ATC,Align Timer Count" "0: Remain in align for 16 cycles,1: Remain in align for 24 cycles,2: Remain in align for 32 cycles,3: Remain in align for 48 cycles,4: Remain in align for 64 cycles,5: Remain in align for 96 cycles,6: Remain in align for 128 cycles,7: Remain in align for 192 cycles,8: Remain in align for 256 cycles,9: Remain in align for 384 cycles,10: Remain in align for 512 cycles,11: Remain in align for 768 cycles,12: Remain in align for 1024 cycles,13: Remain in align for 1536 cycles,14: Remain in align for 2048 cycles,15: Remain in align for 3072 cycles"
bitfld.long 0x00 10.--13. "BTC,Bond Timer Count" "0: Remain in bond for 16 cycles,1: Remain in bond for 24 cycles,2: Remain in bond for 32 cycles,3: Remain in bond for 48 cycles,4: Remain in bond for 64 cycles,5: Remain in bond for 96 cycles,6: Remain in bond for 128 cycles,7: Remain in bond for 192 cycles,8: Remain in bond for 256 cycles,9: Remain in bond for 384 cycles,10: Remain in bond for 512 cycles,11: Remain in bond for 768 cycles,12: Remain in bond for 1024 cycles,13: Remain in bond for 1536 cycles,14: Remain in bond for 2048 cycles,15: Remain in bond for 3072 cycles"
newline
bitfld.long 0x00 0.--3. "VTC,Verify Timer Count" "0: Remain in verify for 16 cycles,1: Remain in verify for 24 cycles,2: Remain in verify for 32 cycles,3: Remain in verify for 48 cycles,4: Remain in verify for 64 cycles,5: Remain in verify for 96 cycles,6: Remain in verify for 128 cycles,7: Remain in verify for 192 cycles,8: Remain in verify for 256 cycles,9: Remain in verify for 384 cycles,10: Remain in verify for 512 cycles,11: Remain in verify for 768 cycles,12: Remain in verify for 1024 cycles,13: Remain in verify for 1536 cycles,14: Remain in verify for 2048 cycles,15: Remain in verify for 3072 cycles"
group.long 0x440++0x03
line.long 0x00 "LVDSTX,LVDS TX IO Configuration"
bitfld.long 0x00 16. "PADS_TX_CONF_EN,PADS TX Configuration Enable" "0: PADS TX configuration disabled,1: PADS TX configuration enabled"
bitfld.long 0x00 12.--15. "TX_CONF,LVDS PADS TX Control Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--6. "PREMPH,Pre-Emphasis Configuration" "0,1,2,3"
bitfld.long 0x00 2. "TX_TREF_EN,TX LVDS Termination Reference Enable" "0: c0000120,1: c00330120"
newline
bitfld.long 0x00 1. "CREF_EN,Current Reference Enable" "0: c00000100,1: a04434632"
bitfld.long 0x00 0. "TXAMODE,TX Aurora pad mode enable" "0: c000120,1: c006010120"
group.long 0x444++0x03
line.long 0x00 "LVDSRX,LVDS RX IO Configuration"
bitfld.long 0x00 16. "RX_TREF_EN,RX LVDS Termination Reference Enable" "0: c001210120,1: c0000060"
bitfld.long 0x00 3. "RXCB,RX LVDS Current Boost" "0: Current reference is 100 uA,1: Current reference is 1 mA"
newline
bitfld.long 0x00 1. "RXICE,RX Input Clock Enable" "0: Disable input buffer,1: Enable input buffer"
group.long 0x448++0x03
line.long 0x00 "LVDSTXOBE,LVDS TX OBE Configuration"
bitfld.long 0x00 3. "OBETX3,TX-3 Aurora pad output buffer enable" "0: c60443020,1: c60445020"
bitfld.long 0x00 2. "OBETX2,TX-2 Aurora pad output buffer enable" "0: c60025550,1: c60332020"
newline
bitfld.long 0x00 1. "OBETX1,TX-1 Aurora pad output buffer enable" "0: c60554020,1: c60000020"
bitfld.long 0x00 0. "OBETX0,TX-0 Aurora pad output buffer enable" "0: c66660020,1: c69900020"
group.long 0x480++0x03
line.long 0x00 "CIAC,CIA Control"
bitfld.long 0x00 29. "TPIU_CLK_DISABLE,TPIU clock disable" "0: Enable,1: g000344"
bitfld.long 0x00 28. "TPIU_CLK_SEL,TPIU clock mux select signal" "0: c003373320,1: AURORA_CLK clock"
newline
bitfld.long 0x00 9. "DBYTER,TPIU data bytes is reversed" "0: Disable byte reversal,1: Enable byte reversal"
bitfld.long 0x00 8. "DBITR,TPIU data bit reversal in a byte selection" "0: Disable bit reversal,1: Enable bit reversal"
newline
bitfld.long 0x00 4.--6. "TPIUCM,TPIU Control Mode" "0: Continuous and format mode,1: Normal mode,?,?,?,?,?,7: Trace disable mode"
bitfld.long 0x00 0.--3. "NUM_LANE,Number of Aurora Lanes" "0: c0222770120,?,2: c1110120,?,4: c0777120,?..."
group.long 0x488++0x03
line.long 0x00 "ATPE,Aurora Trace Port Enable"
bitfld.long 0x00 1. "APHYEN,Aurora PHY Enable 0-AP Disable 1-AP Enable" "0,1"
bitfld.long 0x00 0. "ATPEN,Aurora Trace Port Enable" "0: c00340120,1: c000444420"
rgroup.long 0xF00++0x03
line.long 0x00 "ITCTRL,Integration Mode Control"
bitfld.long 0x00 0. "IME,The bit field is always 0 indicating ATP only supports functional mode" "0,1"
rgroup.long 0xFA0++0x03
line.long 0x00 "CLAIMSET,Claim Tag Set"
hexmask.long 0x00 0.--31. 1. "SET,This field is always 0 indicating no claim tag is implemented"
rgroup.long 0xFA4++0x03
line.long 0x00 "CLAIMCLR,Claim Tag Clear"
hexmask.long 0x00 0.--31. 1. "CLR,This field is always 0 indicating no effect on claim tag"
rgroup.long 0xFA8++0x03
line.long 0x00 "DEVAFF0,Device Affinity 0"
hexmask.long 0x00 0.--31. 1. "DEVAFF0,Value of this field is set to 24h"
rgroup.long 0xFAC++0x03
line.long 0x00 "DEVAFF1,Device Affinity 1"
hexmask.long 0x00 0.--31. 1. "DEVAFF1,Value of this field is set to 24h"
wgroup.long 0xFB0++0x03
line.long 0x00 "LAR,Lock Access Register"
hexmask.long 0x00 0.--31. 1. "KEY,The value of this register must match with the expected key when the most significant bit of address is 0 (core access)"
rgroup.long 0xFB4++0x03
line.long 0x00 "LSR,Lock Status Register"
bitfld.long 0x00 2. "nTT,Register size indicator" "0,1"
bitfld.long 0x00 1. "SLK,Software Lock Status" "0: Lock matched and write operations are permitted,1: Lock not matched and write operations are not.."
newline
bitfld.long 0x00 0. "SLI,This field is always 1 and indicates that Software Lock control mechanism exists for this device" "0,1"
rgroup.long 0xFB8++0x03
line.long 0x00 "AUTHSTATUS,Authentication Status"
hexmask.long.byte 0x00 0.--7. 1. "AUTHSTATUS,This field is always 0 indicating that debug level authentication status is not supported"
rgroup.long 0xFBC++0x03
line.long 0x00 "DEVARCH,Device Architecture"
hexmask.long.word 0x00 21.--31. 1. "ARCHITECT,Defines the architect of the component"
bitfld.long 0x00 20. "PRESENT,Indicates the presence of this register" "0,1"
newline
bitfld.long 0x00 16.--19. "REVISION,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "ARCHID,Architecture ID"
rgroup.long 0xFC0++0x03
line.long 0x00 "DEVID2,Device Configuration 2"
hexmask.long 0x00 0.--31. 1. "DEVID2,The value of the field is always 0"
rgroup.long 0xFC4++0x03
line.long 0x00 "DEVID1,Device Configuration 1"
hexmask.long 0x00 0.--31. 1. "DEVID1,The value of the field is always 0"
rgroup.long 0xFC8++0x03
line.long 0x00 "DEVID,Device Configuration"
hexmask.long 0x00 0.--31. 1. "DEVID,The value of the field is always 0"
rgroup.long 0xFCC++0x03
line.long 0x00 "DEVTYPE,Device Type Identifier"
bitfld.long 0x00 4.--7. "SUB,Sub Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "MAJOR,Major Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFD0++0x03
line.long 0x00 "PIDR4,Peripheral Identification Register 4"
bitfld.long 0x00 4.--7. "SIZE,4KB Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DES_2,JEP106 Continuation Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFE0++0x03
line.long 0x00 "PIDR0,Peripheral Identification Register 0"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits[7:0]"
rgroup.long 0xFE4++0x03
line.long 0x00 "PIDR1,Peripheral Identification Register 1"
bitfld.long 0x00 4.--7. "DES_0,JEP106 identification code bits[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PART_1,Part number bits[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFE8++0x03
line.long 0x00 "PIDR2,Peripheral Identification Register 2"
bitfld.long 0x00 4.--7. "REVISION,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "JEDEC,This bit is always set which indicates that a JEDEC assigned value is used" "0,1"
newline
bitfld.long 0x00 0.--2. "DES_1,JEP106 identification code bits[6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFEC++0x03
line.long 0x00 "PIDR3,Peripheral Identification Register 3"
bitfld.long 0x00 4.--7. "CMOD,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "REVAND,RevAnd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFF0++0x03
line.long 0x00 "CIDR0,Component Identification Register 0"
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,Preamble"
rgroup.long 0xFF4++0x03
line.long 0x00 "CIDR1,Component Identification Register 1"
bitfld.long 0x00 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFF8++0x03
line.long 0x00 "CIDR2,Component Identification Register 2"
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_2,Preamble"
rgroup.long 0xFFC++0x03
line.long 0x00 "CIDR3,Component Identification Register 3"
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "BOOT (Boot_BMR)"
tree "BOOT_BMR"
base ad:0x400D8900
rgroup.long 0x00++0x03
line.long 0x00 "BOOT_GPR_BMR1,Boot Configuration 1"
hexmask.long.word 0x00 0.--15. 1. "BOOT_CFG,Boot Configuration"
rgroup.long 0x04++0x03
line.long 0x00 "BOOT_GPR_BMR2,Boot Configuration 2"
bitfld.long 0x00 25. "BMODE1,Boot Mode Pin 1" "0,1"
bitfld.long 0x00 24. "BMODE2,Boot Mode Pin 2" "0,1"
bitfld.long 0x00 4. "FUSE_SEL,Select Boot From Fuses" "0,1"
tree.end
tree "BOOT_POR"
base ad:0x400D8000
group.long 0x2C++0x03
line.long 0x00 "POR_1_REG,SRC POR Control"
hexmask.long.word 0x00 16.--31. 1. "HSE_FW_ROLLBACK_MARKER,HSE_M Firmware Rollback Marker"
hexmask.long.byte 0x00 8.--15. 1. "HSE_FW_ROLLBACK_COUNT_B,HSE Firmware Rollback Count - Backup Image"
hexmask.long.byte 0x00 0.--7. 1. "HSE_FW_ROLLBACK_COUNT_A,HSE Firmware Rollback Count - Primary Image"
group.long 0x30++0x03
line.long 0x00 "POR_2_REG,SRC POR Control"
hexmask.long.byte 0x00 16.--23. 1. "APP_IMAGE,Application Image"
hexmask.long.byte 0x00 8.--15. 1. "DCD_IMAGE,DCD Image"
hexmask.long.byte 0x00 0.--7. 1. "SELF_TEST_DCD_IMAGE,Self-Test DCD Image"
tree.end
tree.end
tree "CM7_GPR"
repeat 2. (list 0. 1.) (list ad:0x40152000 ad:0x40156000)
tree "CM7_GPR_$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CORTEXM7_GPR0,Cortex-M7 Core General-Purpose Register 0"
bitfld.long 0x00 1. "CM7_CPU_EVENT_GENERATE,Cortex-M7 Core Event Generate" "0: Do not set event,1: Set event"
bitfld.long 0x00 0. "CM7_CPU_WAIT,Cortex-M7 CPU Wait" "0: Do not assert wait,1: Assert wait"
tree.end
repeat.end
tree.end
tree "CMU_FC"
repeat 16. (list 0. 1. 3. 5. 6. 7. 8. 10. 11. 12. 13. 14. 15. 16. 17. 21.) (list ad:0x400D4000 ad:0x400D4020 ad:0x400D4060 ad:0x400D40A0 ad:0x40151000 ad:0x400D40E0 ad:0x40155000 ad:0x400D4140 ad:0x400D4160 ad:0x400D4180 ad:0x400D41A0 ad:0x400D41C0 ad:0x400D41E0 ad:0x400D4200 ad:0x400D4220 ad:0x400D42A0)
tree "CMU_FC_$1"
base $2
group.long 0x00++0x03
line.long 0x00 "GCR,Global Configuration Register"
bitfld.long 0x00 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking"
group.long 0x04++0x03
line.long 0x00 "RCCR,Reference Count Configuration Register"
hexmask.long.word 0x00 0.--15. 1. "REF_CNT,Reference clock count"
group.long 0x08++0x03
line.long 0x00 "HTCR,High Threshold Configuration Register"
hexmask.long.tbyte 0x00 0.--23. 1. "HFREF,High frequency reference threshold"
group.long 0x0C++0x03
line.long 0x00 "LTCR,Low Threshold Configuration Register"
hexmask.long.tbyte 0x00 0.--23. 1. "LFREF,Low Frequency Reference Threshold"
group.long 0x10++0x03
line.long 0x00 "SR,Status Register"
rbitfld.long 0x00 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running"
eventfld.long 0x00 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: bfv_sr_fhh_0,1: FHH event occurred"
eventfld.long 0x00 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: bfv_sr_fll_0,1: FLL event occurred"
group.long 0x14++0x03
line.long 0x00 "IER,Interrupt Enable Register"
bitfld.long 0x00 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled"
bitfld.long 0x00 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled"
tree.end
repeat.end
repeat 10. (list 22. 23. 24. 25. 26. 27. 28. 29. 30. 31.) (list ad:0x400D42C0 ad:0x440CC000 ad:0x440CC020 ad:0x440CC040 ad:0x440CC060 ad:0x440AC000 ad:0x440CC0A0 ad:0x440CC0C0 ad:0x440CC0E0 ad:0x440CC100)
tree "CMU_FC_$1"
base $2
group.long 0x00++0x03
line.long 0x00 "GCR,Global Configuration Register"
bitfld.long 0x00 0. "FCE,Frequency Check Enable" "0: Stops frequency checking,1: Starts frequency checking"
group.long 0x04++0x03
line.long 0x00 "RCCR,Reference Count Configuration Register"
hexmask.long.word 0x00 0.--15. 1. "REF_CNT,Reference clock count"
group.long 0x08++0x03
line.long 0x00 "HTCR,High Threshold Configuration Register"
hexmask.long.tbyte 0x00 0.--23. 1. "HFREF,High frequency reference threshold"
group.long 0x0C++0x03
line.long 0x00 "LTCR,Low Threshold Configuration Register"
hexmask.long.tbyte 0x00 0.--23. 1. "LFREF,Low Frequency Reference Threshold"
group.long 0x10++0x03
line.long 0x00 "SR,Status Register"
rbitfld.long 0x00 4. "RS,Run Status" "0: Frequency check stopped,1: Frequency check running"
eventfld.long 0x00 1. "FHH,Frequency higher than high frequency reference threshold event status" "0: bfv_sr_fhh_0,1: FHH event occurred"
eventfld.long 0x00 0. "FLL,Frequency lower than low frequency reference threshold event status" "0: bfv_sr_fll_0,1: FLL event occurred"
group.long 0x14++0x03
line.long 0x00 "IER,Interrupt Enable Register"
bitfld.long 0x00 3. "FHHAIE,Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FHH event interrupt disabled,1: Asynchronous FHH event interrupt enabled"
bitfld.long 0x00 2. "FLLAIE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable" "0: Asynchronous FLL event interrupt disabled,1: Asynchronous FLL event interrupt enabled"
tree.end
repeat.end
tree.end
tree "CRC"
base ad:0x40128000
group.long 0x00++0x03
line.long 0x00 "CFG1,Configuration Register"
bitfld.long 0x00 5. "SWAP_BYTEWISE,Swap CRC_INP byte-wise" "0: No_byte_wise_swap,1: Perform byte-wise swap on CRC_INP input data.."
bitfld.long 0x00 4. "SWAP_BITWISE,Swap CRC_INP bit-wise" "0: No_bit_wise_swap,1: Perform bit-wise swap on CRC_INP input data.."
newline
bitfld.long 0x00 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8-H2F AUTOSAR polynomial"
bitfld.long 0x00 1. "SWAP,Swap selection" "0: No swap selection applied on the CRC_OUTP..,1: Swap selection (MSB to LSB LSB to MSB).."
newline
bitfld.long 0x00 0. "INV,Inversion selection" "0: No inversion selection applied on the..,1: Inversion selection (bit x bit) applied on.."
group.long 0x04++0x03
line.long 0x00 "INP1,Input Register"
hexmask.long 0x00 0.--31. 1. "INP,Input data for the CRC computation"
group.long 0x08++0x03
line.long 0x00 "CSTAT1,Current Status Register"
hexmask.long 0x00 0.--31. 1. "CSTAT,CRC signature status"
rgroup.long 0x0C++0x03
line.long 0x00 "OUTP1,Output Register"
hexmask.long 0x00 0.--31. 1. "OUTP,Final CRC signature"
group.long 0x10++0x03
line.long 0x00 "CFG2,Configuration Register"
bitfld.long 0x00 5. "SWAP_BYTEWISE,Swap CRC_INP byte-wise" "0: No_byte_wise_swap,1: Perform byte-wise swap on CRC_INP input data.."
bitfld.long 0x00 4. "SWAP_BITWISE,Swap CRC_INP bit-wise" "0: No_bit_wise_swap,1: Perform bit-wise swap on CRC_INP input data.."
newline
bitfld.long 0x00 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8-H2F AUTOSAR polynomial"
bitfld.long 0x00 1. "SWAP,Swap selection" "0: No swap selection applied on the CRC_OUTP..,1: Swap selection (MSB to LSB LSB to MSB).."
newline
bitfld.long 0x00 0. "INV,Inversion selection" "0: No inversion selection applied on the..,1: Inversion selection (bit x bit) applied on.."
group.long 0x14++0x03
line.long 0x00 "INP2,Input Register"
hexmask.long 0x00 0.--31. 1. "INP,Input data for the CRC computation"
group.long 0x18++0x03
line.long 0x00 "CSTAT2,Current Status Register"
hexmask.long 0x00 0.--31. 1. "CSTAT,CRC signature status"
rgroup.long 0x1C++0x03
line.long 0x00 "OUTP2,Output Register"
hexmask.long 0x00 0.--31. 1. "OUTP,Final CRC signature"
group.long 0x20++0x03
line.long 0x00 "CFG3,Configuration Register"
bitfld.long 0x00 5. "SWAP_BYTEWISE,Swap CRC_INP byte-wise" "0: No_byte_wise_swap,1: Perform byte-wise swap on CRC_INP input data.."
bitfld.long 0x00 4. "SWAP_BITWISE,Swap CRC_INP bit-wise" "0: No_bit_wise_swap,1: Perform bit-wise swap on CRC_INP input data.."
newline
bitfld.long 0x00 2.--3. "POLYG,Polynomial selection" "0: CRC-CCITT polynomial,1: CRC-32 polynomial,2: CRC-8 polynomial,3: CRC-8-H2F AUTOSAR polynomial"
bitfld.long 0x00 1. "SWAP,Swap selection" "0: No swap selection applied on the CRC_OUTP..,1: Swap selection (MSB to LSB LSB to MSB).."
newline
bitfld.long 0x00 0. "INV,Inversion selection" "0: No inversion selection applied on the..,1: Inversion selection (bit x bit) applied on.."
group.long 0x24++0x03
line.long 0x00 "INP3,Input Register"
hexmask.long 0x00 0.--31. 1. "INP,Input data for the CRC computation"
group.long 0x28++0x03
line.long 0x00 "CSTAT3,Current Status Register"
hexmask.long 0x00 0.--31. 1. "CSTAT,CRC signature status"
rgroup.long 0x2C++0x03
line.long 0x00 "OUTP3,Output Register"
hexmask.long 0x00 0.--31. 1. "OUTP,Final CRC signature"
tree.end
tree "CTE"
base ad:0x4409C000
group.long 0x00++0x03
line.long 0x00 "CNTRL,Control 0"
bitfld.long 0x00 30. "RFS_PGEN,Internal SW RFS Pulse Trigger" "0,1"
bitfld.long 0x00 29. "CTE_RST,CTE Synchronous Reset" "0: DEASSERTED,1: ASSERTED"
newline
bitfld.long 0x00 28. "MA_SL_ST,Master Or Slave Select" "0: Master mode,1: Slave mode"
bitfld.long 0x00 26.--27. "eDMA_CTL,eDMA Trigger Control" "0: Trigger generation disabled,1: Trigger generated at the start of the TT,2: Trigger generated at the end of the TT,3: Trigger generation disabled"
newline
bitfld.long 0x00 24.--25. "OPMOD_SL,CTE FSM Operation Mode Select" "0: Halt mode,1: Continuous Run TT1 mode,2: Continuous Run Single Table mode,3: Continuous Toggle Two Tables mode"
bitfld.long 0x00 20.--23. "RCS_DLY,Radar Chirp Synchronization Delay Control" "0: DELAY_NONE,?..."
newline
bitfld.long 0x00 16.--19. "RFS_DLY,Radar Frame Synchronization Delay Control" "0: DELAY_NONE,?..."
hexmask.long.word 0x00 0.--15. 1. "REP_CNT,TT Repetition Counter"
group.long 0x04++0x03
line.long 0x00 "CNTRL1,Control 1"
bitfld.long 0x00 27. "CKSM_RST,Checksum Reset" "0: No reset checksum calculation functions..,1: Reset after the next clock cycle"
bitfld.long 0x00 26. "CHKSM_MD,Checksum Mode" "0: CHECKSUM,1: MISR"
newline
bitfld.long 0x00 25. "CTE_EN,CTE Enable" "0: DISABLED,1: Enabled"
bitfld.long 0x00 24. "TIMEMODE,Time Mode Type" "0: RELATIVE,1: ABSOLUTE"
newline
bitfld.long 0x00 19.--21. "CLKDIV_4,Fourth Clock Divider" "0: Same as CTE clock frequency,1: 1/2 of the CTE clock frequency,2: 1/4 of the CTE clock frequency,3: 1/8 of the CTE clock frequency,4: 1/16 of the CTE clock frequency,5: 1/32 of the CTE clock frequency,6: 1/64 of the CTE clock frequency,7: 1/128 of the CTE clock frequency"
bitfld.long 0x00 16.--18. "CLKDIV_3,Third Clock Divider" "0: Same as CTE clock frequency,1: 1/2 of the CTE clock frequency,2: 1/4 of the CTE clock frequency,3: 1/8 of the CTE clock frequency,4: 1/16 of the CTE clock frequency,5: 1/32 of the CTE clock frequency,6: 1/64 of the CTE clock frequency,7: 1/128 of the CTE clock frequency"
newline
bitfld.long 0x00 11.--13. "CLKDIV_2,Second Clock Divider" "0: Same as CTE clock frequency,1: 1/2 of the CTE clock frequency,2: 1/4 of the CTE clock frequency,3: 1/8 of the CTE clock frequency,4: 1/16 of the CTE clock frequency,5: 1/32 of the CTE clock frequency,6: 1/64 of the CTE clock frequency,7: 1/128 of the CTE clock frequency"
bitfld.long 0x00 8.--10. "CLKDIV_1,First Clock Divider" "0: Same as CTE clock frequency,1: 1/2 of the CTE clock frequency,2: 1/4 of the CTE clock frequency,3: 1/8 of the CTE clock frequency,4: 1/16 of the CTE clock frequency,5: 1/32 of the CTE clock frequency,6: 1/64 of the CTE clock frequency,7: 1/128 of the CTE clock frequency"
newline
bitfld.long 0x00 0.--5. "CTECK_DV,CTE Clock Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x08)++0x03
line.long 0x00 "LUT0_LSB$1,TT 0 (LSB)"
bitfld.long 0x00 28.--31. "SPT_EVT,SPT Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "TIME_0,Time Instance"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x48)++0x03
line.long 0x00 "LUT0_LSB$1,TT 0 (LSB)"
bitfld.long 0x00 28.--31. "SPT_EVT,SPT Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "TIME_0,Time Instance"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x88)++0x03
line.long 0x00 "LUT0_MSB$1,TT 0 (MSB)"
bitfld.long 0x00 21. "eTIME_AUX_0,Timer Auxiliary Clock 0" "0: Module is disabled,1: Module is enabled"
bitfld.long 0x00 18.--19. "RFS_DEF,RFS Definition" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "RCS_DEF,RCS Definition" "0,1,2,3"
bitfld.long 0x00 14.--15. "CTE_TYP7,CTE Pulse 7" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "CTE_TYP6,CTE Pulse 6" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTE_TYP5,CTE Pulse 5" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "CTE_TYP4,CTE Pulse 4" "0,1,2,3"
bitfld.long 0x00 6.--7. "CTE_TYP3,CTE Pulse 3" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "CTE_TYP2,CTE Pulse 2" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTE_TYP1,CTE Pulse 1" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "CTE_TYP0,CTE Pulse 0" "0: DRIVE_0,1: Drive 1 or divided clock see table in..,2: Drive Z or free see table in description,3: No change or 1 see table in description"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xC8)++0x03
line.long 0x00 "LUT0_MSB$1,TT 0 (MSB)"
bitfld.long 0x00 21. "eTIME_AUX_0,Timer Auxiliary Clock 0" "0: Module is disabled,1: Module is enabled"
bitfld.long 0x00 18.--19. "RFS_DEF,RFS Definition" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "RCS_DEF,RCS Definition" "0,1,2,3"
bitfld.long 0x00 14.--15. "CTE_TYP7,CTE Pulse 7" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "CTE_TYP6,CTE Pulse 6" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTE_TYP5,CTE Pulse 5" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "CTE_TYP4,CTE Pulse 4" "0,1,2,3"
bitfld.long 0x00 6.--7. "CTE_TYP3,CTE Pulse 3" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "CTE_TYP2,CTE Pulse 2" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTE_TYP1,CTE Pulse 1" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "CTE_TYP0,CTE Pulse 0" "0: DRIVE_0,1: Drive 1 or divided clock see table in..,2: Drive Z or free see table in description,3: No change or 1 see table in description"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x108)++0x03
line.long 0x00 "LUT1_LSB$1,TT 1 (LSB)"
bitfld.long 0x00 28.--31. "SPT_EVT,SPT Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "TIME_1,Time Instance"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x148)++0x03
line.long 0x00 "LUT1_LSB$1,TT 1 (LSB)"
bitfld.long 0x00 28.--31. "SPT_EVT,SPT Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "TIME_1,Time Instance"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x188)++0x03
line.long 0x00 "LUT1_MSB$1,TT 1 (MSB)"
bitfld.long 0x00 21. "eTIME_AUX_0,Timer Auxiliary Clock 0" "0: Module is disabled,1: Module is enabled"
bitfld.long 0x00 18.--19. "RFS_DEF,RFS Definition" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "RCS_DEF,RCS Definition" "0,1,2,3"
bitfld.long 0x00 14.--15. "CTE_TYP7,CTE Pulse 7" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "CTE_TYP6,CTE Pulse 6" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTE_TYP5,CTE Pulse 5" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "CTE_TYP4,CTE Pulse 4" "0,1,2,3"
bitfld.long 0x00 6.--7. "CTE_TYP3,CTE Pulse 3" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "CTE_TYP2,CTE Pulse 2" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTE_TYP1,CTE Pulse 1" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "CTE_TYP0,CTE Pulse 0" "0,1,2,3"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1C8)++0x03
line.long 0x00 "LUT1_MSB$1,TT 1 (MSB)"
bitfld.long 0x00 21. "eTIME_AUX_0,Timer Auxiliary Clock 0" "0: Module is disabled,1: Module is enabled"
bitfld.long 0x00 18.--19. "RFS_DEF,RFS Definition" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "RCS_DEF,RCS Definition" "0,1,2,3"
bitfld.long 0x00 14.--15. "CTE_TYP7,CTE Pulse 7" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "CTE_TYP6,CTE Pulse 6" "0,1,2,3"
bitfld.long 0x00 10.--11. "CTE_TYP5,CTE Pulse 5" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "CTE_TYP4,CTE Pulse 4" "0,1,2,3"
bitfld.long 0x00 6.--7. "CTE_TYP3,CTE Pulse 3" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "CTE_TYP2,CTE Pulse 2" "0,1,2,3"
bitfld.long 0x00 2.--3. "CTE_TYP1,CTE Pulse 1" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "CTE_TYP0,CTE Pulse 0" "0,1,2,3"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x208)++0x03
line.long 0x00 "SIGTYPE[$1],Signal Type 0"
bitfld.long 0x00 30.--31. "CTE_TYP7,CTE Pulse Type 7" "0: Z,1: TOGGLE,2: CLOCK,3: LOGIC"
bitfld.long 0x00 28.--29. "CTE_TYP6,CTE Pulse Type 6" "0: Z,1: TOGGLE,2: CLOCK,3: LOGIC"
newline
bitfld.long 0x00 26.--27. "CTE_TYP5,CTE Pulse Type 5" "0: Z,1: TOGGLE,2: CLOCK,3: LOGIC"
bitfld.long 0x00 24.--25. "CTE_TYP4,CTE Pulse Type 4" "0: Z,1: TOGGLE,2: CLOCK,3: LOGIC"
newline
bitfld.long 0x00 22.--23. "CTE_TYP3,CTE Pulse Type 3" "0: Z,1: TOGGLE,2: CLOCK,3: LOGIC"
bitfld.long 0x00 20.--21. "CTE_TYP2,CTE Pulse Type 2" "0: Z,1: TOGGLE,2: CLOCK,3: LOGIC"
newline
bitfld.long 0x00 18.--19. "CTE_TYP1,CTE Pulse Type 1" "0: Z,1: TOGGLE,2: CLOCK,3: LOGIC"
bitfld.long 0x00 16.--17. "CTE_TYP0,CTE Pulse Type 0" "0: Z,1: TOGGLE,2: CLOCK,3: LOGIC"
newline
bitfld.long 0x00 11.--14. "SPT_EVT,SPT Event Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x210)++0x03
line.long 0x00 "SIGTYPE[$1],Signal Type 1"
bitfld.long 0x00 2.--3. "RFS,Radar Frame Synchronization" "0: Z,1: TOGGLE,2: CLOCK,3: LOGIC"
bitfld.long 0x00 0.--1. "RCS,Radar Chirp Synchronization" "0: Z,1: TOGGLE,2: CLOCK,3: LOGIC"
repeat.end
group.long 0x220++0x03
line.long 0x00 "INTEN,Interrupt Enable"
bitfld.long 0x00 9. "LST_EXEN,Last Table Execution Enable" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 8. "eDMA_TEN,eDMA Trigger Interrupt Enable" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 7. "RFS_EN,RFS Interrupt Enable (Rising Edge)" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 6. "RCS_EN,RCS Interrupt Enable (Rising Edge)" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 3. "TT1_EDEN,TT 1 End (Rising)" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 2. "TT0_EDEN,TT 0 End (Rising)" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 1. "TT1_STEN,TT 1 Start (Rising)" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 0. "TT0_STEN,TT 0 Start (Rising)" "0: DISABLED,1: ENABLED"
group.long 0x224++0x03
line.long 0x00 "INTSTAT,Interrupt Status"
eventfld.long 0x00 9. "LAST_EXC,Last Execution" "0: Not last time,1: Last time"
eventfld.long 0x00 8. "eDMA_TRG,eDMA Trigger" "0: Not detected,1: DETECTED_YES"
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eventfld.long 0x00 7. "RFS,Radar Frame Synchronization" "0: Not detected,1: DETECTED_YES"
eventfld.long 0x00 6. "RCS,Radar Chirp Synchronization" "0: Not detected,1: DETECTED_YES"
newline
eventfld.long 0x00 3. "TT1_END,TT1 End" "0: End not reached,1: End reached"
eventfld.long 0x00 2. "TT0_END,TT0 End" "0: End not reached,1: End reached"
newline
eventfld.long 0x00 1. "TT1_STRT,TT1 Start" "0: Not started,1: STARTED_YES"
eventfld.long 0x00 0. "TT0_STRT,TT0 Start" "0: Not started,1: STARTED_YES"
group.long 0x270++0x03
line.long 0x00 "CKSM_LSB,LUT Checksum LSB"
hexmask.long 0x00 0.--31. 1. "CHKS_LSB,Checksum Result LSB"
group.long 0x274++0x03
line.long 0x00 "CKSM_MSB,LUT Checksum MSB"
hexmask.long.byte 0x00 0.--7. 1. "CHKS_MSB,Checksum Result MSB"
group.long 0x278++0x03
line.long 0x00 "DBG_REG,Debug"
rbitfld.long 0x00 3.--4. "FSM_ST,OPMOD FSM State" "0: HALT,1: CRUN Table 0,2: CRUN Table 1,?..."
eventfld.long 0x00 2. "SLV_ALGN,RFS/RCS Align Status" "0: Not aligned,1: ALIGNED_YES"
newline
eventfld.long 0x00 1. "CONT_ERR,TT Contention Error" "0: No contention occurred,1: A contention occurred"
rbitfld.long 0x00 0. "LUT_SEL,TT Select" "0: TT0,1: TT1"
group.long 0x27C++0x03
line.long 0x00 "LUT_DUR,TT0 Execution Duration"
hexmask.long 0x00 0.--31. 1. "TT0_DUR,TT0 Duration"
group.long 0x280++0x03
line.long 0x00 "LUT_DUR1,TT1 Execution Duration"
hexmask.long 0x00 0.--31. 1. "TT1_DUR,TT1 Duration"
group.long 0x284++0x03
line.long 0x00 "CLKSEL,Clock Select"
bitfld.long 0x00 18.--19. "CLK_SEL9,Clock Select for RFS" "0: FIRST,1: SECOND,2: THIRD,3: FOURTH"
bitfld.long 0x00 16.--17. "CLK_SEL8,Clock Select for RCS" "0: FIRST,1: SECOND,2: THIRD,3: FOURTH"
newline
bitfld.long 0x00 14.--15. "CLK_SEL7,Clock Select for CTEP7" "0: FIRST,1: SECOND,2: THIRD,3: FOURTH"
bitfld.long 0x00 12.--13. "CLK_SEL6,Clock Select for CTEP6" "0: FIRST,1: SECOND,2: THIRD,3: FOURTH"
newline
bitfld.long 0x00 10.--11. "CLK_SEL5,Clock Select for CTEP5" "0: FIRST,1: SECOND,2: THIRD,3: FOURTH"
bitfld.long 0x00 8.--9. "CLK_SEL4,Clock Select for CTEP4" "0: FIRST,1: SECOND,2: THIRD,3: FOURTH"
newline
bitfld.long 0x00 6.--7. "CLK_SEL3,Clock Select for CTEP3" "0: FIRST,1: SECOND,2: THIRD,3: FOURTH"
bitfld.long 0x00 4.--5. "CLK_SEL2,Clock Select for CTEP2" "0: FIRST,1: SECOND,2: THIRD,3: FOURTH"
newline
bitfld.long 0x00 2.--3. "CLK_SEL1,Clock Select for CTEP1" "0: FIRST,1: SECOND,2: THIRD,3: FOURTH"
bitfld.long 0x00 0.--1. "CLK_SEL0,Clock Select for CTEP0" "0: FIRST,1: SECOND,2: THIRD,3: FOURTH"
tree.end
tree "CTU"
base ad:0x402C8000
group.long 0x00++0x03
line.long 0x00 "TGSISR,Trigger Generator Subunit Input Selection Register"
bitfld.long 0x00 31. "I15_FE,Input 15 Falling Edge Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 30. "I15_RE,Input 15 Rising Edge Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 13. "I6_FE,Input 6 Falling Edge Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 12. "I6_RE,Input 6 Rising Edge Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 5. "I2_FE,Input 2 Falling Edge Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 4. "I2_RE,Input 2 Rising Edge Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 3. "I1_FE,Input 1 Falling Edge Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 2. "I1_RE,Input 1 Rising edge Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 1. "I0_FE,Input 0 Falling Edge Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 0. "I0_RE,Input 0 Rising Edge Enable" "0: Disabled,1: Enabled"
group.word 0x04++0x01
line.word 0x00 "TGSCR,Trigger Generator Subunit Control Register"
bitfld.word 0x00 8. "ET_TM,Enable Toggle Mode for external Trigger" "0: Pulse mode,1: Toggle mode"
bitfld.word 0x00 6.--7. "PRES,Prescaler selection bits for TGS and SU" "0: Value is 1,1: Value is 2,2: Value is 3,3: Value is 4"
bitfld.word 0x00 1.--5. "MRS_SM,MRS Selection in Sequential Mode-5 bits to select one of the 2 x 16inputs shown in the Trigger generator subunit input selection (TGSISR) register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 0. "TGS_M,Trigger Generator Subunit Mode" "0: Triggered Mode,1: Sequential Mode"
group.word 0x06++0x01
line.word 0x00 "T0CR,Trigger Compare Register"
hexmask.word 0x00 0.--15. 1. "TCRV,Trigger Compare Register Value"
group.word 0x08++0x01
line.word 0x00 "T1CR,Trigger Compare Register"
hexmask.word 0x00 0.--15. 1. "TCRV,Trigger Compare Register Value"
group.word 0x0A++0x01
line.word 0x00 "T2CR,Trigger Compare Register"
hexmask.word 0x00 0.--15. 1. "TCRV,Trigger Compare Register Value"
group.word 0x0C++0x01
line.word 0x00 "T3CR,Trigger Compare Register"
hexmask.word 0x00 0.--15. 1. "TCRV,Trigger Compare Register Value"
group.word 0x0E++0x01
line.word 0x00 "T4CR,Trigger Compare Register"
hexmask.word 0x00 0.--15. 1. "TCRV,Trigger Compare Register Value"
group.word 0x10++0x01
line.word 0x00 "T5CR,Trigger Compare Register"
hexmask.word 0x00 0.--15. 1. "TCRV,Trigger Compare Register Value"
group.word 0x12++0x01
line.word 0x00 "T6CR,Trigger Compare Register"
hexmask.word 0x00 0.--15. 1. "TCRV,Trigger Compare Register Value"
group.word 0x14++0x01
line.word 0x00 "T7CR,Trigger Compare Register"
hexmask.word 0x00 0.--15. 1. "TCRV,Trigger Compare Register Value"
group.word 0x16++0x01
line.word 0x00 "TGSCCR,TGS Counter Compare Register"
hexmask.word 0x00 0.--15. 1. "TGSCCV,TGS Counter Compare Value"
group.word 0x18++0x01
line.word 0x00 "TGSCRR,TGS Counter Reload Register"
hexmask.word 0x00 0.--15. 1. "TGSCRV,TGSCRV"
group.long 0x1C++0x03
line.long 0x00 "CLCR1,Commands List Control Register 1"
bitfld.long 0x00 24.--28. "T3_INDEX,Trigger 3 Commands List 1st command address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "T2_INDEX,Trigger 2 Commands List 1st command address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "T1_INDEX,Trigger 1 Commands List 1st command address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "T0_INDEX,Trigger 0 Commands List 1st command address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x20++0x03
line.long 0x00 "CLCR2,Commands List Control Register 2"
bitfld.long 0x00 24.--28. "T7_INDEX,T7_INDEX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "T6_INDEX,Trigger 6 Commands List 1st command address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "T5_INDEX,Trigger 5 Commands List 1st command address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "T4_INDEX,Trigger 4 Commands List 1st command address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x24++0x03
line.long 0x00 "THCR1,Trigger Handler Control Register 1"
bitfld.long 0x00 30. "T3_E,Trigger 3 Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 24. "T3_ADCE,Trigger 3 ADC command output Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 22. "T2_E,Trigger 2 Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 16. "T2_ADCE,Trigger 2 ADC command output Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 14. "T1_E,Trigger 1 Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 8. "T1_ADCE,Trigger 1 ADC command output Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "T0_E,Trigger 0 Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "T0_ADCE,Trigger 0 ADC command output Enable" "0: Disabled,1: Enabled"
group.long 0x28++0x03
line.long 0x00 "THCR2,Trigger Handler Control Register 2"
bitfld.long 0x00 30. "T7_E,Trigger 7 Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 24. "T7_ADCE,Trigger 7 ADC command output Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 22. "T6_E,Trigger 6 Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 16. "T6_ADCE,Trigger 6 ADC command output Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 14. "T5_E,Trigger 5 Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 8. "T5_ADCE,Trigger 5 ADC command output Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "T4_E,Trigger 4 Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "T4_ADCE,Trigger 4 ADC command output Enable" "0: Disabled,1: Enabled"
group.word 0x2C++0x01
line.word 0x00 "CLR_A_1,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x2C++0x01
line.word 0x00 "CLR_B_1,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x2E++0x01
line.word 0x00 "CLR_A_2,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x2E++0x01
line.word 0x00 "CLR_B_2,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x30++0x01
line.word 0x00 "CLR_A_3,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x30++0x01
line.word 0x00 "CLR_B_3,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x32++0x01
line.word 0x00 "CLR_A_4,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x32++0x01
line.word 0x00 "CLR_B_4,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x34++0x01
line.word 0x00 "CLR_A_5,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x34++0x01
line.word 0x00 "CLR_B_5,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x36++0x01
line.word 0x00 "CLR_A_6,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x36++0x01
line.word 0x00 "CLR_B_6,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x38++0x01
line.word 0x00 "CLR_A_7,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x38++0x01
line.word 0x00 "CLR_B_7,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x3A++0x01
line.word 0x00 "CLR_A_8,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x3A++0x01
line.word 0x00 "CLR_B_8,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x3C++0x01
line.word 0x00 "CLR_A_9,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x3C++0x01
line.word 0x00 "CLR_B_9,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x3E++0x01
line.word 0x00 "CLR_A_10,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x3E++0x01
line.word 0x00 "CLR_B_10,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x40++0x01
line.word 0x00 "CLR_A_11,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x40++0x01
line.word 0x00 "CLR_B_11,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x42++0x01
line.word 0x00 "CLR_A_12,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x42++0x01
line.word 0x00 "CLR_B_12,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x44++0x01
line.word 0x00 "CLR_A_13,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x44++0x01
line.word 0x00 "CLR_B_13,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x46++0x01
line.word 0x00 "CLR_A_14,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x46++0x01
line.word 0x00 "CLR_B_14,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x48++0x01
line.word 0x00 "CLR_A_15,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
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bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x48++0x01
line.word 0x00 "CLR_B_15,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x4A++0x01
line.word 0x00 "CLR_A_16,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x4A++0x01
line.word 0x00 "CLR_B_16,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x4C++0x01
line.word 0x00 "CLR_A_17,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x4C++0x01
line.word 0x00 "CLR_B_17,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x4E++0x01
line.word 0x00 "CLR_A_18,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x4E++0x01
line.word 0x00 "CLR_B_18,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x50++0x01
line.word 0x00 "CLR_A_19,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x50++0x01
line.word 0x00 "CLR_B_19,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x52++0x01
line.word 0x00 "CLR_A_20,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x52++0x01
line.word 0x00 "CLR_B_20,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x54++0x01
line.word 0x00 "CLR_A_21,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x54++0x01
line.word 0x00 "CLR_B_21,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x56++0x01
line.word 0x00 "CLR_A_22,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x56++0x01
line.word 0x00 "CLR_B_22,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x58++0x01
line.word 0x00 "CLR_A_23,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x58++0x01
line.word 0x00 "CLR_B_23,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x5A++0x01
line.word 0x00 "CLR_A_24,Commands List Register A for ADC single-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5. "SU,ADC Port A / Port B selection" "0: ADC Port A selected,1: ADC Port B selected"
bitfld.word 0x00 0.--3. "CH,ADC Port channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x5A++0x01
line.word 0x00 "CLR_B_24,Command List Register B for ADC dual-conversion mode commands"
bitfld.word 0x00 15. "CIR,Command execution Interrupt Request enable bit" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "LC,Last Command Bit" "0: NOT_LAST,1: LAST"
bitfld.word 0x00 13. "CMS,Conversion Mode Selection" "0: Single conversion mode,1: Dual conversion mode"
newline
bitfld.word 0x00 10.--12. "FIFO,FIFO used for ADC Port A / Port B" "0: FIFO_0 select,1: FIFO_1 select,2: FIFO_2 select,3: FIFO_3 select,?..."
bitfld.word 0x00 5.--8. "CH_B,ADC Port B Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "CH_A,ADC Port A Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.word 0x6C++0x01
line.word 0x00 "FDCR,FIFO DMA Control Register"
bitfld.word 0x00 3. "DE3,FIFO 3 DMA enable" "0: Disabled,1: Enabled"
bitfld.word 0x00 2. "DE2,FIFO 2 DMA enable" "0: Disabled,1: Enabled"
bitfld.word 0x00 1. "DE1,FIFO 1 DMA enable" "0: Disabled,1: Enabled"
newline
bitfld.word 0x00 0. "DE0,FIFO 0 DMA enable" "0: Disabled,1: Enabled"
group.long 0x70++0x03
line.long 0x00 "FCR,FIFO Control Register"
bitfld.long 0x00 15. "OR_EN3,FIFO 3 Overrun interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 14. "OF_EN3,FIFO 3 threshold Overflow interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 13. "EMPTY_EN3,FIFO 3 Empty interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 12. "FULL_EN3,FIFO 3 Full interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 11. "OR_EN2,FIFO 2 Overrun interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 10. "OF_EN2,FIFO 2 threshold Overflow interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 9. "EMPTY_EN2,FIFO 2 Empty interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 8. "FULL_EN2,FIFO 2 Full interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 7. "OR_EN1,FIFO 1 Overrun interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "OF_EN1,FIFO 1 threshold Overflow interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 5. "EMPTY_EN1,FIFO 1 Empty interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 4. "FULL_EN1,FIFO 1 Full interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 3. "OR_EN0,FIFO 0 Overrun interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 2. "OF_EN0,FIFO 0 threshold Overflow interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 1. "EMPTY_EN0,FIFO 0 Empty interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 0. "FULL_EN0,FIFO 0 Full interrupt enable" "0: Disabled,1: Enabled"
group.long 0x74++0x03
line.long 0x00 "FTH,FIFO Threshold Register"
hexmask.long.byte 0x00 24.--31. 1. "TH3,FIFO 3 Threshold"
hexmask.long.byte 0x00 16.--23. 1. "TH2,FIFO 2 Threshold"
hexmask.long.byte 0x00 8.--15. 1. "TH1,FIFO 1 Threshold"
newline
hexmask.long.byte 0x00 0.--7. 1. "TH0,FIFO 0 Threshold"
group.long 0x7C++0x03
line.long 0x00 "FST,FIFO Status Register"
eventfld.long 0x00 15. "OR3,FIFO 3 Overrun interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
rbitfld.long 0x00 14. "OF3,FIFO 3 threshold Overflow interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
rbitfld.long 0x00 13. "EMP3,FIFO 3 Empty interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
newline
rbitfld.long 0x00 12. "FULL3,FIFO 3 Full interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
eventfld.long 0x00 11. "OR2,FIFO 2 Overrun interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
rbitfld.long 0x00 10. "OF2,FIFO 2 threshold Overflow interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
newline
rbitfld.long 0x00 9. "EMP2,FIFO 2 Empty interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
rbitfld.long 0x00 8. "FULL2,FIFO 2 Full interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
eventfld.long 0x00 7. "OR1,FIFO 1 Overrun interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
newline
rbitfld.long 0x00 6. "OF1,FIFO 1 threshold Overflow interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
rbitfld.long 0x00 5. "EMP1,FIFO 1 Empty interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
rbitfld.long 0x00 4. "FULL1,FULL1" "0: Interrupt has not occurred,1: Interrupt has occurred"
newline
eventfld.long 0x00 3. "OR0,FIFO 0 Overrun interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
rbitfld.long 0x00 2. "OF0,FIFO 0 threshold Overflow interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
rbitfld.long 0x00 1. "EMP0,FIFO 0 Empty interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
newline
rbitfld.long 0x00 0. "FULL0,FIFO 0 Full interrupt flag" "0: Interrupt has not occurred,1: Interrupt has occurred"
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x80)++0x03
line.long 0x00 "FR[$1],FIFO Right Aligned Data Register $1"
bitfld.long 0x00 19. "ADC,This bit indicates from which ADC Port the value in the DATA field corresponds to" "0: Data coming from ADC Port B,1: Data coming from ADC Port A"
bitfld.long 0x00 16.--18. "N_CH,Number of the channel that DATA field corresponds to" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--11. 1. "DATA,Data of stored channel"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0xA0)++0x03
line.long 0x00 "FL[$1],FIFO Signed Left Aligned Data Register $1"
bitfld.long 0x00 19. "ADC,This bit indicates from which ADC Port the value in the DATA field corresponds to" "0: Data coming from ADC Port B,1: Data coming from ADC Port A"
bitfld.long 0x00 16.--18. "N_CH,Number of the channel that DATA field corresponds to" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 3.--14. 1. "LA_DATA,LA_DATA"
repeat.end
group.word 0xC0++0x01
line.word 0x00 "EFR,Error Flag Register"
eventfld.word 0x00 13. "LIST_BE,List Busy Error" "0: NO_ERROR,1: ERROR"
eventfld.word 0x00 10. "ERRCMP,Error Compare" "0: NO_MATCH,1: MATCH"
eventfld.word 0x00 5. "ADC_OE,ADC command generation Overrun Error" "0: NO_ERROR,1: ERROR"
newline
eventfld.word 0x00 4. "TGS_OSM,The TGS Overrun in Sequential Mode" "0: NO_OVERRUN,1: OVERRUN"
eventfld.word 0x00 3. "MRS_O,Master Reload Signal Overrun" "0: NO_OVERRUN,1: OVERRUN"
eventfld.word 0x00 2. "ICE,Invalid Command Error" "0: NO_ERROR,1: ERROR"
newline
eventfld.word 0x00 1. "SM_TO,Trigger Overrun (more than 8 ES) in TGS Sequential Mode" "0: NO_OVERRUN,1: OVERRUN"
eventfld.word 0x00 0. "MRS_RE,Master Reload Signal Reload Error" "0: NO_ERROR,1: ERROR"
group.word 0xC2++0x01
line.word 0x00 "IFR,Interrupt Flag Register"
eventfld.word 0x00 11. "SERR_B,If this bit is set it means that the time between the start of a conversion and the end of that conversion is out of the expected range which is defined by the EXPBR and CNTRNGR registers" "0,1"
eventfld.word 0x00 10. "SERR_A,If this bit is set it means that the time between the start of a conversion and the end of that conversion is out of the expected range defined by the EXPAR and CNTRNGR registers" "0,1"
eventfld.word 0x00 9. "ADC_I,ADC command interrupt flag is set when a new command is issued" "0,1"
newline
eventfld.word 0x00 8. "T7_I,Trigger 7 interrupt flag is set when the corresponding trigger is issued" "0,1"
eventfld.word 0x00 7. "T6_I,Trigger 6 interrupt flag is set when the corresponding trigger is issued" "0,1"
eventfld.word 0x00 6. "T5_I,Trigger 5 interrupt flag is set when the corresponding trigger is issued" "0,1"
newline
eventfld.word 0x00 5. "T4_I,Trigger 4 interrupt flag is set when the corresponding trigger is issued" "0,1"
eventfld.word 0x00 4. "T3_I,Trigger 3 interrupt flag is set when the corresponding trigger is issued" "0,1"
eventfld.word 0x00 3. "T2_I,Trigger 2 interrupt flag is set when the corresponding trigger is issued" "0,1"
newline
eventfld.word 0x00 2. "T1_I,Trigger 1 interrupt flag is set when the corresponding trigger is issued" "0,1"
eventfld.word 0x00 1. "T0_I,Trigger 0 interrupt flag is set when the corresponding trigger is issued" "0,1"
eventfld.word 0x00 0. "MRS_I,MRS Interrupt flag is set when the Master Reload Signal occurs" "0,1"
group.word 0xC4++0x01
line.word 0x00 "IR,Interrupt/DMA Register"
bitfld.word 0x00 15. "T7_IE,Trigger 7 Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.word 0x00 14. "T6_IE,Trigger 6 Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.word 0x00 13. "T5_IE,Trigger 5 Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.word 0x00 12. "T4_IE,Trigger 4 Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.word 0x00 11. "T3_IE,Trigger 3 Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.word 0x00 10. "T2_IE,Trigger 2 Interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.word 0x00 9. "T1_IE,Trigger 1 Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.word 0x00 8. "T0_IE,Trigger 0 Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.word 0x00 5. "SAF_CNT_B_EN,Enable the ADC Port B counter to check the conversion time" "0: Disabled,1: Enabled"
newline
bitfld.word 0x00 4. "SAF_CNT_A_EN,Enable the ADC Port A counter to check the conversion time" "0: Disabled,1: Enabled"
bitfld.word 0x00 3. "DMA_DE,If this bit is set a dma done acts as a write '1' in the GRE bit" "0,1"
bitfld.word 0x00 2. "MRS_DMAE,If GRE bit is set DMA request is issued on MRS occurrence" "0,1"
newline
bitfld.word 0x00 1. "MRS_IE,MRS Interrupt Enable" "0: Disabled,1: Enabled"
bitfld.word 0x00 0. "IEE,Interrupt Error Enable" "0: Disabled,1: Enabled"
group.word 0xC6++0x01
line.word 0x00 "COTR,Control ON Time Register"
hexmask.word.byte 0x00 0.--7. 1. "COTGT,COTGT"
group.word 0xC8++0x01
line.word 0x00 "CR,Control Register"
bitfld.word 0x00 15. "T7_SG,Trigger 7 Software Generated" "0: S/W not generated,1: S/W generated"
bitfld.word 0x00 14. "T6_SG,Trigger 6 Software Generated" "0: S/W not generated,1: S/W generated"
bitfld.word 0x00 13. "T5_SG,Trigger 5 Software Generated" "0: S/W not generated,1: S/W generated"
newline
bitfld.word 0x00 12. "T4_SG,Trigger 4 Software Generated" "0: S/W not generated,1: S/W generated"
bitfld.word 0x00 11. "T3_SG,Trigger 3 Software Generated" "0: S/W not generated,1: S/W generated"
bitfld.word 0x00 10. "T2_SG,Trigger 2 Software Generated" "0: S/W not generated,1: S/W generated"
newline
bitfld.word 0x00 9. "T1_SG,Trigger 1 Software Generated" "0: S/W not generated,1: S/W generated"
bitfld.word 0x00 8. "T0_SG,Trigger 0 Software Generated" "0: S/W not generated,1: S/W generated"
bitfld.word 0x00 7. "CTU_ADC_R,CTU command list control state machine Reset" "0,1"
newline
bitfld.word 0x00 6. "CTU_ODIS,CTU Output Disable" "0: Enabled,1: Disabled"
bitfld.word 0x00 5. "DFE,Writing a 1b to this bit creates a trigger in CTU timer clock domain which is used to register the value of Digital Filter in the register CTU_DFR into CTU timer clock domain" "0: Disabled,1: Enabled"
bitfld.word 0x00 4. "CGRE,Clear GRE to 0" "0,1"
newline
rbitfld.word 0x00 3. "FGRE,Flag GRE" "0,1"
bitfld.word 0x00 2. "MRS_SG,MRS Software Generated" "0: S/W not generated,1: S/W generated"
bitfld.word 0x00 1. "GRE,General Reload Enable" "0: Disabled,1: Enabled"
newline
bitfld.word 0x00 0. "TGSISR_RE,TGS Input Selection Register Reload Enable" "0,1"
group.word 0xCA++0x01
line.word 0x00 "DFR,Digital Filter Register"
hexmask.word.byte 0x00 0.--7. 1. "FILTER_N,Digital Filter value"
group.word 0xCC++0x01
line.word 0x00 "EXPAR,Expected Value A Register"
hexmask.word 0x00 0.--15. 1. "EXPA,This value is the expected number of system clock cycles needed by ADC Port A to complete a conversion"
group.word 0xCE++0x01
line.word 0x00 "EXPBR,Expected Value B Register"
hexmask.word 0x00 0.--15. 1. "EXPB,This value is the expected number of system clock cycles needed by ADC Port B to complete a conversion"
group.word 0xD0++0x01
line.word 0x00 "CNTRNGR,Counter Range Register"
hexmask.word.byte 0x00 0.--7. 1. "CNTRNG,CNTRNG"
group.long 0xD4++0x03
line.long 0x00 "LISTCSR,List Control/Status Register"
rbitfld.long 0x00 31. "LIST1_BLK,List 1 Blocked flag" "0,1"
rbitfld.long 0x00 24.--28. "LIST1_ADDR,List Address 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 23. "LIST0_BLK,List 0 Blocked flag" "0,1"
newline
rbitfld.long 0x00 16.--20. "LIST0_ADDR,List Address 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0. "PAR_LIST,Parallel mode List" "0: List is executed in streaming mode,1: List is executed in parallel mode"
tree.end
tree "DFS"
base ad:0x400C0000
rgroup.long 0x0C++0x03
line.long 0x00 "PORTSR,Port Status Register"
bitfld.long 0x00 1. "PORTSTAT1,Lock status for port 1" "0: Port n is not locked,1: Port n is locked"
bitfld.long 0x00 0. "PORTSTAT0,Lock status for port 0" "0: Port n is not locked,1: Port n is locked"
group.long 0x10++0x03
line.long 0x00 "PORTLOLSR,Port Loss of Lock Status"
eventfld.long 0x00 1. "LOLF1,Loss of lock flag" "0: The DFS detects no loss of lock for channel..,1: The DFS detected a loss of lock for channel.."
eventfld.long 0x00 0. "LOLF0,Loss of lock flag" "0: The DFS detects no loss of lock for channel..,1: The DFS detected a loss of lock for channel.."
group.long 0x14++0x03
line.long 0x00 "PORTRESET,Port Reset"
bitfld.long 0x00 1. "RESET1,Enable control for port n" "0: Port n is enabled,1: Port n is disabled"
bitfld.long 0x00 0. "RESET0,Enable control for port n" "0: Port n is enabled,1: Port n is disabled"
group.long 0x18++0x03
line.long 0x00 "CTL,Control"
bitfld.long 0x00 1. "DFS_RESET,This field controls the master reset of the DFS" "0: The DFS phase generator is out of reset,1: The DFS phase generator is in reset"
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0x1C)++0x03
line.long 0x00 "DVPORT[$1],Divider for Port n $1"
hexmask.long.byte 0x00 8.--15. 1. "MFI,This field provides the integer part of division factor for port n"
bitfld.long 0x00 0.--5. "MFN,This field provides the numerator of fractional part of division factor for port n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
tree.end
tree "DMA (DMA MP)"
base ad:0x40204000
group.long 0x00++0x03
line.long 0x00 "CSR,Management Page Control"
rbitfld.long 0x00 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel"
rbitfld.long 0x00 24.--28. "ACTIVE_ID,Active Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 9. "CX,Cancel Transfer" "0: NORMAL_OPERATION,1: Cancel the remaining data transfer"
bitfld.long 0x00 8. "ECX,Cancel Transfer With Error" "0: NORMAL_OPERATION,1: Cancel the remaining data transfer"
newline
bitfld.long 0x00 7. "GMRC,Global Master ID Replication Control" "0: Master ID replication disabled for all channels,1: Master ID replication available and.."
bitfld.long 0x00 6. "GCLC,Global Channel Linking Control" "0: Channel linking disabled for all channels,1: Channel linking available and controlled by.."
newline
bitfld.long 0x00 5. "HALT,Halt DMA Operations" "0: NORMAL_OPERATION,1: Stall the start of any new channels"
bitfld.long 0x00 4. "HAE,Halt After Error" "0: NORMAL_OPERATION,1: Any error causes the HALT field to be set to 1"
newline
bitfld.long 0x00 2. "ERCA,Enable Round Robin Channel Arbitration" "0: Round-robin channel arbitration disabled,1: Round-robin channel arbitration enabled"
bitfld.long 0x00 1. "EDBG,Enable Debug" "0: Debug mode disabled,1: Debug mode is enabled"
rgroup.long 0x04++0x03
line.long 0x00 "ES,Management Page Error Status"
bitfld.long 0x00 31. "VLD,Valid" "0: No CHn_ES[ERR] fields are set to 1,1: At least one CHn_ES[ERR] field is set to 1.."
bitfld.long 0x00 24.--28. "ERRCHN,Error Channel Number or Canceled Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 9. "UCE,Uncorrectable TCD Error During Channel Execution" "0: No uncorrectable ECC error,1: Last recorded error was an uncorrectable TCD.."
bitfld.long 0x00 8. "ECX,Transfer Canceled" "0: NO_CANCELED_TRANSFERS,1: Last recorded entry was a canceled transfer.."
newline
bitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
bitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
newline
bitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
bitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
newline
bitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: The last recorded error was NBYTES equal to.."
bitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
newline
bitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was a bus error on a source"
bitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was a bus error on a.."
rgroup.long 0x08++0x03
line.long 0x00 "INT,Management Page Interrupt Request Status"
hexmask.long 0x00 0.--31. 1. "INT,Interrupt Request Status"
rgroup.long 0x0C++0x03
line.long 0x00 "HRS,Management Page Hardware Request Status"
hexmask.long 0x00 0.--31. 1. "HRS,Hardware Request Status"
repeat 32. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "CH_GRPRI[$1],Channel Arbitration Group $1"
bitfld.long 0x00 0.--4. "GRPRI,Arbitration Group For Channel n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
tree.end
tree "DMA_CRC"
base ad:0x40200000
group.long 0x00++0x03
line.long 0x00 "GEC,Global Enable CRC Register"
bitfld.long 0x00 7. "SWAP_BYTE,Swap Byte" "0: Do not swap,1: Byte-wise swap on the input data"
bitfld.long 0x00 1. "SWAP_BIT,Swap Bit" "0: Do not swap,1: Bit-wise swap on the input data"
bitfld.long 0x00 0. "GBL_EN,Global Enable bit" "0: Disable CRC in all channels,1: Enable CRC in all channels"
repeat 8. (increment 0 1)(increment  0 0x10)
tree "Control_Register[$1]"
group.long ($2+0x10)++0x03
line.long 0x00 "CTL,CRC Control Register"
bitfld.long 0x00 31. "EN,CRC Logic" "0: Disable CRC,1: Enable CRC"
bitfld.long 0x00 16.--18. "MODE,CRC Mode" "0: Normal CRC Mode,?..."
bitfld.long 0x00 15. "INIT_SEL,Initial values of the CRC" "0: Initialize CRC with the content of the..,1: Continue accumulating previous CRC values.."
newline
bitfld.long 0x00 8.--11. "POLY_SEL,Polynomial Select" "0: Select CRC-32 0x04C11DB7,1: Select CRC-32 0x1EDC6F41,2: Select CRC-32 0xF4ACFB13,3: Select CRC-16 0x1021,4: Select CRC-8 0x2F,5: Select CRC-8 0x1D,?..."
bitfld.long 0x00 0.--5. "CH_SEL,Channel Select" "0: Select Channel 0,1: Select Channel 1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,62: Select Channel 62,63: Select Channel 63"
group.long ($2+0x14)++0x03
line.long 0x00 "ICRC,Initial CRC Value Register"
hexmask.long 0x00 0.--31. 1. "INI_CRC_VAL,Initial CRC Value"
rgroup.long ($2+0x18)++0x03
line.long 0x00 "FCRC,Final CRC Value Register"
hexmask.long 0x00 0.--31. 1. "CHKSUM_VAL,Final CRC Value"
tree.end
repeat.end
tree.end
tree "DMA_TCD"
base ad:0x40208000
group.long 0x00++0x03
line.long 0x00 "CH0_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x04++0x03
line.long 0x00 "CH0_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x08++0x03
line.long 0x00 "CH0_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x0C++0x03
line.long 0x00 "CH0_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x10++0x03
line.long 0x00 "CH0_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x20++0x03
line.long 0x00 "TCD0_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x24++0x01
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x26++0x01
line.word 0x00 "TCD0_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x28++0x03
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x28++0x03
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2C++0x03
line.long 0x00 "TCD0_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x30++0x03
line.long 0x00 "TCD0_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x34++0x01
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x36++0x01
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x36++0x01
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x38++0x03
line.long 0x00 "TCD0_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x3C++0x01
line.word 0x00 "TCD0_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x3E++0x01
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x3E++0x01
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x4000++0x03
line.long 0x00 "CH1_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x4004++0x03
line.long 0x00 "CH1_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x4008++0x03
line.long 0x00 "CH1_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x400C++0x03
line.long 0x00 "CH1_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x4010++0x03
line.long 0x00 "CH1_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x4020++0x03
line.long 0x00 "TCD1_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x4024++0x01
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x4026++0x01
line.word 0x00 "TCD1_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x4028++0x03
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x4028++0x03
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x402C++0x03
line.long 0x00 "TCD1_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x4030++0x03
line.long 0x00 "TCD1_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x4034++0x01
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x4036++0x01
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x4036++0x01
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x4038++0x03
line.long 0x00 "TCD1_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x403C++0x01
line.word 0x00 "TCD1_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x403E++0x01
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x403E++0x01
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x8000++0x03
line.long 0x00 "CH2_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x8004++0x03
line.long 0x00 "CH2_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x8008++0x03
line.long 0x00 "CH2_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x800C++0x03
line.long 0x00 "CH2_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x8010++0x03
line.long 0x00 "CH2_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x8020++0x03
line.long 0x00 "TCD2_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x8024++0x01
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x8026++0x01
line.word 0x00 "TCD2_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x8028++0x03
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x8028++0x03
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x802C++0x03
line.long 0x00 "TCD2_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x8030++0x03
line.long 0x00 "TCD2_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x8034++0x01
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x8036++0x01
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x8036++0x01
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x8038++0x03
line.long 0x00 "TCD2_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x803C++0x01
line.word 0x00 "TCD2_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x803E++0x01
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x803E++0x01
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0xC000++0x03
line.long 0x00 "CH3_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0xC004++0x03
line.long 0x00 "CH3_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0xC008++0x03
line.long 0x00 "CH3_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0xC00C++0x03
line.long 0x00 "CH3_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC010++0x03
line.long 0x00 "CH3_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0xC020++0x03
line.long 0x00 "TCD3_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0xC024++0x01
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0xC026++0x01
line.word 0x00 "TCD3_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0xC028++0x03
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0xC028++0x03
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0xC02C++0x03
line.long 0x00 "TCD3_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0xC030++0x03
line.long 0x00 "TCD3_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0xC034++0x01
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0xC036++0x01
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0xC036++0x01
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0xC038++0x03
line.long 0x00 "TCD3_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0xC03C++0x01
line.word 0x00 "TCD3_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0xC03E++0x01
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0xC03E++0x01
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x10000++0x03
line.long 0x00 "CH4_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x10004++0x03
line.long 0x00 "CH4_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x10008++0x03
line.long 0x00 "CH4_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1000C++0x03
line.long 0x00 "CH4_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x10010++0x03
line.long 0x00 "CH4_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x10020++0x03
line.long 0x00 "TCD4_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x10024++0x01
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x10026++0x01
line.word 0x00 "TCD4_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x10028++0x03
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x10028++0x03
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1002C++0x03
line.long 0x00 "TCD4_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x10030++0x03
line.long 0x00 "TCD4_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x10034++0x01
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x10036++0x01
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x10036++0x01
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x10038++0x03
line.long 0x00 "TCD4_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1003C++0x01
line.word 0x00 "TCD4_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1003E++0x01
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1003E++0x01
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x14000++0x03
line.long 0x00 "CH5_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x14004++0x03
line.long 0x00 "CH5_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x14008++0x03
line.long 0x00 "CH5_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1400C++0x03
line.long 0x00 "CH5_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x14010++0x03
line.long 0x00 "CH5_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x14020++0x03
line.long 0x00 "TCD5_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x14024++0x01
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x14026++0x01
line.word 0x00 "TCD5_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x14028++0x03
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x14028++0x03
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1402C++0x03
line.long 0x00 "TCD5_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x14030++0x03
line.long 0x00 "TCD5_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x14034++0x01
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x14036++0x01
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x14036++0x01
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x14038++0x03
line.long 0x00 "TCD5_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1403C++0x01
line.word 0x00 "TCD5_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1403E++0x01
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1403E++0x01
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x18000++0x03
line.long 0x00 "CH6_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x18004++0x03
line.long 0x00 "CH6_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x18008++0x03
line.long 0x00 "CH6_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1800C++0x03
line.long 0x00 "CH6_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x18010++0x03
line.long 0x00 "CH6_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x18020++0x03
line.long 0x00 "TCD6_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x18024++0x01
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x18026++0x01
line.word 0x00 "TCD6_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x18028++0x03
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x18028++0x03
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1802C++0x03
line.long 0x00 "TCD6_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x18030++0x03
line.long 0x00 "TCD6_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x18034++0x01
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x18036++0x01
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x18036++0x01
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x18038++0x03
line.long 0x00 "TCD6_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1803C++0x01
line.word 0x00 "TCD6_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1803E++0x01
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1803E++0x01
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x1C000++0x03
line.long 0x00 "CH7_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x1C004++0x03
line.long 0x00 "CH7_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x1C008++0x03
line.long 0x00 "CH7_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x1C00C++0x03
line.long 0x00 "CH7_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C010++0x03
line.long 0x00 "CH7_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x1C020++0x03
line.long 0x00 "TCD7_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x1C024++0x01
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x1C026++0x01
line.word 0x00 "TCD7_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x1C028++0x03
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1C028++0x03
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x1C02C++0x03
line.long 0x00 "TCD7_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x1C030++0x03
line.long 0x00 "TCD7_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x1C034++0x01
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x1C036++0x01
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x1C036++0x01
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x1C038++0x03
line.long 0x00 "TCD7_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x1C03C++0x01
line.word 0x00 "TCD7_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x1C03E++0x01
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x1C03E++0x01
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x20000++0x03
line.long 0x00 "CH8_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x20004++0x03
line.long 0x00 "CH8_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x20008++0x03
line.long 0x00 "CH8_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2000C++0x03
line.long 0x00 "CH8_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x20010++0x03
line.long 0x00 "CH8_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x20020++0x03
line.long 0x00 "TCD8_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x20024++0x01
line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x20026++0x01
line.word 0x00 "TCD8_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x20028++0x03
line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x20028++0x03
line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2002C++0x03
line.long 0x00 "TCD8_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x20030++0x03
line.long 0x00 "TCD8_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x20034++0x01
line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x20036++0x01
line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x20036++0x01
line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x20038++0x03
line.long 0x00 "TCD8_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2003C++0x01
line.word 0x00 "TCD8_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2003E++0x01
line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2003E++0x01
line.word 0x00 "TCD8_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x24000++0x03
line.long 0x00 "CH9_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x24004++0x03
line.long 0x00 "CH9_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x24008++0x03
line.long 0x00 "CH9_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2400C++0x03
line.long 0x00 "CH9_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x24010++0x03
line.long 0x00 "CH9_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x24020++0x03
line.long 0x00 "TCD9_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x24024++0x01
line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x24026++0x01
line.word 0x00 "TCD9_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x24028++0x03
line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x24028++0x03
line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2402C++0x03
line.long 0x00 "TCD9_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x24030++0x03
line.long 0x00 "TCD9_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x24034++0x01
line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x24036++0x01
line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x24036++0x01
line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x24038++0x03
line.long 0x00 "TCD9_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2403C++0x01
line.word 0x00 "TCD9_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2403E++0x01
line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2403E++0x01
line.word 0x00 "TCD9_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x28000++0x03
line.long 0x00 "CH10_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x28004++0x03
line.long 0x00 "CH10_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x28008++0x03
line.long 0x00 "CH10_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2800C++0x03
line.long 0x00 "CH10_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x28010++0x03
line.long 0x00 "CH10_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x28020++0x03
line.long 0x00 "TCD10_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x28024++0x01
line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x28026++0x01
line.word 0x00 "TCD10_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x28028++0x03
line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x28028++0x03
line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2802C++0x03
line.long 0x00 "TCD10_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x28030++0x03
line.long 0x00 "TCD10_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x28034++0x01
line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x28036++0x01
line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x28036++0x01
line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x28038++0x03
line.long 0x00 "TCD10_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2803C++0x01
line.word 0x00 "TCD10_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2803E++0x01
line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2803E++0x01
line.word 0x00 "TCD10_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x2C000++0x03
line.long 0x00 "CH11_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x2C004++0x03
line.long 0x00 "CH11_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x2C008++0x03
line.long 0x00 "CH11_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x2C00C++0x03
line.long 0x00 "CH11_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2C010++0x03
line.long 0x00 "CH11_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x2C020++0x03
line.long 0x00 "TCD11_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x2C024++0x01
line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x2C026++0x01
line.word 0x00 "TCD11_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x2C028++0x03
line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2C028++0x03
line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x2C02C++0x03
line.long 0x00 "TCD11_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x2C030++0x03
line.long 0x00 "TCD11_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x2C034++0x01
line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x2C036++0x01
line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x2C036++0x01
line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x2C038++0x03
line.long 0x00 "TCD11_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x2C03C++0x01
line.word 0x00 "TCD11_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x2C03E++0x01
line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x2C03E++0x01
line.word 0x00 "TCD11_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x30000++0x03
line.long 0x00 "CH12_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x30004++0x03
line.long 0x00 "CH12_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x30008++0x03
line.long 0x00 "CH12_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x3000C++0x03
line.long 0x00 "CH12_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x30010++0x03
line.long 0x00 "CH12_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x30020++0x03
line.long 0x00 "TCD12_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x30024++0x01
line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x30026++0x01
line.word 0x00 "TCD12_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x30028++0x03
line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x30028++0x03
line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x3002C++0x03
line.long 0x00 "TCD12_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x30030++0x03
line.long 0x00 "TCD12_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x30034++0x01
line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x30036++0x01
line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x30036++0x01
line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x30038++0x03
line.long 0x00 "TCD12_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x3003C++0x01
line.word 0x00 "TCD12_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x3003E++0x01
line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x3003E++0x01
line.word 0x00 "TCD12_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x34000++0x03
line.long 0x00 "CH13_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x34004++0x03
line.long 0x00 "CH13_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x34008++0x03
line.long 0x00 "CH13_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x3400C++0x03
line.long 0x00 "CH13_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34010++0x03
line.long 0x00 "CH13_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x34020++0x03
line.long 0x00 "TCD13_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x34024++0x01
line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x34026++0x01
line.word 0x00 "TCD13_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x34028++0x03
line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x34028++0x03
line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x3402C++0x03
line.long 0x00 "TCD13_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x34030++0x03
line.long 0x00 "TCD13_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x34034++0x01
line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x34036++0x01
line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x34036++0x01
line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x34038++0x03
line.long 0x00 "TCD13_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x3403C++0x01
line.word 0x00 "TCD13_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x3403E++0x01
line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x3403E++0x01
line.word 0x00 "TCD13_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x38000++0x03
line.long 0x00 "CH14_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x38004++0x03
line.long 0x00 "CH14_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x38008++0x03
line.long 0x00 "CH14_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x3800C++0x03
line.long 0x00 "CH14_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38010++0x03
line.long 0x00 "CH14_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x38020++0x03
line.long 0x00 "TCD14_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x38024++0x01
line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x38026++0x01
line.word 0x00 "TCD14_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x38028++0x03
line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x38028++0x03
line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x3802C++0x03
line.long 0x00 "TCD14_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x38030++0x03
line.long 0x00 "TCD14_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x38034++0x01
line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x38036++0x01
line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x38036++0x01
line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x38038++0x03
line.long 0x00 "TCD14_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x3803C++0x01
line.word 0x00 "TCD14_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x3803E++0x01
line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x3803E++0x01
line.word 0x00 "TCD14_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x3C000++0x03
line.long 0x00 "CH15_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x3C004++0x03
line.long 0x00 "CH15_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x3C008++0x03
line.long 0x00 "CH15_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x3C00C++0x03
line.long 0x00 "CH15_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3C010++0x03
line.long 0x00 "CH15_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x3C020++0x03
line.long 0x00 "TCD15_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x3C024++0x01
line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x3C026++0x01
line.word 0x00 "TCD15_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x3C028++0x03
line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x3C028++0x03
line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x3C02C++0x03
line.long 0x00 "TCD15_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x3C030++0x03
line.long 0x00 "TCD15_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x3C034++0x01
line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x3C036++0x01
line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x3C036++0x01
line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x3C038++0x03
line.long 0x00 "TCD15_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x3C03C++0x01
line.word 0x00 "TCD15_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x3C03E++0x01
line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x3C03E++0x01
line.word 0x00 "TCD15_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x200000++0x03
line.long 0x00 "CH16_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x200004++0x03
line.long 0x00 "CH16_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x200008++0x03
line.long 0x00 "CH16_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x20000C++0x03
line.long 0x00 "CH16_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x200010++0x03
line.long 0x00 "CH16_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x200020++0x03
line.long 0x00 "TCD16_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x200024++0x01
line.word 0x00 "TCD16_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x200026++0x01
line.word 0x00 "TCD16_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x200028++0x03
line.long 0x00 "TCD16_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x200028++0x03
line.long 0x00 "TCD16_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x20002C++0x03
line.long 0x00 "TCD16_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x200030++0x03
line.long 0x00 "TCD16_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x200034++0x01
line.word 0x00 "TCD16_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x200036++0x01
line.word 0x00 "TCD16_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x200036++0x01
line.word 0x00 "TCD16_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x200038++0x03
line.long 0x00 "TCD16_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x20003C++0x01
line.word 0x00 "TCD16_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x20003E++0x01
line.word 0x00 "TCD16_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x20003E++0x01
line.word 0x00 "TCD16_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x204000++0x03
line.long 0x00 "CH17_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x204004++0x03
line.long 0x00 "CH17_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x204008++0x03
line.long 0x00 "CH17_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x20400C++0x03
line.long 0x00 "CH17_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x204010++0x03
line.long 0x00 "CH17_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x204020++0x03
line.long 0x00 "TCD17_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x204024++0x01
line.word 0x00 "TCD17_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x204026++0x01
line.word 0x00 "TCD17_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x204028++0x03
line.long 0x00 "TCD17_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x204028++0x03
line.long 0x00 "TCD17_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x20402C++0x03
line.long 0x00 "TCD17_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x204030++0x03
line.long 0x00 "TCD17_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x204034++0x01
line.word 0x00 "TCD17_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x204036++0x01
line.word 0x00 "TCD17_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x204036++0x01
line.word 0x00 "TCD17_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x204038++0x03
line.long 0x00 "TCD17_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x20403C++0x01
line.word 0x00 "TCD17_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x20403E++0x01
line.word 0x00 "TCD17_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x20403E++0x01
line.word 0x00 "TCD17_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x208000++0x03
line.long 0x00 "CH18_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x208004++0x03
line.long 0x00 "CH18_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x208008++0x03
line.long 0x00 "CH18_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x20800C++0x03
line.long 0x00 "CH18_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x208010++0x03
line.long 0x00 "CH18_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x208020++0x03
line.long 0x00 "TCD18_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x208024++0x01
line.word 0x00 "TCD18_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x208026++0x01
line.word 0x00 "TCD18_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x208028++0x03
line.long 0x00 "TCD18_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x208028++0x03
line.long 0x00 "TCD18_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x20802C++0x03
line.long 0x00 "TCD18_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x208030++0x03
line.long 0x00 "TCD18_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x208034++0x01
line.word 0x00 "TCD18_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x208036++0x01
line.word 0x00 "TCD18_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x208036++0x01
line.word 0x00 "TCD18_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x208038++0x03
line.long 0x00 "TCD18_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x20803C++0x01
line.word 0x00 "TCD18_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x20803E++0x01
line.word 0x00 "TCD18_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x20803E++0x01
line.word 0x00 "TCD18_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x20C000++0x03
line.long 0x00 "CH19_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x20C004++0x03
line.long 0x00 "CH19_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x20C008++0x03
line.long 0x00 "CH19_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x20C00C++0x03
line.long 0x00 "CH19_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x20C010++0x03
line.long 0x00 "CH19_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x20C020++0x03
line.long 0x00 "TCD19_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x20C024++0x01
line.word 0x00 "TCD19_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x20C026++0x01
line.word 0x00 "TCD19_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x20C028++0x03
line.long 0x00 "TCD19_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x20C028++0x03
line.long 0x00 "TCD19_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x20C02C++0x03
line.long 0x00 "TCD19_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x20C030++0x03
line.long 0x00 "TCD19_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x20C034++0x01
line.word 0x00 "TCD19_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x20C036++0x01
line.word 0x00 "TCD19_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x20C036++0x01
line.word 0x00 "TCD19_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x20C038++0x03
line.long 0x00 "TCD19_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x20C03C++0x01
line.word 0x00 "TCD19_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x20C03E++0x01
line.word 0x00 "TCD19_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x20C03E++0x01
line.word 0x00 "TCD19_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x210000++0x03
line.long 0x00 "CH20_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x210004++0x03
line.long 0x00 "CH20_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x210008++0x03
line.long 0x00 "CH20_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x21000C++0x03
line.long 0x00 "CH20_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x210010++0x03
line.long 0x00 "CH20_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x210020++0x03
line.long 0x00 "TCD20_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x210024++0x01
line.word 0x00 "TCD20_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x210026++0x01
line.word 0x00 "TCD20_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x210028++0x03
line.long 0x00 "TCD20_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x210028++0x03
line.long 0x00 "TCD20_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x21002C++0x03
line.long 0x00 "TCD20_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x210030++0x03
line.long 0x00 "TCD20_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x210034++0x01
line.word 0x00 "TCD20_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x210036++0x01
line.word 0x00 "TCD20_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x210036++0x01
line.word 0x00 "TCD20_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x210038++0x03
line.long 0x00 "TCD20_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x21003C++0x01
line.word 0x00 "TCD20_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x21003E++0x01
line.word 0x00 "TCD20_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x21003E++0x01
line.word 0x00 "TCD20_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x214000++0x03
line.long 0x00 "CH21_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x214004++0x03
line.long 0x00 "CH21_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x214008++0x03
line.long 0x00 "CH21_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x21400C++0x03
line.long 0x00 "CH21_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x214010++0x03
line.long 0x00 "CH21_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x214020++0x03
line.long 0x00 "TCD21_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x214024++0x01
line.word 0x00 "TCD21_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x214026++0x01
line.word 0x00 "TCD21_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x214028++0x03
line.long 0x00 "TCD21_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x214028++0x03
line.long 0x00 "TCD21_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x21402C++0x03
line.long 0x00 "TCD21_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x214030++0x03
line.long 0x00 "TCD21_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x214034++0x01
line.word 0x00 "TCD21_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x214036++0x01
line.word 0x00 "TCD21_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x214036++0x01
line.word 0x00 "TCD21_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x214038++0x03
line.long 0x00 "TCD21_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x21403C++0x01
line.word 0x00 "TCD21_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x21403E++0x01
line.word 0x00 "TCD21_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x21403E++0x01
line.word 0x00 "TCD21_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x218000++0x03
line.long 0x00 "CH22_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x218004++0x03
line.long 0x00 "CH22_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x218008++0x03
line.long 0x00 "CH22_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x21800C++0x03
line.long 0x00 "CH22_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x218010++0x03
line.long 0x00 "CH22_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x218020++0x03
line.long 0x00 "TCD22_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x218024++0x01
line.word 0x00 "TCD22_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x218026++0x01
line.word 0x00 "TCD22_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x218028++0x03
line.long 0x00 "TCD22_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x218028++0x03
line.long 0x00 "TCD22_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x21802C++0x03
line.long 0x00 "TCD22_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x218030++0x03
line.long 0x00 "TCD22_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x218034++0x01
line.word 0x00 "TCD22_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x218036++0x01
line.word 0x00 "TCD22_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x218036++0x01
line.word 0x00 "TCD22_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x218038++0x03
line.long 0x00 "TCD22_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x21803C++0x01
line.word 0x00 "TCD22_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x21803E++0x01
line.word 0x00 "TCD22_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x21803E++0x01
line.word 0x00 "TCD22_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x21C000++0x03
line.long 0x00 "CH23_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x21C004++0x03
line.long 0x00 "CH23_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x21C008++0x03
line.long 0x00 "CH23_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x21C00C++0x03
line.long 0x00 "CH23_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21C010++0x03
line.long 0x00 "CH23_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x21C020++0x03
line.long 0x00 "TCD23_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x21C024++0x01
line.word 0x00 "TCD23_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x21C026++0x01
line.word 0x00 "TCD23_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x21C028++0x03
line.long 0x00 "TCD23_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x21C028++0x03
line.long 0x00 "TCD23_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x21C02C++0x03
line.long 0x00 "TCD23_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x21C030++0x03
line.long 0x00 "TCD23_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x21C034++0x01
line.word 0x00 "TCD23_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x21C036++0x01
line.word 0x00 "TCD23_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x21C036++0x01
line.word 0x00 "TCD23_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x21C038++0x03
line.long 0x00 "TCD23_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x21C03C++0x01
line.word 0x00 "TCD23_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x21C03E++0x01
line.word 0x00 "TCD23_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x21C03E++0x01
line.word 0x00 "TCD23_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x220000++0x03
line.long 0x00 "CH24_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x220004++0x03
line.long 0x00 "CH24_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x220008++0x03
line.long 0x00 "CH24_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x22000C++0x03
line.long 0x00 "CH24_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x220010++0x03
line.long 0x00 "CH24_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x220020++0x03
line.long 0x00 "TCD24_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x220024++0x01
line.word 0x00 "TCD24_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x220026++0x01
line.word 0x00 "TCD24_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x220028++0x03
line.long 0x00 "TCD24_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x220028++0x03
line.long 0x00 "TCD24_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x22002C++0x03
line.long 0x00 "TCD24_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x220030++0x03
line.long 0x00 "TCD24_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x220034++0x01
line.word 0x00 "TCD24_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x220036++0x01
line.word 0x00 "TCD24_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x220036++0x01
line.word 0x00 "TCD24_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x220038++0x03
line.long 0x00 "TCD24_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x22003C++0x01
line.word 0x00 "TCD24_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x22003E++0x01
line.word 0x00 "TCD24_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x22003E++0x01
line.word 0x00 "TCD24_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x224000++0x03
line.long 0x00 "CH25_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x224004++0x03
line.long 0x00 "CH25_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x224008++0x03
line.long 0x00 "CH25_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x22400C++0x03
line.long 0x00 "CH25_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x224010++0x03
line.long 0x00 "CH25_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x224020++0x03
line.long 0x00 "TCD25_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x224024++0x01
line.word 0x00 "TCD25_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x224026++0x01
line.word 0x00 "TCD25_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x224028++0x03
line.long 0x00 "TCD25_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x224028++0x03
line.long 0x00 "TCD25_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x22402C++0x03
line.long 0x00 "TCD25_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x224030++0x03
line.long 0x00 "TCD25_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x224034++0x01
line.word 0x00 "TCD25_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x224036++0x01
line.word 0x00 "TCD25_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x224036++0x01
line.word 0x00 "TCD25_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x224038++0x03
line.long 0x00 "TCD25_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x22403C++0x01
line.word 0x00 "TCD25_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x22403E++0x01
line.word 0x00 "TCD25_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x22403E++0x01
line.word 0x00 "TCD25_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x228000++0x03
line.long 0x00 "CH26_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x228004++0x03
line.long 0x00 "CH26_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x228008++0x03
line.long 0x00 "CH26_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x22800C++0x03
line.long 0x00 "CH26_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x228010++0x03
line.long 0x00 "CH26_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x228020++0x03
line.long 0x00 "TCD26_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x228024++0x01
line.word 0x00 "TCD26_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x228026++0x01
line.word 0x00 "TCD26_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x228028++0x03
line.long 0x00 "TCD26_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x228028++0x03
line.long 0x00 "TCD26_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x22802C++0x03
line.long 0x00 "TCD26_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x228030++0x03
line.long 0x00 "TCD26_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x228034++0x01
line.word 0x00 "TCD26_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x228036++0x01
line.word 0x00 "TCD26_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x228036++0x01
line.word 0x00 "TCD26_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x228038++0x03
line.long 0x00 "TCD26_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x22803C++0x01
line.word 0x00 "TCD26_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x22803E++0x01
line.word 0x00 "TCD26_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x22803E++0x01
line.word 0x00 "TCD26_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x22C000++0x03
line.long 0x00 "CH27_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x22C004++0x03
line.long 0x00 "CH27_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x22C008++0x03
line.long 0x00 "CH27_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x22C00C++0x03
line.long 0x00 "CH27_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22C010++0x03
line.long 0x00 "CH27_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x22C020++0x03
line.long 0x00 "TCD27_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x22C024++0x01
line.word 0x00 "TCD27_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x22C026++0x01
line.word 0x00 "TCD27_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x22C028++0x03
line.long 0x00 "TCD27_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x22C028++0x03
line.long 0x00 "TCD27_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x22C02C++0x03
line.long 0x00 "TCD27_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x22C030++0x03
line.long 0x00 "TCD27_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x22C034++0x01
line.word 0x00 "TCD27_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x22C036++0x01
line.word 0x00 "TCD27_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x22C036++0x01
line.word 0x00 "TCD27_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x22C038++0x03
line.long 0x00 "TCD27_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x22C03C++0x01
line.word 0x00 "TCD27_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x22C03E++0x01
line.word 0x00 "TCD27_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x22C03E++0x01
line.word 0x00 "TCD27_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x230000++0x03
line.long 0x00 "CH28_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x230004++0x03
line.long 0x00 "CH28_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x230008++0x03
line.long 0x00 "CH28_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x23000C++0x03
line.long 0x00 "CH28_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x230010++0x03
line.long 0x00 "CH28_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x230020++0x03
line.long 0x00 "TCD28_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x230024++0x01
line.word 0x00 "TCD28_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x230026++0x01
line.word 0x00 "TCD28_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x230028++0x03
line.long 0x00 "TCD28_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x230028++0x03
line.long 0x00 "TCD28_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x23002C++0x03
line.long 0x00 "TCD28_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x230030++0x03
line.long 0x00 "TCD28_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x230034++0x01
line.word 0x00 "TCD28_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x230036++0x01
line.word 0x00 "TCD28_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x230036++0x01
line.word 0x00 "TCD28_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x230038++0x03
line.long 0x00 "TCD28_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x23003C++0x01
line.word 0x00 "TCD28_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x23003E++0x01
line.word 0x00 "TCD28_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x23003E++0x01
line.word 0x00 "TCD28_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x234000++0x03
line.long 0x00 "CH29_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x234004++0x03
line.long 0x00 "CH29_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x234008++0x03
line.long 0x00 "CH29_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x23400C++0x03
line.long 0x00 "CH29_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x234010++0x03
line.long 0x00 "CH29_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x234020++0x03
line.long 0x00 "TCD29_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x234024++0x01
line.word 0x00 "TCD29_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x234026++0x01
line.word 0x00 "TCD29_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x234028++0x03
line.long 0x00 "TCD29_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x234028++0x03
line.long 0x00 "TCD29_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x23402C++0x03
line.long 0x00 "TCD29_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x234030++0x03
line.long 0x00 "TCD29_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x234034++0x01
line.word 0x00 "TCD29_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x234036++0x01
line.word 0x00 "TCD29_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x234036++0x01
line.word 0x00 "TCD29_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x234038++0x03
line.long 0x00 "TCD29_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x23403C++0x01
line.word 0x00 "TCD29_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x23403E++0x01
line.word 0x00 "TCD29_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x23403E++0x01
line.word 0x00 "TCD29_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x238000++0x03
line.long 0x00 "CH30_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x238004++0x03
line.long 0x00 "CH30_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x238008++0x03
line.long 0x00 "CH30_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x23800C++0x03
line.long 0x00 "CH30_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x238010++0x03
line.long 0x00 "CH30_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x238020++0x03
line.long 0x00 "TCD30_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x238024++0x01
line.word 0x00 "TCD30_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x238026++0x01
line.word 0x00 "TCD30_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x238028++0x03
line.long 0x00 "TCD30_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x238028++0x03
line.long 0x00 "TCD30_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x23802C++0x03
line.long 0x00 "TCD30_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x238030++0x03
line.long 0x00 "TCD30_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x238034++0x01
line.word 0x00 "TCD30_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x238036++0x01
line.word 0x00 "TCD30_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x238036++0x01
line.word 0x00 "TCD30_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x238038++0x03
line.long 0x00 "TCD30_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x23803C++0x01
line.word 0x00 "TCD30_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x23803E++0x01
line.word 0x00 "TCD30_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x23803E++0x01
line.word 0x00 "TCD30_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
group.long 0x23C000++0x03
line.long 0x00 "CH31_CSR,Channel Control and Status"
rbitfld.long 0x00 31. "ACTIVE,Channel Active" "0,1"
eventfld.long 0x00 30. "DONE,Channel Done" "0,1"
newline
bitfld.long 0x00 3. "EBW,Enable Buffered Writes" "0: Buffered writes on system bus disabled,1: Buffered writes on system bus enabled"
bitfld.long 0x00 2. "EEI,Enable Error Interrupt" "0: Error signal for corresponding channel does..,1: Assertion of error signal for corresponding.."
newline
bitfld.long 0x00 1. "EARQ,Enable Asynchronous DMA Request" "0: Disable asynchronous DMA request for the..,1: Enable asynchronous DMA request for the channel"
bitfld.long 0x00 0. "ERQ,Enable DMA Request" "0: DMA hardware request signal for corresponding..,1: DMA hardware request signal for corresponding.."
group.long 0x23C004++0x03
line.long 0x00 "CH31_ES,Channel Error Status"
eventfld.long 0x00 31. "ERR,Error In Channel" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
rbitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,1: Last recorded error was a configuration error.."
newline
rbitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: Last recorded error was a configuration error.."
rbitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: Last recorded error was bus error on source"
newline
rbitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: Last recorded error was bus error on.."
group.long 0x23C008++0x03
line.long 0x00 "CH31_INT,Channel Interrupt Status"
eventfld.long 0x00 0. "INT,Interrupt Request" "0: Interrupt request for corresponding channel..,1: Interrupt request for corresponding channel.."
group.long 0x23C00C++0x03
line.long 0x00 "CH31_SBR,Channel System Bus"
bitfld.long 0x00 17.--19. "ATTR,Attribute Output" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "EMI,Enable Master ID Replication" "0: Master ID replication is disabled,1: Master ID replication is enabled"
newline
rbitfld.long 0x00 15. "PAL,Privileged Access Level" "0: User protection level for DMA transfers,1: Privileged protection level for DMA transfers"
rbitfld.long 0x00 0.--4. "MID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x23C010++0x03
line.long 0x00 "CH31_PRI,Channel Priority"
bitfld.long 0x00 31. "ECP,Enable Channel Preemption" "0: Channel cannot be suspended by a..,1: Channel can be temporarily suspended by a.."
bitfld.long 0x00 30. "DPA,Disable Preempt Ability" "0: Channel can suspend a lower-priority channel,1: Channel cannot suspend any other channel.."
newline
bitfld.long 0x00 0.--2. "APL,Arbitration Priority Level" "0,1,2,3,4,5,6,7"
group.long 0x23C020++0x03
line.long 0x00 "TCD31_SADDR,TCD Source Address"
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
group.word 0x23C024++0x01
line.word 0x00 "TCD31_SOFF,TCD Signed Source Address Offset"
hexmask.word 0x00 0.--15. 1. "SOFF,Source Address Signed Offset"
group.word 0x23C026++0x01
line.word 0x00 "TCD31_ATTR,TCD Transfer Attributes"
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature disabled,1: Source address modulo feature enabled for any..,?..."
bitfld.word 0x00 8.--10. "SSIZE,Source Data Transfer Size" "0: EIGHT_BIT,1: SIXTEEN_BIT,2: THIRTYTWO_BIT,3: SIXTYFOUR_BIT,4: SIXTEEN_BYTE,5: THIRTYTWO_BYTE,6: SIXTYFOUR_BYTE,?..."
newline
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.word 0x00 0.--2. "DSIZE,Destination Data Transfer Size" "0,1,2,3,4,5,6,7"
group.long 0x23C028++0x03
line.long 0x00 "TCD31_NBYTES_MLOFFNO,TCD Transfer Size Without Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long 0x00 0.--29. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x23C028++0x03
line.long 0x00 "TCD31_NBYTES_MLOFFYES,TCD Transfer Size with Minor Loop Offsets"
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: Minor loop offset not applied to SADDR,1: Minor loop offset applied to SADDR"
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset Enable" "0: Minor loop offset not applied to DADDR,1: Minor loop offset applied to DADDR"
newline
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,Minor Loop Offset"
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Number of Bytes To Transfer Per Service Request"
group.long 0x23C02C++0x03
line.long 0x00 "TCD31_SLAST_SDA,TCD Last Source Address Adjustment / Store DADDR Address"
hexmask.long 0x00 0.--31. 1. "SLAST_SDA,Last Source Address Adjustment / Store DADDR Address"
group.long 0x23C030++0x03
line.long 0x00 "TCD31_DADDR,TCD Destination Address"
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
group.word 0x23C034++0x01
line.word 0x00 "TCD31_DOFF,TCD Signed Destination Address Offset"
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
group.word 0x23C036++0x01
line.word 0x00 "TCD31_CITER_ELINKNO,TCD Current Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
group.word 0x23C036++0x01
line.word 0x00 "TCD31_CITER_ELINKYES,TCD Current Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "CITER,Current Major Iteration Count"
group.long 0x23C038++0x03
line.long 0x00 "TCD31_DLAST_SGA,TCD Last Destination Address Adjustment / Scatter Gather Address"
hexmask.long 0x00 0.--31. 1. "DLAST_SGA,Last Destination Address Adjustment / Scatter Gather Address"
group.word 0x23C03C++0x01
line.word 0x00 "TCD31_CSR,TCD Control and Status"
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,1: Enable eDMA master high-priority elevation..,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
bitfld.word 0x00 8.--12. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.word 0x00 7. "ESDA,Enable Store Destination Address" "0: Ability to store destination address to..,1: Ability to store destination address to.."
bitfld.word 0x00 5. "MAJORELINK,Enable Link When Major Loop Complete" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
newline
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: Current channel's TCD is normal format,1: Current channel's TCD specifies.."
bitfld.word 0x00 3. "DREQ,Disable Request" "0: CHANNEL_NOT_AFFECTED,1: Clear the ERQ field to 0 upon major loop.."
newline
bitfld.word 0x00 2. "INTHALF,Enable Interrupt If Major Counter Half-complete" "0: Halfway point interrupt disabled,1: Halfway point interrupt enabled"
bitfld.word 0x00 1. "INTMAJOR,Enable Interrupt If Major count complete" "0: End-of-major loop interrupt disabled,1: End-of-major loop interrupt enabled"
newline
bitfld.word 0x00 0. "START,Channel Start" "0: Channel not explicitly started,1: Channel explicitly started via a.."
group.word 0x23C03E++0x01
line.word 0x00 "TCD31_BITER_ELINKNO,TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled)"
bitfld.word 0x00 15. "ELINK,Enables Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
group.word 0x23C03E++0x01
line.word 0x00 "TCD31_BITER_ELINKYES,TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled)"
bitfld.word 0x00 15. "ELINK,Enable Link" "0: Channel-to-channel linking disabled,1: Channel-to-channel linking enabled"
bitfld.word 0x00 9.--13. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.word 0x00 0.--8. 1. "BITER,Starting Major Iteration Count"
tree.end
tree "DMAMUX"
repeat 2. (list 0. 1.) (list ad:0x402C0000 ad:0x404C0000)
tree "DMAMUX_$1"
base $2
repeat 16. (strings "3" "2" "1" "0" "7" "6" "5" "4" "11" "10" "9" "8" "15" "14" "13" "12" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x00)++0x00
line.byte 0x00 "CHCFG$1,Channel Configuration register"
bitfld.byte 0x00 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled,1: DMA channel is enabled"
bitfld.byte 0x00 6. "TRIG,DMA Channel Trigger Enable" "0: Triggering is disabled,1: Triggering is enabled"
bitfld.byte 0x00 0.--5. "SOURCE,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
tree.end
repeat.end
tree.end
tree "EIM"
tree "EIM_A53"
base ad:0x440AD000
group.long 0x00++0x03
line.long 0x00 "EIMCR,Error Injection Module Configuration Register"
bitfld.long 0x00 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled"
group.long 0x04++0x03
line.long 0x00 "EICHEN,Error Injection Channel Enable register"
bitfld.long 0x00 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
group.long 0x104++0x03
line.long 0x00 "EICHD0_WORD1,Error Injection Channel Descriptor 0 Word1"
hexmask.long.word 0x00 0.--11. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x108++0x03
line.long 0x00 "EICHD0_WORD2,Error Injection Channel Descriptor 0 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
tree.end
tree "EIM_AP1"
base ad:0x440E4000
group.long 0x00++0x03
line.long 0x00 "EIMCR,Error Injection Module Configuration Register"
bitfld.long 0x00 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled"
group.long 0x04++0x03
line.long 0x00 "EICHEN,Error Injection Channel Enable register"
bitfld.long 0x00 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
group.long 0x100++0x03
line.long 0x00 "EICHD0_WORD0,Error Injection Channel Descriptor 0 Word0"
hexmask.long 0x00 0.--31. 1. "CHKBIT_MASK,Checkbit Mask"
group.long 0x104++0x03
line.long 0x00 "EICHD0_WORD1,Error Injection Channel Descriptor 0 Word1"
hexmask.long 0x00 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x108++0x03
line.long 0x00 "EICHD0_WORD2,Error Injection Channel Descriptor 0 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x10C++0x03
line.long 0x00 "EICHD0_WORD3,Error Injection Channel Descriptor 0 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x110++0x03
line.long 0x00 "EICHD0_WORD4,Error Injection Channel Descriptor 0 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x114++0x03
line.long 0x00 "EICHD0_WORD5,Error Injection Channel Descriptor 0 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x118++0x03
line.long 0x00 "EICHD0_WORD6,Error Injection Channel Descriptor 0 Word6"
hexmask.long 0x00 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23"
group.long 0x11C++0x03
line.long 0x00 "EICHD0_WORD7,Error Injection Channel Descriptor 0 Word7"
hexmask.long 0x00 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27"
group.long 0x120++0x03
line.long 0x00 "EICHD0_WORD8,Error Injection Channel Descriptor 0 Word8"
hexmask.long 0x00 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31"
group.long 0x140++0x03
line.long 0x00 "EICHD1_WORD0,Error Injection Channel Descriptor 1 Word0"
hexmask.long 0x00 0.--31. 1. "CHKBIT_MASK,Checkbit Mask"
group.long 0x144++0x03
line.long 0x00 "EICHD1_WORD1,Error Injection Channel Descriptor 1 Word1"
hexmask.long 0x00 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x148++0x03
line.long 0x00 "EICHD1_WORD2,Error Injection Channel Descriptor 1 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x14C++0x03
line.long 0x00 "EICHD1_WORD3,Error Injection Channel Descriptor 1 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x150++0x03
line.long 0x00 "EICHD1_WORD4,Error Injection Channel Descriptor 1 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x154++0x03
line.long 0x00 "EICHD1_WORD5,Error Injection Channel Descriptor 1 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x158++0x03
line.long 0x00 "EICHD1_WORD6,Error Injection Channel Descriptor 1 Word6"
hexmask.long 0x00 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23"
group.long 0x15C++0x03
line.long 0x00 "EICHD1_WORD7,Error Injection Channel Descriptor 1 Word7"
hexmask.long 0x00 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27"
group.long 0x160++0x03
line.long 0x00 "EICHD1_WORD8,Error Injection Channel Descriptor 1 Word8"
hexmask.long 0x00 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31"
tree.end
repeat 2. (list 0. 1.) (list ad:0x40150000 ad:0x40154000)
tree "EIM_CM7_$1"
base $2
group.long 0x00++0x03
line.long 0x00 "EIMCR,Error Injection Module Configuration Register"
bitfld.long 0x00 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled"
group.long 0x04++0x03
line.long 0x00 "EICHEN,Error Injection Channel Enable register"
bitfld.long 0x00 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
group.long 0x100++0x03
line.long 0x00 "EICHD0_WORD0,Error Injection Channel Descriptor 0 Word0"
hexmask.long.word 0x00 16.--31. 1. "CHKBIT_MASK,Checkbit Mask"
group.long 0x104++0x03
line.long 0x00 "EICHD0_WORD1,Error Injection Channel Descriptor 0 Word1"
hexmask.long 0x00 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x108++0x03
line.long 0x00 "EICHD0_WORD2,Error Injection Channel Descriptor 0 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x140++0x03
line.long 0x00 "EICHD1_WORD0,Error Injection Channel Descriptor 1 Word0"
hexmask.long.word 0x00 18.--31. 1. "CHKBIT_MASK,Checkbit Mask"
group.long 0x144++0x03
line.long 0x00 "EICHD1_WORD1,Error Injection Channel Descriptor 1 Word1"
hexmask.long.word 0x00 0.--11. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x148++0x03
line.long 0x00 "EICHD1_WORD2,Error Injection Channel Descriptor 1 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x180++0x03
line.long 0x00 "EICHD2_WORD0,Error Injection Channel Descriptor 2 Word0"
hexmask.long.word 0x00 16.--31. 1. "CHKBIT_MASK,Checkbit Mask"
group.long 0x184++0x03
line.long 0x00 "EICHD2_WORD1,Error Injection Channel Descriptor 2 Word1"
hexmask.long 0x00 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x188++0x03
line.long 0x00 "EICHD2_WORD2,Error Injection Channel Descriptor 2 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x18C++0x03
line.long 0x00 "EICHD2_WORD3,Error Injection Channel Descriptor 2 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x190++0x03
line.long 0x00 "EICHD2_WORD4,Error Injection Channel Descriptor 2 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x1C0++0x03
line.long 0x00 "EICHD3_WORD0,Error Injection Channel Descriptor 3 Word0"
hexmask.long 0x00 4.--31. 1. "CHKBIT_MASK,Checkbit Mask"
group.long 0x1C4++0x03
line.long 0x00 "EICHD3_WORD1,Error Injection Channel Descriptor 3 Word1"
hexmask.long.byte 0x00 0.--7. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x1C8++0x03
line.long 0x00 "EICHD3_WORD2,Error Injection Channel Descriptor 3 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x1CC++0x03
line.long 0x00 "EICHD3_WORD3,Error Injection Channel Descriptor 3 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x1D0++0x03
line.long 0x00 "EICHD3_WORD4,Error Injection Channel Descriptor 3 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x200++0x03
line.long 0x00 "EICHD4_WORD0,Error Injection Channel Descriptor 4 Word0"
hexmask.long 0x00 4.--31. 1. "CHKBIT_MASK,Checkbit Mask"
group.long 0x204++0x03
line.long 0x00 "EICHD4_WORD1,Error Injection Channel Descriptor 4 Word1"
hexmask.long 0x00 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x208++0x03
line.long 0x00 "EICHD4_WORD2,Error Injection Channel Descriptor 4 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x20C++0x03
line.long 0x00 "EICHD4_WORD3,Error Injection Channel Descriptor 4 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x210++0x03
line.long 0x00 "EICHD4_WORD4,Error Injection Channel Descriptor 4 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x240++0x03
line.long 0x00 "EICHD5_WORD0,Error Injection Channel Descriptor 5 Word0"
hexmask.long 0x00 4.--31. 1. "CHKBIT_MASK,Checkbit Mask"
group.long 0x244++0x03
line.long 0x00 "EICHD5_WORD1,Error Injection Channel Descriptor 5 Word1"
hexmask.long 0x00 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x248++0x03
line.long 0x00 "EICHD5_WORD2,Error Injection Channel Descriptor 5 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x24C++0x03
line.long 0x00 "EICHD5_WORD3,Error Injection Channel Descriptor 5 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x250++0x03
line.long 0x00 "EICHD5_WORD4,Error Injection Channel Descriptor 5 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x284++0x03
line.long 0x00 "EICHD6_WORD1,Error Injection Channel Descriptor 6 Word1"
hexmask.long 0x00 0.--29. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
tree.end
repeat.end
tree "EIM_DSP"
base ad:0x440A4000
group.long 0x00++0x03
line.long 0x00 "EIMCR,Error Injection Module Configuration Register"
bitfld.long 0x00 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled"
group.long 0x04++0x03
line.long 0x00 "EICHEN,Error Injection Channel Enable register"
bitfld.long 0x00 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 19. "EICH12EN,Error Injection Channel 12 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 18. "EICH13EN,Error Injection Channel 13 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 17. "EICH14EN,Error Injection Channel 14 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 16. "EICH15EN,Error Injection Channel 15 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 15. "EICH16EN,Error Injection Channel 16 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 14. "EICH17EN,Error Injection Channel 17 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 13. "EICH18EN,Error Injection Channel 18 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 12. "EICH19EN,Error Injection Channel 19 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
group.long 0x104++0x03
line.long 0x00 "EICHD0_WORD1,Error Injection Channel Descriptor 0 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x108++0x03
line.long 0x00 "EICHD0_WORD2,Error Injection Channel Descriptor 0 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x10C++0x03
line.long 0x00 "EICHD0_WORD3,Error Injection Channel Descriptor 0 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x110++0x03
line.long 0x00 "EICHD0_WORD4,Error Injection Channel Descriptor 0 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x114++0x03
line.long 0x00 "EICHD0_WORD5,Error Injection Channel Descriptor 0 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x144++0x03
line.long 0x00 "EICHD1_WORD1,Error Injection Channel Descriptor 1 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x148++0x03
line.long 0x00 "EICHD1_WORD2,Error Injection Channel Descriptor 1 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x14C++0x03
line.long 0x00 "EICHD1_WORD3,Error Injection Channel Descriptor 1 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x150++0x03
line.long 0x00 "EICHD1_WORD4,Error Injection Channel Descriptor 1 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x154++0x03
line.long 0x00 "EICHD1_WORD5,Error Injection Channel Descriptor 1 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x184++0x03
line.long 0x00 "EICHD2_WORD1,Error Injection Channel Descriptor 2 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x188++0x03
line.long 0x00 "EICHD2_WORD2,Error Injection Channel Descriptor 2 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x18C++0x03
line.long 0x00 "EICHD2_WORD3,Error Injection Channel Descriptor 2 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x190++0x03
line.long 0x00 "EICHD2_WORD4,Error Injection Channel Descriptor 2 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x194++0x03
line.long 0x00 "EICHD2_WORD5,Error Injection Channel Descriptor 2 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x1C4++0x03
line.long 0x00 "EICHD3_WORD1,Error Injection Channel Descriptor 3 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x1C8++0x03
line.long 0x00 "EICHD3_WORD2,Error Injection Channel Descriptor 3 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x1CC++0x03
line.long 0x00 "EICHD3_WORD3,Error Injection Channel Descriptor 3 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x1D0++0x03
line.long 0x00 "EICHD3_WORD4,Error Injection Channel Descriptor 3 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x1D4++0x03
line.long 0x00 "EICHD3_WORD5,Error Injection Channel Descriptor 3 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x204++0x03
line.long 0x00 "EICHD4_WORD1,Error Injection Channel Descriptor 4 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x208++0x03
line.long 0x00 "EICHD4_WORD2,Error Injection Channel Descriptor 4 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x20C++0x03
line.long 0x00 "EICHD4_WORD3,Error Injection Channel Descriptor 4 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x210++0x03
line.long 0x00 "EICHD4_WORD4,Error Injection Channel Descriptor 4 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x214++0x03
line.long 0x00 "EICHD4_WORD5,Error Injection Channel Descriptor 4 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x244++0x03
line.long 0x00 "EICHD5_WORD1,Error Injection Channel Descriptor 5 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x248++0x03
line.long 0x00 "EICHD5_WORD2,Error Injection Channel Descriptor 5 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x24C++0x03
line.long 0x00 "EICHD5_WORD3,Error Injection Channel Descriptor 5 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x250++0x03
line.long 0x00 "EICHD5_WORD4,Error Injection Channel Descriptor 5 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x254++0x03
line.long 0x00 "EICHD5_WORD5,Error Injection Channel Descriptor 5 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x284++0x03
line.long 0x00 "EICHD6_WORD1,Error Injection Channel Descriptor 6 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x288++0x03
line.long 0x00 "EICHD6_WORD2,Error Injection Channel Descriptor 6 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x28C++0x03
line.long 0x00 "EICHD6_WORD3,Error Injection Channel Descriptor 6 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x290++0x03
line.long 0x00 "EICHD6_WORD4,Error Injection Channel Descriptor 6 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x294++0x03
line.long 0x00 "EICHD6_WORD5,Error Injection Channel Descriptor 6 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x2C4++0x03
line.long 0x00 "EICHD7_WORD1,Error Injection Channel Descriptor 7 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x2C8++0x03
line.long 0x00 "EICHD7_WORD2,Error Injection Channel Descriptor 7 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x2CC++0x03
line.long 0x00 "EICHD7_WORD3,Error Injection Channel Descriptor 7 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x2D0++0x03
line.long 0x00 "EICHD7_WORD4,Error Injection Channel Descriptor 7 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x2D4++0x03
line.long 0x00 "EICHD7_WORD5,Error Injection Channel Descriptor 7 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x304++0x03
line.long 0x00 "EICHD8_WORD1,Error Injection Channel Descriptor 8 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x308++0x03
line.long 0x00 "EICHD8_WORD2,Error Injection Channel Descriptor 8 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x30C++0x03
line.long 0x00 "EICHD8_WORD3,Error Injection Channel Descriptor 8 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x310++0x03
line.long 0x00 "EICHD8_WORD4,Error Injection Channel Descriptor 8 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x314++0x03
line.long 0x00 "EICHD8_WORD5,Error Injection Channel Descriptor 8 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x344++0x03
line.long 0x00 "EICHD9_WORD1,Error Injection Channel Descriptor 9 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x348++0x03
line.long 0x00 "EICHD9_WORD2,Error Injection Channel Descriptor 9 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x34C++0x03
line.long 0x00 "EICHD9_WORD3,Error Injection Channel Descriptor 9 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x350++0x03
line.long 0x00 "EICHD9_WORD4,Error Injection Channel Descriptor 9 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x354++0x03
line.long 0x00 "EICHD9_WORD5,Error Injection Channel Descriptor 9 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x384++0x03
line.long 0x00 "EICHD10_WORD1,Error Injection Channel Descriptor 10 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x388++0x03
line.long 0x00 "EICHD10_WORD2,Error Injection Channel Descriptor 10 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x38C++0x03
line.long 0x00 "EICHD10_WORD3,Error Injection Channel Descriptor 10 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x390++0x03
line.long 0x00 "EICHD10_WORD4,Error Injection Channel Descriptor 10 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x394++0x03
line.long 0x00 "EICHD10_WORD5,Error Injection Channel Descriptor 10 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x3C4++0x03
line.long 0x00 "EICHD11_WORD1,Error Injection Channel Descriptor 11 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x3C8++0x03
line.long 0x00 "EICHD11_WORD2,Error Injection Channel Descriptor 11 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x3CC++0x03
line.long 0x00 "EICHD11_WORD3,Error Injection Channel Descriptor 11 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x3D0++0x03
line.long 0x00 "EICHD11_WORD4,Error Injection Channel Descriptor 11 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x3D4++0x03
line.long 0x00 "EICHD11_WORD5,Error Injection Channel Descriptor 11 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x404++0x03
line.long 0x00 "EICHD12_WORD1,Error Injection Channel Descriptor 12 Word1"
hexmask.long 0x00 0.--26. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x444++0x03
line.long 0x00 "EICHD13_WORD1,Error Injection Channel Descriptor 13 Word1"
hexmask.long 0x00 0.--26. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x484++0x03
line.long 0x00 "EICHD14_WORD1,Error Injection Channel Descriptor 14 Word1"
hexmask.long 0x00 0.--30. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x4C4++0x03
line.long 0x00 "EICHD15_WORD1,Error Injection Channel Descriptor 15 Word1"
hexmask.long 0x00 0.--30. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x504++0x03
line.long 0x00 "EICHD16_WORD1,Error Injection Channel Descriptor 16 Word1"
hexmask.long 0x00 0.--30. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x544++0x03
line.long 0x00 "EICHD17_WORD1,Error Injection Channel Descriptor 17 Word1"
hexmask.long 0x00 0.--30. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x584++0x03
line.long 0x00 "EICHD18_WORD1,Error Injection Channel Descriptor 18 Word1"
hexmask.long 0x00 0.--30. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x5C4++0x03
line.long 0x00 "EICHD19_WORD1,Error Injection Channel Descriptor 19 Word1"
hexmask.long 0x00 0.--30. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
tree.end
tree "EIM_RT0"
base ad:0x40114000
group.long 0x00++0x03
line.long 0x00 "EIMCR,Error Injection Module Configuration Register"
bitfld.long 0x00 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled"
group.long 0x04++0x03
line.long 0x00 "EICHEN,Error Injection Channel Enable register"
bitfld.long 0x00 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 19. "EICH12EN,Error Injection Channel 12 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 18. "EICH13EN,Error Injection Channel 13 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
group.long 0x104++0x03
line.long 0x00 "EICHD0_WORD1,Error Injection Channel Descriptor 0 Word1"
hexmask.long.word 0x00 0.--15. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x108++0x03
line.long 0x00 "EICHD0_WORD2,Error Injection Channel Descriptor 0 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x10C++0x03
line.long 0x00 "EICHD0_WORD3,Error Injection Channel Descriptor 0 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x110++0x03
line.long 0x00 "EICHD0_WORD4,Error Injection Channel Descriptor 0 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x114++0x03
line.long 0x00 "EICHD0_WORD5,Error Injection Channel Descriptor 0 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x118++0x03
line.long 0x00 "EICHD0_WORD6,Error Injection Channel Descriptor 0 Word6"
hexmask.long 0x00 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23"
group.long 0x11C++0x03
line.long 0x00 "EICHD0_WORD7,Error Injection Channel Descriptor 0 Word7"
hexmask.long 0x00 0.--31. 1. "B24_27DATA_MASK,Data Mask Bytes 24-27"
group.long 0x120++0x03
line.long 0x00 "EICHD0_WORD8,Error Injection Channel Descriptor 0 Word8"
hexmask.long 0x00 0.--31. 1. "B28_31DATA_MASK,Data Mask Bytes 28-31"
group.long 0x144++0x03
line.long 0x00 "EICHD1_WORD1,Error Injection Channel Descriptor 1 Word1"
hexmask.long.word 0x00 0.--9. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x180++0x03
line.long 0x00 "EICHD2_WORD0,Error Injection Channel Descriptor 2 Word0"
hexmask.long.byte 0x00 24.--31. 1. "CHKBIT_MASK,Checkbit Mask"
group.long 0x184++0x03
line.long 0x00 "EICHD2_WORD1,Error Injection Channel Descriptor 2 Word1"
hexmask.long 0x00 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x188++0x03
line.long 0x00 "EICHD2_WORD2,Error Injection Channel Descriptor 2 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x1C4++0x03
line.long 0x00 "EICHD3_WORD1,Error Injection Channel Descriptor 3 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x1C8++0x03
line.long 0x00 "EICHD3_WORD2,Error Injection Channel Descriptor 3 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x204++0x03
line.long 0x00 "EICHD4_WORD1,Error Injection Channel Descriptor 4 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x208++0x03
line.long 0x00 "EICHD4_WORD2,Error Injection Channel Descriptor 4 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x20C++0x03
line.long 0x00 "EICHD4_WORD3,Error Injection Channel Descriptor 4 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x210++0x03
line.long 0x00 "EICHD4_WORD4,Error Injection Channel Descriptor 4 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x214++0x03
line.long 0x00 "EICHD4_WORD5,Error Injection Channel Descriptor 4 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x218++0x03
line.long 0x00 "EICHD4_WORD6,Error Injection Channel Descriptor 4 Word6"
hexmask.long 0x00 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23"
group.long 0x244++0x03
line.long 0x00 "EICHD5_WORD1,Error Injection Channel Descriptor 5 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x248++0x03
line.long 0x00 "EICHD5_WORD2,Error Injection Channel Descriptor 5 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x284++0x03
line.long 0x00 "EICHD6_WORD1,Error Injection Channel Descriptor 6 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x288++0x03
line.long 0x00 "EICHD6_WORD2,Error Injection Channel Descriptor 6 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x2C4++0x03
line.long 0x00 "EICHD7_WORD1,Error Injection Channel Descriptor 7 Word1"
hexmask.long.tbyte 0x00 0.--23. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x2C8++0x03
line.long 0x00 "EICHD7_WORD2,Error Injection Channel Descriptor 7 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x2CC++0x03
line.long 0x00 "EICHD7_WORD3,Error Injection Channel Descriptor 7 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x2D0++0x03
line.long 0x00 "EICHD7_WORD4,Error Injection Channel Descriptor 7 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x304++0x03
line.long 0x00 "EICHD8_WORD1,Error Injection Channel Descriptor 8 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x308++0x03
line.long 0x00 "EICHD8_WORD2,Error Injection Channel Descriptor 8 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x344++0x03
line.long 0x00 "EICHD9_WORD1,Error Injection Channel Descriptor 9 Word1"
hexmask.long 0x00 0.--25. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x384++0x03
line.long 0x00 "EICHD10_WORD1,Error Injection Channel Descriptor 10 Word1"
hexmask.long 0x00 0.--25. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x3C4++0x03
line.long 0x00 "EICHD11_WORD1,Error Injection Channel Descriptor 11 Word1"
hexmask.long.tbyte 0x00 0.--19. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x404++0x03
line.long 0x00 "EICHD12_WORD1,Error Injection Channel Descriptor 12 Word1"
hexmask.long.tbyte 0x00 0.--23. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x408++0x03
line.long 0x00 "EICHD12_WORD2,Error Injection Channel Descriptor 12 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x40C++0x03
line.long 0x00 "EICHD12_WORD3,Error Injection Channel Descriptor 12 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x410++0x03
line.long 0x00 "EICHD12_WORD4,Error Injection Channel Descriptor 12 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x444++0x03
line.long 0x00 "EICHD13_WORD1,Error Injection Channel Descriptor 13 Word1"
hexmask.long.word 0x00 0.--13. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
tree.end
tree "EIM_RT2"
base ad:0x40116000
group.long 0x00++0x03
line.long 0x00 "EIMCR,Error Injection Module Configuration Register"
bitfld.long 0x00 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled"
group.long 0x04++0x03
line.long 0x00 "EICHEN,Error Injection Channel Enable register"
bitfld.long 0x00 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 29. "EICH2EN,Error Injection Channel 2 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 28. "EICH3EN,Error Injection Channel 3 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 27. "EICH4EN,Error Injection Channel 4 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 26. "EICH5EN,Error Injection Channel 5 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 25. "EICH6EN,Error Injection Channel 6 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 24. "EICH7EN,Error Injection Channel 7 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 23. "EICH8EN,Error Injection Channel 8 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 22. "EICH9EN,Error Injection Channel 9 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
newline
bitfld.long 0x00 21. "EICH10EN,Error Injection Channel 10 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
bitfld.long 0x00 20. "EICH11EN,Error Injection Channel 11 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
group.long 0x104++0x03
line.long 0x00 "EICHD0_WORD1,Error Injection Channel Descriptor 0 Word1"
hexmask.long.tbyte 0x00 0.--19. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x108++0x03
line.long 0x00 "EICHD0_WORD2,Error Injection Channel Descriptor 0 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x10C++0x03
line.long 0x00 "EICHD0_WORD3,Error Injection Channel Descriptor 0 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x110++0x03
line.long 0x00 "EICHD0_WORD4,Error Injection Channel Descriptor 0 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x114++0x03
line.long 0x00 "EICHD0_WORD5,Error Injection Channel Descriptor 0 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x118++0x03
line.long 0x00 "EICHD0_WORD6,Error Injection Channel Descriptor 0 Word6"
hexmask.long 0x00 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23"
group.long 0x144++0x03
line.long 0x00 "EICHD1_WORD1,Error Injection Channel Descriptor 1 Word1"
bitfld.long 0x00 0.--5. "B0_3DATA_MASK,Data Mask Bytes 0-3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x184++0x03
line.long 0x00 "EICHD2_WORD1,Error Injection Channel Descriptor 2 Word1"
bitfld.long 0x00 0.--5. "B0_3DATA_MASK,Data Mask Bytes 0-3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1C4++0x03
line.long 0x00 "EICHD3_WORD1,Error Injection Channel Descriptor 3 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x1C8++0x03
line.long 0x00 "EICHD3_WORD2,Error Injection Channel Descriptor 3 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x1CC++0x03
line.long 0x00 "EICHD3_WORD3,Error Injection Channel Descriptor 3 Word3"
hexmask.long 0x00 0.--31. 1. "B8_11DATA_MASK,Data Mask Bytes 8-11"
group.long 0x1D0++0x03
line.long 0x00 "EICHD3_WORD4,Error Injection Channel Descriptor 3 Word4"
hexmask.long 0x00 0.--31. 1. "B12_15DATA_MASK,Data Mask Bytes 12-15"
group.long 0x1D4++0x03
line.long 0x00 "EICHD3_WORD5,Error Injection Channel Descriptor 3 Word5"
hexmask.long 0x00 0.--31. 1. "B16_19DATA_MASK,Data Mask Bytes 16-19"
group.long 0x1D8++0x03
line.long 0x00 "EICHD3_WORD6,Error Injection Channel Descriptor 3 Word6"
hexmask.long 0x00 0.--31. 1. "B20_23DATA_MASK,Data Mask Bytes 20-23"
group.long 0x204++0x03
line.long 0x00 "EICHD4_WORD1,Error Injection Channel Descriptor 4 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x208++0x03
line.long 0x00 "EICHD4_WORD2,Error Injection Channel Descriptor 4 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x244++0x03
line.long 0x00 "EICHD5_WORD1,Error Injection Channel Descriptor 5 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x248++0x03
line.long 0x00 "EICHD5_WORD2,Error Injection Channel Descriptor 5 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x284++0x03
line.long 0x00 "EICHD6_WORD1,Error Injection Channel Descriptor 6 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x288++0x03
line.long 0x00 "EICHD6_WORD2,Error Injection Channel Descriptor 6 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x2C4++0x03
line.long 0x00 "EICHD7_WORD1,Error Injection Channel Descriptor 7 Word1"
bitfld.long 0x00 0.--5. "B0_3DATA_MASK,Data Mask Bytes 0-3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x304++0x03
line.long 0x00 "EICHD8_WORD1,Error Injection Channel Descriptor 8 Word1"
bitfld.long 0x00 0.--3. "B0_3DATA_MASK,Data Mask Bytes 0-3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x344++0x03
line.long 0x00 "EICHD9_WORD1,Error Injection Channel Descriptor 9 Word1"
bitfld.long 0x00 0.--3. "B0_3DATA_MASK,Data Mask Bytes 0-3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x384++0x03
line.long 0x00 "EICHD10_WORD1,Error Injection Channel Descriptor 10 Word1"
hexmask.long 0x00 0.--27. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
group.long 0x388++0x03
line.long 0x00 "EICHD10_WORD2,Error Injection Channel Descriptor 10 Word2"
hexmask.long 0x00 0.--31. 1. "B4_7DATA_MASK,Data Mask Bytes 4-7"
group.long 0x3C4++0x03
line.long 0x00 "EICHD11_WORD1,Error Injection Channel Descriptor 11 Word1"
bitfld.long 0x00 0.--1. "B0_3DATA_MASK,Data Mask Bytes 0-3" "0,1,2,3"
tree.end
tree.end
tree "ERM"
tree "ERM_AP1"
base ad:0x440E8000
group.long 0x00++0x03
line.long 0x00 "CR0,ERM Configuration Register 0"
bitfld.long 0x00 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.."
bitfld.long 0x00 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.."
group.long 0x10++0x03
line.long 0x00 "SR0,ERM Status Register 0"
eventfld.long 0x00 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0.."
eventfld.long 0x00 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0.."
rgroup.long 0x100++0x03
line.long 0x00 "EAR0,ERM Memory 0 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
rgroup.long 0x104++0x03
line.long 0x00 "SYN0,ERM Memory 0 Syndrome Register"
hexmask.long.byte 0x00 24.--31. 1. "SYNDROME,SYNDROME"
group.long 0x108++0x03
line.long 0x00 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
tree.end
repeat 2. (list 0. 1.) (list ad:0x40153000 ad:0x40157000)
tree "ERM_CM7_$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CR0,ERM Configuration Register 0"
bitfld.long 0x00 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.."
bitfld.long 0x00 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.."
newline
bitfld.long 0x00 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.."
bitfld.long 0x00 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.."
newline
bitfld.long 0x00 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.."
bitfld.long 0x00 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.."
newline
bitfld.long 0x00 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.."
bitfld.long 0x00 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.."
newline
bitfld.long 0x00 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.."
bitfld.long 0x00 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.."
newline
bitfld.long 0x00 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.."
bitfld.long 0x00 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.."
group.long 0x10++0x03
line.long 0x00 "SR0,ERM Status Register 0"
eventfld.long 0x00 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0.."
eventfld.long 0x00 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0.."
newline
eventfld.long 0x00 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1.."
eventfld.long 0x00 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1.."
newline
eventfld.long 0x00 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2.."
eventfld.long 0x00 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2.."
newline
eventfld.long 0x00 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3.."
eventfld.long 0x00 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3.."
newline
eventfld.long 0x00 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4.."
eventfld.long 0x00 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4.."
newline
eventfld.long 0x00 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5.."
eventfld.long 0x00 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5.."
rgroup.long 0x100++0x03
line.long 0x00 "EAR0,ERM Memory 0 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
rgroup.long 0x104++0x03
line.long 0x00 "SYN0,ERM Memory 0 Syndrome Register"
hexmask.long.byte 0x00 24.--31. 1. "SYNDROME,SYNDROME"
group.long 0x108++0x03
line.long 0x00 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x110++0x03
line.long 0x00 "EAR1,ERM Memory 1 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
rgroup.long 0x114++0x03
line.long 0x00 "SYN1,ERM Memory 1 Syndrome Register"
hexmask.long.byte 0x00 24.--31. 1. "SYNDROME,SYNDROME"
group.long 0x118++0x03
line.long 0x00 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
group.long 0x128++0x03
line.long 0x00 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
group.long 0x138++0x03
line.long 0x00 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
group.long 0x148++0x03
line.long 0x00 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
group.long 0x158++0x03
line.long 0x00 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
tree.end
repeat.end
tree "ERM_RT0"
base ad:0x40118000
group.long 0x00++0x03
line.long 0x00 "CR0,ERM Configuration Register 0"
bitfld.long 0x00 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.."
bitfld.long 0x00 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.."
newline
bitfld.long 0x00 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.."
bitfld.long 0x00 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.."
newline
bitfld.long 0x00 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.."
bitfld.long 0x00 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.."
newline
bitfld.long 0x00 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.."
bitfld.long 0x00 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.."
newline
bitfld.long 0x00 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.."
bitfld.long 0x00 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.."
newline
bitfld.long 0x00 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.."
bitfld.long 0x00 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.."
newline
bitfld.long 0x00 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.."
bitfld.long 0x00 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.."
newline
bitfld.long 0x00 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.."
bitfld.long 0x00 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.."
group.long 0x04++0x03
line.long 0x00 "CR1,ERM Configuration Register 1"
bitfld.long 0x00 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.."
bitfld.long 0x00 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.."
newline
bitfld.long 0x00 27. "ESCIE9,ESCIE9" "0: Interrupt notification of Memory 9 single-bit..,1: Interrupt notification of Memory 9 single-bit.."
bitfld.long 0x00 26. "ENCIE9,ENCIE9" "0: Interrupt notification of Memory 9..,1: Interrupt notification of Memory 9.."
group.long 0x10++0x03
line.long 0x00 "SR0,ERM Status Register 0"
eventfld.long 0x00 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0.."
eventfld.long 0x00 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0.."
newline
eventfld.long 0x00 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1.."
eventfld.long 0x00 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1.."
newline
eventfld.long 0x00 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2.."
eventfld.long 0x00 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2.."
newline
eventfld.long 0x00 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3.."
eventfld.long 0x00 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3.."
newline
eventfld.long 0x00 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4.."
eventfld.long 0x00 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4.."
newline
eventfld.long 0x00 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5.."
eventfld.long 0x00 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5.."
newline
eventfld.long 0x00 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6.."
eventfld.long 0x00 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6.."
newline
eventfld.long 0x00 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7.."
eventfld.long 0x00 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7.."
group.long 0x14++0x03
line.long 0x00 "SR1,ERM Status Register 1"
eventfld.long 0x00 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8.."
eventfld.long 0x00 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8.."
newline
eventfld.long 0x00 27. "SBC9,SBC9" "0: No single-bit correction event on Memory 9..,1: Single-bit correction event on Memory 9.."
eventfld.long 0x00 26. "NCE9,NCE9" "0: No non-correctable error event on Memory 9..,1: Non-correctable error event on Memory 9.."
rgroup.long 0x100++0x03
line.long 0x00 "EAR0,ERM Memory 0 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
rgroup.long 0x104++0x03
line.long 0x00 "SYN0,ERM Memory 0 Syndrome Register"
hexmask.long.byte 0x00 24.--31. 1. "SYNDROME,SYNDROME"
group.long 0x108++0x03
line.long 0x00 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x110++0x03
line.long 0x00 "EAR1,ERM Memory 1 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
rgroup.long 0x114++0x03
line.long 0x00 "SYN1,ERM Memory 1 Syndrome Register"
hexmask.long.byte 0x00 24.--31. 1. "SYNDROME,SYNDROME"
group.long 0x118++0x03
line.long 0x00 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x120++0x03
line.long 0x00 "EAR2,ERM Memory 2 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
rgroup.long 0x124++0x03
line.long 0x00 "SYN2,ERM Memory 2 Syndrome Register"
hexmask.long.byte 0x00 24.--31. 1. "SYNDROME,SYNDROME"
group.long 0x128++0x03
line.long 0x00 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x130++0x03
line.long 0x00 "EAR3,ERM Memory 3 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
rgroup.long 0x134++0x03
line.long 0x00 "SYN3,ERM Memory 3 Syndrome Register"
hexmask.long.byte 0x00 24.--31. 1. "SYNDROME,SYNDROME"
group.long 0x138++0x03
line.long 0x00 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x140++0x03
line.long 0x00 "EAR4,ERM Memory 4 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
rgroup.long 0x144++0x03
line.long 0x00 "SYN4,ERM Memory 4 Syndrome Register"
hexmask.long.byte 0x00 24.--31. 1. "SYNDROME,SYNDROME"
group.long 0x148++0x03
line.long 0x00 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x150++0x03
line.long 0x00 "EAR5,ERM Memory 5 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
rgroup.long 0x154++0x03
line.long 0x00 "SYN5,ERM Memory 5 Syndrome Register"
hexmask.long.byte 0x00 24.--31. 1. "SYNDROME,SYNDROME"
group.long 0x158++0x03
line.long 0x00 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x160++0x03
line.long 0x00 "EAR6,ERM Memory 6 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
rgroup.long 0x164++0x03
line.long 0x00 "SYN6,ERM Memory 6 Syndrome Register"
hexmask.long.byte 0x00 24.--31. 1. "SYNDROME,SYNDROME"
group.long 0x168++0x03
line.long 0x00 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x170++0x03
line.long 0x00 "EAR7,ERM Memory 7 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
rgroup.long 0x174++0x03
line.long 0x00 "SYN7,ERM Memory 7 Syndrome Register"
hexmask.long.byte 0x00 24.--31. 1. "SYNDROME,SYNDROME"
group.long 0x178++0x03
line.long 0x00 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x180++0x03
line.long 0x00 "EAR8,ERM Memory 8 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
rgroup.long 0x184++0x03
line.long 0x00 "SYN8,ERM Memory 8 Syndrome Register"
hexmask.long.byte 0x00 24.--31. 1. "SYNDROME,SYNDROME"
group.long 0x188++0x03
line.long 0x00 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x190++0x03
line.long 0x00 "EAR9,ERM Memory 9 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
rgroup.long 0x194++0x03
line.long 0x00 "SYN9,ERM Memory 9 Syndrome Register"
hexmask.long.byte 0x00 24.--31. 1. "SYNDROME,SYNDROME"
group.long 0x198++0x03
line.long 0x00 "CORR_ERR_CNT9,ERM Memory 9 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
tree.end
tree "ERM_RT1"
base ad:0x40119000
group.long 0x00++0x03
line.long 0x00 "CR0,ERM Configuration Register 0"
bitfld.long 0x00 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.."
bitfld.long 0x00 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.."
newline
bitfld.long 0x00 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.."
bitfld.long 0x00 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.."
newline
bitfld.long 0x00 23. "ESCIE2,ESCIE2" "0: Interrupt notification of Memory 2 single-bit..,1: Interrupt notification of Memory 2 single-bit.."
bitfld.long 0x00 22. "ENCIE2,ENCIE2" "0: Interrupt notification of Memory 2..,1: Interrupt notification of Memory 2.."
newline
bitfld.long 0x00 19. "ESCIE3,ESCIE3" "0: Interrupt notification of Memory 3 single-bit..,1: Interrupt notification of Memory 3 single-bit.."
bitfld.long 0x00 18. "ENCIE3,ENCIE3" "0: Interrupt notification of Memory 3..,1: Interrupt notification of Memory 3.."
newline
bitfld.long 0x00 15. "ESCIE4,ESCIE4" "0: Interrupt notification of Memory 4 single-bit..,1: Interrupt notification of Memory 4 single-bit.."
bitfld.long 0x00 14. "ENCIE4,ENCIE4" "0: Interrupt notification of Memory 4..,1: Interrupt notification of Memory 4.."
newline
bitfld.long 0x00 11. "ESCIE5,ESCIE5" "0: Interrupt notification of Memory 5 single-bit..,1: Interrupt notification of Memory 5 single-bit.."
bitfld.long 0x00 10. "ENCIE5,ENCIE5" "0: Interrupt notification of Memory 5..,1: Interrupt notification of Memory 5.."
newline
bitfld.long 0x00 7. "ESCIE6,ESCIE6" "0: Interrupt notification of Memory 6 single-bit..,1: Interrupt notification of Memory 6 single-bit.."
bitfld.long 0x00 6. "ENCIE6,ENCIE6" "0: Interrupt notification of Memory 6..,1: Interrupt notification of Memory 6.."
newline
bitfld.long 0x00 3. "ESCIE7,ESCIE7" "0: Interrupt notification of Memory 7 single-bit..,1: Interrupt notification of Memory 7 single-bit.."
bitfld.long 0x00 2. "ENCIE7,ENCIE7" "0: Interrupt notification of Memory 7..,1: Interrupt notification of Memory 7.."
group.long 0x04++0x03
line.long 0x00 "CR1,ERM Configuration Register 1"
bitfld.long 0x00 31. "ESCIE8,ESCIE8" "0: Interrupt notification of Memory 8 single-bit..,1: Interrupt notification of Memory 8 single-bit.."
bitfld.long 0x00 30. "ENCIE8,ENCIE8" "0: Interrupt notification of Memory 8..,1: Interrupt notification of Memory 8.."
group.long 0x10++0x03
line.long 0x00 "SR0,ERM Status Register 0"
eventfld.long 0x00 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0.."
eventfld.long 0x00 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0.."
newline
eventfld.long 0x00 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1.."
eventfld.long 0x00 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1.."
newline
eventfld.long 0x00 23. "SBC2,SBC2" "0: No single-bit correction event on Memory 2..,1: Single-bit correction event on Memory 2.."
eventfld.long 0x00 22. "NCE2,NCE2" "0: No non-correctable error event on Memory 2..,1: Non-correctable error event on Memory 2.."
newline
eventfld.long 0x00 19. "SBC3,SBC3" "0: No single-bit correction event on Memory 3..,1: Single-bit correction event on Memory 3.."
eventfld.long 0x00 18. "NCE3,NCE3" "0: No non-correctable error event on Memory 3..,1: Non-correctable error event on Memory 3.."
newline
eventfld.long 0x00 15. "SBC4,SBC4" "0: No single-bit correction event on Memory 4..,1: Single-bit correction event on Memory 4.."
eventfld.long 0x00 14. "NCE4,NCE4" "0: No non-correctable error event on Memory 4..,1: Non-correctable error event on Memory 4.."
newline
eventfld.long 0x00 11. "SBC5,SBC5" "0: No single-bit correction event on Memory 5..,1: Single-bit correction event on Memory 5.."
eventfld.long 0x00 10. "NCE5,NCE5" "0: No non-correctable error event on Memory 5..,1: Non-correctable error event on Memory 5.."
newline
eventfld.long 0x00 7. "SBC6,SBC6" "0: No single-bit correction event on Memory 6..,1: Single-bit correction event on Memory 6.."
eventfld.long 0x00 6. "NCE6,NCE6" "0: No non-correctable error event on Memory 6..,1: Non-correctable error event on Memory 6.."
newline
eventfld.long 0x00 3. "SBC7,SBC7" "0: No single-bit correction event on Memory 7..,1: Single-bit correction event on Memory 7.."
eventfld.long 0x00 2. "NCE7,NCE7" "0: No non-correctable error event on Memory 7..,1: Non-correctable error event on Memory 7.."
group.long 0x14++0x03
line.long 0x00 "SR1,ERM Status Register 1"
eventfld.long 0x00 31. "SBC8,SBC8" "0: No single-bit correction event on Memory 8..,1: Single-bit correction event on Memory 8.."
eventfld.long 0x00 30. "NCE8,NCE8" "0: No non-correctable error event on Memory 8..,1: Non-correctable error event on Memory 8.."
rgroup.long 0x100++0x03
line.long 0x00 "EAR0,ERM Memory 0 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
group.long 0x108++0x03
line.long 0x00 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x110++0x03
line.long 0x00 "EAR1,ERM Memory 1 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
group.long 0x118++0x03
line.long 0x00 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x120++0x03
line.long 0x00 "EAR2,ERM Memory 2 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
group.long 0x128++0x03
line.long 0x00 "CORR_ERR_CNT2,ERM Memory 2 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x130++0x03
line.long 0x00 "EAR3,ERM Memory 3 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
group.long 0x138++0x03
line.long 0x00 "CORR_ERR_CNT3,ERM Memory 3 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x140++0x03
line.long 0x00 "EAR4,ERM Memory 4 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
group.long 0x148++0x03
line.long 0x00 "CORR_ERR_CNT4,ERM Memory 4 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x150++0x03
line.long 0x00 "EAR5,ERM Memory 5 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
group.long 0x158++0x03
line.long 0x00 "CORR_ERR_CNT5,ERM Memory 5 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x160++0x03
line.long 0x00 "EAR6,ERM Memory 6 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
group.long 0x168++0x03
line.long 0x00 "CORR_ERR_CNT6,ERM Memory 6 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x170++0x03
line.long 0x00 "EAR7,ERM Memory 7 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
group.long 0x178++0x03
line.long 0x00 "CORR_ERR_CNT7,ERM Memory 7 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x180++0x03
line.long 0x00 "EAR8,ERM Memory 8 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
group.long 0x188++0x03
line.long 0x00 "CORR_ERR_CNT8,ERM Memory 8 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
tree.end
tree "ERM_RT2"
base ad:0x4011A000
group.long 0x00++0x03
line.long 0x00 "CR0,ERM Configuration Register 0"
bitfld.long 0x00 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.."
bitfld.long 0x00 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.."
newline
bitfld.long 0x00 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.."
bitfld.long 0x00 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.."
group.long 0x10++0x03
line.long 0x00 "SR0,ERM Status Register 0"
eventfld.long 0x00 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0.."
eventfld.long 0x00 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0.."
newline
eventfld.long 0x00 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1.."
eventfld.long 0x00 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1.."
rgroup.long 0x100++0x03
line.long 0x00 "EAR0,ERM Memory 0 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
group.long 0x108++0x03
line.long 0x00 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x110++0x03
line.long 0x00 "EAR1,ERM Memory 1 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
group.long 0x118++0x03
line.long 0x00 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
tree.end
tree "ERM_SPT"
base ad:0x440A5000
group.long 0x00++0x03
line.long 0x00 "CR0,ERM Configuration Register 0"
bitfld.long 0x00 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.."
bitfld.long 0x00 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.."
newline
bitfld.long 0x00 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.."
bitfld.long 0x00 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.."
group.long 0x10++0x03
line.long 0x00 "SR0,ERM Status Register 0"
eventfld.long 0x00 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0.."
eventfld.long 0x00 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0.."
newline
eventfld.long 0x00 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1.."
eventfld.long 0x00 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1.."
rgroup.long 0x100++0x03
line.long 0x00 "EAR0,ERM Memory 0 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
group.long 0x108++0x03
line.long 0x00 "CORR_ERR_CNT0,ERM Memory 0 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
rgroup.long 0x110++0x03
line.long 0x00 "EAR1,ERM Memory 1 Error Address Register"
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
group.long 0x118++0x03
line.long 0x00 "CORR_ERR_CNT1,ERM Memory 1 Correctable Error Count Register"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Memory n Correctable Error Count"
tree.end
tree.end
tree "FCCU"
base ad:0x4010C000
group.long 0x00++0x03
line.long 0x00 "CTRL,Control"
bitfld.long 0x00 9. "DEBUG,Debug Mode Enable" "0: Disabled,1: Enabled"
rbitfld.long 0x00 6.--7. "OPS,Operation Status" "0: Idle,1: In progress,2: Aborted,3: Successful"
newline
bitfld.long 0x00 0.--4. "OPR,Operation Run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
wgroup.long 0x04++0x03
line.long 0x00 "CTRLK,Control Key"
hexmask.long 0x00 0.--31. 1. "CTRLK,Locked-Operation Control Key"
group.long 0x08++0x03
line.long 0x00 "CFG,Configuration"
bitfld.long 0x00 24. "FCCU_SET_AFTER_RESET,Fault-Output (EOUT) Activate" "0: Inactive (the EOUT signals are in a..,1: Active (the EOUT signals indicate FCCU's.."
bitfld.long 0x00 22.--23. "FCCU_SET_CLEAR,Fault-Output (EOUT) Control" "0: Controlled by the FSM,1: Always low,2: Controlled by the FSM,3: High until a fault occurs on a channel.."
newline
bitfld.long 0x00 15. "FOPE,Fault-Output (EOUT) Prescaler Extension" "0,1"
bitfld.long 0x00 10. "SM,Fault-Output (EOUT) Switching Mode" "0: Slow,1: Fast"
newline
bitfld.long 0x00 9. "PS,Fault-Output (EOUT) Polarity Selection" "0: For the faulty indication EOUT1 is high and..,1: For the faulty indication EOUT1 is low and.."
bitfld.long 0x00 6.--8. "FOM,Fault-Output (EOUT) Mode" "0: Dual-Rail,1: Time-Switching,2: Bi-Stable,?,?,5: Test 0 (controlled by the EINOUT register..,6: Test 1 (controlled by the EINOUT register..,7: Test 2 (controlled by the EINOUT register.."
newline
bitfld.long 0x00 0.--5. "FOP,Fault-Output (EOUT) Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0x1C)++0x03
line.long 0x00 "NCF_CFG$1,Non-critical Fault Configuration"
bitfld.long 0x00 31. "NCFC31,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 30. "NCFC30,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 29. "NCFC29,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 28. "NCFC28,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 27. "NCFC27,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 26. "NCFC26,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 25. "NCFC25,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 24. "NCFC24,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 23. "NCFC23,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 22. "NCFC22,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 21. "NCFC21,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 20. "NCFC20,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 19. "NCFC19,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 18. "NCFC18,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 17. "NCFC17,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 16. "NCFC16,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 15. "NCFC15,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 14. "NCFC14,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 13. "NCFC13,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 12. "NCFC12,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 11. "NCFC11,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 10. "NCFC10,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 9. "NCFC9,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 8. "NCFC8,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 7. "NCFC7,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 6. "NCFC6,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 5. "NCFC5,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 4. "NCFC4,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 3. "NCFC3,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 2. "NCFC2,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
newline
bitfld.long 0x00 1. "NCFC1,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
bitfld.long 0x00 0. "NCFC0,Non-critical Fault Configuration n" "0: Hardware-recoverable,1: Software-recoverable"
repeat.end
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x4C)++0x03
line.long 0x00 "NCFS_CFG$1,Non-critical Fault-State Configuration"
bitfld.long 0x00 30.--31. "NCFSC15,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
bitfld.long 0x00 28.--29. "NCFSC14,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
newline
bitfld.long 0x00 26.--27. "NCFSC13,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
bitfld.long 0x00 24.--25. "NCFSC12,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
newline
bitfld.long 0x00 22.--23. "NCFSC11,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
bitfld.long 0x00 20.--21. "NCFSC10,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
newline
bitfld.long 0x00 18.--19. "NCFSC9,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
bitfld.long 0x00 16.--17. "NCFSC8,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
newline
bitfld.long 0x00 14.--15. "NCFSC7,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
bitfld.long 0x00 12.--13. "NCFSC6,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
newline
bitfld.long 0x00 10.--11. "NCFSC5,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
bitfld.long 0x00 8.--9. "NCFSC4,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
newline
bitfld.long 0x00 6.--7. "NCFSC3,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
bitfld.long 0x00 4.--5. "NCFSC2,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
newline
bitfld.long 0x00 2.--3. "NCFSC1,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
bitfld.long 0x00 0.--1. "NCFSC0,Non-critical Fault-State Configuration n" "0: Disabled,1: Enabled (rst_sfunc_b) (short),2: Enabled (rst_lfunc_b) (long),3: Disabled"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x80)++0x03
line.long 0x00 "NCF_S[$1],Non-critical Fault Status $1"
eventfld.long 0x00 31. "NCFS31,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 30. "NCFS30,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 29. "NCFS29,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 28. "NCFS28,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 27. "NCFS27,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 26. "NCFS26,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 25. "NCFS25,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 24. "NCFS24,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 23. "NCFS23,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 22. "NCFS22,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 21. "NCFS21,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 20. "NCFS20,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 19. "NCFS19,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 18. "NCFS18,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 17. "NCFS17,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 16. "NCFS16,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 15. "NCFS15,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 14. "NCFS14,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 13. "NCFS13,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 12. "NCFS12,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 11. "NCFS11,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 10. "NCFS10,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 9. "NCFS9,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 8. "NCFS8,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 7. "NCFS7,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 6. "NCFS6,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 5. "NCFS5,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 4. "NCFS4,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 3. "NCFS3,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 2. "NCFS2,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
newline
eventfld.long 0x00 1. "NCFS1,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
eventfld.long 0x00 0. "NCFS0,Non-critical Fault Status n" "0: No unrecovered fault,1: Unrecovered fault"
repeat.end
group.long 0x90++0x03
line.long 0x00 "NCFK,Non-critical Fault Key"
hexmask.long 0x00 0.--31. 1. "NCFK,Non-critical Fault Key"
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0x94)++0x03
line.long 0x00 "NCF_E$1,Non-critical Fault Enable"
bitfld.long 0x00 31. "NCFE31,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 30. "NCFE30,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 29. "NCFE29,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 28. "NCFE28,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 27. "NCFE27,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 26. "NCFE26,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 25. "NCFE25,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 24. "NCFE24,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 23. "NCFE23,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 22. "NCFE22,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 21. "NCFE21,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 20. "NCFE20,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 19. "NCFE19,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 18. "NCFE18,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 17. "NCFE17,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 16. "NCFE16,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 15. "NCFE15,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 14. "NCFE14,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 13. "NCFE13,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 12. "NCFE12,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 11. "NCFE11,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 10. "NCFE10,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 9. "NCFE9,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 8. "NCFE8,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 7. "NCFE7,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "NCFE6,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 5. "NCFE5,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 4. "NCFE4,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 3. "NCFE3,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 2. "NCFE2,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 1. "NCFE1,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "NCFE0,Non-critical Fault Enable n" "0: Disabled,1: Enabled"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0xA4)++0x03
line.long 0x00 "NCF_TOE$1,Non-critical-Fault Alarm-State Timeout Enable"
bitfld.long 0x00 31. "NCFTOE31,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 30. "NCFTOE30,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 29. "NCFTOE29,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 28. "NCFTOE28,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 27. "NCFTOE27,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 26. "NCFTOE26,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 25. "NCFTOE25,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 24. "NCFTOE24,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 23. "NCFTOE23,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 22. "NCFTOE22,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 21. "NCFTOE21,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 20. "NCFTOE20,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 19. "NCFTOE19,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 18. "NCFTOE18,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 17. "NCFTOE17,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 16. "NCFTOE16,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 15. "NCFTOE15,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 14. "NCFTOE14,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 13. "NCFTOE13,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 12. "NCFTOE12,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 11. "NCFTOE11,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 10. "NCFTOE10,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 9. "NCFTOE9,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 8. "NCFTOE8,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 7. "NCFTOE7,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "NCFTOE6,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 5. "NCFTOE5,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 4. "NCFTOE4,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 3. "NCFTOE3,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 2. "NCFTOE2,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 1. "NCFTOE1,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "NCFTOE0,Non-critical-Fault Alarm-State Timeout Enable n" "0: Disabled,1: Enabled"
repeat.end
group.long 0xB4++0x03
line.long 0x00 "NCF_TO,Non-critical-Fault Alarm-State Timeout Interval"
hexmask.long 0x00 0.--31. 1. "TO,Non-critical-Fault Alarm-State Timeout Interval"
group.long 0xB8++0x03
line.long 0x00 "CFG_TO,Configuration-State Timeout Interval"
bitfld.long 0x00 0.--2. "TO,Configuration-State Timeout Interval" "0,1,2,3,4,5,6,7"
group.long 0xBC++0x03
line.long 0x00 "EINOUT,IO Control"
rbitfld.long 0x00 5. "EIN1,Error Input 1" "0: id0,1: High"
rbitfld.long 0x00 4. "EIN0,Error Input 0" "0: id0,1: High"
newline
bitfld.long 0x00 1. "EOUT1,EOUT1" "0: force EOUT[1] = 0,1: force EOUT[1] = 1"
bitfld.long 0x00 0. "EOUT0,EOUT0" "0: force EOUT[0] = 0,1: force EOUT[0] = 1"
rgroup.long 0xC0++0x03
line.long 0x00 "STAT,Status"
bitfld.long 0x00 4.--5. "PhysicErrorPin,EOUT Signal States" "0: EOUT1 is low EOUT0 is low,1: EOUT1 is low EOUT0 is high,2: EOUT1 is high EOUT0 is low,3: EOUT1 is high EOUT0 is high"
bitfld.long 0x00 3. "ESTAT,FCCU Faulty Condition" "0: Not in faulty condition (in non-faulty or..,1: In faulty condition"
newline
bitfld.long 0x00 0.--2. "STATUS,FCCU State" "0: NORMAL,1: CONFIG,2: id010,3: id011,?..."
rgroup.long 0xC4++0x03
line.long 0x00 "N2AF_STATUS,Normal-to-Alarm Freeze Status"
hexmask.long.byte 0x00 0.--7. 1. "NAFS,Normal-to-Alarm Freeze Status"
rgroup.long 0xC8++0x03
line.long 0x00 "A2FF_STATUS,Alarm-to-Fault Freeze Status"
bitfld.long 0x00 8.--9. "AF_SRC,Alarm-to-Fault Source" "0: No Alarm-to-Fault-state fault,?,2: Non-critical fault,3: Multiple Alarm-to-Fault-state faults"
hexmask.long.byte 0x00 0.--7. 1. "AFFS,Alarm-to-Fault Freeze Status"
rgroup.long 0xCC++0x03
line.long 0x00 "N2FF_STATUS,Normal-to-Fault Freeze Status"
bitfld.long 0x00 8.--9. "NF_SRC,Normal-to-Fault Source" "0: No Normal-to-Fault-state fault,?,2: Non-critical fault,3: Multiple Normal-to-Fault-state faults"
hexmask.long.byte 0x00 0.--7. 1. "NFFS,Normal-to-Fault Freeze Status"
rgroup.long 0xD0++0x03
line.long 0x00 "F2AF_STATUS,Fault-to-Alarm Freeze Status"
hexmask.long.word 0x00 0.--8. 1. "FAFS,Fault-to-Alarm Freeze Status"
wgroup.long 0xDC++0x03
line.long 0x00 "NCFF,Non-critical Fault Fake"
hexmask.long.byte 0x00 0.--6. 1. "FNCFC,FNCFC"
group.long 0xE0++0x03
line.long 0x00 "IRQ_STAT,IRQ Status"
rbitfld.long 0x00 2. "NMI_STAT,NMI Interrupt Status" "0: NMI interrupt is OFF,1: NMI interrupt is ON"
rbitfld.long 0x00 1. "ALRM_STAT,Alarm Interrupt Status" "0: Alarm interrupt is OFF,1: Alarm interrupt is ON"
newline
eventfld.long 0x00 0. "CFG_TO_STAT,Configuration-State Timeout Status" "0: No configuration-stat timeout error,1: Configuration-state timeout error"
group.long 0xE4++0x03
line.long 0x00 "IRQ_EN,IRQ Enable"
bitfld.long 0x00 0. "CFG_TO_IEN,Configuration-State Timeout Interrupt Enable" "0: Configuration-state timeout interrupt disabled,1: Configuration-state timeout interrupt enabled"
wgroup.long 0xF0++0x03
line.long 0x00 "TRANS_LOCK,Transient Configuration Lock"
hexmask.long.word 0x00 0.--8. 1. "TRANSKEY,Transient Configuration Lock"
wgroup.long 0xF4++0x03
line.long 0x00 "PERMNT_LOCK,Permanent Configuration Lock"
hexmask.long.word 0x00 0.--8. 1. "PERMNTKEY,Permanent Configuration Lock"
group.long 0xF8++0x03
line.long 0x00 "DELTA_T,Delta T"
hexmask.long.word 0x00 0.--13. 1. "DELTA_T,Minimum Fault-Output (EOUT) Timer Interval"
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0xFC)++0x03
line.long 0x00 "IRQ_ALARM_EN[$1],Non-critical Alarm-State Interrupt-Request Enable $1"
bitfld.long 0x00 31. "IRQEN31,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 30. "IRQEN30,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 29. "IRQEN29,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 28. "IRQEN28,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 27. "IRQEN27,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 26. "IRQEN26,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 25. "IRQEN25,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 24. "IRQEN24,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 23. "IRQEN23,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 22. "IRQEN22,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 21. "IRQEN21,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 20. "IRQEN20,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 19. "IRQEN19,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 18. "IRQEN18,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 17. "IRQEN17,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 16. "IRQEN16,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 15. "IRQEN15,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 14. "IRQEN14,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 13. "IRQEN13,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 12. "IRQEN12,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 11. "IRQEN11,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 10. "IRQEN10,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 9. "IRQEN9,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 8. "IRQEN8,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 7. "IRQEN7,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "IRQEN6,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 5. "IRQEN5,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 4. "IRQEN4,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 3. "IRQEN3,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 2. "IRQEN2,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 1. "IRQEN1,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "IRQEN0,Non-critical Alarm-State Interrupt-Request Enable n" "0: Disabled,1: Enabled"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x10C)++0x03
line.long 0x00 "NMI_EN[$1],Non-critical Fault-State Non-maskable-Interrupt-Request Enable $1"
bitfld.long 0x00 31. "NMIEN31,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 30. "NMIEN30,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 29. "NMIEN29,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 28. "NMIEN28,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 27. "NMIEN27,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 26. "NMIEN26,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 25. "NMIEN25,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 24. "NMIEN24,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 23. "NMIEN23,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 22. "NMIEN22,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 21. "NMIEN21,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 20. "NMIEN20,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 19. "NMIEN19,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 18. "NMIEN18,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 17. "NMIEN17,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 16. "NMIEN16,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 15. "NMIEN15,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 14. "NMIEN14,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 13. "NMIEN13,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 12. "NMIEN12,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 11. "NMIEN11,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 10. "NMIEN10,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
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bitfld.long 0x00 9. "NMIEN9,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 8. "NMIEN8,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
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bitfld.long 0x00 7. "NMIEN7,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "NMIEN6,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
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bitfld.long 0x00 5. "NMIEN5,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 4. "NMIEN4,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
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bitfld.long 0x00 3. "NMIEN3,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 2. "NMIEN2,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
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bitfld.long 0x00 1. "NMIEN1,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "NMIEN0,Non-critical Fault-State Non-maskable-Interrupt-Request Enable n" "0: Disabled,1: Enabled"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x11C)++0x03
line.long 0x00 "EOUT_SIG_EN[$1],Non-critical Fault-State EOUT Signaling Enable $1"
bitfld.long 0x00 31. "EOUTEN31,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 30. "EOUTEN30,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 29. "EOUTEN29,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 28. "EOUTEN28,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 27. "EOUTEN27,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 26. "EOUTEN26,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 25. "EOUTEN25,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 24. "EOUTEN24,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 23. "EOUTEN23,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 22. "EOUTEN22,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 21. "EOUTEN21,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 20. "EOUTEN20,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 19. "EOUTEN19,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 18. "EOUTEN18,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 17. "EOUTEN17,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 16. "EOUTEN16,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 15. "EOUTEN15,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 14. "EOUTEN14,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 13. "EOUTEN13,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 12. "EOUTEN12,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 11. "EOUTEN11,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 10. "EOUTEN10,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 9. "EOUTEN9,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 8. "EOUTEN8,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 7. "EOUTEN7,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 6. "EOUTEN6,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 5. "EOUTEN5,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 4. "EOUTEN4,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 3. "EOUTEN3,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 2. "EOUTEN2,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
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bitfld.long 0x00 1. "EOUTEN1,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
bitfld.long 0x00 0. "EOUTEN0,Non-critical Fault-State EOUT Signaling Enable n" "0: In Bi-Stable fault-output mode both EOUT..,1: Both EOUT signaling and FIF assertion are.."
repeat.end
rgroup.long 0x12C++0x03
line.long 0x00 "TMR_ALARM,Alarm-State Timer"
hexmask.long 0x00 0.--31. 1. "COUNT,Alarm-State Timer Count"
rgroup.long 0x134++0x03
line.long 0x00 "TMR_CFG,Configuration-State Timer"
hexmask.long 0x00 0.--31. 1. "COUNT,Configuration-State Timer Count"
rgroup.long 0x138++0x03
line.long 0x00 "TMR_ETMR,Fault-Output Timer"
hexmask.long 0x00 0.--31. 1. "COUNT,Fault-Output Timer Count"
tree.end
tree "FLEXCAN (CAN)"
repeat 2. (list 0. 1.) (list ad:0x40280000 ad:0x40480000)
tree "CAN_$1"
base $2
group.long 0x00++0x03
line.long 0x00 "MCR,Module Configuration Register"
bitfld.long 0x00 31. "MDIS,Module Disable" "0: Enable the FlexCAN module,1: Disable the FlexCAN module"
bitfld.long 0x00 30. "FRZ,Freeze Enable" "0: Not enabled to enter Freeze mode,1: Enabled to enter Freeze mode"
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bitfld.long 0x00 29. "RFEN,Legacy Rx FIFO Enable" "0: Legacy Rx FIFO not enabled,1: Legacy Rx FIFO enabled"
bitfld.long 0x00 28. "HALT,Halt FlexCAN" "0: No Freeze mode request,1: Enters Freeze mode if the FRZ bit is asserted"
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rbitfld.long 0x00 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN module is either in Normal mode..,1: FlexCAN module is either in Disable mode Stop.."
bitfld.long 0x00 25. "SOFTRST,Soft Reset" "0: SOFTRST_no_reset_request,1: Resets the registers affected by soft reset"
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rbitfld.long 0x00 24. "FRZACK,Freeze Mode Acknowledge" "0: FlexCAN not in Freeze mode prescaler running,1: FlexCAN in Freeze mode prescaler stopped"
bitfld.long 0x00 21. "WRNEN,Warning Interrupt Enable" "0: TWRNINT and RWRNINT bits are zero independent..,1: TWRNINT and RWRNINT bits are set when the.."
newline
rbitfld.long 0x00 20. "LPMACK,Low-Power Mode Acknowledge" "0: FlexCAN is not in a low-power mode,1: FlexCAN is in a low-power mode"
bitfld.long 0x00 17. "SRXDIS,Self Reception Disable" "0: Self-reception enabled,1: Self-reception disabled"
newline
bitfld.long 0x00 16. "IRMQ,Individual Rx Masking And Queue Enable" "0: Individual Rx masking and queue feature are..,1: Individual Rx masking and queue feature are.."
bitfld.long 0x00 15. "DMA,DMA Enable" "0: DMA feature for Legacy RX FIFO or Enhanced Rx..,1: DMA feature for Legacy RX FIFO or Enhanced Rx.."
newline
bitfld.long 0x00 13. "LPRIOEN,Local Priority Enable" "0: Local Priority disabled,1: Local Priority enabled"
bitfld.long 0x00 12. "AEN,Abort Enable" "0: Abort disabled,1: Abort enabled"
newline
bitfld.long 0x00 11. "FDEN,CAN FD operation enable" "0: CAN FD is disabled,1: CAN FD is enabled"
bitfld.long 0x00 8.--9. "IDAM,ID Acceptance Mode" "0: Format A,1: Format B,2: Format C,3: Format D"
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hexmask.long.byte 0x00 0.--6. 1. "MAXMB,Number Of The Last Message Buffer"
group.long 0x04++0x03
line.long 0x00 "CTRL1,Control 1 Register"
hexmask.long.byte 0x00 24.--31. 1. "PRESDIV,Prescaler Division Factor"
bitfld.long 0x00 22.--23. "RJW,Resync Jump Width" "0,1,2,3"
newline
bitfld.long 0x00 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Bus Off interrupt disabled,1: Bus Off interrupt enabled"
bitfld.long 0x00 14. "ERRMSK,Error Interrupt Mask" "0: Error interrupt disabled,1: Error interrupt enabled"
newline
bitfld.long 0x00 12. "LPB,Loop Back Mode" "0: Loop Back disabled,1: Loop Back enabled"
bitfld.long 0x00 11. "TWRNMSK,Tx Warning Interrupt Mask" "0: Tx Warning interrupt disabled,1: Tx Warning interrupt enabled"
newline
bitfld.long 0x00 10. "RWRNMSK,Rx Warning Interrupt Mask" "0: Rx Warning interrupt disabled,1: Rx Warning interrupt enabled"
bitfld.long 0x00 7. "SMP,CAN Bit Sampling" "0: Just one sample is used to determine the bit..,1: Three samples are used to determine the value.."
newline
bitfld.long 0x00 6. "BOFFREC,Bus Off Recovery" "0: Automatic recovering from Bus Off state enabled,1: Automatic recovering from Bus Off state.."
bitfld.long 0x00 5. "TSYN,Timer Sync" "0: Timer sync feature disabled,1: Timer sync feature enabled"
newline
bitfld.long 0x00 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted..,1: Lowest number buffer is transmitted first"
bitfld.long 0x00 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated,1: FlexCAN module operates in Listen-Only mode"
newline
bitfld.long 0x00 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "TIMER,Free Running Timer"
hexmask.long.word 0x00 0.--15. 1. "TIMER,Timer Value"
group.long 0x10++0x03
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register"
hexmask.long 0x00 0.--31. 1. "MG,Rx Mailboxes Global Mask Bits"
group.long 0x14++0x03
line.long 0x00 "RX14MASK,Rx 14 Mask Register"
hexmask.long 0x00 0.--31. 1. "RX14M,Rx Buffer 14 Mask Bits"
group.long 0x18++0x03
line.long 0x00 "RX15MASK,Rx 15 Mask Register"
hexmask.long 0x00 0.--31. 1. "RX15M,Rx Buffer 15 Mask Bits"
group.long 0x1C++0x03
line.long 0x00 "ECR,Error Counter"
hexmask.long.byte 0x00 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for fast bits"
hexmask.long.byte 0x00 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for fast bits"
newline
hexmask.long.byte 0x00 8.--15. 1. "RXERRCNT,Receive Error Counter"
hexmask.long.byte 0x00 0.--7. 1. "TXERRCNT,Transmit Error Counter"
group.long 0x20++0x03
line.long 0x00 "ESR1,Error and Status 1 Register"
rbitfld.long 0x00 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as recessive is.."
rbitfld.long 0x00 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as dominant is received.."
newline
rbitfld.long 0x00 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A CRC error occurred since last read of this.."
rbitfld.long 0x00 27. "FRMERR_FAST,Form Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A form error occurred since last read of this.."
newline
rbitfld.long 0x00 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A stuffing error occurred since last read of.."
eventfld.long 0x00 21. "ERROVR,Error Overrun" "0: Overrun has not occurred,1: Overrun has occurred"
newline
eventfld.long 0x00 20. "ERRINT_FAST,Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set" "0: errors_data_phase_no,1: Indicates setting of any error bit detected.."
eventfld.long 0x00 19. "BOFFDONEINT,Bus Off Done Interrupt" "0: No such occurrence,1: FlexCAN module has completed Bus Off process"
newline
rbitfld.long 0x00 18. "SYNCH,CAN Synchronization Status" "0: FlexCAN is not synchronized to the CAN bus,1: FlexCAN is synchronized to the CAN bus"
eventfld.long 0x00 17. "TWRNINT,Tx Warning Interrupt Flag" "0: No such occurrence,1: The Tx error counter transitioned from less.."
newline
eventfld.long 0x00 16. "RWRNINT,Rx Warning Interrupt Flag" "0: No such occurrence,1: The Rx error counter transitioned from less.."
rbitfld.long 0x00 15. "BIT1ERR,Bit1 Error" "0: No such occurrence,1: At least one bit sent as recessive is.."
newline
rbitfld.long 0x00 14. "BIT0ERR,Bit0 Error" "0: No such occurrence,1: At least one bit sent as dominant is received.."
rbitfld.long 0x00 13. "ACKERR,Acknowledge Error" "0: No such occurrence,1: An ACK error occurred since last read of this.."
newline
rbitfld.long 0x00 12. "CRCERR,Cyclic Redundancy Check Error" "0: No such occurrence,1: A CRC error occurred since last read of this.."
rbitfld.long 0x00 11. "FRMERR,Form Error" "0: No such occurrence,1: A Form Error occurred since last read of this.."
newline
rbitfld.long 0x00 10. "STFERR,Stuffing Error" "0: No such occurrence,1: A stuffing error occurred since last read of.."
rbitfld.long 0x00 9. "TXWRN,TX Error Warning" "0: No such occurrence,1: TXERRCNT is greater than or equal to 96"
newline
rbitfld.long 0x00 8. "RXWRN,Rx Error Warning" "0: No such occurrence,1: RXERRCNT is greater than or equal to 96"
rbitfld.long 0x00 7. "IDLE,IDLE" "0: No such occurrence,1: CAN bus is now IDLE"
newline
rbitfld.long 0x00 6. "TX,FlexCAN In Transmission" "0: FlexCAN is not transmitting a message,1: FlexCAN is transmitting a message"
rbitfld.long 0x00 4.--5. "FLTCONF,Fault Confinement State" "0: error_active,1: error_passive,2: bus_off,3: bus_off"
newline
rbitfld.long 0x00 3. "RX,FlexCAN In Reception" "0: FlexCAN is not receiving a message,1: FlexCAN is receiving a message"
eventfld.long 0x00 2. "BOFFINT,Bus Off Interrupt" "0: No such occurrence,1: FlexCAN module entered Bus Off state"
newline
eventfld.long 0x00 1. "ERRINT,Error Interrupt" "0: No such occurrence,1: Indicates setting of any error bit in the.."
group.long 0x24++0x03
line.long 0x00 "IMASK2,Interrupt Masks 2 Register"
hexmask.long 0x00 0.--31. 1. "BUF63TO32M,Buffer MBi Mask"
group.long 0x28++0x03
line.long 0x00 "IMASK1,Interrupt Masks 1 Register"
hexmask.long 0x00 0.--31. 1. "BUF31TO0M,Buffer MBi Mask"
group.long 0x2C++0x03
line.long 0x00 "IFLAG2,Interrupt Flags 2 Register"
hexmask.long 0x00 0.--31. 1. "BUF63TO32I,Buffer MBi Interrupt"
group.long 0x30++0x03
line.long 0x00 "IFLAG1,Interrupt Flags 1 Register"
hexmask.long.tbyte 0x00 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt"
eventfld.long 0x00 7. "BUF7I,Buffer MB7 Interrupt Or Legacy Rx FIFO Overflow" "0: No occurrence of MB7 completing..,1: MB7 completed transmission/reception when.."
newline
eventfld.long 0x00 6. "BUF6I,Buffer MB6 Interrupt Or Legacy Rx FIFO Warning" "0: No occurrence of MB6 completing..,1: MB6 completed transmission/reception when.."
eventfld.long 0x00 5. "BUF5I,Buffer MB5 Interrupt Or Frames available in Legacy Rx FIFO" "0: No occurrence of MB5 completing..,1: MB5 completed transmission/reception when.."
newline
eventfld.long 0x00 1.--4. "BUF4TO1I,Buffer MBi Interrupt Or Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
eventfld.long 0x00 0. "BUF0I,Buffer MB0 Interrupt Or Clear Legacy FIFO bit" "0: The corresponding buffer has no occurrence of..,1: The corresponding buffer has successfully.."
group.long 0x34++0x03
line.long 0x00 "CTRL2,Control 2 Register"
bitfld.long 0x00 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames" "0: ERRINT_FAST error interrupt disabled,1: ERRINT_FAST error interrupt enabled"
bitfld.long 0x00 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Bus off done interrupt disabled,1: Bus off done interrupt enabled"
newline
bitfld.long 0x00 29. "ECRWRE,Error-correction Configuration Register Write Enable" "0: Disable update,1: Enable update"
bitfld.long 0x00 28. "WRMFRZ,Write-Access To Memory In Freeze Mode" "0: Maintain the write access restrictions,1: Enable unrestricted write access to FlexCAN.."
newline
bitfld.long 0x00 24.--27. "RFFN,Number Of Legacy Rx FIFO Filters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 19.--23. "TASD,Tx Arbitration Start Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 18. "MRP,Mailboxes Reception Priority" "0: Matching starts from Legacy Rx FIFO or..,1: Matching starts from mailboxes and continues.."
bitfld.long 0x00 17. "RRS,Remote Request Storing" "0: remote_response_frame_not_generated,1: remote_response_frame_generated"
newline
bitfld.long 0x00 16. "EACEN,Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes" "0: Rx mailbox filter's IDE bit is always..,1: Enables the comparison of both Rx mailbox.."
bitfld.long 0x00 15. "TIMER_SRC,Timer Source" "0: The free running timer is clocked by the CAN..,1: The free running timer is clocked by an.."
newline
bitfld.long 0x00 14. "PREXCEN,Protocol Exception Enable" "0: Protocol exception is disabled,1: Protocol exception is enabled"
bitfld.long 0x00 13. "BTE,Bit Timing Expansion enable" "0: CAN Bit timing expansion is disabled,1: CAN bit timing expansion is enabled"
newline
bitfld.long 0x00 12. "ISOCANFDEN,ISO CAN FD Enable" "0: FlexCAN operates using the non-ISO CAN FD..,1: FlexCAN operates using the ISO CAN FD.."
bitfld.long 0x00 11. "EDFLTDIS,Edge Filter Disable" "0: Edge filter is enabled,1: Edge filter is disabled"
newline
bitfld.long 0x00 8.--9. "MBTSBASE,Message Buffer Time Stamp Base" "0: Message buffer time stamp base is TIMER,1: Message buffer time stamp base is lower 16..,2: Message buffer time stamp base is upper 16..,?..."
bitfld.long 0x00 6.--7. "TSTAMPCAP,Time Stamp Capture Point" "0: The high resolution time stamp capture is..,1: The high resolution time stamp is captured in..,2: The high resolution time stamp is captured in..,3: The high resolution time stamp is captured in.."
rgroup.long 0x38++0x03
line.long 0x00 "ESR2,Error and Status 2 Register"
hexmask.long.byte 0x00 16.--22. 1. "LPTM,Lowest Priority Tx Mailbox"
bitfld.long 0x00 14. "VPS,Valid Priority Status" "0: Contents of IMB and LPTM are invalid,1: Contents of IMB and LPTM are valid"
newline
bitfld.long 0x00 13. "IMB,Inactive Mailbox" "0: If ESR2[VPS] is asserted the ESR2[LPTM] is..,1: If ESR2[VPS] is asserted there is at least.."
rgroup.long 0x44++0x03
line.long 0x00 "CRCR,CRC Register"
hexmask.long.byte 0x00 16.--22. 1. "MBCRC,CRC Mailbox"
hexmask.long.word 0x00 0.--14. 1. "TXCRC,Transmitted CRC value"
group.long 0x48++0x03
line.long 0x00 "RXFGMASK,Legacy Rx FIFO Global Mask Register"
hexmask.long 0x00 0.--31. 1. "FGM,Legacy Rx FIFO Global Mask Bits"
rgroup.long 0x4C++0x03
line.long 0x00 "RXFIR,Legacy Rx FIFO Information Register"
hexmask.long.word 0x00 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator"
group.long 0x50++0x03
line.long 0x00 "CBT,CAN Bit Timing Register"
bitfld.long 0x00 31. "BTF,Bit Timing Format Enable" "0: Extended bit time definitions disabled,1: Extended bit time definitions enabled"
hexmask.long.word 0x00 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor"
newline
bitfld.long 0x00 16.--20. "ERJW,Extended Resync Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10.--15. "EPROPSEG,Extended Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 5.--9. "EPSEG1,Extended Phase Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "EPSEG2,Extended Phase Segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x6C++0x03
line.long 0x00 "IMASK3,Interrupt Masks 3 Register"
hexmask.long 0x00 0.--31. 1. "BUF95TO64M,Buffer MBi Mask"
group.long 0x74++0x03
line.long 0x00 "IFLAG3,Interrupt Flags 3 Register"
hexmask.long 0x00 0.--31. 1. "BUF95TO64,Buffer MBi Interrupt"
repeat 96. (increment 0 1) (increment 0 0x04)
group.long ($2+0x880)++0x03
line.long 0x00 "RXIMR[$1],Rx Individual Mask Registers $1"
hexmask.long 0x00 0.--31. 1. "MI,Individual Mask Bits"
repeat.end
group.long 0xAE0++0x03
line.long 0x00 "MECR,Memory Error Control Register"
bitfld.long 0x00 31. "ECRWRDIS,Error Configuration Register Write Disable" "0: Write is enabled,1: Write is disabled"
bitfld.long 0x00 15. "HAERRIE,Host Access Error Injection Enable" "0: Injection is disabled,1: Injection is enabled"
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bitfld.long 0x00 14. "FAERRIE,FlexCAN Access Error Injection Enable" "0: Injection is disabled,1: Injection is enabled"
bitfld.long 0x00 13. "EXTERRIE,Extended Error Injection Enable" "0: Error injection is applied only to the 32-bit..,1: Error injection is applied to the 64-bit word"
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bitfld.long 0x00 9. "RERRDIS,Error Report Disable" "0: Enable updates of the error report registers,1: Disable updates of the error report registers"
bitfld.long 0x00 8. "ECCDIS,Error Correction Disable" "0: Enable memory error correction,1: Disable memory error correction"
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bitfld.long 0x00 7. "NCEFAFRZ,Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode" "0: Keep normal operation,1: Put FlexCAN in Freeze mode (see section.."
group.long 0xAE4++0x03
line.long 0x00 "ERRIAR,Error Injection Address Register"
hexmask.long.word 0x00 2.--13. 1. "INJADDR_H,Error Injection Address High"
rbitfld.long 0x00 0.--1. "INJADDR_L,Error Injection Address Low" "0,1,2,3"
group.long 0xAE8++0x03
line.long 0x00 "ERRIDPR,Error Injection Data Pattern Register"
hexmask.long 0x00 0.--31. 1. "DFLIP,Data flip pattern"
group.long 0xAEC++0x03
line.long 0x00 "ERRIPPR,Error Injection Parity Pattern Register"
bitfld.long 0x00 24.--28. "PFLIP3,Parity Flip Pattern For Byte 3 (most significant)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "PFLIP2,Parity Flip Pattern For Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. "PFLIP1,Parity Flip Pattern For Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "PFLIP0,Parity Flip Pattern For Byte 0 (Least Significant)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xAF0++0x03
line.long 0x00 "RERRAR,Error Report Address Register"
bitfld.long 0x00 24. "NCE,Non-Correctable Error" "0: Reporting a correctable error,1: Reporting a non-correctable error"
bitfld.long 0x00 16.--18. "SAID,SAID" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x00 0.--13. 1. "ERRADDR,Address Where Error Detected"
rgroup.long 0xAF4++0x03
line.long 0x00 "RERRDR,Error Report Data Register"
hexmask.long 0x00 0.--31. 1. "RDATA,Raw data word read from memory with error"
rgroup.long 0xAF8++0x03
line.long 0x00 "RERRSYNR,Error Report Syndrome Register"
bitfld.long 0x00 31. "BE3,Byte Enabled For Byte 3 (most significant)" "0: The byte was not,1: The byte was"
bitfld.long 0x00 24.--28. "SYND3,Error Syndrome For Byte 3 (most significant)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 23. "BE2,Byte Enabled For Byte 2" "0: The byte was not,1: The byte was"
bitfld.long 0x00 16.--20. "SYND2,Error Syndrome For Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 15. "BE1,Byte Enabled For Byte 1" "0: The byte was not,1: The byte was"
bitfld.long 0x00 8.--12. "SYND1,Error Syndrome for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "BE0,Byte Enabled For Byte 0 (least significant)" "0: The byte was not,1: The byte was"
bitfld.long 0x00 0.--4. "SYND0,Error Syndrome For Byte 0 (least significant)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xAFC++0x03
line.long 0x00 "ERRSR,Error Status Register"
eventfld.long 0x00 19. "HANCEIF,Host Access With Non-Correctable Error Interrupt Flag" "0: No non-correctable errors were detected in..,1: A non-correctable error was detected in a.."
eventfld.long 0x00 18. "FANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag" "0: No non-correctable errors were detected in..,1: A non-correctable error was detected in a.."
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eventfld.long 0x00 16. "CEIF,Correctable Error Interrupt Flag" "0: No correctable errors were detected so far,1: A correctable error was detected"
eventfld.long 0x00 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag" "0: No overrun on non-correctable errors in host..,1: Overrun on non-correctable errors in host.."
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eventfld.long 0x00 2. "FANCEIOF,FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag" "0: No overrun on non-correctable errors in..,1: Overrun on non-correctable errors in FlexCAN.."
eventfld.long 0x00 0. "CEIOF,Correctable Error Interrupt Overrun Flag" "0: No overrun on correctable errors,1: Overrun on correctable errors"
group.long 0xBF0++0x03
line.long 0x00 "EPRS,Enhanced CAN Bit Timing Prescalers"
hexmask.long.word 0x00 16.--25. 1. "EDPRESDIV,Extended Data Phase Prescaler Division Factor"
hexmask.long.word 0x00 0.--9. 1. "ENPRESDIV,Extended Nominal Prescaler Division Factor"
group.long 0xBF4++0x03
line.long 0x00 "ENCBT,Enhanced Nominal CAN Bit Timing"
hexmask.long.byte 0x00 22.--28. 1. "NRJW,Nominal Resynchronization Jump Width"
hexmask.long.byte 0x00 12.--18. 1. "NTSEG2,Nominal Time Segment 2"
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hexmask.long.byte 0x00 0.--7. 1. "NTSEG1,Nominal Time Segment 1"
group.long 0xBF8++0x03
line.long 0x00 "EDCBT,Enhanced Data Phase CAN bit Timing"
bitfld.long 0x00 22.--25. "DRJW,Data Phase Resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "DTSEG2,Data Phase Time Segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--4. "DTSEG1,Data Phase Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xBFC++0x03
line.long 0x00 "ETDC,Enhanced Transceiver Delay Compensation"
bitfld.long 0x00 31. "ETDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled"
bitfld.long 0x00 30. "TDMDIS,Transceiver Delay Measurement Disable" "0: TDC measurement is enabled,1: TDC measurement is disabled"
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hexmask.long.byte 0x00 16.--22. 1. "ETDCOFF,Enhanced Transceiver Delay Compensation Offset"
eventfld.long 0x00 15. "ETDCFAIL,Transceiver Delay Compensation Fail" "0: Measured loop delay is in range,1: Measured loop delay is out of range"
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hexmask.long.byte 0x00 0.--7. 1. "ETDCVAL,Enhanced Transceiver Delay Compensation Value"
group.long 0xC00++0x03
line.long 0x00 "FDCTRL,CAN FD Control Register"
bitfld.long 0x00 31. "FDRATE,Bit Rate Switch Enable" "0: Transmit a frame in nominal rate,1: Transmit a frame with bit rate switching if.."
bitfld.long 0x00 22.--23. "MBDSR2,Message Buffer Data Size for Region 2" "0: Selects 8 bytes per message buffer,1: Selects 16 bytes per message buffer,2: Selects 32 bytes per message buffer,3: Selects 64 bytes per message buffer"
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bitfld.long 0x00 19.--20. "MBDSR1,Message Buffer Data Size for Region 1" "0: Selects 8 bytes per message buffer,1: Selects 16 bytes per message buffer,2: Selects 32 bytes per message buffer,3: Selects 64 bytes per message buffer"
bitfld.long 0x00 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: Selects 8 bytes per message buffer,1: Selects 16 bytes per message buffer,2: Selects 32 bytes per message buffer,3: Selects 64 bytes per message buffer"
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bitfld.long 0x00 15. "TDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled"
eventfld.long 0x00 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: Measured loop delay is in range,1: Measured loop delay is out of range"
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bitfld.long 0x00 8.--12. "TDCOFF,Transceiver Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 0.--5. "TDCVAL,Transceiver Delay Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC04++0x03
line.long 0x00 "FDCBT,CAN FD Bit Timing Register"
hexmask.long.word 0x00 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor"
bitfld.long 0x00 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 10.--14. "FPROPSEG,Fast Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7"
rgroup.long 0xC08++0x03
line.long 0x00 "FDCRC,CAN FD CRC Register"
hexmask.long.byte 0x00 24.--30. 1. "FD_MBCRC,CRC Mailbox Number for FD_TXCRC"
hexmask.long.tbyte 0x00 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value"
group.long 0xC0C++0x03
line.long 0x00 "ERFCR,Enhanced Rx FIFO Control Register"
bitfld.long 0x00 31. "ERFEN,Enhanced Rx FIFO enable" "0: Enhanced Rx FIFO is disabled,1: Enhanced Rx FIFO is enabled"
bitfld.long 0x00 26.--30. "DMALW,DMA Last Word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 16.--22. 1. "NEXIF,Number of Extended ID Filter Elements"
bitfld.long 0x00 8.--13. "NFE,Number of Enhanced Rx FIFO Filter Elements" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--4. "ERFWM,Enhanced Rx FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC10++0x03
line.long 0x00 "ERFIER,Enhanced Rx FIFO Interrupt Enable Register"
bitfld.long 0x00 31. "ERFUFWIE,Enhanced Rx FIFO Underflow Interrupt Enable" "0: Enhanced Rx FIFO Underflow interrupt is..,1: Enhanced Rx FIFO Underflow interrupt is enabled"
bitfld.long 0x00 30. "ERFOVFIE,Enhanced Rx FIFO Overflow Interrupt Enable" "0: Enhanced Rx FIFO Overflow is disabled,1: Enhanced Rx FIFO Overflow is enabled"
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bitfld.long 0x00 29. "ERFWMIIE,Enhanced Rx FIFO Watermark Indication Interrupt Enable" "0: Enhanced Rx FIFO Watermark interrupt is..,1: Enhanced Rx FIFO Watermark interrupt is enabled"
bitfld.long 0x00 28. "ERFDAIE,Enhanced Rx FIFO Data Available Interrupt Enable" "0: Enhanced Rx FIFO Data Available interrupt is..,1: Enhanced Rx FIFO Data Available interrupt is.."
group.long 0xC14++0x03
line.long 0x00 "ERFSR,Enhanced Rx FIFO Status Register"
eventfld.long 0x00 31. "ERFUFW,Enhanced Rx FIFO Underflow" "0: No such occurrence,1: Enhanced Rx FIFO underflow"
eventfld.long 0x00 30. "ERFOVF,Enhanced Rx FIFO Overflow" "0: No such occurrence,1: Enhanced Rx FIFO overflow"
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eventfld.long 0x00 29. "ERFWMI,Enhanced Rx FIFO Watermark Indication" "0: No such occurrence,1: The number of messages in FIFO is greater.."
eventfld.long 0x00 28. "ERFDA,Enhanced Rx FIFO Data Available" "0: No such occurrence,1: There is at least one message stored in.."
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bitfld.long 0x00 27. "ERFCLR,Enhanced Rx FIFO Clear" "0: no_effect,1: Clear Enhanced Rx FIFO content"
rbitfld.long 0x00 17. "ERFE,Enhanced Rx FIFO empty" "0: Enhanced Rx FIFO is not empty,1: Enhanced Rx FIFO is empty"
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rbitfld.long 0x00 16. "ERFF,Enhanced Rx FIFO full" "0: Enhanced Rx FIFO is not full,1: Enhanced Rx FIFO is full"
rbitfld.long 0x00 0.--5. "ERFEL,Enhanced Rx FIFO Elements" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 96. (increment 0 1) (increment 0 0x04)
group.long ($2+0xC30)++0x03
line.long 0x00 "HR_TIME_STAMP[$1],High Resolution Time Stamp $1"
hexmask.long 0x00 0.--31. 1. "TS,High Resolution Time Stamp"
repeat.end
repeat 128. (increment 0 1) (increment 0 0x04)
group.long ($2+0x3000)++0x03
line.long 0x00 "ERFFEL[$1],Enhanced Rx FIFO Filter Element $1"
hexmask.long 0x00 0.--31. 1. "FEL,Filter Element Bits"
repeat.end
tree.end
repeat.end
tree.end
tree "FLEXTIMER (FTM)"
base ad:0x402A0000
group.long 0x00++0x03
line.long 0x00 "SC,Status And Control"
bitfld.long 0x00 24.--27. "FLTPS,Filter Prescaler" "0: FLTPS_divideby1,1: FLTPS_divideby2,2: FLTPS_divideby3,3: FLTPS_divideby4,4: FLTPS_divideby5,5: FLTPS_divideby6,6: FLTPS_divideby7,7: FLTPS_divideby8,8: FLTPS_divideby9,9: FLTPS_divideby10,10: FLTPS_divideby11,11: FLTPS_divideby12,12: FLTPS_divideby13,13: FLTPS_divideby14,14: FLTPS_divideby15,15: FLTPS_divideby16"
bitfld.long 0x00 23. "PWMEN7,Channel 7 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
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bitfld.long 0x00 22. "PWMEN6,Channel 6 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
bitfld.long 0x00 21. "PWMEN5,Channel 5 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
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bitfld.long 0x00 20. "PWMEN4,Channel 4 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
bitfld.long 0x00 19. "PWMEN3,Channel 3 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
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bitfld.long 0x00 18. "PWMEN2,Channel 2 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
bitfld.long 0x00 17. "PWMEN1,Channel 1 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
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bitfld.long 0x00 16. "PWMEN0,Channel 0 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
bitfld.long 0x00 9. "TOF,Timer Overflow Flag" "0: FTM counter has not overflowed,1: FTM counter has overflowed"
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bitfld.long 0x00 8. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts,1: Enable TOF interrupts"
bitfld.long 0x00 7. "RF,Reload Flag" "0: A selected reload point did not happen,1: A selected reload point happened"
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bitfld.long 0x00 6. "RIE,Reload Point Interrupt Enable" "0: Reload point interrupt is disabled,1: Reload point interrupt is enabled"
bitfld.long 0x00 5. "CPWMS,Center-Aligned PWM Select" "0: FTM counter operates in Up Counting mode,1: FTM counter operates in Up-Down Counting mode"
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bitfld.long 0x00 3.--4. "CLKS,Clock Source Selection" "0: No clock selected,1: CLKS_ftminputclock,2: Fixed frequency clock,3: External clock"
bitfld.long 0x00 0.--2. "PS,Prescale Factor Selection" "0: PS_divideby1,1: PS_divideby2,2: PS_divideby4,3: PS_divideby8,4: PS_divideby16,5: PS_divideby32,6: PS_divideby64,7: PS_divideby128"
group.long 0x04++0x03
line.long 0x00 "CNT,Counter"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Counter Value"
group.long 0x08++0x03
line.long 0x00 "MOD,Modulo"
hexmask.long.word 0x00 0.--15. 1. "MOD,MOD"
group.long 0x4C++0x03
line.long 0x00 "CNTIN,Counter Initial Value"
hexmask.long.word 0x00 0.--15. 1. "INIT,INIT"
group.long 0x50++0x03
line.long 0x00 "STATUS,Capture And Compare Status"
bitfld.long 0x00 7. "CH7F,Channel 7 Flag" "0: No channel event has occurred,1: A channel event has occurred"
bitfld.long 0x00 6. "CH6F,Channel 6 Flag" "0: No channel event has occurred,1: A channel event has occurred"
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bitfld.long 0x00 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred,1: A channel event has occurred"
bitfld.long 0x00 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred,1: A channel event has occurred"
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bitfld.long 0x00 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred,1: A channel event has occurred"
bitfld.long 0x00 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred,1: A channel event has occurred"
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bitfld.long 0x00 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred,1: A channel event has occurred"
bitfld.long 0x00 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred,1: A channel event has occurred"
group.long 0x54++0x03
line.long 0x00 "MODE,Features Mode Selection"
bitfld.long 0x00 4. "CAPTEST,Capture Test Mode Enable" "0: Capture test mode is disabled,1: Capture test mode is enabled"
bitfld.long 0x00 3. "PWMSYNC,PWM Synchronization Mode" "0: No restrictions,1: Software trigger can only be used by MOD and.."
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bitfld.long 0x00 2. "WPDIS,Write Protection Disable" "0: Write protection is enabled,1: Write protection is disabled"
bitfld.long 0x00 1. "INIT,Initialize The Channels Output" "0,1"
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bitfld.long 0x00 0. "FTMEN,FTM Enable" "0: TPM compatibility,1: Free running counter and synchronization are.."
group.long 0x58++0x03
line.long 0x00 "SYNC,Synchronization"
bitfld.long 0x00 7. "SWSYNC,PWM Synchronization Software Trigger" "0: Software trigger is not selected,1: Software trigger is selected"
bitfld.long 0x00 6. "TRIG2,PWM Synchronization Hardware Trigger 2" "0: Trigger is disabled,1: Trigger is enabled"
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bitfld.long 0x00 5. "TRIG1,PWM Synchronization Hardware Trigger 1" "0: Trigger is disabled,1: Trigger is enabled"
bitfld.long 0x00 4. "TRIG0,PWM Synchronization Hardware Trigger 0" "0: Trigger is disabled,1: Trigger is enabled"
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bitfld.long 0x00 3. "SYNCHOM,Output Mask Synchronization" "0: OUTMASK register is updated with the value of..,1: OUTMASK register is updated with the value of.."
bitfld.long 0x00 2. "REINIT,FTM Counter Reinitialization by Synchronization" "0: FTM counter continues to count normally,1: FTM counter is updated with its initial value.."
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bitfld.long 0x00 1. "CNTMAX,Maximum Loading Point Enable" "0: The maximum loading point is disabled,1: The maximum loading point is enabled"
bitfld.long 0x00 0. "CNTMIN,Minimum Loading Point Enable" "0: The minimum loading point is disabled,1: The minimum loading point is enabled"
group.long 0x5C++0x03
line.long 0x00 "OUTINIT,Initial State For Channels Output"
bitfld.long 0x00 7. "CH7OI,Channel 7 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
bitfld.long 0x00 6. "CH6OI,Channel 6 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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bitfld.long 0x00 5. "CH5OI,Channel 5 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
bitfld.long 0x00 4. "CH4OI,Channel 4 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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bitfld.long 0x00 3. "CH3OI,Channel 3 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
bitfld.long 0x00 2. "CH2OI,Channel 2 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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bitfld.long 0x00 1. "CH1OI,Channel 1 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
bitfld.long 0x00 0. "CH0OI,Channel 0 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
group.long 0x60++0x03
line.long 0x00 "OUTMASK,Output Mask"
bitfld.long 0x00 7. "CH7OM,Channel 7 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
bitfld.long 0x00 6. "CH6OM,Channel 6 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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bitfld.long 0x00 5. "CH5OM,Channel 5 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
bitfld.long 0x00 4. "CH4OM,Channel 4 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
newline
bitfld.long 0x00 3. "CH3OM,Channel 3 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
bitfld.long 0x00 2. "CH2OM,Channel 2 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
newline
bitfld.long 0x00 1. "CH1OM,Channel 1 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
bitfld.long 0x00 0. "CH0OM,Channel 0 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
group.long 0x64++0x03
line.long 0x00 "COMBINE,Function For Linked Channels"
bitfld.long 0x00 31. "MCOMBINE3,Modified Combine Mode For n = 6" "0,1"
bitfld.long 0x00 29. "SYNCEN3,Synchronization Enable For n = 6" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
newline
bitfld.long 0x00 28. "DTEN3,Deadtime Enable For n = 6" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
bitfld.long 0x00 27. "DECAP3,Dual Edge Capture Mode Captures For n = 6" "0: The dual edge captures are inactive,1: The dual edge captures are active"
newline
bitfld.long 0x00 26. "DECAPEN3,Dual Edge Capture Mode Enable For n = 6" "0,1"
bitfld.long 0x00 25. "COMP3,Complement Of Channel (n) for n = 6" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
newline
bitfld.long 0x00 24. "COMBINE3,Combine Channels For n = 6" "0,1"
bitfld.long 0x00 23. "MCOMBINE2,Modified Combine Mode For n = 4" "0,1"
newline
bitfld.long 0x00 21. "SYNCEN2,Synchronization Enable For n = 4" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
bitfld.long 0x00 20. "DTEN2,Deadtime Enable For n = 4" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
newline
bitfld.long 0x00 19. "DECAP2,Dual Edge Capture Mode Captures For n = 4" "0: The dual edge captures are inactive,1: The dual edge captures are active"
bitfld.long 0x00 18. "DECAPEN2,Dual Edge Capture Mode Enable For n = 4" "0,1"
newline
bitfld.long 0x00 17. "COMP2,Complement Of Channel (n) For n = 4" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
bitfld.long 0x00 16. "COMBINE2,Combine Channels For n = 4" "0,1"
newline
bitfld.long 0x00 15. "MCOMBINE1,Modified Combine Mode For n = 2" "0,1"
bitfld.long 0x00 13. "SYNCEN1,Synchronization Enable For n = 2" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
newline
bitfld.long 0x00 12. "DTEN1,Deadtime Enable For n = 2" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
bitfld.long 0x00 11. "DECAP1,Dual Edge Capture Mode Captures For n = 2" "0: The dual edge captures are inactive,1: The dual edge captures are active"
newline
bitfld.long 0x00 10. "DECAPEN1,Dual Edge Capture Mode Enable For n = 2" "0,1"
bitfld.long 0x00 9. "COMP1,Complement Of Channel (n) For n = 2" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
newline
bitfld.long 0x00 8. "COMBINE1,Combine Channels For n = 2" "0,1"
bitfld.long 0x00 7. "MCOMBINE0,Modified Combine Mode For n = 0" "0,1"
newline
bitfld.long 0x00 5. "SYNCEN0,Synchronization Enable For n = 0" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
bitfld.long 0x00 4. "DTEN0,Deadtime Enable For n = 0" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
newline
bitfld.long 0x00 3. "DECAP0,Dual Edge Capture Mode Captures For n = 0" "0: The dual edge captures are inactive,1: The dual edge captures are active"
bitfld.long 0x00 2. "DECAPEN0,Dual Edge Capture Mode Enable For n = 0" "0,1"
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bitfld.long 0x00 1. "COMP0,Complement Of Channel (n) For n = 0" "0: If the channels (n) and (n+1) are in Combine..,1: The channel (n+1) output is the complement of.."
bitfld.long 0x00 0. "COMBINE0,Combine Channels For n = 0" "0,1"
group.long 0x68++0x03
line.long 0x00 "DEADTIME,Deadtime Configuration"
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
newline
bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x6C++0x03
line.long 0x00 "EXTTRIG,FTM External Trigger"
bitfld.long 0x00 9. "CH7TRIG,Channel 7 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
bitfld.long 0x00 8. "CH6TRIG,Channel 6 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 7. "TRIGF,Channel Trigger Flag" "0: No channel trigger was generated,1: A channel trigger was generated"
bitfld.long 0x00 6. "INITTRIGEN,Initialization Trigger Enable" "0: The generation of initialization trigger is..,1: The generation of initialization trigger is.."
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bitfld.long 0x00 5. "CH1TRIG,Channel 1 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
bitfld.long 0x00 4. "CH0TRIG,Channel 0 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 3. "CH5TRIG,Channel 5 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
bitfld.long 0x00 2. "CH4TRIG,Channel 4 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
newline
bitfld.long 0x00 1. "CH3TRIG,Channel 3 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
bitfld.long 0x00 0. "CH2TRIG,Channel 2 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
group.long 0x70++0x03
line.long 0x00 "POL,Channels Polarity"
bitfld.long 0x00 7. "POL7,Channel 7 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
bitfld.long 0x00 6. "POL6,Channel 6 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
bitfld.long 0x00 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
newline
bitfld.long 0x00 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
bitfld.long 0x00 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
newline
bitfld.long 0x00 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
bitfld.long 0x00 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
group.long 0x74++0x03
line.long 0x00 "FMS,Fault Mode Status"
bitfld.long 0x00 6. "WPEN,Write Protection Enable" "0: Write protection is disabled,1: Write protection is enabled"
group.long 0x78++0x03
line.long 0x00 "FILTER,Input Capture Filter Control"
bitfld.long 0x00 12.--15. "CH3FVAL,Channel 3 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "CH2FVAL,Channel 2 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "CH1FVAL,Channel 1 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "CH0FVAL,Channel 0 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80++0x03
line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status"
bitfld.long 0x00 7. "PHAFLTREN,Phase A Input Filter Enable" "0: Phase A input filter is disabled,1: Phase A input filter is enabled"
bitfld.long 0x00 6. "PHBFLTREN,Phase B Input Filter Enable" "0: Phase B input filter is disabled,1: Phase B input filter is enabled"
newline
bitfld.long 0x00 5. "PHAPOL,Phase A Input Polarity" "0: Normal polarity,1: Inverted polarity"
bitfld.long 0x00 4. "PHBPOL,Phase B Input Polarity" "0: Normal polarity,1: Inverted polarity"
newline
bitfld.long 0x00 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase A and phase B encoding mode,1: Count and direction encoding mode"
rbitfld.long 0x00 2. "QUADIR,FTM Counter Direction In Quadrature Decoder Mode" "0: Counting direction is decreasing (FTM counter..,1: Counting direction is increasing (FTM counter.."
newline
rbitfld.long 0x00 1. "TOFDIR,Timer Overflow Direction In Quadrature Decoder Mode" "0: TOF bit was set on the bottom of counting,1: TOF bit was set on the top of counting"
bitfld.long 0x00 0. "QUADEN,Quadrature Decoder Mode Enable" "0: Quadrature Decoder mode is disabled,1: Quadrature Decoder mode is enabled"
group.long 0x84++0x03
line.long 0x00 "CONF,Configuration"
bitfld.long 0x00 11. "ITRIGR,Initialization trigger on Reload Point" "0: Initialization trigger is generated on..,1: Initialization trigger is generated when a.."
bitfld.long 0x00 10. "GTBEOUT,Global Time Base Output" "0: A global time base signal generation is..,1: A global time base signal generation is enabled"
newline
bitfld.long 0x00 9. "GTBEEN,Global Time Base Enable" "0: Use of an external global time base is disabled,1: Use of an external global time base is enabled"
bitfld.long 0x00 6.--7. "BDMMODE,Debug Mode" "0,1,2,3"
newline
bitfld.long 0x00 0.--4. "LDFQ,Frequency of the Reload Opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x8C++0x03
line.long 0x00 "SYNCONF,Synchronization Configuration"
bitfld.long 0x00 20. "HWSOC,Software output control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the SWOCTRL.."
bitfld.long 0x00 19. "HWINVC,Inverting control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the INVCTRL.."
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bitfld.long 0x00 18. "HWOM,Output mask synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the OUTMASK.."
bitfld.long 0x00 17. "HWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate MOD HCR..,1: A hardware trigger activates MOD HCR CNTIN.."
newline
bitfld.long 0x00 16. "HWRSTCNT,FTM counter synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the FTM..,1: A hardware trigger activates the FTM counter.."
bitfld.long 0x00 12. "SWSOC,Software output control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the SWOCTRL.."
newline
bitfld.long 0x00 11. "SWINVC,Inverting control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the INVCTRL.."
bitfld.long 0x00 10. "SWOM,Output mask synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the OUTMASK.."
newline
bitfld.long 0x00 9. "SWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by the software trigger" "0: The software trigger does not activate MOD..,1: The software trigger activates MOD HCR CNTIN.."
bitfld.long 0x00 8. "SWRSTCNT,FTM counter synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the FTM.."
newline
bitfld.long 0x00 7. "SYNCMODE,Synchronization Mode" "0: Legacy PWM synchronization is selected,1: Enhanced PWM synchronization is selected"
bitfld.long 0x00 5. "SWOC,SWOCTRL Register Synchronization" "0: SWOCTRL register is updated with its buffer..,1: SWOCTRL register is updated with its buffer.."
newline
bitfld.long 0x00 4. "INVC,INVCTRL Register Synchronization" "0: INVCTRL register is updated with its buffer..,1: INVCTRL register is updated with its buffer.."
bitfld.long 0x00 2. "CNTINC,CNTIN Register Synchronization" "0: CNTIN register is updated with its buffer..,1: CNTIN register is updated with its buffer.."
newline
bitfld.long 0x00 0. "HWTRIGMODE,Hardware Trigger Mode" "0: FTM clears the TRIGj bit when the hardware..,1: FTM does not clear the TRIGj bit when the.."
group.long 0x90++0x03
line.long 0x00 "INVCTRL,FTM Inverting Control"
bitfld.long 0x00 3. "INV3EN,Pair Channels 3 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
bitfld.long 0x00 2. "INV2EN,Pair Channels 2 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
newline
bitfld.long 0x00 1. "INV1EN,Pair Channels 1 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
bitfld.long 0x00 0. "INV0EN,Pair Channels 0 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
group.long 0x94++0x03
line.long 0x00 "SWOCTRL,FTM Software Output Control"
bitfld.long 0x00 15. "CH7OCV,Channel 7 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
bitfld.long 0x00 14. "CH6OCV,Channel 6 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
newline
bitfld.long 0x00 13. "CH5OCV,Channel 5 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
bitfld.long 0x00 12. "CH4OCV,Channel 4 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
newline
bitfld.long 0x00 11. "CH3OCV,Channel 3 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
bitfld.long 0x00 10. "CH2OCV,Channel 2 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
newline
bitfld.long 0x00 9. "CH1OCV,Channel 1 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
bitfld.long 0x00 8. "CH0OCV,Channel 0 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
newline
bitfld.long 0x00 7. "CH7OC,Channel 7 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
bitfld.long 0x00 6. "CH6OC,Channel 6 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
newline
bitfld.long 0x00 5. "CH5OC,Channel 5 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
bitfld.long 0x00 4. "CH4OC,Channel 4 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
newline
bitfld.long 0x00 3. "CH3OC,Channel 3 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
bitfld.long 0x00 2. "CH2OC,Channel 2 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
newline
bitfld.long 0x00 1. "CH1OC,Channel 1 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
bitfld.long 0x00 0. "CH0OC,Channel 0 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
group.long 0x98++0x03
line.long 0x00 "PWMLOAD,FTM PWM Load"
bitfld.long 0x00 11. "GLDOK,Global Load OK" "0: No action,1: LDOK bit is set"
bitfld.long 0x00 10. "GLEN,Global Load Enable" "0: Global Load Ok disabled,1: Global Load OK enabled"
newline
bitfld.long 0x00 9. "LDOK,Load Enable" "0: Loading updated values is disabled,1: Loading updated values is enabled"
bitfld.long 0x00 8. "HCSEL,Half Cycle Select" "0: Half cycle reload is disabled and it is not..,1: Half cycle reload is enabled and it is.."
newline
bitfld.long 0x00 7. "CH7SEL,Channel 7 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
bitfld.long 0x00 6. "CH6SEL,Channel 6 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
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bitfld.long 0x00 5. "CH5SEL,Channel 5 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
bitfld.long 0x00 4. "CH4SEL,Channel 4 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
newline
bitfld.long 0x00 3. "CH3SEL,Channel 3 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
bitfld.long 0x00 2. "CH2SEL,Channel 2 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
newline
bitfld.long 0x00 1. "CH1SEL,Channel 1 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
bitfld.long 0x00 0. "CH0SEL,Channel 0 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
group.long 0x9C++0x03
line.long 0x00 "HCR,Half Cycle Register"
hexmask.long.word 0x00 0.--15. 1. "HCVAL,Half Cycle Value"
group.long 0x200++0x03
line.long 0x00 "MOD_MIRROR,Mirror of Modulo Value"
hexmask.long.word 0x00 16.--31. 1. "MOD,Mirror of the Modulo Integer Value"
bitfld.long 0x00 11.--15. "FRACMOD,Modulo Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x204)++0x03
line.long 0x00 "CV_MIRROR[$1],Mirror of Channel (n) Match Value $1"
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 8. (increment 0 1)(increment  0 0x8)
tree "CONTROLS[$1]"
group.long ($2+0x0C)++0x03
line.long 0x00 "CSC,Channel (n) Status And Control"
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
newline
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
bitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
newline
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
newline
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
newline
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
newline
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
group.long ($2+0x10)++0x03
line.long 0x00 "CV,Channel (n) Value"
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
tree.end
repeat.end
tree.end
tree "FXOSC"
base ad:0x40084000
group.long 0x00++0x03
line.long 0x00 "CTRL,FXOSC Control Register"
bitfld.long 0x00 31. "OSC_BYP,Oscillator bypass" "0: Internal oscillator not bypassed,1: Internal oscillator bypassed"
bitfld.long 0x00 24. "COMP_EN,Comparator enable" "0: Comparator disabled,1: Comparator enabled"
hexmask.long.byte 0x00 16.--23. 1. "EOCV,End of count value"
newline
bitfld.long 0x00 4.--7. "GM_SEL,Crystal overdrive protection" "0: gm_sel_0000,1: gm_sel_0001,2: gm_sel_0010,3: gm_sel_0011,4: gm_sel_0100,5: gm_sel_0101,6: gm_sel_0110,7: gm_sel_0111,8: gm_sel_1000,9: gm_sel_1001,10: gm_sel_1010,11: gm_sel_1011,12: gm_sel_1100,13: gm_sel_1101,14: gm_sel_1110,15: gm_sel_1111"
bitfld.long 0x00 2. "ALC_D,Automatic level controller enable" "0: Enables automatic level controller,1: Disables automatic level controller"
bitfld.long 0x00 0. "OSCON,Crystal oscillator power-down control" "0: Disables FXOSC,1: Enables FXOSC"
rgroup.long 0x04++0x03
line.long 0x00 "STAT,Oscillator Status Register"
bitfld.long 0x00 31. "OSC_STAT,Crystal oscillator status" "0: Crystal oscillator is off or on but not stable,1: Crystal oscillator is on and providing a.."
tree.end
tree "GMAC (Realtime GMAC)"
tree "GMAC_0"
base ad:0x400F4000
group.long 0x00++0x03
line.long 0x00 "MAC_Configuration,The MAC Configuration Register establishes the operating mode of the MAC"
bitfld.long 0x00 31. "ARPEN,ARP Offload Enable When this bit is set the MAC can recognize an incoming ARP request packet and schedules the ARP packet for transmission" "0: ARP Offload is disabled,1: ARP Offload is enabled"
newline
bitfld.long 0x00 28.--30. "SARC,Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted packets" "0: mti_sa_ctrl_i and ati_sa_ctrl_i input signals..,?,2: Contents of MAC Addr-0 inserted in SA field,3: Contents of MAC Addr-0 replaces SA field,?,?,6: Contents of MAC Addr-1 inserted in SA field,7: Contents of MAC Addr-1 replaces SA field"
newline
bitfld.long 0x00 27. "IPC,Checksum Offload When set this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP UDP or ICMP payload checksum checking" "0: IP header/payload checksum checking is disabled,1: IP header/payload checksum checking is enabled"
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bitfld.long 0x00 24.--26. "IPG,Inter-Packet Gap These bits control the minimum IPG between packets during transmission" "0: 96 bit times IPG,1: 88 bit times IPG,2: 80 bit times IPG,3: 72 bit times IPG,4: 64 bit times IPG,5: 56 bit times IPG,6: 48 bit times IPG,7: 40 bit times IPG"
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bitfld.long 0x00 23. "GPSLCE,Giant Packet Size Limit Control Enable When this bit is set the MAC considers the value in GPSL field in MAC_Ext_Configuration register to declare a received packet as Giant packet" "0: Giant Packet Size Limit Control is disabled,1: Giant Packet Size Limit Control is enabled"
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bitfld.long 0x00 22. "S2KP,IEEE 802" "0: Support up to 2K packet is disabled,1: Support up to 2K packet is Enabled"
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bitfld.long 0x00 21. "CST,CRC stripping for Type packets When this bit is set the last four bytes (FCS) of all packets of Ether type (type field greater than 1 536) are stripped and dropped before forwarding the packet to the application" "0: CRC stripping for Type packets is disabled,1: CRC stripping for Type packets is enabled"
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bitfld.long 0x00 20. "ACS,Automatic Pad or CRC Stripping When this bit is set the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1 536 bytes" "0: Automatic Pad or CRC Stripping is disabled,1: Automatic Pad or CRC Stripping is enabled"
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bitfld.long 0x00 19. "WD,Watchdog Disable When this bit is set the MAC disables the watchdog timer on the receiver" "0: Watchdog is enabled,1: Watchdog is disabled"
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bitfld.long 0x00 18. "BE,Packet Burst Enable When this bit is set the MAC allows packet bursting during transmission in the GMII half-duplex mode" "0: Packet Burst is disabled,1: Packet Burst is enabled"
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bitfld.long 0x00 17. "JD,Jabber Disable When this bit is set the MAC disables the jabber timer on the transmitter" "0: Jabber is enabled,1: Jabber is disabled"
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bitfld.long 0x00 16. "JE,Jumbo Packet Enable When this bit is set the MAC allows jumbo packets of 9 018 bytes (9 022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status" "0: Jumbo packet is disabled,1: Jumbo packet is enabled"
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bitfld.long 0x00 15. "PS,Port Select This bit selects the Ethernet line speed" "0: For 1000 or 2500 Mbps operations,1: For 10 or 100 Mbps operations"
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bitfld.long 0x00 14. "FES,Speed This bit selects the speed mode" "0: 10 Mbps when PS bit is 1 and 1 Gbps when PS..,1: 100 Mbps when PS bit is 1 and 2.5 Gbps when.."
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bitfld.long 0x00 13. "DM,Duplex Mode When this bit is set the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously" "0: Half-duplex mode,1: Full-duplex mode"
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bitfld.long 0x00 12. "LM,Loopback Mode When this bit is set the MAC operates in the loopback mode at GMII or MII" "0: Loopback is disabled,1: Loopback is enabled"
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bitfld.long 0x00 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode" "0: ECRSFD is disabled,1: ECRSFD is enabled"
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bitfld.long 0x00 10. "DO,Disable Receive Own When this bit is set the MAC disables the reception of packets when the gmii_txen_o is asserted in the half-duplex mode" "0: Enable Receive Own,1: Disable Receive Own"
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bitfld.long 0x00 9. "DCRS,Disable Carrier Sense During Transmission When this bit is set the MAC transmitter ignores the (G)MII CRS signal during packet transmission in the half-duplex mode" "0: Enable Carrier Sense During Transmission,1: Disable Carrier Sense During Transmission"
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bitfld.long 0x00 8. "DR,Disable Retry When this bit is set the MAC attempts only one transmission" "0: Enable Retry,1: Disable Retry"
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bitfld.long 0x00 5.--6. "BL,Back-Off Limit The back-off limit determines the random integer number (r) of slot time delays (4 096 bit times for 1000/2500 Mbps 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after.." "0: k = min(n 10),1: k = min(n 8),2: k = min(n 4),3: k = min(n 1)"
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bitfld.long 0x00 4. "DC,Deferral Check When this bit is set the deferral check function is enabled in the MAC" "0: Deferral check function is disabled,1: Deferral check function is enabled"
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bitfld.long 0x00 2.--3. "PRELEN,Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,?..."
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bitfld.long 0x00 1. "TE,Transmitter Enable When this bit is set the Tx state machine of the MAC is enabled for transmission on the GMII or MII interface" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x00 0. "RE,Receiver Enable When this bit is set the Rx state machine of the MAC is enabled for receiving packets from the GMII or MII interface" "0: Receiver is disabled,1: Receiver is enabled"
group.long 0x04++0x03
line.long 0x00 "MAC_Ext_Configuration,The MAC Extended Configuration Register establishes the operating mode of the MAC"
bitfld.long 0x00 30. "APDIM,ARP Packet Drop if IP Address Mismatch When this bit is set Packet for which Target Protocol Address does not match IPv4 address is dropped in the MTL layer" "0: mux select to drop the arp packet if target..,1: mux select to drop the arp packet if target.."
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bitfld.long 0x00 25.--29. "EIPG,Extended Inter-Packet Gap The value in this field is applicable when the EIPGEN bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 24. "EIPGEN,Extended Inter-Packet Gap Enable When this bit is set the MAC interprets EIPG field and IPG field in MAC_Configuration register together as minimum IPG greater than 96 bit times in steps of 8 bit times" "0: Extended Inter-Packet Gap is disabled,1: Extended Inter-Packet Gap is enabled"
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bitfld.long 0x00 20.--22. "HDSMS,Maximum Size for Splitting the Header Data These bits indicate the maximum header size allowed for splitting the header data in the received packet" "0: Maximum Size for Splitting the Header Data is..,1: Maximum Size for Splitting the Header Data is..,2: Maximum Size for Splitting the Header Data is..,3: Maximum Size for Splitting the Header Data is..,4: Maximum Size for Splitting the Header Data is..,?..."
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bitfld.long 0x00 19. "PDC,Packet Duplication Control When this bit is set the received packet with Multicast/Broadcast Destination address is routed to multiple Receive DMA Channels" "0: Packet Duplication Control is disabled,1: Packet Duplication Control is enabled"
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bitfld.long 0x00 18. "USP,Unicast Slow Protocol Packet Detect When this bit is set the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC_Address0_High and MAC_Address0_Low registers" "0: Unicast Slow Protocol Packet Detection is..,1: Unicast Slow Protocol Packet Detection is.."
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bitfld.long 0x00 17. "SPEN,Slow Protocol Detection Enable When this bit is set MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Slow Protocol Sub-Type and Code fields in Rx status" "0: Slow Protocol Detection is disabled,1: Slow Protocol Detection is enabled"
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bitfld.long 0x00 16. "DCRCC,Disable CRC Checking for Received Packets When this bit is set the MAC receiver does not check the CRC field in the received packets" "0: CRC Checking is enabled,1: CRC Checking is disabled"
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hexmask.long.word 0x00 0.--13. 1. "GPSL,Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes the MAC declares the received packet as Giant packet"
group.long 0x08++0x03
line.long 0x00 "MAC_Packet_Filter,The MAC Packet Filter register contains the filter controls for receiving packets"
bitfld.long 0x00 31. "RA,Receive All When this bit is set the MAC Receiver module passes all received packets to the application irrespective of whether they pass the address filter or not" "0: Receive All is disabled,1: Receive All is enabled"
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bitfld.long 0x00 21. "DNTU,Drop Non-TCP/UDP over IP Packets When this bit is set the MAC drops the non-TCP or UDP over IP packets" "0: Forward Non-TCP/UDP over IP Packets,1: Drop Non-TCP/UDP over IP Packets"
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bitfld.long 0x00 20. "IPFE,Layer 3 and Layer 4 Filter Enable When this bit is set the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters" "0: Layer 3 and Layer 4 Filters are disabled,1: Layer 3 and Layer 4 Filters are enabled"
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bitfld.long 0x00 16. "VTFE,VLAN Tag Filter Enable When this bit is set the MAC drops the VLAN tagged packets that do not match the VLAN Tag" "0: VLAN Tag Filter is disabled,1: VLAN Tag Filter is enabled"
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bitfld.long 0x00 10. "HPF,Hash or Perfect Filter When this bit is set the address filter passes a packet if it matches either the perfect filtering or hash filtering as set by the HMC or HUC bit" "0: Hash or Perfect Filter is disabled,1: Hash or Perfect Filter is enabled"
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bitfld.long 0x00 9. "SAF,Source Address Filter Enable When this bit is set the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers" "0: SA Filtering is disabled,1: SA Filtering is enabled"
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bitfld.long 0x00 8. "SAIF,SA Inverse Filtering When this bit is set the Address Check block operates in the inverse filtering mode for SA address comparison" "0: SA Inverse Filtering is disabled,1: SA Inverse Filtering is enabled"
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bitfld.long 0x00 6.--7. "PCF,Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets)" "0: MAC filters all control packets from reaching..,1: MAC forwards all control packets except Pause..,2: MAC forwards all control packets to the..,3: MAC forwards the control packets that pass.."
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bitfld.long 0x00 5. "DBF,Disable Broadcast Packets When this bit is set the AFM module blocks all the incoming broadcast packets" "0: Enable Broadcast Packets,1: Disable Broadcast Packets"
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bitfld.long 0x00 4. "PM,Pass All Multicast When this bit is set it indicates that all the received packets with a multicast destination address (first bit in the destination address field is '1') are passed" "0: Pass All Multicast is disabled,1: Pass All Multicast is enabled"
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bitfld.long 0x00 3. "DAIF,DA Inverse Filtering When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets" "0: DA Inverse Filtering is disabled,1: DA Inverse Filtering is enabled"
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bitfld.long 0x00 2. "HMC,Hash Multicast When this bit is set the MAC performs the destination address filtering of received multicast packets according to the hash table" "0: Hash Multicast is disabled,1: Hash Multicast is enabled"
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bitfld.long 0x00 1. "HUC,Hash Unicast When this bit is set the MAC performs the destination address filtering of unicast packets according to the hash table" "0: Hash Unicast is disabled,1: Hash Unicast is enabled"
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bitfld.long 0x00 0. "PR,Promiscuous Mode When this bit is set the Address Filtering module passes all incoming packets irrespective of the destination or source address" "0: Promiscuous Mode is disabled,1: Promiscuous Mode is enabled"
group.long 0x0C++0x03
line.long 0x00 "MAC_Watchdog_Timeout,The Watchdog Timeout register controls the watchdog timeout for received packets"
bitfld.long 0x00 8. "PWE,Programmable Watchdog Enable When this bit is set and the WD bit of the MAC_Configuration register is reset the WTO field is used as watchdog timeout for a received packet" "0: Programmable Watchdog is disabled,1: Programmable Watchdog is enabled"
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bitfld.long 0x00 0.--3. "WTO,Watchdog Timeout When the PWE bit is set and the WD bit of the MAC_Configuration register is reset this field is used as watchdog timeout for a received packet" "0: M_2KBYTES,1: M_3KBYTES,2: M_4KBYTES,3: M_5KBYTES,4: M_6KBYTES,5: M_7KBYTES,6: M_8KBYTES,7: M_9KBYTES,8: M_10KBYTES,9: M_11KBYTES,10: M_12KBYTES,11: M_13KBYTES,12: M_14KBYTES,13: M_15KBYTES,14: M_16383BYTES,?..."
group.long 0x10++0x03
line.long 0x00 "MAC_Hash_Table_Reg0,The Hash Table Register 0 contains the first 32 bits of the hash table when the width of the hash table is 128 or 256 bits"
hexmask.long 0x00 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table"
group.long 0x14++0x03
line.long 0x00 "MAC_Hash_Table_Reg1,The Hash Table Register 1 contains the second 32 bits of the hash table"
hexmask.long 0x00 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table"
group.long 0x50++0x03
line.long 0x00 "MAC_VLAN_Tag_Ctrl,This register is the redefined format of the MAC VLAN Tag Register"
bitfld.long 0x00 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status When this bit is set the MAC provides the inner VLAN Tag in the Rx status" "0: Inner VLAN Tag in Rx status is disabled,1: Inner VLAN Tag in Rx status is enabled"
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bitfld.long 0x00 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
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bitfld.long 0x00 27. "ERIVLT,Enable Inner VLAN Tag Comparison When this bit VTHM bit and the EDVLP field are set the MAC receiver enables VLAN Hash filtering operation on the inner VLAN Tag (if present)" "0: Inner VLAN tag is disabled,1: Inner VLAN tag is enabled"
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bitfld.long 0x00 26. "EDVLP,Enable Double VLAN Processing When this bit is set the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present)" "0: Double VLAN Processing is disabled,1: Double VLAN Processing is enabled"
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bitfld.long 0x00 25. "VTHM,VLAN Tag Hash Table Match Enable When this bit is set the most significant four bits of CRC of VLAN Tag are used to index the content of the MAC_VLAN_Hash_Table register" "0: VLAN Tag Hash Table Match is disabled,1: VLAN Tag Hash Table Match is enabled"
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bitfld.long 0x00 24. "EVLRXS,Enable VLAN Tag in Rx status When this bit is set MAC provides the outer VLAN Tag in the Rx status" "0: VLAN Tag in Rx status is disabled,1: VLAN Tag in Rx status is enabled"
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bitfld.long 0x00 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
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bitfld.long 0x00 20. "DOVLTC,Disable VLAN Type Check for VLAN Hash Filtering When this bit is set the MAC VLAN Hash Filter does not check whether the VLAN Tag specified by the ERIVLT bit is of type S-VLAN or C-VLAN" "0: VLAN Type Check is enabled,1: VLAN Type Check is disabled"
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bitfld.long 0x00 19. "ERSVLM,Enable Receive S-VLAN Match for VLAN Hash Filtering When this bit is set the MAC receiver enables VLAN Hash filtering or matching for S-VLAN (Type = 0x88A8) packets" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled"
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bitfld.long 0x00 18. "ESVL,Enable S-VLAN When this bit is set the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets" "0: S-VLAN is disabled,1: S-VLAN is enabled"
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bitfld.long 0x00 17. "VTIM,VLAN Tag Inverse Match Enable When this bit is set this bit enables the VLAN Tag inverse matching" "0: VLAN Tag Inverse Match is disabled,1: VLAN Tag Inverse Match is enabled"
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bitfld.long 0x00 16. "ETV,Enable 12-Bit VLAN Tag Comparison for VLAN Hash Filtering When this bit is set a 12-bit VLAN identifier is used for VLAN Hash filtering instead of the complete 16-bit VLAN tag" "0: 12-Bit VLAN Tag Comparison is disabled,1: 12-Bit VLAN Tag Comparison is enabled"
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bitfld.long 0x00 2.--3. "OFS,Offset This field holds the address offset of the MAC VLAN Tag Filter Register which the application is trying to access" "0,1,2,3"
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bitfld.long 0x00 1. "CT,Command Type This bit indicates if the current register access is a read or a" "0: Write operation,1: Read operation"
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bitfld.long 0x00 0. "OB,Operation Busy This bit is set along with a read or write command for initiating the indirect access to per VLAN Tag Filter register" "0: Operation Busy is disabled,1: Operation Busy is enabled"
group.long 0x54++0x03
line.long 0x00 "MAC_VLAN_Tag_Data,This register holds the read/write data for Indirect Access of the Per VLAN Tag registers"
bitfld.long 0x00 25. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1"
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bitfld.long 0x00 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled"
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bitfld.long 0x00 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled"
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bitfld.long 0x00 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled"
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bitfld.long 0x00 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled"
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bitfld.long 0x00 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison"
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bitfld.long 0x00 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled"
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hexmask.long.word 0x00 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison"
group.long 0x58++0x03
line.long 0x00 "MAC_VLAN_Hash_Table,When VTHM bit of the MAC_VLAN_Tag register is set the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag"
hexmask.long.word 0x00 0.--15. 1. "VLHT,VLAN Hash Table This field contains the 16-bit VLAN Hash Table"
group.long 0x60++0x03
line.long 0x00 "MAC_VLAN_Incl,The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets"
rbitfld.long 0x00 31. "BUSY,Busy This bit indicates the status of the read/write operation of indirect access to the queue/channel specific VLAN inclusion register" "0: Busy status not detected,1: Busy status detected"
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bitfld.long 0x00 30. "RDWR,Read write control This bit controls the read or write operation for indirectly accessing the queue/channel specific VLAN Inclusion register" "0: Read operation of indirect access,1: Write operation of indirect access"
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bitfld.long 0x00 24. "ADDR,Address This field selects one of the queue/channel specific VLAN Inclusion register for read/write access" "0,1"
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bitfld.long 0x00 21. "CBTI,Channel based tag insertion When this bit is set outer VLAN tag is inserted for every packets transmitted by the MAC" "0: Channel based tag insertion is disabled,1: Channel based tag insertion is enabled"
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bitfld.long 0x00 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled"
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bitfld.long 0x00 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted or replaced,1: S-VLAN type (0x88A8) is inserted or replaced"
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bitfld.long 0x00 18. "VLP,VLAN Priority Control When this bit is set the control bits[17:16] are used for VLAN deletion insertion or replacement" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled"
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bitfld.long 0x00 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
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hexmask.long.word 0x00 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced"
group.long 0x64++0x03
line.long 0x00 "MAC_Inner_VLAN_Incl,The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet"
bitfld.long 0x00 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled"
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bitfld.long 0x00 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 17th and 18th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted"
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bitfld.long 0x00 18. "VLP,VLAN Priority Control When this bit is set the VLC field is used for VLAN deletion insertion or replacement" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled"
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bitfld.long 0x00 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
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hexmask.long.word 0x00 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced"
group.long 0x70++0x03
line.long 0x00 "MAC_Q0_Tx_Flow_Ctrl,The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC"
hexmask.long.word 0x00 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet"
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bitfld.long 0x00 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled"
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bitfld.long 0x00 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot..,1: Pause Time minus 28 Slot Times (PT -28 slot..,2: Pause Time minus 36 Slot Times (PT -36 slot..,3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?..."
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bitfld.long 0x00 1. "TFE,Transmit Flow Control Enable Full-Duplex Mode: In the full-duplex mode when this bit is set the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled"
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bitfld.long 0x00 0. "FCB_BPA,Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.."
group.long 0x90++0x03
line.long 0x00 "MAC_Rx_Flow_Ctrl,The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet"
bitfld.long 0x00 1. "UP,Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802" "0: Unicast Pause Packet Detect disabled,1: Unicast Pause Packet Detect enabled"
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bitfld.long 0x00 0. "RFE,Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex mode the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time" "0: Receive Flow Control is disabled,1: Receive Flow Control is enabled"
group.long 0x94++0x03
line.long 0x00 "MAC_RxQ_Ctrl4,The Receive Queue Control 4 register controls the routing of unicast and multicast packets that fail the Destination or Source address filter to the Rx queues"
bitfld.long 0x00 17. "VFFQ,VLAN Tag Filter Fail Packets Queue This field holds the Rx queue number to which the tagged packets failing the Destination or Source Address filter (and UFFQE/MFFQE not enabled) or failing the VLAN tag filter must be routed to" "0,1"
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bitfld.long 0x00 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable When this bit is set the tagged packets which fail the Destination or Source address filter or fail the VLAN tag filter are routed to the Rx Queue Number programmed in the VFFQ" "0: VLAN tag Filter Fail Packets Queuing is..,1: VLAN tag Filter Fail Packets Queuing is enabled"
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bitfld.long 0x00 9. "MFFQ,Multicast Address Filter Fail Packets Queue" "0,1"
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bitfld.long 0x00 8. "MFFQE,Multicast Address Filter Fail Packets Queuing Enable" "0: Multicast Address Filter Fail Packets Queuing..,1: Multicast Address Filter Fail Packets Queuing.."
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bitfld.long 0x00 1. "UFFQ,Unicast Address Filter Fail Packets Queue" "0,1"
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bitfld.long 0x00 0. "UFFQE,Unicast Address Filter Fail Packets Queuing Enable" "0: Unicast Address Filter Fail Packets Queuing..,1: Unicast Address Filter Fail Packets Queuing.."
group.long 0xA0++0x03
line.long 0x00 "MAC_RxQ_Ctrl0,The Receive Queue Control 0 register controls the queue management in the MAC Receiver"
bitfld.long 0x00 2.--3. "RXQ1EN,Receive Queue 1 Enable This field is similar to the RXQ0EN field" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
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bitfld.long 0x00 0.--1. "RXQ0EN,Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
group.long 0xA4++0x03
line.long 0x00 "MAC_RxQ_Ctrl1,The Receive Queue Control 1 register controls the routing of multicast broadcast AV DCB and untagged packets to the Rx queues"
bitfld.long 0x00 29. "TBRQE,Type Field Based Rx Queuing Enable When this bit is set it enables Type Field based Rx Queuing where the Type field of received packet is compared with programmed TYP field in MAC_TMRQ_Regs(#i) and if a match occurs the packet is routed to the.." "0,1"
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bitfld.long 0x00 28. "OMCBCQ,Over-riding MC-BC queue priority select" "0: overriding MCBCQ priority disabled,1: overriding MCBCQ priority enabled"
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bitfld.long 0x00 24.--26. "FPRQ,Frame Preemption Residue Queue This field holds the Rx queue number to which the residual preemption frames must be forwarded" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 22.--23. "TPQC,Tagged PTP over Ethernet Packets Queuing Control" "0,1,2,3"
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bitfld.long 0x00 21. "TACPQE,Tagged AV Control Packets Queuing Enable" "0: Tagged AV Control Packets Queuing is disabled,1: Tagged AV Control Packets Queuing is enabled"
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bitfld.long 0x00 20. "MCBCQEN,Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed to Rx Queue specified in MCBCQ field" "0: Multicast and Broadcast Queue is disabled,1: Multicast and Broadcast Queue is enabled"
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bitfld.long 0x00 16.--18. "MCBCQ,Multicast and Broadcast Queue This field specifies the Rx Queue onto which Multicast or Broadcast Packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7"
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bitfld.long 0x00 12.--14. "UPQ,Untagged Packet Queue This field indicates the Rx Queue to which Untagged Packets are to be routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7"
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bitfld.long 0x00 4.--6. "PTPQ,PTP Packets Queue This field specifies the Rx queue on which the PTP packets sent over the Ethernet payload (not over IPv4 or IPv6) are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7"
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bitfld.long 0x00 0.--2. "AVCPQ,AV Untagged Control Packets Queue This field specifies the Receive queue on which the received AV tagged and untagged control packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7"
group.long 0xA8++0x03
line.long 0x00 "MAC_RxQ_Ctrl2,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the RxQueues 0 to 3"
hexmask.long.byte 0x00 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1 This field decides the priorities assigned to Rx Queue 1"
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hexmask.long.byte 0x00 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0 This field decides the priorities assigned to Rx Queue 0"
rgroup.long 0xB0++0x03
line.long 0x00 "MAC_Interrupt_Status,The Interrupt Status register contains the status of interrupts"
bitfld.long 0x00 20. "MFRIS,MMC FPE Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Receive Interrupt Register" "0: MMC FPE Receive Interrupt status not active,1: MMC FPE Receive Interrupt status active"
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bitfld.long 0x00 19. "MFTIS,MMC FPE Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Transmit Interrupt Register" "0: MMC FPE Transmit Interrupt status not active,1: MMC FPE Transmit Interrupt status active"
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bitfld.long 0x00 18. "MDIOIS,MDIO Interrupt Status This bit indicates an interrupt event after the completion of MDIO operation" "0: MDIO Interrupt status not active,1: MDIO Interrupt status active"
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bitfld.long 0x00 17. "FPEIS,Frame Preemption Interrupt Status This bit indicates an interrupt event during the operation of Frame Preemption (Bits[19:16] of MAC_FPE_CTRL_STS register is set)" "0: Frame Preemption Interrupt status not active,1: Frame Preemption Interrupt status active"
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bitfld.long 0x00 14. "RXSTSIS,Receive Status Interrupt This bit indicates the status of received packets" "0: Receive Interrupt status not active,1: Receive Interrupt status active"
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bitfld.long 0x00 13. "TXSTSIS,Transmit Status Interrupt This bit indicates the status of transmitted packets" "0: Transmit Interrupt status not active,1: Transmit Interrupt status active"
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bitfld.long 0x00 12. "TSIS,Timestamp Interrupt Status If the Timestamp feature is enabled this bit is set when any of the following conditions is true: - The system time value is equal to or exceeds the value specified in the Target Time High and Low registers" "0: Timestamp Interrupt status not active,1: Timestamp Interrupt status active"
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bitfld.long 0x00 10. "MMCTXIS,MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register" "0: MMC Transmit Interrupt status not active,1: MMC Transmit Interrupt status active"
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bitfld.long 0x00 9. "MMCRXIS,MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register" "0: MMC Receive Interrupt status not active,1: MMC Receive Interrupt status active"
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bitfld.long 0x00 8. "MMCIS,MMC Interrupt Status This bit is set high when Bit 11 Bit 10 or Bit 9 is set high" "0: MMC Interrupt status not active,1: MMC Interrupt status active"
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bitfld.long 0x00 5. "LPIIS,LPI Interrupt Status When the Energy Efficient Ethernet feature is enabled this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver" "0: LPI Interrupt status not active,1: LPI Interrupt status active"
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bitfld.long 0x00 4. "PMTIS,PMT Interrupt Status This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (RWKPRCVD and MGKPRCVD bits in MAC_PMT_Control_Status register)" "0: PMT Interrupt status not active,1: PMT Interrupt status active"
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bitfld.long 0x00 3. "PHYIS,PHY Interrupt This bit is set when rising edge is detected on the phy_intr_i input" "0: PHY Interrupt not detected,1: PHY Interrupt detected"
group.long 0xB4++0x03
line.long 0x00 "MAC_Interrupt_Enable,The Interrupt Enable register contains the masks for generating the interrupts"
bitfld.long 0x00 18. "MDIOIE,MDIO Interrupt Enable When this bit is set it enables the assertion of the interrupt when MDIOIS field is set in the MAC_Interrupt_Status register" "0: MDIO Interrupt is disabled,1: MDIO Interrupt is enabled"
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bitfld.long 0x00 17. "FPEIE,Frame Preemption Interrupt Enable When this bit is set it enables the assertion of the interrupt when FPEIS field is set in the MAC_Interrupt_Status register" "0: Frame Preemption Interrupt is disabled,1: Frame Preemption Interrupt is enabled"
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bitfld.long 0x00 14. "RXSTSIE,Receive Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the MAC_Interrupt_Status register" "0: Receive Status Interrupt is disabled,1: Receive Status Interrupt is enabled"
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bitfld.long 0x00 13. "TXSTSIE,Transmit Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the MAC_Interrupt_Status register" "0: Timestamp Status Interrupt is disabled,1: Timestamp Status Interrupt is enabled"
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bitfld.long 0x00 12. "TSIE,Timestamp Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TSIS bit in MAC_Interrupt_Status register" "0: Timestamp Interrupt is disabled,1: Timestamp Interrupt is enabled"
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bitfld.long 0x00 5. "LPIIE,LPI Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of LPIIS bit in MAC_Interrupt_Status register" "0: LPI Interrupt is disabled,1: LPI Interrupt is enabled"
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bitfld.long 0x00 4. "PMTIE,PMT Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PMTIS bit in MAC_Interrupt_Status register" "0: PMT Interrupt is disabled,1: PMT Interrupt is enabled"
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bitfld.long 0x00 3. "PHYIE,PHY Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PHYIS bit in MAC_Interrupt_Status register" "0: PHY Interrupt is disabled,1: PHY Interrupt is enabled"
rgroup.long 0xB8++0x03
line.long 0x00 "MAC_Rx_Tx_Status,The Receive Transmit Status register contains the Receive and Transmit Error status"
bitfld.long 0x00 8. "RWT,Receive Watchdog Timeout This bit is set when a packet with length greater than 2 048 bytes is received (10 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_Configuration register" "0: No receive watchdog timeout,1: Receive watchdog timed out"
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bitfld.long 0x00 5. "EXCOL,Excessive Collisions When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet" "0: No collision,1: Excessive collision is sensed"
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bitfld.long 0x00 4. "LCOL,Late Collision When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode 512 bytes.." "0: No collision,1: Late collision is sensed"
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bitfld.long 0x00 3. "EXDEF,Excessive Deferral When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the MAC_Configuration register this bit indicates that the transmission ended because of excessive deferral of over 24 288 bit times (155 680.." "0: No Excessive deferral,1: Excessive deferral"
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bitfld.long 0x00 2. "LCARR,Loss of Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the loss of carrier occurred during packet transmission that is the phy_crs_i signal was inactive for one or more transmission clock periods.." "0: Carrier is present,1: Loss of carrier"
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bitfld.long 0x00 1. "NCARR,No Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission" "0: Carrier is present,1: No carrier"
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bitfld.long 0x00 0. "TJT,Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2 048 bytes (10 240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_Configuration register" "0: No Transmit Jabber Timeout,1: Transmit Jabber Timeout occurred"
group.long 0xC0++0x03
line.long 0x00 "MAC_PMT_Control_Status,The PMT Control and Status Register"
bitfld.long 0x00 31. "RWKFILTRST,Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set the remote wake-up packet filter register pointer is reset to 3'b000" "0: Remote Wake-Up Packet Filter Register Pointer..,1: Remote Wake-Up Packet Filter Register Pointer.."
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rbitfld.long 0x00 24.--28. "RWKPTR,Remote Wake-up FIFO Pointer This field gives the current value (0 to 7 15 or 31 when 4 8 or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter register pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "RWKPFE,Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN the MAC receiver drops all received frames until it receives the expected Wake-up frame" "0: Remote Wake-up Packet Forwarding is disabled,1: Remote Wake-up Packet Forwarding is enabled"
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bitfld.long 0x00 9. "GLBLUCAST,Global Unicast When this bit set any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wake-up packet" "0: Global unicast is disabled,1: Global unicast is enabled"
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rbitfld.long 0x00 6. "RWKPRCVD,Remote Wake-Up Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a remote wake-up packet" "0: Remote wake-up packet is received,1: Remote wake-up packet is received"
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rbitfld.long 0x00 5. "MGKPRCVD,Magic Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a magic packet" "0: No Magic packet is received,1: Magic packet is received"
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bitfld.long 0x00 2. "RWKPKTEN,Remote Wake-Up Packet Enable When this bit is set a power management event is generated when the MAC receives a remote wake-up packet" "0: Remote wake-up packet is disabled,1: Remote wake-up packet is enabled"
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bitfld.long 0x00 1. "MGKPKTEN,Magic Packet Enable When this bit is set a power management event is generated when the MAC receives a magic packet" "0: Magic Packet is disabled,1: Magic Packet is enabled"
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bitfld.long 0x00 0. "PWRDWN,Power Down When this bit is set the MAC receiver drops all received packets until it receives the expected magic packet or remote wake-up packet" "0: Power down is disabled,1: Power down is enabled"
group.long 0xC4++0x03
line.long 0x00 "MAC_RWK_Packet_Filter,The Remote Wakeup Filter registers are implemented as 8 16 or 32 indirect access registers (wkuppktfilter_reg#i) based on whether 4 8 or 16 Remote Wakeup Filters are selected in the configuration and accessed by application through.."
hexmask.long 0x00 0.--31. 1. "WKUPFRMFTR,RWK Packet Filter This field contains the various controls of RWK Packet filter"
group.long 0xD0++0x03
line.long 0x00 "MAC_LPI_Control_Status,The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status"
bitfld.long 0x00 21. "LPITCSE,LPI Tx Clock Stop Enable When this bit is set the MAC asserts sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped" "0: LPI Tx Clock Stop is disabled,1: LPI Tx Clock Stop is enabled"
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bitfld.long 0x00 20. "LPIATE,LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state" "0: LPI Timer is disabled,1: LPI Timer is enabled"
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bitfld.long 0x00 19. "LPITXA,LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side" "0: LPI Tx Automate is disabled,1: LPI Tx Automate is enabled"
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bitfld.long 0x00 17. "PLS,PHY Link Status This bit indicates the link status of the PHY" "0: link is down,1: link is okay (UP)"
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bitfld.long 0x00 16. "LPIEN,LPI Enable When this bit is set it instructs the MAC Transmitter to enter the LPI state" "0: LPI state is disabled,1: LPI state is enabled"
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rbitfld.long 0x00 9. "RLPIST,Receive LPI State When this bit is set it indicates that the MAC is receiving the LPI pattern on the GMII or MII interface" "0: Receive LPI state not detected,1: Receive LPI state detected"
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rbitfld.long 0x00 8. "TLPIST,Transmit LPI State When this bit is set it indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface" "0: Transmit LPI state not detected,1: Transmit LPI state detected"
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rbitfld.long 0x00 3. "RLPIEX,Receive LPI Exit When this bit is set it indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface exited the LPI state and resumed the normal reception" "0: Receive LPI exit not detected,1: Receive LPI exit detected"
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rbitfld.long 0x00 2. "RLPIEN,Receive LPI Entry When this bit is set it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state" "0: Receive LPI entry not detected,1: Receive LPI entry detected"
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rbitfld.long 0x00 1. "TLPIEX,Transmit LPI Exit When this bit is set it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired" "0: Transmit LPI exit not detected,1: Transmit LPI exit detected"
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rbitfld.long 0x00 0. "TLPIEN,Transmit LPI Entry When this bit is set it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit" "0: Transmit LPI entry not detected,1: Transmit LPI entry detected"
group.long 0xD4++0x03
line.long 0x00 "MAC_LPI_Timers_Control,The LPI Timers Control register controls the timeout values in the LPI states"
hexmask.long.word 0x00 16.--25. 1. "LST,LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY"
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hexmask.long.word 0x00 0.--15. 1. "TWT,LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission"
group.long 0xD8++0x03
line.long 0x00 "MAC_LPI_Entry_Timer,This register controls the Tx LPI entry timer"
hexmask.long.tbyte 0x00 3.--19. 1. "LPIET,LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI mode after it has transmitted all the frames"
group.long 0xDC++0x03
line.long 0x00 "MAC_1US_Tic_Counter,This register controls the generation of the Reference time (1 microsecond tic) for all the LPI timers"
hexmask.long.word 0x00 0.--11. 1. "TIC_1US_CNTR,1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us"
rgroup.long 0x110++0x03
line.long 0x00 "MAC_Version,The version register identifies the version of the module"
hexmask.long.byte 0x00 8.--15. 1. "CFGVER,IP configuration version"
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hexmask.long.byte 0x00 0.--7. 1. "IPVER,IP Version"
rgroup.long 0x114++0x03
line.long 0x00 "MAC_Debug,The Debug register provides the debug status of various MAC blocks"
bitfld.long 0x00 17.--18. "TFCSTS,MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module" "0: Idle state,1: Waiting for one of the following,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission"
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bitfld.long 0x00 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and it is not in the Idle state" "0: MAC GMII or MII Transmit Protocol Engine..,1: MAC GMII or MII Transmit Protocol Engine.."
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bitfld.long 0x00 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status When this bit is set this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module" "0,1,2,3"
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bitfld.long 0x00 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII receive protocol engine is actively receiving data and it is not in the Idle state" "0: MAC GMII or MII Receive Protocol Engine..,1: MAC GMII or MII Receive Protocol Engine.."
rgroup.long 0x11C++0x03
line.long 0x00 "MAC_HW_Feature0,This register indicates the presence of first set of the optional features or functions of the DWC_ether_qos"
bitfld.long 0x00 28.--30. "ACTPHYSEL,Active PHY Selected When you have multiple PHY interfaces in your configuration this field indicates the sampled value of phy_intf_sel_i during reset de-assertion" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,7: REVMIII"
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bitfld.long 0x00 27. "SAVLANINS,Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected" "0: Source Address or VLAN Insertion Enable..,1: Source Address or VLAN Insertion Enable.."
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bitfld.long 0x00 25.--26. "TSSTSSEL,Timestamp System Time Source This bit indicates the source of the Timestamp system time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: Internal,1: External,2: BOTH,?..."
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bitfld.long 0x00 24. "MACADR64SEL,MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected" "0: MAC Addresses 64-127 Select option is not..,1: MAC Addresses 64-127 Select option is selected"
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bitfld.long 0x00 23. "MACADR32SEL,MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected" "0: MAC Addresses 32-63 Select option is not..,1: MAC Addresses 32-63 Select option is selected"
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bitfld.long 0x00 18.--22. "ADDMACADRSEL,MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is selected for Enable Additional 1-31 MAC Address Registers option" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16. "RXCOESEL,Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected" "0: Receive Checksum Offload Enable option is not..,1: Receive Checksum Offload Enable option is.."
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bitfld.long 0x00 14. "TXCOESEL,Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected" "0: Transmit Checksum Offload Enable option is..,1: Transmit Checksum Offload Enable option is.."
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bitfld.long 0x00 13. "EEESEL,Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected" "0: Energy Efficient Ethernet Enable option is..,1: Energy Efficient Ethernet Enable option is.."
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bitfld.long 0x00 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: IEEE 1588-2008 Timestamp Enable option is not..,1: IEEE 1588-2008 Timestamp Enable option is.."
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bitfld.long 0x00 9. "ARPOFFSEL,ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected" "0: ARP Offload Enable option is not selected,1: ARP Offload Enable option is selected"
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bitfld.long 0x00 8. "MMCSEL,RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected" "0: RMON Module Enable option is not selected,1: RMON Module Enable option is selected"
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bitfld.long 0x00 7. "MGKSEL,PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected" "0: PMT Magic Packet Enable option is not selected,1: PMT Magic Packet Enable option is selected"
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bitfld.long 0x00 6. "RWKSEL,PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected" "0: PMT Remote Wake-up Packet Enable option is..,1: PMT Remote Wake-up Packet Enable option is.."
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bitfld.long 0x00 5. "SMASEL,SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected" "0: SMA (MDIO) Interface not selected,1: SMA (MDIO) Interface selected"
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bitfld.long 0x00 4. "VLHASH,VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected" "0: VLAN Hash Filter not selected,1: VLAN Hash Filter selected"
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bitfld.long 0x00 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface) This bit is set to 1 when the TBI SGMII or RTBI PHY interface option is selected" "0: No PCS Registers (TBI SGMII or RTBI PHY..,1: PCS Registers (TBI SGMII or RTBI PHY interface)"
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bitfld.long 0x00 2. "HDSEL,Half-duplex Support This bit is set to 1 when the half-duplex mode is selected" "0: No Half-duplex support,1: Half-duplex support"
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bitfld.long 0x00 1. "GMIISEL,1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation" "0: No 1000 Mbps support,1: 1000 Mbps support"
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bitfld.long 0x00 0. "MIISEL,10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation" "0: No 10 or 100 Mbps support,1: 10 or 100 Mbps support"
rgroup.long 0x120++0x03
line.long 0x00 "MAC_HW_Feature1,This register indicates the presence of second set of the optional features or functions of the DWC_ether_qos"
bitfld.long 0x00 27.--30. "L3L4FNUM,Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters" "0: No L3 or L4 Filter,1: 1 L3 or L4 Filter,2: 2 L3 or L4 Filters,3: 3 L3 or L4 Filters,4: 4 L3 or L4 Filters,5: 5 L3 or L4 Filters,6: 6 L3 or L4 Filters,7: 7 L3 or L4 Filters,8: 8 L3 or L4 Filters,?..."
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bitfld.long 0x00 24.--25. "HASHTBLSZ,Hash Table Size This field indicates the size of the hash table" "0: No hash table,1: M_64,2: M_128,3: M_256"
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bitfld.long 0x00 23. "POUOST,One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One step timestamp for PTP over UDP/IP feature is selected" "0: One Step for PTP over UDP/IP Feature is not..,1: One Step for PTP over UDP/IP Feature is.."
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bitfld.long 0x00 21. "RAVSEL,Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option on Rx Side Only is selected" "0: Rx Side Only AV Feature is not selected,1: Rx Side Only AV Feature is selected"
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bitfld.long 0x00 20. "AVSEL,AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected" "0: AV Feature is not selected,1: AV Feature is selected"
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bitfld.long 0x00 19. "DBGMEMA,DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected" "0: DMA Debug Registers option is not selected,1: DMA Debug Registers option is selected"
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bitfld.long 0x00 18. "TSOEN,TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected" "0: TCP Segmentation Offload Feature is not..,1: TCP Segmentation Offload Feature is selected"
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bitfld.long 0x00 17. "SPHEN,Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected" "0: Split Header Feature is not selected,1: Split Header Feature is selected"
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bitfld.long 0x00 16. "DCBEN,DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected" "0: DCB Feature is not selected,1: DCB Feature is selected"
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bitfld.long 0x00 14.--15. "ADDR64,Address Width" "0: M_32,1: M_40,2: M_48,?..."
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bitfld.long 0x00 13. "ADVTHWORD,IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected" "0: IEEE 1588 High Word Register option is not..,1: IEEE 1588 High Word Register option is selected"
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bitfld.long 0x00 12. "PTOEN,PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected" "0: PTP Offload feature is not selected,1: PTP Offload feature is selected"
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bitfld.long 0x00 11. "OSTEN,One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected" "0: One-Step Timestamping feature is not selected,1: One-Step Timestamping feature is selected"
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bitfld.long 0x00 6.--10. "TXFIFOSIZE,MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(TXFIFO_SIZE) -7" "0: 128 bytes,1: 256 bytes,2: 512 bytes,3: 1024 bytes,4: 2048 bytes,5: 4096 bytes,6: 8192 bytes,7: 16384 bytes,8: M_32KB,9: M_64KB,10: M_128KB,?..."
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bitfld.long 0x00 5. "SPRAM,Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected" "0: Single Port RAM feature is not selected,1: Single Port RAM feature is selected"
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bitfld.long 0x00 0.--4. "RXFIFOSIZE,MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(RXFIFO_SIZE) -7" "0: 128 bytes,1: 256 bytes,2: 512 bytes,3: 1024 bytes,4: 2048 bytes,5: 4096 bytes,6: 8192 bytes,7: 16384 bytes,8: M_32KB,9: M_64KB,10: M_128KB,11: M_256KB,?..."
rgroup.long 0x124++0x03
line.long 0x00 "MAC_HW_Feature2,This register indicates the presence of third set of the optional features or functions of the DWC_ether_qos"
bitfld.long 0x00 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary input,3: 3 auxiliary input,4: 4 auxiliary input,?..."
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bitfld.long 0x00 24.--26. "PPSOUTNUM,Number of PPS Outputs This field indicates the number of PPS outputs" "0: No PPS output,1: 1 PPS output,2: 2 PPS output,3: 3 PPS output,4: 4 PPS output,?..."
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bitfld.long 0x00 22.--23. "TDCSZ,Tx DMA Descriptor Cache Size in terms of 16 bytes descriptors" "0,1,2,3"
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bitfld.long 0x00 18.--21. "TXCHCNT,Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels" "0: 1 MTL Tx Channel,1: M_1TDCSZ,2: M_2TDCSZ,3: M_3TDCSZ,4: 5 MTL Tx Channels,5: 6 MTL Tx Channels,6: 7 MTL Tx Channels,7: 8 MTL Tx Channels,?..."
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bitfld.long 0x00 16.--17. "RDCSZ,Rx DMA Descriptor Cache Size in terms of 16 bytes descriptors" "0,1,2,3"
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bitfld.long 0x00 12.--15. "RXCHCNT,Number of DMA Receive Channels This field indicates the number of DMA Receive channels" "0: 1 MTL Rx Channel,1: M_1RDCSZ,2: M_2RDCSZ,3: M_3RDCSZ,4: 5 MTL Rx Channels,5: 6 MTL Rx Channels,6: 7 MTL Rx Channels,7: 8 MTL Rx Channels,?..."
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bitfld.long 0x00 6.--9. "TXQCNT,Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues" "0: 1 MTL Tx Queue,1: 2 MTL Tx Queues,2: 3 MTL Tx Queues,3: 4 MTL Tx Queues,4: 5 MTL Tx Queues,5: 6 MTL Tx Queues,6: 7 MTL Tx Queues,7: 8 MTL Tx Queues,?..."
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bitfld.long 0x00 0.--3. "RXQCNT,Number of MTL Receive Queues This field indicates the number of MTL Receive queues" "0: 1 MTL Rx Queue,1: 2 MTL Rx Queues,2: 3 MTL Rx Queues,3: 4 MTL Rx Queues,4: 5 MTL Rx Queues,5: 6 MTL Rx Queues,6: 7 MTL Rx Queues,7: 8 MTL Rx Queues,?..."
rgroup.long 0x128++0x03
line.long 0x00 "MAC_HW_Feature3,This register indicates the presence of fourth set the optional features or functions of the DWC_ether_qos"
bitfld.long 0x00 28.--29. "ASP,Automotive Safety Package Following are the encoding for the different Safety features" "0: No Safety features selected,1: Only ECC protection for external memory..,2: All the Automotive Safety features are..,3: All the Automotive Safety features are.."
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bitfld.long 0x00 27. "TBSSEL,Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected" "0: Time Based Scheduling Enable feature is not..,1: Time Based Scheduling Enable feature is.."
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bitfld.long 0x00 26. "FPESEL,Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected" "0: Frame Preemption Enable feature is not selected,1: Frame Preemption Enable feature is selected"
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bitfld.long 0x00 20.--21. "ESTWID,Width of the Time Interval field in the Gate Control List This field indicates the width of the Configured Time Interval Field" "0: Width not configured,1: WIDTH16,2: WIDTH20,3: WIDTH24"
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bitfld.long 0x00 17.--19. "ESTDEP,Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5" "0: No Depth configured,1: DEPTH64,2: DEPTH128,3: DEPTH256,4: DEPTH512,5: DEPTH1024,?..."
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bitfld.long 0x00 16. "ESTSEL,Enhancements to Scheduled Traffic Enable This bit is set to 1 when the Enable Enhancements to Scheduling Traffic feature is selected" "0: Enable Enhancements to Scheduling Traffic..,1: Enable Enhancements to Scheduling Traffic.."
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bitfld.long 0x00 13.--14. "FRPES,Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser Entries supported by Flexible Receive Parser" "0: 64 Entries,1: 128 Entries,2: 256 Entries,?..."
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bitfld.long 0x00 11.--12. "FRPBS,Flexible Receive Parser Buffer size This field indicates the supported Max Number of bytes of the packet data to be Parsed by Flexible Receive Parser" "0: M_64BYTES,1: M_128BYTES,2: M_256BYTES,?..."
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bitfld.long 0x00 10. "FRPSEL,Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible Programmable Receive Parser option is selected" "0: Flexible Receive Parser feature is not selected,1: Flexible Receive Parser feature is selected"
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bitfld.long 0x00 9. "PDUPSEL,Broadcast/Multicast Packet Duplication This bit is set to 1 when the Broadcast/Multicast Packet Duplication feature is selected" "0: Broadcast/Multicast Packet Duplication..,1: Broadcast/Multicast Packet Duplication.."
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bitfld.long 0x00 5. "DVLAN,Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected" "0: Double VLAN option is not selected,1: Double VLAN option is selected"
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bitfld.long 0x00 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected" "0: Enable Queue/Channel based VLAN tag insertion..,1: Enable Queue/Channel based VLAN tag insertion.."
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bitfld.long 0x00 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,?..."
group.long 0x140++0x03
line.long 0x00 "MAC_DPP_FSM_Interrupt_Status,This register contains the status of Automotive Safety related Data Path Parity Errors Interface Timeout Errors FSM State Parity Errors and FSM State Timeout Errors"
bitfld.long 0x00 27. "MRWCPES,MTL RWC data path Parity checker Error Status This filed when set indicates that parity error is detected on the MTL RWC data interface (or at PC12 as shown in Receive data path parity protection diagram)" "0: MTL RWC data path Parity checker Error Status..,1: MTL RWC data path Parity checker Error Status.."
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bitfld.long 0x00 26. "MTFCPES,MAC TFC data path Parity checker Error Status This filed when set indicates that parity error is detected on the MAC TFC data interface (or at PC11 as shown in Transmit data path parity protection diagram)" "0: MAC TFC data path Parity checker Error Status..,1: MAC TFC data path Parity checker Error Status.."
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bitfld.long 0x00 25. "MTBUPES,MAC TBU data path Parity checker Error Status This filed when set indicates that parity error is detected on the MAC TBU data interface (or at PC10 as shown in Transmit data path parity protection diagram)" "0: MAC TBU data path Parity checker Error Status..,1: MAC TBU data path Parity checker Error Status.."
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bitfld.long 0x00 24. "FSMPES,FSM State Parity Error Status This field when set indicates one of the FSMs State registers has a parity error detected" "0: FSM State Parity Error Status not detected,1: FSM State Parity Error Status detected"
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bitfld.long 0x00 16. "MSTTES,Master Read/Write Timeout Error Status This field when set indicates that an Application/CSR Timeout has occurred on the master (AXI/AHB/ARI/ATI) interface" "0: Master Read/Write Timeout Error Status not..,1: Master Read/Write Timeout Error Status detected"
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bitfld.long 0x00 12. "PTES,PTP FSM Timeout Error Status This field when set indicates that one of the PTP FSM Timeout has occurred" "0: PTP FSM Timeout Error Status not detected,1: PTP FSM Timeout Error Status detected"
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bitfld.long 0x00 11. "ATES,APP FSM Timeout Error Status This field when set indicates that one of the APP FSM Timeout has occurred" "0: APP FSM Timeout Error Status not detected,1: APP FSM Timeout Error Status detected"
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bitfld.long 0x00 9. "RTES,Rx FSM Timeout Error Status This field when set indicates that one of the Rx FSM Timeout has occurred" "0: Rx FSM Timeout Error Status not detected,1: Rx FSM Timeout Error Status detected"
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bitfld.long 0x00 8. "TTES,Tx FSM Timeout Error Status This field when set indicates that one of the Tx FSM Timeout has occurred" "0: Tx FSM Timeout Error Status not detected,1: Tx FSM Timeout Error Status detected"
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bitfld.long 0x00 5. "ARPES,Application Receive interface data path Parity Error Status This bit when set indicates that a parity error is detected at the following checkers based on the system configuration: - In MTL configuration (DWC_EQOS_SYS=1) parity checker (PC6 as.." "0: Application Receive interface data path..,1: Application Receive interface data path.."
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bitfld.long 0x00 4. "MTSPES,MTL TX Status data path Parity checker Error Status This filed when set indicates that parity error is detected on the MTL TX Status data on ati interface (or at PC5 as shown in Transmit data path parity protection diagram)" "0: MTL TX Status data path Parity checker Error..,1: MTL TX Status data path Parity checker Error.."
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bitfld.long 0x00 3. "MPES,MTL data path Parity checker Error Status This bit when set indicates that a parity error is detected at the MTL transmit write controller parity checker (or at PC4 as shown in Transmit data path parity protection diagram)" "0: MTL data path Parity checker Error Status not..,1: MTL data path Parity checker Error Status.."
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bitfld.long 0x00 2. "RDPES,Read Descriptor Parity checker Error Status This bit when set indicates that a parity error is detected at the DMA Read descriptor parity checker (or at PC3 as shown in Transmit data path parity protection diagram)" "0: Read Descriptor Parity checker Error Status..,1: Read Descriptor Parity checker Error Status.."
group.long 0x148++0x03
line.long 0x00 "MAC_FSM_Control,This register is used to control the FSM State parity and timeout error injection in Debug mode"
bitfld.long 0x00 28. "PLGRNML,PTP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for PTP domain else normal mode tic generation is used" "0: normal mode tic generation is used for PTP..,1: large mode tic generation is used for PTP.."
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bitfld.long 0x00 27. "ALGRNML,APP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for APP domain else normal mode tic generation is used" "0: normal mode tic generation is used for APP..,1: large mode tic generation is used for APP.."
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bitfld.long 0x00 25. "RLGRNML,Rx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Rx domain else normal mode tic generation is used" "0: normal mode tic generation is used for Rx..,1: large mode tic generation is used for Rx domain"
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bitfld.long 0x00 24. "TLGRNML,Tx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Tx domain else normal mode tic generation is used" "0: normal mode tic generation is used for Tx..,1: large mode tic generation is used for Tx domain"
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bitfld.long 0x00 20. "PPEIN,PTP FSM Parity Error Injection This field when set indicates that Error Injection for PTP FSM Parity is enabled" "0: PTP FSM Parity Error Injection is disabled,1: PTP FSM Parity Error Injection is enabled"
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bitfld.long 0x00 19. "APEIN,APP FSM Parity Error Injection This field when set indicates that Error Injection for APP FSM Parity is enabled" "0: APP FSM Parity Error Injection is disabled,1: APP FSM Parity Error Injection is enabled"
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bitfld.long 0x00 17. "RPEIN,Rx FSM Parity Error Injection This field when set indicates that Error Injection for RX FSM Parity is enabled" "0: Rx FSM Parity Error Injection is disabled,1: Rx FSM Parity Error Injection is enabled"
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bitfld.long 0x00 16. "TPEIN,Tx FSM Parity Error Injection This field when set indicates that Error Injection for TX FSM Parity is enabled" "0: Tx FSM Parity Error Injection is disabled,1: Tx FSM Parity Error Injection is enabled"
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bitfld.long 0x00 12. "PTEIN,PTP FSM Timeout Error Injection This field when set indicates that Error Injection for PTP FSM timeout is enabled" "0: PTP FSM Timeout Error Injection is disabled,1: PTP FSM Timeout Error Injection is enabled"
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bitfld.long 0x00 11. "ATEIN,APP FSM Timeout Error Injection This field when set indicates that Error Injection for APP FSM timeout is enabled" "0: APP FSM Timeout Error Injection is disabled,1: APP FSM Timeout Error Injection is enabled"
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bitfld.long 0x00 9. "RTEIN,Rx FSM Timeout Error Injection This field when set indicates that Error Injection for RX FSM timeout is enabled" "0: Rx FSM Timeout Error Injection is disabled,1: Rx FSM Timeout Error Injection is enabled"
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bitfld.long 0x00 8. "TTEIN,Tx FSM Timeout Error Injection This field when set indicates that Error Injection for TX FSM timeout is enabled" "0: Tx FSM Timeout Error Injection is disabled,1: Tx FSM Timeout Error Injection is enabled"
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bitfld.long 0x00 1. "PRTYEN,This bit when set indicates that the FSM parity feature is enabled" "0: FSM Parity feature is disabled,1: FSM Parity feature is enabled"
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bitfld.long 0x00 0. "TMOUTEN,This bit when set indicates that the FSM timeout feature is enabled" "0: FSM timeout feature is disabled,1: FSM timeout feature is enabled"
group.long 0x14C++0x03
line.long 0x00 "MAC_FSM_ACT_Timer,This register is used to select the FSM and Interface Timeout values"
bitfld.long 0x00 20.--23. "LTMRMD,Large Mode Timeout Value This field provides the mode value to be used for large mode FSM and other interface time outs" "0: Timer disabled,1: M_1MICRO_SEC,2: 1.024ms (~4ms),3: 16.384ms (~16ms),4: 65.536ms (~64ms),5: 262.144ms (~256ms),6: 1.048sec (~1sec),7: 4.194sec (~4sec),8: 16.777sec (~16sec),9: 33.554sec (~32sec),10: 67.108sec (~64sec),?..."
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bitfld.long 0x00 16.--19. "NTMRMD,Normal Mode Timeout Value This field provides the value to be used for normal mode FSM and other interface time outs" "0: Timer disabled,1: M_1MICRO_SEC,2: 1.024ms (~4ms),3: 16.384ms (~16ms),4: 65.536ms (~64ms),5: 262.144ms (~256ms),6: 1.048sec (~1sec),7: 4.194sec (~4sec),8: 16.777sec (~16sec),9: 33.554sec (~32sec),10: 67.108sec (~64sec),?..."
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hexmask.long.word 0x00 0.--9. 1. "TMR,CSR Clocks for 1us Tic This field indicates the number of CSR clocks required to generate 1us tic"
group.long 0x150++0x03
line.long 0x00 "SCS_REG1,NXP Reserved Register"
hexmask.long 0x00 0.--31. 1. "MAC_SCS1,NXP Reserved All the bits must be set to 0"
group.long 0x200++0x03
line.long 0x00 "MAC_MDIO_Address,The MDIO Address register controls the management cycles to external PHY through a management interface"
bitfld.long 0x00 27. "PSE,Preamble Suppression Enable When this bit is set the SMA suppresses the 32-bit preamble and transmits MDIO frames with only 1 preamble bit" "0: Preamble Suppression disabled,1: Preamble Suppression enabled"
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bitfld.long 0x00 26. "BTB,Back to Back transactions When this bit is set and the NTC has value greater than 0 then the MAC informs the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted)" "0: Back to Back transactions disabled,1: Back to Back transactions enabled"
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bitfld.long 0x00 21.--25. "PA,Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. "RDA,Register/Device Address These bits select the PHY register in selected Clause 22 PHY device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--14. "NTC,Number of Trailing Clocks This field controls the number of trailing clock cycles generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "CR,CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design" "0: CSR clock = 60-100 MHz MDC clock = CSR clock/42,1: CSR clock = 100-150 MHz MDC clock = CSR..,2: CSR clock = 20-35 MHz MDC clock = CSR clock/16,3: CSR clock = 35-60 MHz MDC clock = CSR clock/26,4: CSR clock = 150-250 MHz MDC clock = CSR..,5: CSR clock = 250-300 MHz MDC clock = CSR..,6: CSR clock = 300-500 MHz MDC clock = CSR..,7: CSR clock = 500-800 MHz MDC clock = CSR,?,?,?,11: 0) ensures that the MDC clock is approximately,?..."
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bitfld.long 0x00 4. "SKAP,Skip Address Packet When this bit is set the SMA does not send the address packets before read write or post-read increment address packets" "0: Skip Address Packet is disabled,1: Skip Address Packet is enabled"
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bitfld.long 0x00 3. "GOC_1,GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or RevMII GOC_1 and GOC_O is encoded as follows" "0: GMII Operation Command 1 is disabled,1: GMII Operation Command 1 is enabled"
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bitfld.long 0x00 2. "GOC_0,GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII" "0: GMII Operation Command 0 is disabled,1: GMII Operation Command 0 is enabled"
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bitfld.long 0x00 1. "C45E,Clause 45 PHY Enable When this bit is set Clause 45 capable PHY is connected to MDIO" "0: Clause 45 PHY is disabled,1: Clause 45 PHY is enabled"
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bitfld.long 0x00 0. "GB,GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave" "0: GMII Busy is disabled,1: GMII Busy is enabled"
group.long 0x204++0x03
line.long 0x00 "MAC_MDIO_Data,The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in MAC_MDIO_Address"
hexmask.long.word 0x00 16.--31. 1. "RA,Register Address This field is valid only when C45E is set"
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hexmask.long.word 0x00 0.--15. 1. "GD,GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation"
group.long 0x210++0x03
line.long 0x00 "MAC_ARP_Address,The ARP Address register contains the IPv4 Destination Address of the MAC"
hexmask.long 0x00 0.--31. 1. "ARPPA,ARP Protocol Address This field contains the IPv4 Destination Address of the MAC"
group.long 0x230++0x03
line.long 0x00 "MAC_CSR_SW_Ctrl,This register contains software programmable controls for changing the CSR access response and status bits clearing"
bitfld.long 0x00 8. "SEEN,Slave Error Response Enable When this bit is set the MAC responds with Slave Error for accesses to reserved registers in CSR space" "0: Slave Error Response is disabled,1: Slave Error Response is enabled"
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bitfld.long 0x00 0. "RCWE,Register Clear on Write 1 Enable When this bit is set the access mode of some register fields changes to Clear on Write 1 the application needs to set that respective bit to 1 to clear it" "0: Register Clear on Write 1 is disabled,1: Register Clear on Write 1 is enabled"
group.long 0x234++0x03
line.long 0x00 "MAC_FPE_CTRL_STS,This register controls the operation of Frame Preemption"
bitfld.long 0x00 19. "TRSP,Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field)" "0: Not transmitted Respond Frame,1: transmitted Respond Frame"
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bitfld.long 0x00 18. "TVER,Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field)" "0: Not transmitted Verify Frame,1: transmitted Verify Frame"
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bitfld.long 0x00 17. "RRSP,Received Respond Frame Set when a Respond mPacket is received" "0: Not received Respond Frame,1: Received Respond Frame"
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bitfld.long 0x00 16. "RVER,Received Verify Frame Set when a Verify mPacket is received" "0: Not received Verify Frame,1: Received Verify Frame"
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bitfld.long 0x00 3. "S1_SET_0,NXP Reserved Must be set to 0" "0,1"
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bitfld.long 0x00 2. "SRSP,Send Respond mPacket When set indicates hardware to send a Respond mPacket" "0: Send Respond mPacket is disabled,1: Send Respond mPacket is enabled"
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bitfld.long 0x00 1. "SVER,Send Verify mPacket When set indicates hardware to send a verify mPacket" "0: Send Verify mPacket is disabled,1: Send Verify mPacket is enabled"
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bitfld.long 0x00 0. "EFPE,Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled" "0: Tx Frame Preemption is disabled,1: Tx Frame Preemption is enabled"
group.long 0x238++0x03
line.long 0x00 "MAC_Ext_Cfg1,This register contains Split mode control field and offset field for Split Header feature"
bitfld.long 0x00 24. "SAVE,Split AV Enable - When this bit is set to 1 and the received packet is an AV Type packet the header is split at SAVO bytes from the beginning of Length/Type field of the packet for L2 Split" "0,1"
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hexmask.long.byte 0x00 16.--22. 1. "SAVO,Split AV Offset When SAVE bit is set to 1 and the received packet is an AV Type packet these bits indicate the value of the offset from the beginning of Length/Type field at which header should be split when appropriate SPLM is selected"
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bitfld.long 0x00 8.--9. "SPLM,Split Mode These bits indicate the mode of splitting the incoming Rx packets" "0: Split at L3/L4 header,1: Split at L2 header with an offset,2: Combination mode,?..."
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hexmask.long.byte 0x00 0.--6. 1. "SPLOFST,Split Offset These bits indicate the value of offset from the beginning of Length/Type field at which header split should take place when the appropriate SPLM is selected"
rgroup.long 0x240++0x03
line.long 0x00 "MAC_Presn_Time_ns,This register contains the 32-bit binary rollover equivalent time of the PTP System Time in ns Exists when DWC_EQOS_FLEXI_PPS_OUT_EN is configured"
hexmask.long 0x00 0.--31. 1. "MPTN,MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary rollover equivalent time of the PTP System Time in ns"
group.long 0x244++0x03
line.long 0x00 "MAC_Presn_Time_Updt,This field holds the 32-bit value of MAC 1722 Presentation Time in ns that should be added to the Current Presentation Time Counter value"
hexmask.long 0x00 0.--31. 1. "MPTU,MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time"
group.long 0x300++0x03
line.long 0x00 "MAC_Address0_High,The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station"
rbitfld.long 0x00 31. "AE,Address Enable This bit is always set to 1" "0: INVALID,1: This bit is always set to 1"
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bitfld.long 0x00 16.--17. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address0 content is routed" "0,1,2,3"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address"
group.long 0x304++0x03
line.long 0x00 "MAC_Address0_Low,The MAC Address0 Low register holds the lower 32 bits of the 6-byte first MAC address of the station"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address0[31:0] This field contains the lower 32 bits of the first 6-byte MAC address"
group.long 0x308++0x03
line.long 0x00 "MAC_Address1_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--17. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x30C++0x03
line.long 0x00 "MAC_Address1_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x310++0x03
line.long 0x00 "MAC_Address2_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--17. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x314++0x03
line.long 0x00 "MAC_Address2_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x700++0x03
line.long 0x00 "MMC_Control,This register establishes the operating mode of MMC"
bitfld.long 0x00 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit" "0: Update MMC Counters for Dropped Broadcast..,1: Update MMC Counters for Dropped Broadcast.."
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bitfld.long 0x00 5. "CNTPRSTLVL,Full-Half Preset When this bit is low and the CNTPRST bit is set all MMC counters get preset to almost-half value" "0: Full-Half Preset is disabled,1: Full-Half Preset is enabled"
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bitfld.long 0x00 4. "CNTPRST,Counters Preset When this bit is set all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit" "0: Counters Preset is disabled,1: Counters Preset is enabled"
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bitfld.long 0x00 3. "CNTFREEZ,MMC Counter Freeze When this bit is set it freezes all MMC counters to their current value" "0: MMC Counter Freeze is disabled,1: MMC Counter Freeze is enabled"
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bitfld.long 0x00 2. "RSTONRD,Reset on Read When this bit is set the MMC counters are reset to zero after Read (self-clearing after reset)" "0: Reset on Read is disabled,1: Reset on Read is enabled"
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bitfld.long 0x00 1. "CNTSTOPRO,Counter Stop Rollover When this bit is set the counter does not roll over to zero after reaching the maximum value" "0: Counter Stop Rollover is disabled,1: Counter Stop Rollover is enabled"
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bitfld.long 0x00 0. "CNTRST,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset"
rgroup.long 0x704++0x03
line.long 0x00 "MMC_Rx_Interrupt,This register maintains the interrupts generated from all Receive statistics counters"
bitfld.long 0x00 27. "RXLPITRCIS,MMC Receive LPI transition counter interrupt status This bit is set when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI transition Counter Interrupt..,1: MMC Receive LPI transition Counter Interrupt.."
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bitfld.long 0x00 26. "RXLPIUSCIS,MMC Receive LPI microsecond counter interrupt status This bit is set when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI microsecond Counter Interrupt..,1: MMC Receive LPI microsecond Counter Interrupt.."
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bitfld.long 0x00 25. "RXCTRLPIS,MMC Receive Control Packet Counter Interrupt Status This bit is set when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.."
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bitfld.long 0x00 24. "RXRCVERRPIS,MMC Receive Error Packet Counter Interrupt Status This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt..,1: MMC Receive Error Packet Counter Interrupt.."
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bitfld.long 0x00 23. "RXWDOGPIS,MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.."
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bitfld.long 0x00 22. "RXVLANGBPIS,MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.."
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bitfld.long 0x00 21. "RXFOVPIS,MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.."
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bitfld.long 0x00 20. "RXPAUSPIS,MMC Receive Pause Packet Counter Interrupt Status This bit is set when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt..,1: MMC Receive Pause Packet Counter Interrupt.."
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bitfld.long 0x00 19. "RXORANGEPIS,MMC Receive Out Of Range Error Packet Counter Interrupt Status" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.."
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bitfld.long 0x00 18. "RXLENERPIS,MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.."
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bitfld.long 0x00 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.."
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bitfld.long 0x00 16. "RX1024TMAXOCTGBPIS,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.."
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bitfld.long 0x00 15. "RX512T1023OCTGBPIS,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.."
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bitfld.long 0x00 14. "RX256T511OCTGBPIS,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.."
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bitfld.long 0x00 13. "RX128T255OCTGBPIS,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.."
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bitfld.long 0x00 12. "RX65T127OCTGBPIS,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.."
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bitfld.long 0x00 11. "RX64OCTGBPIS,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.."
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bitfld.long 0x00 10. "RXOSIZEGPIS,MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.."
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bitfld.long 0x00 9. "RXUSIZEGPIS,MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.."
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bitfld.long 0x00 8. "RXJABERPIS,MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.."
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bitfld.long 0x00 7. "RXRUNTPIS,MMC Receive Runt Packet Counter Interrupt Status This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt..,1: MMC Receive Runt Packet Counter Interrupt.."
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bitfld.long 0x00 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.."
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bitfld.long 0x00 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter..,1: MMC Receive CRC Error Packet Counter.."
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bitfld.long 0x00 4. "RXMCGPIS,MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.."
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bitfld.long 0x00 3. "RXBCGPIS,MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.."
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bitfld.long 0x00 2. "RXGOCTIS,MMC Receive Good Octet Counter Interrupt Status This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt..,1: MMC Receive Good Octet Counter Interrupt.."
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bitfld.long 0x00 1. "RXGBOCTIS,MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.."
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bitfld.long 0x00 0. "RXGBPKTIS,MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.."
rgroup.long 0x708++0x03
line.long 0x00 "MMC_Tx_Interrupt,This register maintains the interrupts generated from all Transmit statistics counters"
bitfld.long 0x00 27. "TXLPITRCIS,MMC Transmit LPI transition counter interrupt status This bit is set when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI transition Counter Interrupt..,1: MMC Transmit LPI transition Counter Interrupt.."
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bitfld.long 0x00 26. "TXLPIUSCIS,MMC Transmit LPI microsecond counter interrupt status This bit is set when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI microsecond Counter..,1: MMC Transmit LPI microsecond Counter.."
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bitfld.long 0x00 25. "TXOSIZEGPIS,MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.."
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bitfld.long 0x00 24. "TXVLANGPIS,MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter..,1: MMC Transmit VLAN Good Packet Counter.."
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bitfld.long 0x00 23. "TXPAUSPIS,MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the txpausepacketserror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt..,1: MMC Transmit Pause Packet Counter Interrupt.."
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bitfld.long 0x00 22. "TXEXDEFPIS,MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet..,1: MMC Transmit Excessive Deferral Packet.."
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bitfld.long 0x00 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt..,1: MMC Transmit Good Packet Counter Interrupt.."
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bitfld.long 0x00 20. "TXGOCTIS,MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt..,1: MMC Transmit Good Octet Counter Interrupt.."
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bitfld.long 0x00 19. "TXCARERPIS,MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.."
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bitfld.long 0x00 18. "TXEXCOLPIS,MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet..,1: MMC Transmit Excessive Collision Packet.."
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bitfld.long 0x00 17. "TXLATCOLPIS,MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.."
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bitfld.long 0x00 16. "TXDEFPIS,MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter..,1: MMC Transmit Deferred Packet Counter.."
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bitfld.long 0x00 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.."
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bitfld.long 0x00 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.."
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bitfld.long 0x00 13. "TXUFLOWERPIS,MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.."
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bitfld.long 0x00 12. "TXBCGBPIS,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet..,1: MMC Transmit Broadcast Good Bad Packet.."
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bitfld.long 0x00 11. "TXMCGBPIS,MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet..,1: MMC Transmit Multicast Good Bad Packet.."
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bitfld.long 0x00 10. "TXUCGBPIS,MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.."
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bitfld.long 0x00 9. "TX1024TMAXOCTGBPIS,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.."
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bitfld.long 0x00 8. "TX512T1023OCTGBPIS,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad..,1: MMC Transmit 512 to 1023 Octet Good Bad.."
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bitfld.long 0x00 7. "TX256T511OCTGBPIS,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.."
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bitfld.long 0x00 6. "TX128T255OCTGBPIS,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.."
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bitfld.long 0x00 5. "TX65T127OCTGBPIS,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half the maximum value and also when it reaches the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.."
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bitfld.long 0x00 4. "TX64OCTGBPIS,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.."
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bitfld.long 0x00 3. "TXMCGPIS,MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.."
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bitfld.long 0x00 2. "TXBCGPIS,MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.."
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bitfld.long 0x00 1. "TXGBPKTIS,MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter..,1: MMC Transmit Good Bad Packet Counter.."
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bitfld.long 0x00 0. "TXGBOCTIS,MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.."
group.long 0x70C++0x03
line.long 0x00 "MMC_Rx_Interrupt_Mask,This register maintains the masks for interrupts generated from all Receive statistics counters"
bitfld.long 0x00 27. "RXLPITRCIM,MMC Receive LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI transition counter interrupt..,1: MMC Receive LPI transition counter interrupt.."
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bitfld.long 0x00 26. "RXLPIUSCIM,MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI microsecond counter interrupt..,1: MMC Receive LPI microsecond counter interrupt.."
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bitfld.long 0x00 25. "RXCTRLPIM,MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.."
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bitfld.long 0x00 24. "RXRCVERRPIM,MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt..,1: MMC Receive Error Packet Counter Interrupt.."
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bitfld.long 0x00 23. "RXWDOGPIM,MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.."
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bitfld.long 0x00 22. "RXVLANGBPIM,MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.."
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bitfld.long 0x00 21. "RXFOVPIM,MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.."
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bitfld.long 0x00 20. "RXPAUSPIM,MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt..,1: MMC Receive Pause Packet Counter Interrupt.."
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bitfld.long 0x00 19. "RXORANGEPIM,MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.."
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bitfld.long 0x00 18. "RXLENERPIM,MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.."
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bitfld.long 0x00 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.."
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bitfld.long 0x00 16. "RX1024TMAXOCTGBPIM,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.."
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bitfld.long 0x00 15. "RX512T1023OCTGBPIM,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.."
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bitfld.long 0x00 14. "RX256T511OCTGBPIM,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.."
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bitfld.long 0x00 13. "RX128T255OCTGBPIM,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.."
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bitfld.long 0x00 12. "RX65T127OCTGBPIM,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.."
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bitfld.long 0x00 11. "RX64OCTGBPIM,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.."
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bitfld.long 0x00 10. "RXOSIZEGPIM,MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.."
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bitfld.long 0x00 9. "RXUSIZEGPIM,MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.."
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bitfld.long 0x00 8. "RXJABERPIM,MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.."
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bitfld.long 0x00 7. "RXRUNTPIM,MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt..,1: MMC Receive Runt Packet Counter Interrupt.."
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bitfld.long 0x00 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.."
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bitfld.long 0x00 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter..,1: MMC Receive CRC Error Packet Counter.."
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bitfld.long 0x00 4. "RXMCGPIM,MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.."
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bitfld.long 0x00 3. "RXBCGPIM,MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.."
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bitfld.long 0x00 2. "RXGOCTIM,MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt Mask..,1: MMC Receive Good Octet Counter Interrupt Mask.."
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bitfld.long 0x00 1. "RXGBOCTIM,MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.."
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bitfld.long 0x00 0. "RXGBPKTIM,MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.."
group.long 0x710++0x03
line.long 0x00 "MMC_Tx_Interrupt_Mask,This register maintains the masks for interrupts generated from all Transmit statistics counters"
bitfld.long 0x00 27. "TXLPITRCIM,MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI transition counter interrupt..,1: MMC Transmit LPI transition counter interrupt.."
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bitfld.long 0x00 26. "TXLPIUSCIM,MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI microsecond counter..,1: MMC Transmit LPI microsecond counter.."
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bitfld.long 0x00 25. "TXOSIZEGPIM,MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.."
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bitfld.long 0x00 24. "TXVLANGPIM,MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter..,1: MMC Transmit VLAN Good Packet Counter.."
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bitfld.long 0x00 23. "TXPAUSPIM,MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt..,1: MMC Transmit Pause Packet Counter Interrupt.."
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bitfld.long 0x00 22. "TXEXDEFPIM,MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet..,1: MMC Transmit Excessive Deferral Packet.."
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bitfld.long 0x00 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt..,1: MMC Transmit Good Packet Counter Interrupt.."
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bitfld.long 0x00 20. "TXGOCTIM,MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt..,1: MMC Transmit Good Octet Counter Interrupt.."
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bitfld.long 0x00 19. "TXCARERPIM,MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.."
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bitfld.long 0x00 18. "TXEXCOLPIM,MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet..,1: MMC Transmit Excessive Collision Packet.."
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bitfld.long 0x00 17. "TXLATCOLPIM,MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.."
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bitfld.long 0x00 16. "TXDEFPIM,MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter..,1: MMC Transmit Deferred Packet Counter.."
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bitfld.long 0x00 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.."
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bitfld.long 0x00 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.."
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bitfld.long 0x00 13. "TXUFLOWERPIM,MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.."
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bitfld.long 0x00 12. "TXBCGBPIM,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet..,1: MMC Transmit Broadcast Good Bad Packet.."
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bitfld.long 0x00 11. "TXMCGBPIM,MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet..,1: MMC Transmit Multicast Good Bad Packet.."
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bitfld.long 0x00 10. "TXUCGBPIM,MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.."
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bitfld.long 0x00 9. "TX1024TMAXOCTGBPIM,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.."
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bitfld.long 0x00 8. "TX512T1023OCTGBPIM,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad..,1: MMC Transmit 512 to 1023 Octet Good Bad.."
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bitfld.long 0x00 7. "TX256T511OCTGBPIM,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.."
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bitfld.long 0x00 6. "TX128T255OCTGBPIM,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.."
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bitfld.long 0x00 5. "TX65T127OCTGBPIM,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.."
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bitfld.long 0x00 4. "TX64OCTGBPIM,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.."
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bitfld.long 0x00 3. "TXMCGPIM,MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.."
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bitfld.long 0x00 2. "TXBCGPIM,MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.."
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bitfld.long 0x00 1. "TXGBPKTIM,MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter..,1: MMC Transmit Good Bad Packet Counter.."
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bitfld.long 0x00 0. "TXGBOCTIM,MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.."
rgroup.long 0x714++0x03
line.long 0x00 "Tx_Octet_Count_Good_Bad,This register provides the number of bytes transmitted by the DWC_ether_qos exclusive of preamble and retried bytes in good and bad packets"
hexmask.long 0x00 0.--31. 1. "TXOCTGB,Tx Octet Count Good Bad This field indicates the number of bytes transmitted exclusive of preamble and retried bytes in good and bad packets"
rgroup.long 0x718++0x03
line.long 0x00 "Tx_Packet_Count_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos exclusive of retried packets"
hexmask.long 0x00 0.--31. 1. "TXPKTGB,Tx Packet Count Good Bad This field indicates the number of good and bad packets transmitted exclusive of retried packets"
rgroup.long 0x71C++0x03
line.long 0x00 "Tx_Broadcast_Packets_Good,This register provides the number of good broadcast packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXBCASTG,Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted"
rgroup.long 0x720++0x03
line.long 0x00 "Tx_Multicast_Packets_Good,This register provides the number of good multicast packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXMCASTG,Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted"
rgroup.long 0x724++0x03
line.long 0x00 "Tx_64Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 64 bytes exclusive of preamble and retried packets"
hexmask.long 0x00 0.--31. 1. "TX64OCTGB,Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets transmitted with length 64 bytes exclusive of preamble and retried packets"
rgroup.long 0x728++0x03
line.long 0x00 "Tx_65To127Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried packets"
hexmask.long 0x00 0.--31. 1. "TX65_127OCTGB,Tx 65To127Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x72C++0x03
line.long 0x00 "Tx_128To255Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 128 to 255 (inclusive) bytes exclusive of preamble and retried packets"
hexmask.long 0x00 0.--31. 1. "TX128_255OCTGB,Tx 128To255Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 128 and 255 (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x730++0x03
line.long 0x00 "Tx_256To511Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 256 to 511 (inclusive) bytes exclusive of preamble and retried packets"
hexmask.long 0x00 0.--31. 1. "TX256_511OCTGB,Tx 256To511Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 256 and 511 (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x734++0x03
line.long 0x00 "Tx_512To1023Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 512 to 1023 (inclusive) bytes exclusive of preamble and retried packets"
hexmask.long 0x00 0.--31. 1. "TX512_1023OCTGB,Tx 512To1023Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 512 and 1023 (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x738++0x03
line.long 0x00 "Tx_1024ToMaxOctets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 1024 to maxsize (inclusive) bytes exclusive of preamble and retried packets"
hexmask.long 0x00 0.--31. 1. "TX1024_MAXOCTGB,Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x73C++0x03
line.long 0x00 "Tx_Unicast_Packets_Good_Bad,This register provides the number of good and bad unicast packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXUCASTGB,Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted"
rgroup.long 0x740++0x03
line.long 0x00 "Tx_Multicast_Packets_Good_Bad,This register provides the number of good and bad multicast packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXMCASTGB,Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted"
rgroup.long 0x744++0x03
line.long 0x00 "Tx_Broadcast_Packets_Good_Bad,This register provides the number of good and bad broadcast packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXBCASTGB,Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted"
rgroup.long 0x748++0x03
line.long 0x00 "Tx_Underflow_Error_Packets,This register provides the number of packets aborted by DWC_ether_qos because of packets underflow error"
hexmask.long 0x00 0.--31. 1. "TXUNDRFLW,Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error"
rgroup.long 0x74C++0x03
line.long 0x00 "Tx_Single_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_ether_qos after a single collision in the half-duplex mode"
hexmask.long 0x00 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode"
rgroup.long 0x750++0x03
line.long 0x00 "Tx_Multiple_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_ether_qos after multiple collisions in the half-duplex mode"
hexmask.long 0x00 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode"
rgroup.long 0x754++0x03
line.long 0x00 "Tx_Deferred_Packets,This register provides the number of successfully transmitted by DWC_ether_qos after a deferral in the half-duplex mode"
hexmask.long 0x00 0.--31. 1. "TXDEFRD,Tx Deferred Packets This field indicates the number of successfully transmitted after a deferral in the half-duplex mode"
rgroup.long 0x758++0x03
line.long 0x00 "Tx_Late_Collision_Packets,This register provides the number of packets aborted by DWC_ether_qos because of late collision error"
hexmask.long 0x00 0.--31. 1. "TXLATECOL,Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error"
rgroup.long 0x75C++0x03
line.long 0x00 "Tx_Excessive_Collision_Packets,This register provides the number of packets aborted by DWC_ether_qos because of excessive (16) collision errors"
hexmask.long 0x00 0.--31. 1. "TXEXSCOL,Tx Excessive Collision Packets This field indicates the number of packets aborted because of excessive (16) collision errors"
rgroup.long 0x760++0x03
line.long 0x00 "Tx_Carrier_Error_Packets,This register provides the number of packets aborted by DWC_ether_qos because of carrier sense error (no carrier or loss of carrier)"
hexmask.long 0x00 0.--31. 1. "TXCARR,Tx Carrier Error Packets This field indicates the number of packets aborted because of carrier sense error (no carrier or loss of carrier)"
rgroup.long 0x764++0x03
line.long 0x00 "Tx_Octet_Count_Good,This register provides the number of bytes transmitted by DWC_ether_qos exclusive of preamble only in good packets"
hexmask.long 0x00 0.--31. 1. "TXOCTG,Tx Octet Count Good This field indicates the number of bytes transmitted exclusive of preamble only in good packets"
rgroup.long 0x768++0x03
line.long 0x00 "Tx_Packet_Count_Good,This register provides the number of good packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXPKTG,Tx Packet Count Good This field indicates the number of good packets transmitted"
rgroup.long 0x76C++0x03
line.long 0x00 "Tx_Excessive_Deferral_Error,This register provides the number of packets aborted by DWC_ether_qos because of excessive deferral error (deferred for more than two max-sized packet times)"
hexmask.long 0x00 0.--31. 1. "TXEXSDEF,Tx Excessive Deferral Error This field indicates the number of packets aborted because of excessive deferral error (deferred for more than two max-sized packet times)"
rgroup.long 0x770++0x03
line.long 0x00 "Tx_Pause_Packets,This register provides the number of good Pause packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXPAUSE,Tx Pause Packets This field indicates the number of good Pause packets transmitted"
rgroup.long 0x774++0x03
line.long 0x00 "Tx_VLAN_Packets_Good,This register provides the number of good VLAN packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXVLANG,Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted"
rgroup.long 0x778++0x03
line.long 0x00 "Tx_OSize_Packets_Good,This register provides the number of packets transmitted by DWC_ether_qos without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged packets 2000 bytes if enabled in S2KP bit of the.."
hexmask.long 0x00 0.--31. 1. "TXOSIZG,Tx OSize Packets Good This field indicates the number of packets transmitted without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged packets 2000 bytes if enabled in S2KP bit of the MAC_Configuration register)"
rgroup.long 0x780++0x03
line.long 0x00 "Rx_Packets_Count_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXPKTGB,Rx Packets Count Good Bad This field indicates the number of good and bad packets received"
rgroup.long 0x784++0x03
line.long 0x00 "Rx_Octet_Count_Good_Bad,This register provides the number of bytes received by DWC_ther_qos exclusive of preamble in good and bad packets"
hexmask.long 0x00 0.--31. 1. "RXOCTGB,Rx Octet Count Good Bad This field indicates the number of bytes received exclusive of preamble in good and bad packets"
rgroup.long 0x788++0x03
line.long 0x00 "Rx_Octet_Count_Good,This register provides the number of bytes received by DWC_ether_qos exclusive of preamble only in good packets"
hexmask.long 0x00 0.--31. 1. "RXOCTG,Rx Octet Count Good This field indicates the number of bytes received exclusive of preamble only in good packets"
rgroup.long 0x78C++0x03
line.long 0x00 "Rx_Broadcast_Packets_Good,This register provides the number of good broadcast packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXBCASTG,Rx Broadcast Packets Good This field indicates the number of good broadcast packets received"
rgroup.long 0x790++0x03
line.long 0x00 "Rx_Multicast_Packets_Good,This register provides the number of good multicast packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXMCASTG,Rx Multicast Packets Good This field indicates the number of good multicast packets received"
rgroup.long 0x794++0x03
line.long 0x00 "Rx_CRC_Error_Packets,This register provides the number of packets received by DWC_ether_qos with CRC error"
hexmask.long 0x00 0.--31. 1. "RXCRCERR,Rx CRC Error Packets This field indicates the number of packets received with CRC error"
rgroup.long 0x798++0x03
line.long 0x00 "Rx_Alignment_Error_Packets,This register provides the number of packets received by DWC_ether_qos with alignment (dribble) error"
hexmask.long 0x00 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error"
rgroup.long 0x79C++0x03
line.long 0x00 "Rx_Runt_Error_Packets,This register provides the number of packets received by DWC_ether_qos with runt (length less than 64 bytes and CRC error) error"
hexmask.long 0x00 0.--31. 1. "RXRUNTERR,Rx Runt Error Packets This field indicates the number of packets received with runt (length less than 64 bytes and CRC error) error"
rgroup.long 0x7A0++0x03
line.long 0x00 "Rx_Jabber_Error_Packets,This register provides the number of giant packets received by DWC_ether_qos with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error"
hexmask.long 0x00 0.--31. 1. "RXJABERR,Rx Jabber Error Packets This field indicates the number of giant packets received with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error"
rgroup.long 0x7A4++0x03
line.long 0x00 "Rx_Undersize_Packets_Good,This register provides the number of packets received by DWC_ether_qos with length less than 64 bytes without any errors"
hexmask.long 0x00 0.--31. 1. "RXUNDERSZG,Rx Undersize Packets Good This field indicates the number of packets received with length less than 64 bytes without any errors"
rgroup.long 0x7A8++0x03
line.long 0x00 "Rx_Oversize_Packets_Good,This register provides the number of packets received by DWC_ether_qos without errors with length greater than the maxsize (1 518 bytes or 1 522 bytes for VLAN tagged packets 2000 bytes if enabled in the S2KP bit of the.."
hexmask.long 0x00 0.--31. 1. "RXOVERSZG,Rx Oversize Packets Good This field indicates the number of packets received without errors with length greater than the maxsize (1 518 bytes or 1 522 bytes for VLAN tagged packets 2000 bytes if enabled in the S2KP bit of the MAC_Configuration.."
rgroup.long 0x7AC++0x03
line.long 0x00 "Rx_64Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length 64 bytes exclusive of the preamble"
hexmask.long 0x00 0.--31. 1. "RX64OCTGB,Rx 64 Octets Packets Good Bad This field indicates the number of good and bad packets received with length 64 bytes exclusive of the preamble"
rgroup.long 0x7B0++0x03
line.long 0x00 "Rx_65To127Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 65 and 127 (inclusive) bytes exclusive of the preamble"
hexmask.long 0x00 0.--31. 1. "RX65_127OCTGB,Rx 65-127 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 65 and 127 (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7B4++0x03
line.long 0x00 "Rx_128To255Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 128 and 255 (inclusive) bytes exclusive of the preamble"
hexmask.long 0x00 0.--31. 1. "RX128_255OCTGB,Rx 128-255 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 128 and 255 (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7B8++0x03
line.long 0x00 "Rx_256To511Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 256 and 511 (inclusive) bytes exclusive of the preamble"
hexmask.long 0x00 0.--31. 1. "RX256_511OCTGB,Rx 256-511 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 256 and 511 (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7BC++0x03
line.long 0x00 "Rx_512To1023Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 512 and 1023 (inclusive) bytes exclusive of the preamble"
hexmask.long 0x00 0.--31. 1. "RX512_1023OCTGB,RX 512-1023 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 512 and 1023 (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7C0++0x03
line.long 0x00 "Rx_1024ToMaxOctets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 1024 and maxsize (inclusive) bytes exclusive of the preamble"
hexmask.long 0x00 0.--31. 1. "RX1024_MAXOCTGB,Rx 1024-Max Octets Good Bad This field indicates the number of good and bad packets received with length between 1024 and maxsize (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7C4++0x03
line.long 0x00 "Rx_Unicast_Packets_Good,This register provides the number of good unicast packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good This field indicates the number of good unicast packets received"
rgroup.long 0x7C8++0x03
line.long 0x00 "Rx_Length_Error_Packets,This register provides the number of packets received by DWC_ether_qos with length error (Length Type field not equal to packet size) for all packets with valid length field"
hexmask.long 0x00 0.--31. 1. "RXLENERR,Rx Length Error Packets This field indicates the number of packets received with length error (Length Type field not equal to packet size) for all packets with valid length field"
rgroup.long 0x7CC++0x03
line.long 0x00 "Rx_Out_Of_Range_Type_Packets,This register provides the number of packets received by DWC_ether_qos with length field not equal to the valid packet size (greater than 1 500 but less than 1 536)"
hexmask.long 0x00 0.--31. 1. "RXOUTOFRNG,Rx Out of Range Type Packet This field indicates the number of packets received with length field not equal to the valid packet size (greater than 1 500 but less than 1 536)"
rgroup.long 0x7D0++0x03
line.long 0x00 "Rx_Pause_Packets,This register provides the number of good and valid Pause packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXPAUSEPKT,Rx Pause Packets This field indicates the number of good and valid Pause packets received"
rgroup.long 0x7D4++0x03
line.long 0x00 "Rx_FIFO_Overflow_Packets,This register provides the number of missed received packets because of FIFO overflow in DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXFIFOOVFL,Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow"
rgroup.long 0x7D8++0x03
line.long 0x00 "Rx_VLAN_Packets_Good_Bad,This register provides the number of good and bad VLAN packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXVLANPKTGB,Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received"
rgroup.long 0x7DC++0x03
line.long 0x00 "Rx_Watchdog_Error_Packets,This register provides the number of packets received by DWC_ether_qos with error because of watchdog timeout error (packets with a data load larger than 2 048 bytes (when JE and WD bits are reset in MAC_Configuration register).."
hexmask.long 0x00 0.--31. 1. "RXWDGERR,Rx Watchdog Error Packets This field indicates the number of packets received with error because of watchdog timeout error (packets with a data load larger than 2 048 bytes (when JE and WD bits are reset in MAC_Configuration register) 10 240.."
rgroup.long 0x7E0++0x03
line.long 0x00 "Rx_Receive_Error_Packets,This register provides the number of packets received by DWC_ether_qos with Receive error or Packet Extension error on the GMII or MII interface"
hexmask.long 0x00 0.--31. 1. "RXRCVERR,Rx Receive Error Packets This field indicates the number of packets received with Receive error or Packet Extension error on the GMII or MII interface"
rgroup.long 0x7E4++0x03
line.long 0x00 "Rx_Control_Packets_Good,This register provides the number of good control packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXCTRLG,Rx Control Packets Good This field indicates the number of good control packets received"
rgroup.long 0x7EC++0x03
line.long 0x00 "Tx_LPI_USEC_Cntr,This register provides the number of microseconds Tx LPI is asserted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXLPIUSC,Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted"
rgroup.long 0x7F0++0x03
line.long 0x00 "Tx_LPI_Tran_Cntr,This register provides the number of times DWC_ether_qos has entered Tx LPI"
hexmask.long 0x00 0.--31. 1. "TXLPITRC,Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred"
rgroup.long 0x7F4++0x03
line.long 0x00 "Rx_LPI_USEC_Cntr,This register provides the number of microseconds Rx LPI is sampled by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXLPIUSC,Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted"
rgroup.long 0x7F8++0x03
line.long 0x00 "Rx_LPI_Tran_Cntr,This register provides the number of times DWC_ether_qos has entered Rx LPI"
hexmask.long 0x00 0.--31. 1. "RXLPITRC,Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred"
rgroup.long 0x8A0++0x03
line.long 0x00 "MMC_FPE_Tx_Interrupt,This register maintains the interrupts generated from all FPE related Transmit statistics counters"
bitfld.long 0x00 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx Hold Request Counter Interrupt Status..,1: MMC Tx Hold Request Counter Interrupt Status.."
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bitfld.long 0x00 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status This bit is set when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx FPE Fragment Counter Interrupt status..,1: MMC Tx FPE Fragment Counter Interrupt status.."
group.long 0x8A4++0x03
line.long 0x00 "MMC_FPE_Tx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Transmit statistics counters"
bitfld.long 0x00 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Hold Request Counter Interrupt..,1: MMC Transmit Hold Request Counter Interrupt.."
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bitfld.long 0x00 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Fragment Counter Interrupt Mask..,1: MMC Transmit Fragment Counter Interrupt Mask.."
rgroup.long 0x8A8++0x03
line.long 0x00 "MMC_Tx_FPE_Fragment_Cntr,This register provides the number of additional mPackets transmitted due to preemption"
hexmask.long 0x00 0.--31. 1. "TXFFC,Tx FPE Fragment counter This field indicates the number of additional mPackets that has been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled during FPE Enabled configuration"
rgroup.long 0x8AC++0x03
line.long 0x00 "MMC_Tx_Hold_Req_Cntr,This register provides the count of number of times a hold request is given to MAC"
hexmask.long 0x00 0.--31. 1. "TXHRC,Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC"
rgroup.long 0x8C0++0x03
line.long 0x00 "MMC_FPE_Rx_Interrupt,This register maintains the interrupts generated from all FPE related Receive statistics counters"
bitfld.long 0x00 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Status..,1: MMC Rx FPE Fragment Counter Interrupt Status.."
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bitfld.long 0x00 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt..,1: MMC Rx Packet Assembly OK Counter Interrupt.."
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bitfld.long 0x00 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt..,1: MMC Rx Packet SMD Error Counter Interrupt.."
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bitfld.long 0x00 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter..,1: MMC Rx Packet Assembly Error Counter.."
group.long 0x8C4++0x03
line.long 0x00 "MMC_FPE_Rx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Receive statistics counters"
bitfld.long 0x00 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Mask is..,1: MMC Rx FPE Fragment Counter Interrupt Mask is.."
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bitfld.long 0x00 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt..,1: MMC Rx Packet Assembly OK Counter Interrupt.."
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bitfld.long 0x00 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt..,1: MMC Rx Packet SMD Error Counter Interrupt.."
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bitfld.long 0x00 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter..,1: MMC Rx Packet Assembly Error Counter.."
rgroup.long 0x8C8++0x03
line.long 0x00 "MMC_Rx_Packet_Assembly_Err_Cntr,This register provides the number of MAC frames with reassembly errors on the Receiver due to mismatch in the Fragment Count value"
hexmask.long 0x00 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter This field indicates the number of MAC frames with reassembly errors on the Receiver due to mismatch in the Fragment Count value"
rgroup.long 0x8CC++0x03
line.long 0x00 "MMC_Rx_Packet_SMD_Err_Cntr,This register provides the number of received MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame"
hexmask.long 0x00 0.--31. 1. "PSEC,Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame"
rgroup.long 0x8D0++0x03
line.long 0x00 "MMC_Rx_Packet_Assembly_OK_Cntr,This register provides the number of MAC frames that were successfully reassembled and delivered to MAC"
hexmask.long 0x00 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were successfully reassembled and delivered to MAC"
rgroup.long 0x8D4++0x03
line.long 0x00 "MMC_Rx_FPE_Fragment_Cntr,This register provides the number of additional mPackets received due to preemption"
hexmask.long 0x00 0.--31. 1. "FFC,Rx FPE Fragment Counter This field indicates the number of additional mPackets received due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE Enabled configuration"
group.long 0x900++0x03
line.long 0x00 "MAC_L3_L4_Control0,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4"
bitfld.long 0x00 28. "DMCHEN0,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
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bitfld.long 0x00 24. "DMCHN0,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1"
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bitfld.long 0x00 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
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bitfld.long 0x00 20. "L4DPM0,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
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bitfld.long 0x00 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
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bitfld.long 0x00 18. "L4SPM0,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
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bitfld.long 0x00 16. "L4PEN0,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
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bitfld.long 0x00 11.--15. "L3HDBM0,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--10. "L3HSBM0,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
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bitfld.long 0x00 4. "L3DAM0,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
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bitfld.long 0x00 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
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bitfld.long 0x00 2. "L3SAM0,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
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bitfld.long 0x00 0. "L3PEN0,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x904++0x03
line.long 0x00 "MAC_Layer4_Address0,The MAC_Layer4_Address(#i) MAC_L3_L4_Control(#i) MAC_Layer3_Addr0_Reg(#i) MAC_Layer3_Addr1_Reg(#i) MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.."
hexmask.long.word 0x00 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
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hexmask.long.word 0x00 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0x910++0x03
line.long 0x00 "MAC_Layer3_Addr0_Reg0,For IPv4 packets the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field"
hexmask.long 0x00 0.--31. 1. "L3A00,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0x914++0x03
line.long 0x00 "MAC_Layer3_Addr1_Reg0,For IPv4 packets the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field"
hexmask.long 0x00 0.--31. 1. "L3A10,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0x918++0x03
line.long 0x00 "MAC_Layer3_Addr2_Reg0,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A20,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0x91C++0x03
line.long 0x00 "MAC_Layer3_Addr3_Reg0,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A30,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0x930++0x03
line.long 0x00 "MAC_L3_L4_Control1,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4"
bitfld.long 0x00 28. "DMCHEN1,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
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bitfld.long 0x00 24. "DMCHN1,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1"
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bitfld.long 0x00 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
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bitfld.long 0x00 20. "L4DPM1,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
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bitfld.long 0x00 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
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bitfld.long 0x00 18. "L4SPM1,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
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bitfld.long 0x00 16. "L4PEN1,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
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bitfld.long 0x00 11.--15. "L3HDBM1,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--10. "L3HSBM1,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
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bitfld.long 0x00 4. "L3DAM1,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
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bitfld.long 0x00 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
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bitfld.long 0x00 2. "L3SAM1,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
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bitfld.long 0x00 0. "L3PEN1,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x934++0x03
line.long 0x00 "MAC_Layer4_Address1,The MAC_Layer4_Address(#i) MAC_L3_L4_Control(#i) MAC_Layer3_Addr0_Reg(#i) MAC_Layer3_Addr1_Reg(#i) MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.."
hexmask.long.word 0x00 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
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hexmask.long.word 0x00 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0x940++0x03
line.long 0x00 "MAC_Layer3_Addr0_Reg1,For IPv4 packets the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field"
hexmask.long 0x00 0.--31. 1. "L3A01,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0x944++0x03
line.long 0x00 "MAC_Layer3_Addr1_Reg1,For IPv4 packets the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field"
hexmask.long 0x00 0.--31. 1. "L3A11,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0x948++0x03
line.long 0x00 "MAC_Layer3_Addr2_Reg1,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A21,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0x94C++0x03
line.long 0x00 "MAC_Layer3_Addr3_Reg1,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A31,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0x960++0x03
line.long 0x00 "MAC_L3_L4_Control2,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4"
bitfld.long 0x00 28. "DMCHEN2,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
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bitfld.long 0x00 24. "DMCHN2,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1"
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bitfld.long 0x00 21. "L4DPIM2,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
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bitfld.long 0x00 20. "L4DPM2,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
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bitfld.long 0x00 19. "L4SPIM2,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
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bitfld.long 0x00 18. "L4SPM2,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
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bitfld.long 0x00 16. "L4PEN2,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
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bitfld.long 0x00 11.--15. "L3HDBM2,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--10. "L3HSBM2,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "L3DAIM2,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
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bitfld.long 0x00 4. "L3DAM2,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
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bitfld.long 0x00 3. "L3SAIM2,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
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bitfld.long 0x00 2. "L3SAM2,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
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bitfld.long 0x00 0. "L3PEN2,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x964++0x03
line.long 0x00 "MAC_Layer4_Address2,The MAC_Layer4_Address(#i) MAC_L3_L4_Control(#i) MAC_Layer3_Addr0_Reg(#i) MAC_Layer3_Addr1_Reg(#i) MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.."
hexmask.long.word 0x00 16.--31. 1. "L4DP2,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
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hexmask.long.word 0x00 0.--15. 1. "L4SP2,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0x970++0x03
line.long 0x00 "MAC_Layer3_Addr0_Reg2,For IPv4 packets the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field"
hexmask.long 0x00 0.--31. 1. "L3A02,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0x974++0x03
line.long 0x00 "MAC_Layer3_Addr1_Reg2,For IPv4 packets the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field"
hexmask.long 0x00 0.--31. 1. "L3A12,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0x978++0x03
line.long 0x00 "MAC_Layer3_Addr2_Reg2,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A22,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0x97C++0x03
line.long 0x00 "MAC_Layer3_Addr3_Reg2,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A32,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0x990++0x03
line.long 0x00 "MAC_L3_L4_Control3,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4"
bitfld.long 0x00 28. "DMCHEN3,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
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bitfld.long 0x00 24. "DMCHN3,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1"
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bitfld.long 0x00 21. "L4DPIM3,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
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bitfld.long 0x00 20. "L4DPM3,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
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bitfld.long 0x00 19. "L4SPIM3,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
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bitfld.long 0x00 18. "L4SPM3,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
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bitfld.long 0x00 16. "L4PEN3,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
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bitfld.long 0x00 11.--15. "L3HDBM3,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--10. "L3HSBM3,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "L3DAIM3,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
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bitfld.long 0x00 4. "L3DAM3,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
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bitfld.long 0x00 3. "L3SAIM3,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
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bitfld.long 0x00 2. "L3SAM3,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
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bitfld.long 0x00 0. "L3PEN3,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x994++0x03
line.long 0x00 "MAC_Layer4_Address3,The MAC_Layer4_Address(#i) MAC_L3_L4_Control(#i) MAC_Layer3_Addr0_Reg(#i) MAC_Layer3_Addr1_Reg(#i) MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.."
hexmask.long.word 0x00 16.--31. 1. "L4DP3,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
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hexmask.long.word 0x00 0.--15. 1. "L4SP3,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0x9A0++0x03
line.long 0x00 "MAC_Layer3_Addr0_Reg3,For IPv4 packets the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field"
hexmask.long 0x00 0.--31. 1. "L3A03,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0x9A4++0x03
line.long 0x00 "MAC_Layer3_Addr1_Reg3,For IPv4 packets the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field"
hexmask.long 0x00 0.--31. 1. "L3A13,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0x9A8++0x03
line.long 0x00 "MAC_Layer3_Addr2_Reg3,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A23,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0x9AC++0x03
line.long 0x00 "MAC_Layer3_Addr3_Reg3,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A33,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0xA70++0x03
line.long 0x00 "MAC_Indir_Access_Ctrl,This register provides the Indirect Access control and status for MAC_<MSEl>_<AOFF> registers"
bitfld.long 0x00 16.--19. "MSEL,Mode Select This field is used in indirect access of MAC_<MSEL>_<AOFF>" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 8.--15. 1. "AOFF,Address Offset This field is used in indirect access of MAC_<MSEL>_<AOFF>"
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bitfld.long 0x00 5. "AUTO,Auto increment" "0,1"
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bitfld.long 0x00 1. "COM,Command type This bit indicates the register access type" "0: Write operation,1: Read operation"
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bitfld.long 0x00 0. "OB,Operation Busy" "0,1"
group.long 0xA74++0x03
line.long 0x00 "MAC_Indir_Access_Data,This register holds the read/write data for Indirect Access of MAC_<MSEL_<AOFF> registers"
hexmask.long 0x00 0.--31. 1. "DATA,This field contains data to read/write for Indirect address access associated with MAC_Indir_Access_Ctrl register"
group.long 0xB00++0x03
line.long 0x00 "MAC_Timestamp_Control,This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver"
bitfld.long 0x00 28. "AV8021ASMEN,AV 802" "0: AV 802.1AS Mode is disabled,1: AV 802.1AS Mode is enabled"
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bitfld.long 0x00 24. "TXTSSTSM,Transmit Timestamp Status Mode When this bit is set the MAC overwrites the earlier transmit timestamp status even if it is not read by the software" "0: Transmit Timestamp Status Mode is disabled,1: Transmit Timestamp Status Mode is enabled"
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bitfld.long 0x00 20. "ESTI,External System Time Input When this bit is set the MAC uses the external 64-bit reference System Time input for the following: - To take the timestamp provided as status - To insert the timestamp in transmit PTP packets when One-step Timestamp or.." "0: External System Time Input is disabled,1: External System Time Input is enabled"
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bitfld.long 0x00 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering When this bit is set the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet" "0: MAC Address for PTP Packet Filtering is..,1: MAC Address for PTP Packet Filtering is enabled"
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bitfld.long 0x00 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken" "0,1,2,3"
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bitfld.long 0x00 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master When this bit is set the snapshot is taken only for the messages that are relevant to the master node" "0: Snapshot for Messages Relevant to Master is..,1: Snapshot for Messages Relevant to Master is.."
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bitfld.long 0x00 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages When this bit is set the timestamp snapshot is taken only for event messages (SYNC Delay_Req Pdelay_Req or Pdelay_Resp)" "0: Timestamp Snapshot for Event Messages is..,1: Timestamp Snapshot for Event Messages is.."
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bitfld.long 0x00 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets" "0: Processing of PTP Packets Sent over IPv4-UDP..,1: Processing of PTP Packets Sent over IPv4-UDP.."
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bitfld.long 0x00 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets" "0: Processing of PTP Packets Sent over IPv6-UDP..,1: Processing of PTP Packets Sent over IPv6-UDP.."
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bitfld.long 0x00 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets When this bit is set the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets" "0: Processing of PTP over Ethernet Packets is..,1: Processing of PTP over Ethernet Packets is.."
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bitfld.long 0x00 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format When this bit is set the IEEE 1588 version 2 format is used to process the PTP packets" "0: PTP Packet Processing for Version 2 Format is..,1: PTP Packet Processing for Version 2 Format is.."
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bitfld.long 0x00 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control When this bit is set the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is 1 nanosecond accuracy) and increments the timestamp (High) seconds" "0: Timestamp Digital or Binary Rollover Control..,1: Timestamp Digital or Binary Rollover Control.."
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bitfld.long 0x00 8. "TSENALL,Enable Timestamp for All Packets When this bit is set the timestamp snapshot is enabled for all packets received by the MAC" "0: Timestamp for All Packets disabled,1: Timestamp for All Packets enabled"
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bitfld.long 0x00 6. "PTGE,Presentation Time Generation Enable When this bit is set the Presentation Time generation is enabled" "0: Presentation Time Generation is disabled,1: Presentation Time Generation is enabled"
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bitfld.long 0x00 5. "TSADDREG,Update Addend Register When this bit is set the content of the Timestamp Addend register is updated in the PTP block for fine correction" "0: Addend Register is not updated,1: Addend Register is updated"
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bitfld.long 0x00 3. "TSUPDT,Update Timestamp When this bit is set the system time is updated (added or subtracted) with the value specified in MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not updated,1: Timestamp is updated"
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bitfld.long 0x00 2. "TSINIT,Initialize Timestamp When this bit is set the system time is initialized (overwritten) with the value specified in the MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not initialized,1: Timestamp is initialized"
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bitfld.long 0x00 1. "TSCFUPDT,Fine or Coarse Timestamp Update When this bit is set the Fine method is used to update system timestamp" "0: Coarse method is used to update system..,1: Fine method is used to update system timestamp"
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bitfld.long 0x00 0. "TSENA,Enable Timestamp When this bit is set the timestamp is added for Transmit and Receive packets" "0: Timestamp is disabled,1: Timestamp is enabled"
group.long 0xB04++0x03
line.long 0x00 "MAC_Sub_Second_Increment,This register specifies the value to be added to the internal system time register every cycle of clk_ptp_ref_i clock"
hexmask.long.byte 0x00 16.--23. 1. "SSINC,Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register"
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hexmask.long.byte 0x00 8.--15. 1. "SNSINC,Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value represented in nanoseconds multiplied by 2^8"
rgroup.long 0xB08++0x03
line.long 0x00 "MAC_System_Time_Seconds,The System Time Seconds register along with System Time Nanoseconds register indicates the current value of the system time maintained by the MAC"
hexmask.long 0x00 0.--31. 1. "TSS,Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC"
rgroup.long 0xB0C++0x03
line.long 0x00 "MAC_System_Time_Nanoseconds,The System Time Nanoseconds register along with System Time Seconds register indicates the current value of the system time maintained by the MAC"
hexmask.long 0x00 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field has the sub-second representation of time with an accuracy of 0"
group.long 0xB10++0x03
line.long 0x00 "MAC_System_Time_Seconds_Update,The System Time Seconds Update register along with the System Time Nanoseconds Update register initializes or updates the system time maintained by the MAC"
hexmask.long 0x00 0.--31. 1. "TSS,Timestamp Seconds The value in this field is the seconds part of the update"
group.long 0xB14++0x03
line.long 0x00 "MAC_System_Time_Nanoseconds_Update,MAC System Time Nanoseconds Update register"
bitfld.long 0x00 31. "ADDSUB,Add or Subtract Time When this bit is set the time value is subtracted with the contents of the update register" "0: Add time,1: Subtract time"
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hexmask.long 0x00 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field is the sub-seconds part of the update"
group.long 0xB18++0x03
line.long 0x00 "MAC_Timestamp_Addend,Timestamp Addend register"
hexmask.long 0x00 0.--31. 1. "TSAR,Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization"
group.long 0xB1C++0x03
line.long 0x00 "MAC_System_Time_Higher_Word_Seconds,System Time - Higher Word Seconds register"
hexmask.long.word 0x00 0.--15. 1. "TSHWR,Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value"
rgroup.long 0xB20++0x03
line.long 0x00 "MAC_Timestamp_Status,Timestamp Status register"
bitfld.long 0x00 25.--29. "ATSNS,Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set" "0: Auxiliary Timestamp Snapshot Trigger Missed..,1: Auxiliary Timestamp Snapshot Trigger Missed.."
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bitfld.long 0x00 16.--19. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "TXTSSIS,Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop transmit status is enabled in MTL this bit is set when the captured transmit timestamp is updated in the MAC_Tx_Timestamp_Status_Nanoseconds and.." "0: Tx Timestamp Status Interrupt status not..,1: Tx Timestamp Status Interrupt status detected"
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bitfld.long 0x00 9. "TSTRGTERR3,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
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bitfld.long 0x00 8. "TSTARGT3,Timestamp Target Time Reached for Target Time PPS3 When this bit is set and MCGREN3 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the.." "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.."
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bitfld.long 0x00 7. "TSTRGTERR2,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
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bitfld.long 0x00 6. "TSTARGT2,Timestamp Target Time Reached for Target Time PPS2 When this bit is set and MCGREN2 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the.." "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.."
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bitfld.long 0x00 5. "TSTRGTERR1,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
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bitfld.long 0x00 4. "TSTARGT1,Timestamp Target Time Reached for Target Time PPS1 When this bit is set and MCGREN1 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the.." "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.."
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bitfld.long 0x00 3. "TSTRGTERR0,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
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bitfld.long 0x00 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO" "0: Auxiliary Timestamp Trigger Snapshot status..,1: Auxiliary Timestamp Trigger Snapshot status.."
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bitfld.long 0x00 1. "TSTARGT0,Timestamp Target Time Reached When this bit is set and MCGREN0 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and.." "0: Timestamp Target Time Reached status not..,1: Timestamp Target Time Reached status detected"
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bitfld.long 0x00 0. "TSSOVF,Timestamp Seconds Overflow When this bit is set it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF" "0: Timestamp Seconds Overflow status not detected,1: Timestamp Seconds Overflow status detected"
rgroup.long 0xB30++0x03
line.long 0x00 "MAC_Tx_Timestamp_Status_Nanoseconds,This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled"
bitfld.long 0x00 31. "TXTSSMIS,Transmit Timestamp Status Missed When this bit is set it indicates one of the following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the MAC_Timestamp_Control register is reset - The timestamp of the previous packet is.." "0: Transmit Timestamp Status Missed status not..,1: Transmit Timestamp Status Missed status.."
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hexmask.long 0x00 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp"
rgroup.long 0xB34++0x03
line.long 0x00 "MAC_Tx_Timestamp_Status_Seconds,The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted"
hexmask.long 0x00 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp"
group.long 0xB40++0x03
line.long 0x00 "MAC_Auxiliary_Control,The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot"
bitfld.long 0x00 7. "ATSEN3,Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
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bitfld.long 0x00 6. "ATSEN2,Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
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bitfld.long 0x00 5. "ATSEN1,Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
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bitfld.long 0x00 4. "ATSEN0,Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
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bitfld.long 0x00 0. "ATSFC,Auxiliary Snapshot FIFO Clear When set this bit resets the pointers of the Auxiliary Snapshot FIFO" "0: Auxiliary Snapshot FIFO Clear is disabled,1: Auxiliary Snapshot FIFO Clear is enabled"
rgroup.long 0xB48++0x03
line.long 0x00 "MAC_Auxiliary_Timestamp_Nanoseconds,The Auxiliary Timestamp Nanoseconds register along with MAC_Auxiliary_Timestamp_Seconds gives the 64-bit timestamp stored as auxiliary snapshot"
hexmask.long 0x00 0.--30. 1. "AUXTSLO,Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp"
rgroup.long 0xB4C++0x03
line.long 0x00 "MAC_Auxiliary_Timestamp_Seconds,The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register"
hexmask.long 0x00 0.--31. 1. "AUXTSHI,Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp"
group.long 0xB50++0x03
line.long 0x00 "MAC_Timestamp_Ingress_Asym_Corr,The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages"
hexmask.long 0x00 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet"
group.long 0xB54++0x03
line.long 0x00 "MAC_Timestamp_Egress_Asym_Corr,The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages"
hexmask.long 0x00 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet"
group.long 0xB58++0x03
line.long 0x00 "MAC_Timestamp_Ingress_Corr_Nanosecond,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path"
hexmask.long 0x00 0.--31. 1. "TSIC,Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression"
group.long 0xB5C++0x03
line.long 0x00 "MAC_Timestamp_Egress_Corr_Nanosecond,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path"
hexmask.long 0x00 0.--31. 1. "TSEC,Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression"
group.long 0xB60++0x03
line.long 0x00 "MAC_Timestamp_Ingress_Corr_Subnanosec,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value for ingress direction"
hexmask.long.byte 0x00 8.--15. 1. "TSICSNS,Timestamp Ingress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the ingress path correction value as defined by the Ingress Correction expression"
group.long 0xB64++0x03
line.long 0x00 "MAC_Timestamp_Egress_Corr_Subnanosec,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value for egress direction"
hexmask.long.byte 0x00 8.--15. 1. "TSECSNS,Timestamp Egress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the egress path correction value as defined by the Egress Correction expression"
rgroup.long 0xB68++0x03
line.long 0x00 "MAC_Timestamp_Ingress_Latency,This register holds the Ingress MAC latency"
hexmask.long.word 0x00 16.--27. 1. "ITLNS,Ingress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken"
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hexmask.long.byte 0x00 8.--15. 1. "ITLSNS,Ingress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken"
rgroup.long 0xB6C++0x03
line.long 0x00 "MAC_Timestamp_Egress_Latency,This register holds the Egress MAC latency"
hexmask.long.word 0x00 16.--27. 1. "ETLNS,Egress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC"
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hexmask.long.byte 0x00 8.--15. 1. "ETLSNS,Egress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC"
group.long 0xB70++0x03
line.long 0x00 "MAC_PPS_Control,PPS Control register"
bitfld.long 0x00 31. "MCGREN3,MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode" "0,1"
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bitfld.long 0x00 29.--30. "TRGTMODSEL3,Target Time Register Mode for PPS3 Output This field indicates the Target Time registers (MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds) mode for PPS3 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
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bitfld.long 0x00 28. "TIMESEL,Time Select When this bit is set 64 bit PTP time is used to capture time at MCGR trigger[0] input When this bit is reset presentation time is used to capture time at trigger input maintaining backward compatibility" "0,1"
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bitfld.long 0x00 24.--27. "PPSCMD3,Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "MCGREN2,MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode" "0: 2nd PPS instance is disabled to operate in..,1: 2nd PPS instance is enabled to operate in PPS.."
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bitfld.long 0x00 21.--22. "TRGTMODSEL2,Target Time Register Mode for PPS2 Output This field indicates the Target Time registers (MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds) mode for PPS2 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
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bitfld.long 0x00 16.--19. "PPSCMD2,Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "MCGREN1,MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode" "0: 1st PPS instance is disabled to operate in..,1: 1st PPS instance is enabled to operate in PPS.."
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bitfld.long 0x00 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS1 Output This field indicates the Target Time registers (MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds) mode for PPS1 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
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bitfld.long 0x00 8.--11. "PPSCMD1,Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "MCGREN0,MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode" "0: 0th PPS instance is enabled to operate in PPS..,1: 0th PPS instance is enabled to operate in.."
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bitfld.long 0x00 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output This field indicates the Target Time registers (MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds) mode for PPS0 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
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bitfld.long 0x00 4. "PPSEN0,Flexible PPS Output Mode Enable When this bit is" "0: Flexible PPS Output Mode is disabled,1: Flexible PPS Output Mode is enabled"
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bitfld.long 0x00 0.--3. "PPSCTRL_PPSCMD,PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB80++0x03
line.long 0x00 "MAC_PPS0_Target_Time_Seconds,The PPS Target Time Seconds register along with PPS Target Time Nanoseconds register is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers"
hexmask.long 0x00 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register This field stores the time in seconds"
group.long 0xB84++0x03
line.long 0x00 "MAC_PPS0_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register"
bitfld.long 0x00 31. "TRGTBUSY0,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
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hexmask.long 0x00 0.--30. 1. "TTSL0,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
group.long 0xB88++0x03
line.long 0x00 "MAC_PPS0_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSINT0,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
group.long 0xB8C++0x03
line.long 0x00 "MAC_PPS0_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
group.long 0xB90++0x03
line.long 0x00 "MAC_PPS1_Target_Time_Seconds,The PPS Target Time Seconds register along with PPS Target Time Nanoseconds register is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers"
hexmask.long 0x00 0.--31. 1. "TSTRH1,PPS Target Time Seconds Register This field stores the time in seconds"
group.long 0xB94++0x03
line.long 0x00 "MAC_PPS1_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register"
bitfld.long 0x00 31. "TRGTBUSY1,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
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hexmask.long 0x00 0.--30. 1. "TTSL1,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
group.long 0xB98++0x03
line.long 0x00 "MAC_PPS1_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSINT1,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
group.long 0xB9C++0x03
line.long 0x00 "MAC_PPS1_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSWIDTH1,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
group.long 0xBA0++0x03
line.long 0x00 "MAC_PPS2_Target_Time_Seconds,The PPS Target Time Seconds register along with PPS Target Time Nanoseconds register is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers"
hexmask.long 0x00 0.--31. 1. "TSTRH2,PPS Target Time Seconds Register This field stores the time in seconds"
group.long 0xBA4++0x03
line.long 0x00 "MAC_PPS2_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register"
bitfld.long 0x00 31. "TRGTBUSY2,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
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hexmask.long 0x00 0.--30. 1. "TTSL2,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
group.long 0xBA8++0x03
line.long 0x00 "MAC_PPS2_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSINT2,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
group.long 0xBAC++0x03
line.long 0x00 "MAC_PPS2_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSWIDTH2,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
group.long 0xBB0++0x03
line.long 0x00 "MAC_PPS3_Target_Time_Seconds,The PPS Target Time Seconds register along with PPS Target Time Nanoseconds register is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers"
hexmask.long 0x00 0.--31. 1. "TSTRH3,PPS Target Time Seconds Register This field stores the time in seconds"
group.long 0xBB4++0x03
line.long 0x00 "MAC_PPS3_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register"
bitfld.long 0x00 31. "TRGTBUSY3,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
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hexmask.long 0x00 0.--30. 1. "TTSL3,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
group.long 0xBB8++0x03
line.long 0x00 "MAC_PPS3_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSINT3,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
group.long 0xBBC++0x03
line.long 0x00 "MAC_PPS3_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSWIDTH3,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
group.long 0xC00++0x03
line.long 0x00 "MTL_Operation_Mode,The Operation Mode register establishes the Transmit and Receive operating modes and commands"
bitfld.long 0x00 15. "FRPE,Flexible Rx parser Enable" "0: Flexible Rx parser is disabled,1: Flexible Rx parser is enabled"
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bitfld.long 0x00 14. "RXPED,RxParser Software Error/Incomplete Parsing Packet Drop Enable when this bit is set to 0 packets encountering software programming errors (NPE/NVE/frame offset overflow errors) or incomplete parsing are forwarded to application with the.." "0: Flexible Rx parser packet drop in case..,1: Flexible Rx parser packet drop in case.."
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bitfld.long 0x00 9. "CNTCLR,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset"
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bitfld.long 0x00 8. "CNTPRST,Counters Preset When this bit is set - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0" "0: Counters Preset is disabled,1: Counters Preset is enabled"
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bitfld.long 0x00 5.--6. "SCHALG,Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling" "0: WRR algorithm,1: WFQ algorithm when DCB feature is..,2: DWRR algorithm when DCB feature is..,3: Strict priority algorithm"
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bitfld.long 0x00 2. "RAA,Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side" "0: Strict priority (SP),1: Weighted Strict Priority (WSP)"
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bitfld.long 0x00 1. "DTXSTS,Drop Transmit Status" "0: Drop Transmit Status is disabled,1: Drop Transmit Status is enabled"
group.long 0xC08++0x03
line.long 0x00 "MTL_DBG_CTL,The FIFO Debug Access Control and Status register controls the operation mode of FIFO debug access"
bitfld.long 0x00 18. "EIEC,ECC Inject Error Control for Tx Rx TSO and DCACHE memories When EIEE or EIAEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: insert 2 bit errors"
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bitfld.long 0x00 17. "EIAEE,ECC Inject Address Error for Tx Rx TSO and DCACHE memories" "0: Disables the ECC address error injection,1: Enables the ECC address error injection"
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bitfld.long 0x00 16. "EIEE,ECC Inject Error Enable for Tx Rx TSO and DCACHE memories" "0: ECC Inject Error for Tx Rx TSO and DCACHE..,1: ECC Inject Error for Tx Rx TSO and DCACHE.."
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bitfld.long 0x00 15. "STSIE,Transmit Status Available Interrupt Status Enable When this bit is set an interrupt is generated when Transmit status is available in slave mode" "0: Transmit Packet Available Interrupt Status is..,1: Transmit Packet Available Interrupt Status is.."
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bitfld.long 0x00 14. "PKTIE,Receive Packet Available Interrupt Status Enable When this bit is set an interrupt is generated when EOP of received packet is written to the Rx FIFO" "0: Receive Packet Available Interrupt Status is..,1: Receive Packet Available Interrupt Status is.."
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bitfld.long 0x00 12.--13. "FIFOSEL,FIFO Selected for Access This field indicates the FIFO selected for debug access" "0: Tx FIFO,1: Tx Status FIFO (only read access when SLVMOD..,2: TSO FIFO (cannot be accessed when SLVMOD is..,3: Rx FIFO"
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bitfld.long 0x00 11. "FIFOWREN,FIFO Write Enable When this bit is set it enables the Write operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Write is disabled,1: FIFO Write is enabled"
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bitfld.long 0x00 10. "FIFORDEN,FIFO Read Enable When this bit is set it enables the Read operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Read is disabled,1: FIFO Read is enabled"
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bitfld.long 0x00 9. "RSTSEL,Reset Pointers of Selected FIFO When this bit is set the pointers of the currently-selected FIFO are reset when FIFO Debug Access is enabled" "0: Reset Pointers of Selected FIFO is disabled,1: Reset Pointers of Selected FIFO is enabled"
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bitfld.long 0x00 8. "RSTALL,Reset All Pointers When this bit is set the pointers of all FIFOs are reset when FIFO Debug Access is enabled" "0: Reset All Pointers is disabled,1: Reset All Pointers is enabled"
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bitfld.long 0x00 5.--6. "PKTSTATE,Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP"
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bitfld.long 0x00 2.--3. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Write operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid"
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bitfld.long 0x00 1. "DBGMOD,Debug Mode Access to FIFO" "0: Debug Mode Access to FIFO is disabled,1: Debug Mode Access to FIFO is enabled"
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bitfld.long 0x00 0. "FDBGEN,FIFO Debug Access Enable" "0: FIFO Debug Access is disabled,1: FIFO Debug Access is enabled"
group.long 0xC0C++0x03
line.long 0x00 "MTL_DBG_STS,The FIFO Debug Status register contains the status of FIFO debug access"
hexmask.long.tbyte 0x00 15.--31. 1. "LOCR,Remaining Locations in the FIFO - Slave Access Mode: This field indicates the space available in the selected FIFO"
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bitfld.long 0x00 9. "STSI,Transmit Status Available Interrupt Status When set this bit indicates that the Slave mode Tx packet is transmitted and the status is available in Tx Status FIFO" "0: Transmit Status Available Interrupt Status..,1: Transmit Status Available Interrupt Status.."
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bitfld.long 0x00 8. "PKTI,Receive Packet Available Interrupt Status When set this bit indicates that MAC layer has written the EOP of received packet to the Rx FIFO" "0: Receive Packet Available Interrupt Status not..,1: Receive Packet Available Interrupt Status.."
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rbitfld.long 0x00 3.--4. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Read operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid"
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rbitfld.long 0x00 1.--2. "PKTSTATE,Encoded Packet State This field is used to get the control or status information of the selected FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP"
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rbitfld.long 0x00 0. "FIFOBUSY,FIFO Busy When set this bit indicates that a FIFO operation is in progress in the MAC and content of the following fields is not valid: - All other fields of this register - All fields of the MTL_FIFO_Debug_Data register" "0: FIFO Busy not detected,1: FIFO Busy detected"
group.long 0xC10++0x03
line.long 0x00 "MTL_FIFO_Debug_Data,The FIFO Debug Data register contains the data to be written to or read from the FIFOs"
hexmask.long 0x00 0.--31. 1. "FDBGDATA,FIFO Debug Data During debug or slave access write operation this field contains the data to be written to the Tx FIFO Rx FIFO or TSO FIFO"
rgroup.long 0xC20++0x03
line.long 0x00 "MTL_Interrupt_Status,The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC"
bitfld.long 0x00 23. "MTLPIS,MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block" "0: MTL Rx Parser Interrupt status not detected,1: MTL Rx Parser Interrupt status detected"
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bitfld.long 0x00 18. "ESTIS,EST (TAS- 802" "0: EST (TAS- 802.1Qbv) Interrupt status not..,1: EST (TAS- 802.1Qbv) Interrupt status detected"
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bitfld.long 0x00 17. "DBGIS,Debug Interrupt status This bit indicates an interrupt event during the slave access" "0: Debug Interrupt status not detected,1: Debug Interrupt status detected"
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bitfld.long 0x00 1. "Q1IS,Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1" "0: Queue 1 Interrupt status not detected,1: Queue 1 Interrupt status detected"
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bitfld.long 0x00 0. "Q0IS,Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0" "0: Queue 0 Interrupt status not detected,1: Queue 0 Interrupt status detected"
group.long 0xC30++0x03
line.long 0x00 "MTL_RxQ_DMA_Map0,The Receive Queue and DMA Channel Mapping 0 register is reserved in EQOS-CORE and EQOS-MTL configurations"
bitfld.long 0x00 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 1 disabled for DA-based DMA Channel..,1: Queue 1 enabled for DA-based DMA Channel.."
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bitfld.long 0x00 8. "Q1MDMACH,Queue 1 Mapped to DMA Channel This field controls the routing of the received packet in Queue 1 to the DMA channel" "0: DMA Channel,1: DMA Channel"
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bitfld.long 0x00 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 0 disabled for DA-based DMA Channel..,1: Queue 0 enabled for DA-based DMA Channel.."
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bitfld.long 0x00 0. "Q0MDMACH,Queue 0 Mapped to DMA Channel This field controls the routing of the packet received in Queue 0 to the DMA channel" "0: DMA Channel,1: DMA Channel"
group.long 0xC40++0x03
line.long 0x00 "MTL_TBS_CTRL,This register controls the operation of Time Based Scheduling"
hexmask.long.tbyte 0x00 8.--31. 1. "LEOS,Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the Launch time to compute the Launch Expiry time"
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bitfld.long 0x00 4.--6. "LEGOS,Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1. "LEOV,Launch Expiry Offset Valid When set indicates the LEOS field is valid" "0: LEOS field is invalid,1: LEOS field is valid"
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bitfld.long 0x00 0. "ESTM,EST offset Mode When this bit is set the Launch Time value used in Time Based Scheduling is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the current list" "0: EST offset Mode is disabled,1: EST offset Mode is enabled"
group.long 0xC50++0x03
line.long 0x00 "MTL_EST_Control,This register controls the operation of Enhancements to Scheduled Transmission (IEEE802.1Qbv)"
hexmask.long.byte 0x00 24.--31. 1. "PTOV,PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds"
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hexmask.long.word 0x00 12.--23. 1. "CTOV,Current Time Offset Value Provides a 12 bit time offset value in nanosecond that is added to the current time to compensate for all the implementation pipeline delays such as the CDC sync delay buffering delays data path delays and so on"
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bitfld.long 0x00 8.--10. "TILS,Time Interval Left Shift Amount This field provides the left shift amount for the programmed Time Interval values used in the Gate Control Lists" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "LCSE,Loop Count to report Scheduling Error Programmable number of GCL list iterations before reporting an HLBS error defined in EST_Status register" "0: 4 iterations,1: 8 iterations,2: 16 iterations,3: 32 iterations"
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bitfld.long 0x00 5. "DFBS,Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due to not getting scheduled (HLBS field of EST_Status register) after 4 8 16 32 (based on LCSE field of this register) GCL iterations are dropped" "0: Do not Drop Frames causing Scheduling Error,1: Drop Frames causing Scheduling Error"
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bitfld.long 0x00 4. "DDBF,Do not Drop frames during Frame Size Error When set frames are not be dropped during Head-of-Line blocking due to Frame Size Error (HLBF field of EST_Status register)" "0: Drop frames during Frame Size Error,1: Do not Drop frames during Frame Size Error"
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bitfld.long 0x00 3. "QHLBF,Quick Assertion of HLBF Error When set Time Window for Head-of-Line blocking due to Frame Size Error is 1 to 2 loop count of GCL list" "0: Disable Quick assertion of HLBF error,1: Quick Assertion of HLBF Error"
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bitfld.long 0x00 1. "SSWL,Switch to S/W owned list When set indicates that the software has programmed that list that it currently owns (SWOL) and the hardware should switch to the new list based on the new BTR" "0: Switch to S/W owned list is disabled,1: Switch to S/W owned list is enabled"
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bitfld.long 0x00 0. "EEST,Enable EST When reset the gate control list processing is halted and all gates are assumed to be in Open state" "0: EST is disabled,1: EST is enabled"
group.long 0xC54++0x03
line.long 0x00 "MTL_EST_Ext_Control,This register indicates the number of Overhead bytes for EST related scheduling"
bitfld.long 0x00 0.--5. "OVHD,Overhead Bytes Value This field indicates the fixed overhead for every packet to account for EST Scheduler Delay IPG or EIPG and Preamble bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC58++0x03
line.long 0x00 "MTL_EST_Status,This register provides Status related to Enhancements to Scheduled Transmission (IEEE802.1Qbv)"
rbitfld.long 0x00 16.--19. "CGSN,Current GCL Slot Number Indicates the slot number of the GCL list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 8.--15. 1. "BTRL,BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + (N * New Cycle Time) becomes true"
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rbitfld.long 0x00 7. "SWOL,S/W owned list When '0' indicates Gate control list number 0 is owned by software and when 1 indicates the Gate Control list 1 is owned by the software" "0: Gate control list number 0 is owned by software,1: Gate control list number 1 is owned by software"
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bitfld.long 0x00 4. "CGCE,Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the Cycle Time (CTR) is less than or equal to the programmed Time Interval (TI) value after the optional Left Shifting" "0: Constant Gate Control Error not detected,1: Constant Gate Control Error detected"
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rbitfld.long 0x00 3. "HLBS,Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration and get scheduled even after 4 iterations of the GCL" "0: Head-Of-Line Blocking due to Scheduling not..,1: Head-Of-Line Blocking due to Scheduling.."
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rbitfld.long 0x00 2. "HLBF,Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or equal to the duration needed for frame size (or frame fragment.." "0: Head-Of-Line Blocking due to Frame Size not..,1: Head-Of-Line Blocking due to Frame Size.."
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bitfld.long 0x00 1. "BTRE,BTR Error When 1 indicates a programming error in the BTR of SWOL where the programmed value is less than current time" "0: BTR Error not detected,1: BTR Error detected"
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bitfld.long 0x00 0. "SWLC,Switch to S/W owned list Complete When 1 indicates the hardware has successfully switched to the SWOL and the SWOL bit has been updated to that effect" "0: Switch to S/W owned list Complete not detected,1: Switch to S/W owned list Complete detected"
group.long 0xC60++0x03
line.long 0x00 "MTL_EST_Sch_Error,This register provides the One Hot encoded Queue Numbers that are having the Scheduling related error (timeout)"
bitfld.long 0x00 0.--1. "SEQN,Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced error/timeout described in HLBS field of status register" "0,1,2,3"
group.long 0xC64++0x03
line.long 0x00 "MTL_EST_Frm_Size_Error,This register provides the One Hot encoded Queue Numbers that are having the Frame Size related error"
bitfld.long 0x00 0.--1. "FEQN,Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced error described in HLBF field of status register" "0,1,2,3"
rgroup.long 0xC68++0x03
line.long 0x00 "MTL_EST_Frm_Size_Capture,This register captures the Frame Size and Queue Number of the first occurrence of the Frame Size related error"
bitfld.long 0x00 16. "HBFQ,Queue Number of HLBF Captures the binary value of the of the first Queue (number) experiencing HLBF error (see HLBF field of status register)" "0,1"
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hexmask.long.word 0x00 0.--14. 1. "HBFS,Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number indicated in HBFQ field of this register"
group.long 0xC70++0x03
line.long 0x00 "MTL_EST_Intr_Enable,This register implements the Interrupt Enable bits for the various events that generate an interrupt"
bitfld.long 0x00 4. "CGCE,Interrupt Enable for CGCE When set generates interrupt when the Constant Gate Control Error occurs and is indicated in the status" "0: Interrupt for CGCE is disabled,1: Interrupt for CGCE is enabled"
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bitfld.long 0x00 3. "IEHS,Interrupt Enable for HLBS When set generates interrupt when the Head-of-Line Blocking due to Scheduling issue and is indicated in the status" "0: Interrupt for HLBS is disabled,1: Interrupt for HLBS is enabled"
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bitfld.long 0x00 2. "IEHF,Interrupt Enable for HLBF When set generates interrupt when the Head-of-Line Blocking due to Frame Size error occurs and is indicated in the status" "0: Interrupt for HLBF is disabled,1: Interrupt for HLBF is enabled"
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bitfld.long 0x00 1. "IEBE,Interrupt Enable for BTR Error When set generates interrupt when the BTR Error occurs and is indicated in the status" "0: Interrupt for BTR Error is disabled,1: Interrupt for BTR Error is enabled"
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bitfld.long 0x00 0. "IECC,Interrupt Enable for Switch List When set generates interrupt when the configuration change is successful and the hardware has switched to the new list" "0: Interrupt for Switch List is disabled,1: Interrupt for Switch List is enabled"
group.long 0xC80++0x03
line.long 0x00 "MTL_EST_GCL_Control,This register provides the control information for reading/writing to the Gate Control lists"
bitfld.long 0x00 23. "ESTEIEC,ECC Inject Error Control for EST Memory When ESTEIEE or ESTEIAEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: Insert 2 bit errors"
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bitfld.long 0x00 22. "ESTEIAEE,EST ECC Inject Address Error Enable When set along with EEST bit of MTL_EST_Control register enables the ECC address error injection feature" "0: EST ECC Inject Address Error is disabled,1: EST ECC Inject Address Error is enabled"
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bitfld.long 0x00 21. "ESTEIEE,EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_Control register enables the ECC error injection feature" "0: EST ECC Inject Error is disabled,1: EST ECC Inject Error is enabled"
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hexmask.long.byte 0x00 8.--15. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is 0 )"
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bitfld.long 0x00 5. "DBGB,Debug Mode Bank Select When set to 0 indicates R/W in debug mode should be directed to Bank 0 (GCL0 and corresponding Time related registers)" "0: R/W in debug mode should be directed to Bank 0,1: R/W in debug mode should be directed to Bank 1"
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bitfld.long 0x00 4. "DBGM,Debug Mode When set to 1 indicates R/W in debug mode where the memory bank (for GCL and Time related registers) is explicitly provided by DBGB value when set to 0 SWOL bit is used to determine which bank to use" "0: Debug Mode is disabled,1: Debug Mode is enabled"
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bitfld.long 0x00 2. "GCRR,Gate Control Related Registers When set to 1 indicates the R/W access is for the GCL related registers (BTR CTR TER LLR) whose address is provided by GCRA" "0: Gate Control Related Registers are disabled,1: Gate Control Related Registers are enabled"
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bitfld.long 0x00 1. "R1W0,Read '1' Write '0'" "0: Write Operation,1: Read Operation"
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bitfld.long 0x00 0. "SRWO,Start Read/Write Op" "0: Start Read/Write Op disabled,1: Start Read/Write Op enabled"
group.long 0xC84++0x03
line.long 0x00 "MTL_EST_GCL_Data,This register holds the read data or write data in case of reads and writes respectively"
hexmask.long 0x00 0.--31. 1. "GCD,Gate Control Data The data corresponding to the address selected in the GCL_Control register"
group.long 0xC90++0x03
line.long 0x00 "MTL_FPE_CTRL_STS,This register controls the operation of and provides status for Frame Preemption (IEEE802.1Qbu/802.3br)"
rbitfld.long 0x00 28. "HRS,Hold/Release Status" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was.."
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bitfld.long 0x00 8.--9. "PEC,Preemption Classification When set indicates the corresponding Queue must be classified as preemptable when '0' Queue is classified as express" "0,1,2,3"
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bitfld.long 0x00 0.--1. "AFSZ,Additional Fragment Size used to indicate in units of 64 bytes the minimum number of bytes over 64 bytes required in non-final fragments of preempted frames" "0,1,2,3"
group.long 0xC94++0x03
line.long 0x00 "MTL_FPE_Advance,This register holds the Hold and Release Advance time"
hexmask.long.word 0x00 16.--31. 1. "RADV,Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE to the MAC and the MAC being ready to resume transmission of preemptable frames in the absence of there being any express frames available for transmission"
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hexmask.long.word 0x00 0.--15. 1. "HADV,Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of transmission or any preemptable frames that are queued for transmission"
group.long 0xCA0++0x03
line.long 0x00 "MTL_RXP_Control_Status,The MTL_RXP_Control_Status register establishes the operating mode of Rx Parser and provides some status"
rbitfld.long 0x00 31. "RXPI,RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State and waiting for a new packet for processing" "0: RX Parser not in Idle state,1: RX Parser in Idle state"
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bitfld.long 0x00 30. "ELIRS,Enable Last Instruction in RX Status When this bit is set RDES2[31:16] indicates the index of the last instruction executed in Rx Parse when set to 0 indicates MAC filter status" "0,1"
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bitfld.long 0x00 16.--21. "NPE,Number of parsable entries in the Instruction table This control indicates the number of parsable entries in the Instruction Memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "NVE,Number of valid entry address/index in the Instruction table This control indicates the number of valid entries address/index in the Instruction Memory (i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xCA4++0x03
line.long 0x00 "MTL_RXP_Interrupt_Control_Status,The MTL_RXP_Interrupt_Control_Status registers provides enable control for the interrupts and provides interrupt status"
bitfld.long 0x00 19. "PDRFIE,Packet Drop due to RF Interrupt Enable When this bit is set the PDRFIS interrupt is enabled" "0: Packet Drop due to RF Interrupt is disabled,1: Packet Drop due to RF Interrupt is enabled"
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bitfld.long 0x00 18. "FOOVIE,Frame Offset Overflow Interrupt Enable When this bit is set the FOOVIS interrupt is enabled" "0: Frame Offset Overflow Interrupt is disabled,1: Frame Offset Overflow Interrupt is enabled"
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bitfld.long 0x00 17. "NPEOVIE,Number of Parsable Entries Overflow Interrupt Enable When this bit is set the NPEOVIS interrupt is enabled" "0: Number of Parsable Entries Overflow Interrupt..,1: Number of Parsable Entries Overflow Interrupt.."
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bitfld.long 0x00 16. "NVEOVIE,Number of Valid Entries Overflow Interrupt Enable When this bit is set the NVEOVIS interrupt is enabled" "0: Number of Valid Entries Overflow Interrupt is..,1: Number of Valid Entries Overflow Interrupt is.."
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bitfld.long 0x00 3. "PDRFIS,Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the packet by setting RF=1 in the instruction memory then this bit is set to 1" "0: Packet Dropped due to RF Interrupt Status not..,1: Packet Dropped due to RF Interrupt Status.."
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bitfld.long 0x00 2. "FOOVIS,Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's 'Frame Offset' found to be more than EOF offset then then this bit is set" "0: Frame Offset Overflow Interrupt Status not..,1: Frame Offset Overflow Interrupt Status detected"
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bitfld.long 0x00 1. "NPEOVIS,Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the number of parsed entries found to be more than NPE[] (Number of Parseable Entries in MTL_RXP_Control register) then this bit is set to 1" "0: Number of Parsable Entries Overflow Interrupt..,1: Number of Parsable Entries Overflow Interrupt.."
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bitfld.long 0x00 0. "NVEOVIS,Number of Valid Entry Address/Index Overflow Interrupt Status While parsing if the Instruction address found to be more than NVE (Number of Valid Entry Address/index in MTL_RXP_Control register) then this bit is set to 1" "0: Number of Valid Entries Overflow Interrupt..,1: Number of Valid Entries Overflow Interrupt.."
rgroup.long 0xCA8++0x03
line.long 0x00 "MTL_RXP_Drop_Cnt,The MTL_RXP_Drop_Cnt register provides the drop count of Rx Parser initiated drops"
bitfld.long 0x00 31. "RXPDCOVF,Rx Parser Drop Counter Overflow Bit When set this bit indicates that the MTL_RXP_Drop_cnt (RXPDC) Counter field crossed the maximum limit" "0: Rx Parser Drop count overflow not occurred,1: Rx Parser Drop count overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPDC,Rx Parser Drop count This 31-bit counter is implemented when a Rx Parser Drops a packet due to RF =1"
rgroup.long 0xCAC++0x03
line.long 0x00 "MTL_RXP_Error_Cnt,The MTL_RXP_Error_Cnt register provides the Rx Parser related error occurrence count"
bitfld.long 0x00 31. "RXPECOVF,Rx Parser Error Counter Overflow Bit When set this bit indicates that the MTL_RXP_Error_cnt (RXPEC) Counter field crossed the maximum limit" "0: Rx Parser Error count overflow not occurred,1: Rx Parser Error count overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPEC,Rx Parser Error count This 31-bit counter is implemented when a Rx Parser encounters following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry address > EOF data entry address The counter is cleared when the.."
group.long 0xCB0++0x03
line.long 0x00 "MTL_RXP_Indirect_Acc_Control_Status,The MTL_RXP_Indirect_Acc_Control_Status register provides the Indirect Access control and status for Rx Parser memory"
bitfld.long 0x00 31. "STARTBUSY,FRP Instruction Table Access Busy - Set to 1 by the software indicates to start the Read/Write operation from/to the Rx Parser Memory" "0: hardware not busy,1: hardware is busy (Read/Write operation.."
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bitfld.long 0x00 22. "RXPEIEC,ECC Inject Error Control for Rx Parser Memory When RXPEIEE or RXPEIAEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: Insert 2 bit errors"
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bitfld.long 0x00 21. "RXPEIAEE,ECC Inject Address Error Enable for Rx Parser Memory" "0: ECC Inject Address Error for Rx Parser Memory..,1: ECC Inject Address Error for Rx Parser Memory.."
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bitfld.long 0x00 20. "RXPEIEE,ECC Inject Error Enable for Rx Parser Memory" "0: ECC Inject Error for Rx Parser Memory is..,1: ECC Inject Error for Rx Parser Memory is.."
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bitfld.long 0x00 16. "WRRDN,Read Write Control" "0: Read operation to the Rx Parser Memory,1: Write operation to the Rx Parser Memory"
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hexmask.long.byte 0x00 0.--7. 1. "ADDR,FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table"
rgroup.long 0xCB4++0x03
line.long 0x00 "MTL_RXP_Indirect_Acc_Data,The MTL_RXP_Indirect_Acc_Data registers holds the data associated to Indirect Access to Rx Parser memory"
hexmask.long 0x00 0.--31. 1. "DATA,FRP Instruction Table Write/Read Data Software should write this register before issuing any write command"
rgroup.long 0xCB8++0x03
line.long 0x00 "MTL_RXP_Bypass_Cnt,The MTL_RXP_Bypass_Cnt register provides the bypass count of Rx Parser"
bitfld.long 0x00 31. "RXPBCOF,Rx Parser bypass Counter Overflow Bit When set this bit indicates that the MTL_RXP_Bypass_cnt (RXPBC) Counter field crossed the maximum limit" "0: Rx Parser Bypass count overflow not occurred,1: Rx Parser Bypass count overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPBC,Rx Parser Bypass count This 31-bit counter is implemented when a Rx Parser bypass a packet due to AF=1 and RF =1"
group.long 0xCC0++0x03
line.long 0x00 "MTL_ECC_Control,The MTL_ECC_Control register establishes the operating mode of ECC related to MTL memories"
bitfld.long 0x00 8. "MEEAO,MTL ECC Error Address Status Over-ride" "0: MTL ECC Error Address Status Over-ride is..,1: MTL ECC Error Address Status Over-ride is.."
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bitfld.long 0x00 3. "MRXPEE,MTL Rx Parser ECC Enable" "0: MTL Rx Parser ECC is disabled,1: MTL Rx Parser ECC is enabled"
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bitfld.long 0x00 2. "MESTEE,MTL EST ECC Enable" "0: MTL EST ECC is disabled,1: MTL EST ECC is enabled"
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bitfld.long 0x00 1. "MRXEE,MTL Rx FIFO ECC Enable" "0: MTL Rx FIFO ECC is disabled,1: MTL Rx FIFO ECC is enabled"
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bitfld.long 0x00 0. "MTXEE,MTL Tx FIFO ECC Enable" "0: MTL Tx FIFO ECC is disabled,1: MTL Tx FIFO ECC is enabled"
rgroup.long 0xCC4++0x03
line.long 0x00 "MTL_Safety_Interrupt_Status,The MTL_Safety_Interrupt_Status registers provides Safety interrupt status"
bitfld.long 0x00 1. "MEUIS,MTL ECC Uncorrectable error Interrupt Status This bit indicates that an uncorrectable error interrupt event in the MTL ECC safety feature" "0: MTL ECC Uncorrectable error Interrupt Status..,1: MTL ECC Uncorrectable error Interrupt Status.."
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bitfld.long 0x00 0. "MECIS,MTL ECC Correctable error Interrupt Status This bit indicates that a correctable error interrupt event in the MTL ECC safety feature" "0: MTL ECC Correctable error Interrupt Status..,1: MTL ECC Correctable error Interrupt Status.."
group.long 0xCC8++0x03
line.long 0x00 "MTL_ECC_Interrupt_Enable,The MTL_ECC_Interrupt_Enable register provides enable bits for the ECC interrupts"
bitfld.long 0x00 12. "RPCEIE,Rx Parser memory Correctable Error Interrupt Enable When set generates an interrupt when an uncorrectable error is detected at the Rx Parser memory interface" "0: Rx Parser memory Correctable Error Interrupt..,1: Rx Parser memory Correctable Error Interrupt.."
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bitfld.long 0x00 8. "ECEIE,EST memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL EST memory interface" "0: EST memory Correctable Error Interrupt is..,1: EST memory Correctable Error Interrupt is.."
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bitfld.long 0x00 4. "RXCEIE,Rx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Rx memory interface" "0: Rx memory Correctable Error Interrupt is..,1: Rx memory Correctable Error Interrupt is.."
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bitfld.long 0x00 0. "TXCEIE,Tx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Tx memory interface" "0: Tx memory Correctable Error Interrupt is..,1: Tx memory Correctable Error Interrupt is.."
group.long 0xCCC++0x03
line.long 0x00 "MTL_ECC_Interrupt_Status,The MTL_ECC_Interrupt_Status register provides MTL ECC Interrupt Status"
bitfld.long 0x00 14. "RPUES,Rx Parser memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at Rx Parser memory interface" "0: Rx Parser memory Uncorrectable Error Status..,1: Rx Parser memory Uncorrectable Error Status.."
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bitfld.long 0x00 13. "RPAMS,MTL Rx Parser memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of Rx Parser memory" "0: MTL Rx Parser memory Address Mismatch Status..,1: MTL Rx Parser memory Address Mismatch Status.."
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bitfld.long 0x00 12. "RPCES,MTL Rx Parser memory Correctable Error Status This bit when set indicates that correctable error is detected at RX Parser memory interface" "0: MTL Rx Parser memory Correctable Error Status..,1: MTL Rx Parser memory Correctable Error Status.."
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bitfld.long 0x00 10. "EUES,MTL EST memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at MTL EST memory interface" "0: MTL EST memory Uncorrectable Error Status not..,1: MTL EST memory Uncorrectable Error Status.."
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bitfld.long 0x00 9. "EAMS,MTL EST memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of MTL EST memory" "0: MTL EST memory Address Mismatch Status not..,1: MTL EST memory Address Mismatch Status detected"
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bitfld.long 0x00 8. "ECES,MTL EST memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL EST memory" "0: MTL EST memory Correctable Error Status not..,1: MTL EST memory Correctable Error Status.."
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bitfld.long 0x00 6. "RXUES,MTL Rx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL Rx memory interface" "0: MTL Rx memory Uncorrectable Error Status not..,1: MTL Rx memory Uncorrectable Error Status.."
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bitfld.long 0x00 5. "RXAMS,MTL Rx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Rx memory" "0: MTL Rx memory Address Mismatch Status not..,1: MTL Rx memory Address Mismatch Status detected"
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bitfld.long 0x00 4. "RXCES,MTL Rx memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL Rx memory" "0: MTL Rx memory correctable Error Status not..,1: MTL Rx memory correctable Error Status detected"
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bitfld.long 0x00 2. "TXUES,MTL Tx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL TX memory interface" "0: MTL Tx memory Uncorrectable Error Status not..,1: MTL Tx memory Uncorrectable Error Status.."
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bitfld.long 0x00 1. "TXAMS,MTL Tx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Tx memory" "0: MTL Tx memory Address Mismatch Status not..,1: MTL Tx memory Address Mismatch Status detected"
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bitfld.long 0x00 0. "TXCES,MTL Tx memory Correctable Error Status This bit when set indicates that a correctable error is detected at the MTL Tx memory" "0: MTL Tx memory Correctable Error Status not..,1: MTL Tx memory Correctable Error Status detected"
group.long 0xCD0++0x03
line.long 0x00 "MTL_ECC_Err_Sts_Rctl,The MTL_ECC_Err_Sts_Rctl register establishes the control for ECC Error status capture"
bitfld.long 0x00 5. "CUES,Clear Uncorrectable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's uncorrectable error address and uncorrectable error count values are cleared upon reading" "0: Clear Uncorrectable Error Status not detected,1: Clear Uncorrectable Error Status detected"
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bitfld.long 0x00 4. "CCES,Clear Correctable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's correctable error address and correctable error count values are cleared upon reading" "0: Clear Correctable Error Status not detected,1: Clear Correctable Error Status detected"
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bitfld.long 0x00 1.--3. "EMS,MTL ECC Memory Selection When EESRE bit of this register is set this field indicates which memory's error status value to be read" "0: MTL Tx memory,1: MTL Rx memory,2: MTL EST memory,3: MTL Rx Parser memory,4: DMA TSO memory,5: DMA DCACHE memory,?..."
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bitfld.long 0x00 0. "EESRE,MTL ECC Error Status Read Enable When this bit is set based on the EMS field of this register the respective memory's error status values are captured as described: - The correctable and uncorrectable error count values are captured into.." "0: MTL ECC Error Status Read is disabled,1: MTL ECC Error Status Read is enabled"
rgroup.long 0xCD4++0x03
line.long 0x00 "MTL_ECC_Err_Addr_Status,The MTL_ECC_Err_Addr_Status register provides the memory addresses for the correctable and uncorrectable errors"
hexmask.long.word 0x00 16.--31. 1. "EUEAS,MTL ECC Uncorrectable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which an uncorrectable error or address mismatch is detected"
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hexmask.long.word 0x00 0.--15. 1. "ECEAS,MTL ECC Correctable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which a correctable error is detected"
rgroup.long 0xCD8++0x03
line.long 0x00 "MTL_ECC_Err_Cntr_Status,The MTL_ECC_Err_Cntr_Status register provides ECC Error count for Correctable and uncorrectable errors"
bitfld.long 0x00 16.--19. "EUECS,MTL ECC Uncorrectable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's uncorrectable error count value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "ECECS,MTL ECC Correctable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's correctable error count value"
group.long 0xCE0++0x03
line.long 0x00 "MTL_DPP_Control,The MTL_DPP_Control establishes the operating mode of Data Parity protection and error injection"
bitfld.long 0x00 15. "IPEMRWC,IPEMRWC" "0: Insert Parity error in MTL RWC data parity..,1: Insert Parity error in MTL RWC data parity.."
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bitfld.long 0x00 14. "IPEMTFC,Insert Parity error in MAC TFC data parity checker When set to 1 parity/data bit of first valid input parity/data of the MAC TFC data parity checker (or at PC11 as shown in Transmit Data path parity protection diagram) is flipped" "0: Insert Parity error in MAC TFC data parity..,1: Insert Parity error in MAC TFC data parity.."
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bitfld.long 0x00 13. "IPEMTBU,Insert Parity error in MTL RWC data parity checker When set to 1 parity/data bit of first valid input parity/data of the MTL RWC data parity checker (or at PC12 as shown in Receive data path parity protection diagram) is flipped" "0: Insert Parity error in MAC TBU data parity..,1: Insert Parity error in MAC TBU data parity.."
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bitfld.long 0x00 9. "IPERID,Insert Parity Error in RX Interface Data parity checker When set to 1 parity/data bit of first valid input parity/data of the RX Interface Data parity checker is (or at PC6 as shown in Receive data path parity protection diagram) flipped" "0: Insert Parity Error in Rx Interface Data..,1: Insert Parity Error in Rx Interface Data.."
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bitfld.long 0x00 8. "IPEMTS,Insert Parity Error in MTL Tx Status FIFO parity checker When set to 1 parity/data bit of first valid input parity/data of the MTL Tx Status FIFO parity checker (or at PC5 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in MTL TX Status FIFO..,1: Insert Parity Error in MTL TX Status FIFO.."
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bitfld.long 0x00 7. "IPEMTF,Insert Parity Error in MTL Tx FIFO write data parity checker When set to 1 parity/data bit of first valid input parity/data of the MTL Tx FIFO write data parity checker (or at PC4 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in MTL Tx FIFO write data..,1: Insert Parity Error in MTL Tx FIFO write data.."
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bitfld.long 0x00 6. "IPETRD,Insert Parity Error in DMA Tx/Rx Descriptor parity checker When set to 1 parity/data bit of first valid input parity/data of the DMA Tx/Rx Descriptor parity checker (or at PC3 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in DMA Tx/Rx Descriptor..,1: Insert Parity Error in DMA Tx/Rx Descriptor.."
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rbitfld.long 0x00 1. "OPE,Odd Parity Enable When set to 1 enables odd parity protection on all the external interfaces and when set to 0 enables even parity protection on all the external interfaces" "0: Odd Parity is disabled,1: Odd Parity is enabled"
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bitfld.long 0x00 0. "EDPP,Enable Data path Parity Protection When set to 1 enables the parity protection for EQOS datapath by generating and checking the parity on EQOS datapath" "0: Data path Parity Protection is disabled,1: Data path Parity Protection is enabled"
group.long 0xCE4++0x03
line.long 0x00 "MTL_DPP_ECC_EIC,The MTL_DPP_ECC_EIC establishes the operating mode of ECC/DPP error injection"
bitfld.long 0x00 16. "EIM,Error Injection Mode When it set to 0 indicate error injection on data When it set to 1 indicate error injection on ECC/Parity bits(need to check the address error injection mode is disabled)" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "BLEI,Bit Location of error injection This field indicates the bit location of DPP/ECC error injection determination of error in Parity/ECC bits or Data (being protected) depends on the Error Injection Mode(EIM field)"
group.long 0xD00++0x03
line.long 0x00 "MTL_TxQ0_Operation_Mode,The Queue 0 Transmit Operation Mode register establishes the Transmit queue operating modes and commands"
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: M_32BYTES,1: M_64BYTES,2: M_96BYTES,3: M_128BYTES,4: M_192BYTES,5: M_256BYTES,6: M_384BYTES,7: M_512BYTES"
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bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
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bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
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bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
rgroup.long 0xD04++0x03
line.long 0x00 "MTL_TxQ0_Underflow,The Queue 0 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush"
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
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hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
rgroup.long 0xD08++0x03
line.long 0x00 "MTL_TxQ0_Debug,The Queue 0 Transmit Debug register gives the debug status of various blocks related to the Transmit queue"
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
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bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
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bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
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bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
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bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
rgroup.long 0xD14++0x03
line.long 0x00 "MTL_TxQ0_ETS_Status,The Queue 0 ETS Status register provides the average traffic transmitted in Queue 0"
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
group.long 0xD18++0x03
line.long 0x00 "MTL_TxQ0_Quantum_Weight,The Queue 0 Quantum or Weights register contains the quantum value for Deficit Weighted Round Robin (DWRR) weights for the Weighted Round Robin (WRR) and Weighted Fair Queuing (WFQ) for Queue 0"
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0 traffic this field contains the quantum value in bytes to be added to credit during every queue scanning cycle"
group.long 0xD2C++0x03
line.long 0x00 "MTL_Q0_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 0 interrupts"
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
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bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
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bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
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bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
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bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
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bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
group.long 0xD30++0x03
line.long 0x00 "MTL_RxQ0_Operation_Mode,The Queue 0 Receive Operation Mode register establishes the Receive queue operating modes and command"
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
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bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
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bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
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bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
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bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
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bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
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bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: M_64BYTE,1: M_32BYTE,2: M_96BYTE,3: M_128BYTE"
rgroup.long 0xD34++0x03
line.long 0x00 "MTL_RxQ0_Missed_Packet_Overflow_Cnt,The Queue 0 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow"
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
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hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
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bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
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hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
rgroup.long 0xD38++0x03
line.long 0x00 "MTL_RxQ0_Debug,The Queue 0 Receive Debug register gives the debug status of various blocks related to the Receive queue"
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
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bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
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bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
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bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
group.long 0xD3C++0x03
line.long 0x00 "MTL_RxQ0_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application"
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
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bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
group.long 0xD40++0x03
line.long 0x00 "MTL_TxQ1_Operation_Mode,The Queue 1 Transmit Operation Mode register establishes the Transmit queue operating modes and commands"
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: M_32BYTES,1: M_64BYTES,2: M_96BYTES,3: M_128BYTES,4: M_192BYTES,5: M_256BYTES,6: M_384BYTES,7: M_512BYTES"
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bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
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bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
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bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
rgroup.long 0xD44++0x03
line.long 0x00 "MTL_TxQ1_Underflow,The Queue 1 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush"
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
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hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
rgroup.long 0xD48++0x03
line.long 0x00 "MTL_TxQ1_Debug,The Queue 1 Transmit Debug register gives the debug status of various blocks related to the Transmit queue"
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
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bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
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bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
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bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
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bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
group.long 0xD50++0x03
line.long 0x00 "MTL_TxQ1_ETS_Control,The Queue ETS Control register controls the enhanced transmission selection operation"
bitfld.long 0x00 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH(#i)_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "0: M_1_SLOT,1: M_2_SLOT,2: M_4_SLOT,3: M_8_SLOT,4: M_16_SLOT,?..."
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bitfld.long 0x00 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled"
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bitfld.long 0x00 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled"
rgroup.long 0xD54++0x03
line.long 0x00 "MTL_TxQ1_ETS_Status,The Queue 1 ETS Status register provides the average traffic transmitted in Queue 1"
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
group.long 0xD58++0x03
line.long 0x00 "MTL_TxQ1_Quantum_Weight,The Queue 1 idleSlopeCredit Quantum or Weights register provides the average traffic transmitted in Queue 1"
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1"
group.long 0xD5C++0x03
line.long 0x00 "MTL_TxQ1_SendSlopeCredit,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue"
hexmask.long.word 0x00 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1"
group.long 0xD60++0x03
line.long 0x00 "MTL_TxQ1_HiCredit,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue"
hexmask.long 0x00 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm"
group.long 0xD64++0x03
line.long 0x00 "MTL_TxQ1_LoCredit,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue"
hexmask.long 0x00 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm"
group.long 0xD6C++0x03
line.long 0x00 "MTL_Q1_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 1 interrupts"
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
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bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
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bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
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bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
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bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
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bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
group.long 0xD70++0x03
line.long 0x00 "MTL_RxQ1_Operation_Mode,The Queue 1 Receive Operation Mode register establishes the Receive queue operating modes and command"
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
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bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
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bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
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bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
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bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
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bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
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bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: M_64BYTE,1: M_32BYTE,2: M_96BYTE,3: M_128BYTE"
rgroup.long 0xD74++0x03
line.long 0x00 "MTL_RxQ1_Missed_Packet_Overflow_Cnt,The Queue 1 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow"
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
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hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
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bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
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hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
rgroup.long 0xD78++0x03
line.long 0x00 "MTL_RxQ1_Debug,The Queue 1 Receive Debug register gives the debug status of various blocks related to the Receive queue"
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
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bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
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bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
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bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
group.long 0xD7C++0x03
line.long 0x00 "MTL_RxQ1_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application"
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
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bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
group.long 0x1000++0x03
line.long 0x00 "DMA_Mode,The Bus Mode register establishes the bus operating modes for the DMA"
bitfld.long 0x00 16.--17. "INTM,Interrupt Mode This field defines the interrupt mode of DWC_ether_qos" "0: See above description,1: See above description,2: See above description,?..."
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bitfld.long 0x00 12.--14. "PR,Priority Ratio These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA" "0: The priority ratio is 1:1,1: The priority ratio is 2:1,2: The priority ratio is 3:1,3: The priority ratio is 4:1,4: The priority ratio is 5:1,5: The priority ratio is 6:1,6: The priority ratio is 7:1,7: The priority ratio is 8:1"
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bitfld.long 0x00 11. "TXPR,Transmit Priority When set this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus or Descriptor reads from DCACHE memory when DWC_EQOS_DCEXT is enabled" "0: Transmit Priority is disabled,1: Transmit Priority is enabled"
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bitfld.long 0x00 9. "ARBC,ARBC is NXP Reserved This field must be set to 0" "0: NXP reserved field disabled,1: NXP reserved field enabled up on NXP request"
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bitfld.long 0x00 2.--4. "TAA,Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for the Transmit side when multiple Tx DMAs are selected" "0: Fixed priority (Channel 0 has the lowest..,1: Weighted Strict Priority (WSP),2: Weighted Round-Robin (WRR),?..."
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bitfld.long 0x00 1. "DA,DMA Tx or Rx Arbitration Scheme This bit specifies the arbitration scheme between the Transmit and Receive paths of all channels" "0: Weighted Round-Robin with Rx,1: Fixed Priority"
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bitfld.long 0x00 0. "SWR,Software Reset When this bit is set the MAC and the DMA controller reset the logic and all internal registers of the DMA MTL and MAC" "0: Software Reset is disabled,1: Software Reset is enabled"
group.long 0x1004++0x03
line.long 0x00 "DMA_SysBus_Mode,The System Bus mode register controls the behavior of the AHB or AXI master"
bitfld.long 0x00 15. "RB,Rebuild INCRx Burst When this bit is set high and the AHB master gets SPLIT RETRY or Early Burst Termination (EBT) response the AHB master interface rebuilds the pending beats of any initiated burst transfer with INCRx and SINGLE transfers" "0: Rebuild INCRx Burst is disabled,1: Rebuild INCRx Burst is enabled"
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bitfld.long 0x00 14. "MB,Mixed Burst When this bit is high and the FB bit is low the AHB master performs undefined bursts transfers (INCR) for burst length of 16 or more" "0: Mixed Burst is disabled,1: Mixed Burst is enabled"
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bitfld.long 0x00 12. "AAL,Address-Aligned Beats When this bit is set to 1 the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels" "0: Address-Aligned Beats is disabled,1: Address-Aligned Beats is enabled"
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bitfld.long 0x00 0. "FB,Fixed Burst Length" "0: Fixed Burst Length is disabled,1: Fixed Burst Length is enabled"
rgroup.long 0x1008++0x03
line.long 0x00 "DMA_Interrupt_Status,The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels MTL queues and the MAC"
bitfld.long 0x00 17. "MACIS,MAC Interrupt Status This bit indicates an interrupt event in the MAC" "0: MAC Interrupt Status not detected,1: MAC Interrupt Status detected"
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bitfld.long 0x00 16. "MTLIS,MTL Interrupt Status This bit indicates an interrupt event in the MTL" "0: MTL Interrupt Status not detected,1: MTL Interrupt Status detected"
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bitfld.long 0x00 1. "DC1IS,DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1" "0: DMA Channel 1 Interrupt Status not detected,1: DMA Channel 1 Interrupt Status detected"
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bitfld.long 0x00 0. "DC0IS,DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0" "0: DMA Channel 0 Interrupt Status not detected,1: DMA Channel 0 Interrupt Status detected"
rgroup.long 0x100C++0x03
line.long 0x00 "DMA_Debug_Status0,The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0-Channel 2 for debugging purpose"
bitfld.long 0x00 20.--23. "TPS1,DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
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bitfld.long 0x00 16.--19. "RPS1,DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
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bitfld.long 0x00 12.--15. "TPS0,DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
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bitfld.long 0x00 8.--11. "RPS0,DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
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bitfld.long 0x00 0. "AXWHSTS,AHB Master Status When high this bit indicates that the AHB master FSMs are in the non-idle state" "0: AXI Master Write Channel or AHB Master Status..,1: AXI Master Write Channel or AHB Master Status.."
group.long 0x1050++0x03
line.long 0x00 "DMA_TBS_CTRL0,This register is used to control the TBS attributes"
hexmask.long.tbyte 0x00 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time"
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bitfld.long 0x00 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid" "0: Fetch Time Offset is invalid,1: Fetch Time Offset is valid"
rgroup.long 0x1080++0x03
line.long 0x00 "DMA_Safety_Interrupt_Status,This register indicates summary (whether error occurred in DMA/MTL/MAC and correctable/uncorrectable) of the Automotive Safety related error interrupts"
bitfld.long 0x00 31. "MCSIS,MAC Safety Uncorrectable Interrupt Status Indicates a uncorrectable Safety related Interrupt is set in the MAC module" "0: MAC Safety Uncorrectable Interrupt Status not..,1: MAC Safety Uncorrectable Interrupt Status.."
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bitfld.long 0x00 29. "MSUIS,MTL Safety Uncorrectable error Interrupt Status This bit indicates an uncorrectable error interrupt event in MTL" "0: MTL Safety Uncorrectable error Interrupt..,1: MTL Safety Uncorrectable error Interrupt.."
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bitfld.long 0x00 28. "MSCIS,MTL Safety Correctable error Interrupt Status This bit indicates a correctable error interrupt event in MTL" "0: MTL Safety Correctable error Interrupt Status..,1: MTL Safety Correctable error Interrupt Status.."
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bitfld.long 0x00 1. "DEUIS,DMA ECC Uncorrectable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature" "0: DMA ECC Uncorrectable error Interrupt Status..,1: DMA ECC Uncorrectable error Interrupt Status.."
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bitfld.long 0x00 0. "DECIS,DMA ECC Correctable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature" "0: DMA ECC Correctable error Interrupt Status..,1: DMA ECC Correctable error Interrupt Status.."
group.long 0x1100++0x03
line.long 0x00 "DMA_CH0_Control,The DMA Channeli Control register specifies the MSS value for segmentation length to skip between two descriptors and also the features such as header splitting and 8xPBL mode"
bitfld.long 0x00 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled"
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bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
group.long 0x1104++0x03
line.long 0x00 "DMA_CH0_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL TCP segmentation and Tx Channel weights"
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
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bitfld.long 0x00 22. "ETIC,Early Transmit Interrupt Control When this bit is set Early Transmit Interrupt (ETI) status is set after completion of transfer of data from buffers of a transmit descriptor in which IOC bit (TDES2[31]) is set" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
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bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
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bitfld.long 0x00 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
group.long 0x1108++0x03
line.long 0x00 "DMA_CH0_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL buffer size and extended status"
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
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bitfld.long 0x00 22. "ERIC,Early Receive Interrupt Control When this bit is set Early Receive Interrupt (ERI) status is set after the completion of every burst transfer of data from the Rx DMA to the buffer" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
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bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
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rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
group.long 0x1114++0x03
line.long 0x00 "DMA_CH0_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list"
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
group.long 0x111C++0x03
line.long 0x00 "DMA_CH0_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list"
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
group.long 0x1120++0x03
line.long 0x00 "DMA_CH0_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor"
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
group.long 0x1128++0x03
line.long 0x00 "DMA_CH0_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor"
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
group.long 0x112C++0x03
line.long 0x00 "DMA_CH0_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring"
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
group.long 0x1130++0x03
line.long 0x00 "DMA_CH0_Rx_Control2,The Channeli Receive Control register controls the Rx features such as Rx Descriptor Ring Length and Alternate Rx Buffer Size"
hexmask.long.byte 0x00 17.--23. 1. "ARBS,Alternate Receive Buffer Size Indicates size in bytes for Buffer 1 when ARBS is programmed to a non-zero value (when split header feature is not enabled)"
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hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
group.long 0x1134++0x03
line.long 0x00 "DMA_CH0_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register"
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
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bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
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bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
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bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
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bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
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bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
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bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
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bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
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bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
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bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
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bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
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bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
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bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
group.long 0x1138++0x03
line.long 0x00 "DMA_CH0_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA"
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
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hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
group.long 0x113C++0x03
line.long 0x00 "DMA_CH0_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path"
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
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bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
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bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
rgroup.long 0x1144++0x03
line.long 0x00 "DMA_CH0_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x114C++0x03
line.long 0x00 "DMA_CH0_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
rgroup.long 0x1154++0x03
line.long 0x00 "DMA_CH0_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x115C++0x03
line.long 0x00 "DMA_CH0_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
group.long 0x1160++0x03
line.long 0x00 "DMA_CH0_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA"
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
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bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
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bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
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bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
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bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
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bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
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bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
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bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
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bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
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bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
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bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
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bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
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bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
rgroup.long 0x1164++0x03
line.long 0x00 "DMA_CH0_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register"
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
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hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register"
rgroup.long 0x1168++0x03
line.long 0x00 "DMA_CH0_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser"
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented when a Rx Parser Accept a packet due to AF =1"
rgroup.long 0x116C++0x03
line.long 0x00 "DMA_CH0_RX_ERI_Cnt,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted"
hexmask.long.word 0x00 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer"
group.long 0x1180++0x03
line.long 0x00 "DMA_CH1_Control,The DMA Channeli Control register specifies the MSS value for segmentation length to skip between two descriptors and also the features such as header splitting and 8xPBL mode"
bitfld.long 0x00 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled"
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bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
group.long 0x1184++0x03
line.long 0x00 "DMA_CH1_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL TCP segmentation and Tx Channel weights"
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
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bitfld.long 0x00 22. "ETIC,Early Transmit Interrupt Control When this bit is set Early Transmit Interrupt (ETI) status is set after completion of transfer of data from buffers of a transmit descriptor in which IOC bit (TDES2[31]) is set" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
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bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
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bitfld.long 0x00 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
group.long 0x1188++0x03
line.long 0x00 "DMA_CH1_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL buffer size and extended status"
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
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bitfld.long 0x00 22. "ERIC,Early Receive Interrupt Control When this bit is set Early Receive Interrupt (ERI) status is set after the completion of every burst transfer of data from the Rx DMA to the buffer" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
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bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
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rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
group.long 0x1194++0x03
line.long 0x00 "DMA_CH1_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list"
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
group.long 0x119C++0x03
line.long 0x00 "DMA_CH1_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list"
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
group.long 0x11A0++0x03
line.long 0x00 "DMA_CH1_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor"
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
group.long 0x11A8++0x03
line.long 0x00 "DMA_CH1_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor"
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
group.long 0x11AC++0x03
line.long 0x00 "DMA_CH1_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring"
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
group.long 0x11B0++0x03
line.long 0x00 "DMA_CH1_Rx_Control2,The Channeli Receive Control register controls the Rx features such as Rx Descriptor Ring Length and Alternate Rx Buffer Size"
hexmask.long.byte 0x00 17.--23. 1. "ARBS,Alternate Receive Buffer Size Indicates size in bytes for Buffer 1 when ARBS is programmed to a non-zero value (when split header feature is not enabled)"
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hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
group.long 0x11B4++0x03
line.long 0x00 "DMA_CH1_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register"
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
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bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
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bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
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bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
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bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
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bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
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bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
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bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
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bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
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bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
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bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
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bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
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bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
group.long 0x11B8++0x03
line.long 0x00 "DMA_CH1_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA"
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
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hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
group.long 0x11BC++0x03
line.long 0x00 "DMA_CH1_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path"
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
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bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
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bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
rgroup.long 0x11C4++0x03
line.long 0x00 "DMA_CH1_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x11CC++0x03
line.long 0x00 "DMA_CH1_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
rgroup.long 0x11D4++0x03
line.long 0x00 "DMA_CH1_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x11DC++0x03
line.long 0x00 "DMA_CH1_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
group.long 0x11E0++0x03
line.long 0x00 "DMA_CH1_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA"
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
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bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
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bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
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bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
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bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
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bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
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bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
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bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
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bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
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bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
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bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
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bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
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bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
rgroup.long 0x11E4++0x03
line.long 0x00 "DMA_CH1_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register"
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
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hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register"
rgroup.long 0x11E8++0x03
line.long 0x00 "DMA_CH1_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser"
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented when a Rx Parser Accept a packet due to AF =1"
rgroup.long 0x11EC++0x03
line.long 0x00 "DMA_CH1_RX_ERI_Cnt,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted"
hexmask.long.word 0x00 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer"
tree.end
tree "GMAC_1"
base ad:0x44080000
group.long 0x00++0x03
line.long 0x00 "MAC_Configuration,The MAC Configuration Register establishes the operating mode of the MAC"
bitfld.long 0x00 31. "ARPEN,ARP Offload Enable When this bit is set the MAC can recognize an incoming ARP request packet and schedules the ARP packet for transmission" "0: ARP Offload is disabled,1: ARP Offload is enabled"
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bitfld.long 0x00 28.--30. "SARC,Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted packets" "0: mti_sa_ctrl_i and ati_sa_ctrl_i input signals..,?,2: Contents of MAC Addr-0 inserted in SA field,3: Contents of MAC Addr-0 replaces SA field,?,?,6: Contents of MAC Addr-1 inserted in SA field,7: Contents of MAC Addr-1 replaces SA field"
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bitfld.long 0x00 27. "IPC,Checksum Offload When set this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP UDP or ICMP payload checksum checking" "0: IP header/payload checksum checking is disabled,1: IP header/payload checksum checking is enabled"
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bitfld.long 0x00 24.--26. "IPG,Inter-Packet Gap These bits control the minimum IPG between packets during transmission" "0: 96 bit times IPG,1: 88 bit times IPG,2: 80 bit times IPG,3: 72 bit times IPG,4: 64 bit times IPG,5: 56 bit times IPG,6: 48 bit times IPG,7: 40 bit times IPG"
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bitfld.long 0x00 23. "GPSLCE,Giant Packet Size Limit Control Enable When this bit is set the MAC considers the value in GPSL field in MAC_Ext_Configuration register to declare a received packet as Giant packet" "0: Giant Packet Size Limit Control is disabled,1: Giant Packet Size Limit Control is enabled"
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bitfld.long 0x00 22. "S2KP,IEEE 802" "0: Support up to 2K packet is disabled,1: Support up to 2K packet is Enabled"
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bitfld.long 0x00 21. "CST,CRC stripping for Type packets When this bit is set the last four bytes (FCS) of all packets of Ether type (type field greater than 1 536) are stripped and dropped before forwarding the packet to the application" "0: CRC stripping for Type packets is disabled,1: CRC stripping for Type packets is enabled"
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bitfld.long 0x00 20. "ACS,Automatic Pad or CRC Stripping When this bit is set the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1 536 bytes" "0: Automatic Pad or CRC Stripping is disabled,1: Automatic Pad or CRC Stripping is enabled"
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bitfld.long 0x00 19. "WD,Watchdog Disable When this bit is set the MAC disables the watchdog timer on the receiver" "0: Watchdog is enabled,1: Watchdog is disabled"
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bitfld.long 0x00 18. "BE,Packet Burst Enable When this bit is set the MAC allows packet bursting during transmission in the GMII half-duplex mode" "0: Packet Burst is disabled,1: Packet Burst is enabled"
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bitfld.long 0x00 17. "JD,Jabber Disable When this bit is set the MAC disables the jabber timer on the transmitter" "0: Jabber is enabled,1: Jabber is disabled"
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bitfld.long 0x00 16. "JE,Jumbo Packet Enable When this bit is set the MAC allows jumbo packets of 9 018 bytes (9 022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status" "0: Jumbo packet is disabled,1: Jumbo packet is enabled"
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bitfld.long 0x00 15. "PS,Port Select This bit selects the Ethernet line speed" "0: For 1000 or 2500 Mbps operations,1: For 10 or 100 Mbps operations"
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bitfld.long 0x00 14. "FES,Speed This bit selects the speed mode" "0: 10 Mbps when PS bit is 1 and 1 Gbps when PS..,1: 100 Mbps when PS bit is 1 and 2.5 Gbps when.."
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bitfld.long 0x00 13. "DM,Duplex Mode When this bit is set the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously" "0: Half-duplex mode,1: Full-duplex mode"
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bitfld.long 0x00 12. "LM,Loopback Mode When this bit is set the MAC operates in the loopback mode at GMII or MII" "0: Loopback is disabled,1: Loopback is enabled"
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bitfld.long 0x00 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode" "0: ECRSFD is disabled,1: ECRSFD is enabled"
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bitfld.long 0x00 10. "DO,Disable Receive Own When this bit is set the MAC disables the reception of packets when the gmii_txen_o is asserted in the half-duplex mode" "0: Enable Receive Own,1: Disable Receive Own"
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bitfld.long 0x00 9. "DCRS,Disable Carrier Sense During Transmission When this bit is set the MAC transmitter ignores the (G)MII CRS signal during packet transmission in the half-duplex mode" "0: Enable Carrier Sense During Transmission,1: Disable Carrier Sense During Transmission"
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bitfld.long 0x00 8. "DR,Disable Retry When this bit is set the MAC attempts only one transmission" "0: Enable Retry,1: Disable Retry"
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bitfld.long 0x00 5.--6. "BL,Back-Off Limit The back-off limit determines the random integer number (r) of slot time delays (4 096 bit times for 1000/2500 Mbps 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after.." "0: k = min(n 10),1: k = min(n 8),2: k = min(n 4),3: k = min(n 1)"
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bitfld.long 0x00 4. "DC,Deferral Check When this bit is set the deferral check function is enabled in the MAC" "0: Deferral check function is disabled,1: Deferral check function is enabled"
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bitfld.long 0x00 2.--3. "PRELEN,Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,?..."
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bitfld.long 0x00 1. "TE,Transmitter Enable When this bit is set the Tx state machine of the MAC is enabled for transmission on the GMII or MII interface" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x00 0. "RE,Receiver Enable When this bit is set the Rx state machine of the MAC is enabled for receiving packets from the GMII or MII interface" "0: Receiver is disabled,1: Receiver is enabled"
group.long 0x04++0x03
line.long 0x00 "MAC_Ext_Configuration,The MAC Extended Configuration Register establishes the operating mode of the MAC"
bitfld.long 0x00 30. "APDIM,ARP Packet Drop if IP Address Mismatch When this bit is set Packet for which Target Protocol Address does not match IPv4 address is dropped in the MTL layer" "0: mux select to drop the arp packet if target..,1: mux select to drop the arp packet if target.."
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bitfld.long 0x00 25.--29. "EIPG,Extended Inter-Packet Gap The value in this field is applicable when the EIPGEN bit is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 24. "EIPGEN,Extended Inter-Packet Gap Enable When this bit is set the MAC interprets EIPG field and IPG field in MAC_Configuration register together as minimum IPG greater than 96 bit times in steps of 8 bit times" "0: Extended Inter-Packet Gap is disabled,1: Extended Inter-Packet Gap is enabled"
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bitfld.long 0x00 20.--22. "HDSMS,Maximum Size for Splitting the Header Data These bits indicate the maximum header size allowed for splitting the header data in the received packet" "0: Maximum Size for Splitting the Header Data is..,1: Maximum Size for Splitting the Header Data is..,2: Maximum Size for Splitting the Header Data is..,3: Maximum Size for Splitting the Header Data is..,4: Maximum Size for Splitting the Header Data is..,?..."
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bitfld.long 0x00 19. "PDC,Packet Duplication Control When this bit is set the received packet with Multicast/Broadcast Destination address is routed to multiple Receive DMA Channels" "0: Packet Duplication Control is disabled,1: Packet Duplication Control is enabled"
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bitfld.long 0x00 18. "USP,Unicast Slow Protocol Packet Detect When this bit is set the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC_Address0_High and MAC_Address0_Low registers" "0: Unicast Slow Protocol Packet Detection is..,1: Unicast Slow Protocol Packet Detection is.."
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bitfld.long 0x00 17. "SPEN,Slow Protocol Detection Enable When this bit is set MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Slow Protocol Sub-Type and Code fields in Rx status" "0: Slow Protocol Detection is disabled,1: Slow Protocol Detection is enabled"
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bitfld.long 0x00 16. "DCRCC,Disable CRC Checking for Received Packets When this bit is set the MAC receiver does not check the CRC field in the received packets" "0: CRC Checking is enabled,1: CRC Checking is disabled"
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hexmask.long.word 0x00 0.--13. 1. "GPSL,Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes the MAC declares the received packet as Giant packet"
group.long 0x08++0x03
line.long 0x00 "MAC_Packet_Filter,The MAC Packet Filter register contains the filter controls for receiving packets"
bitfld.long 0x00 31. "RA,Receive All When this bit is set the MAC Receiver module passes all received packets to the application irrespective of whether they pass the address filter or not" "0: Receive All is disabled,1: Receive All is enabled"
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bitfld.long 0x00 21. "DNTU,Drop Non-TCP/UDP over IP Packets When this bit is set the MAC drops the non-TCP or UDP over IP packets" "0: Forward Non-TCP/UDP over IP Packets,1: Drop Non-TCP/UDP over IP Packets"
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bitfld.long 0x00 20. "IPFE,Layer 3 and Layer 4 Filter Enable When this bit is set the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters" "0: Layer 3 and Layer 4 Filters are disabled,1: Layer 3 and Layer 4 Filters are enabled"
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bitfld.long 0x00 16. "VTFE,VLAN Tag Filter Enable When this bit is set the MAC drops the VLAN tagged packets that do not match the VLAN Tag" "0: VLAN Tag Filter is disabled,1: VLAN Tag Filter is enabled"
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bitfld.long 0x00 10. "HPF,Hash or Perfect Filter When this bit is set the address filter passes a packet if it matches either the perfect filtering or hash filtering as set by the HMC or HUC bit" "0: Hash or Perfect Filter is disabled,1: Hash or Perfect Filter is enabled"
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bitfld.long 0x00 9. "SAF,Source Address Filter Enable When this bit is set the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers" "0: SA Filtering is disabled,1: SA Filtering is enabled"
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bitfld.long 0x00 8. "SAIF,SA Inverse Filtering When this bit is set the Address Check block operates in the inverse filtering mode for SA address comparison" "0: SA Inverse Filtering is disabled,1: SA Inverse Filtering is enabled"
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bitfld.long 0x00 6.--7. "PCF,Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets)" "0: MAC filters all control packets from reaching..,1: MAC forwards all control packets except Pause..,2: MAC forwards all control packets to the..,3: MAC forwards the control packets that pass.."
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bitfld.long 0x00 5. "DBF,Disable Broadcast Packets When this bit is set the AFM module blocks all the incoming broadcast packets" "0: Enable Broadcast Packets,1: Disable Broadcast Packets"
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bitfld.long 0x00 4. "PM,Pass All Multicast When this bit is set it indicates that all the received packets with a multicast destination address (first bit in the destination address field is '1') are passed" "0: Pass All Multicast is disabled,1: Pass All Multicast is enabled"
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bitfld.long 0x00 3. "DAIF,DA Inverse Filtering When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets" "0: DA Inverse Filtering is disabled,1: DA Inverse Filtering is enabled"
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bitfld.long 0x00 2. "HMC,Hash Multicast When this bit is set the MAC performs the destination address filtering of received multicast packets according to the hash table" "0: Hash Multicast is disabled,1: Hash Multicast is enabled"
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bitfld.long 0x00 1. "HUC,Hash Unicast When this bit is set the MAC performs the destination address filtering of unicast packets according to the hash table" "0: Hash Unicast is disabled,1: Hash Unicast is enabled"
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bitfld.long 0x00 0. "PR,Promiscuous Mode When this bit is set the Address Filtering module passes all incoming packets irrespective of the destination or source address" "0: Promiscuous Mode is disabled,1: Promiscuous Mode is enabled"
group.long 0x0C++0x03
line.long 0x00 "MAC_Watchdog_Timeout,The Watchdog Timeout register controls the watchdog timeout for received packets"
bitfld.long 0x00 8. "PWE,Programmable Watchdog Enable When this bit is set and the WD bit of the MAC_Configuration register is reset the WTO field is used as watchdog timeout for a received packet" "0: Programmable Watchdog is disabled,1: Programmable Watchdog is enabled"
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bitfld.long 0x00 0.--3. "WTO,Watchdog Timeout When the PWE bit is set and the WD bit of the MAC_Configuration register is reset this field is used as watchdog timeout for a received packet" "0: M_2KBYTES,1: M_3KBYTES,2: M_4KBYTES,3: M_5KBYTES,4: M_6KBYTES,5: M_7KBYTES,6: M_8KBYTES,7: M_9KBYTES,8: M_10KBYTES,9: M_11KBYTES,10: M_12KBYTES,11: M_13KBYTES,12: M_14KBYTES,13: M_15KBYTES,14: M_16383BYTES,?..."
group.long 0x10++0x03
line.long 0x00 "MAC_Hash_Table_Reg0,The Hash Table Register 0 contains the first 32 bits of the hash table when the width of the hash table is 128 or 256 bits"
hexmask.long 0x00 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table"
group.long 0x14++0x03
line.long 0x00 "MAC_Hash_Table_Reg1,The Hash Table Register 1 contains the second 32 bits of the hash table"
hexmask.long 0x00 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table"
group.long 0x50++0x03
line.long 0x00 "MAC_VLAN_Tag_Ctrl,This register is the redefined format of the MAC VLAN Tag Register"
bitfld.long 0x00 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status When this bit is set the MAC provides the inner VLAN Tag in the Rx status" "0: Inner VLAN Tag in Rx status is disabled,1: Inner VLAN Tag in Rx status is enabled"
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bitfld.long 0x00 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
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bitfld.long 0x00 27. "ERIVLT,Enable Inner VLAN Tag Comparison When this bit VTHM bit and the EDVLP field are set the MAC receiver enables VLAN Hash filtering operation on the inner VLAN Tag (if present)" "0: Inner VLAN tag is disabled,1: Inner VLAN tag is enabled"
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bitfld.long 0x00 26. "EDVLP,Enable Double VLAN Processing When this bit is set the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present)" "0: Double VLAN Processing is disabled,1: Double VLAN Processing is enabled"
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bitfld.long 0x00 25. "VTHM,VLAN Tag Hash Table Match Enable When this bit is set the most significant four bits of CRC of VLAN Tag are used to index the content of the MAC_VLAN_Hash_Table register" "0: VLAN Tag Hash Table Match is disabled,1: VLAN Tag Hash Table Match is enabled"
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bitfld.long 0x00 24. "EVLRXS,Enable VLAN Tag in Rx status When this bit is set MAC provides the outer VLAN Tag in the Rx status" "0: VLAN Tag in Rx status is disabled,1: VLAN Tag in Rx status is enabled"
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bitfld.long 0x00 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
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bitfld.long 0x00 20. "DOVLTC,Disable VLAN Type Check for VLAN Hash Filtering When this bit is set the MAC VLAN Hash Filter does not check whether the VLAN Tag specified by the ERIVLT bit is of type S-VLAN or C-VLAN" "0: VLAN Type Check is enabled,1: VLAN Type Check is disabled"
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bitfld.long 0x00 19. "ERSVLM,Enable Receive S-VLAN Match for VLAN Hash Filtering When this bit is set the MAC receiver enables VLAN Hash filtering or matching for S-VLAN (Type = 0x88A8) packets" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled"
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bitfld.long 0x00 18. "ESVL,Enable S-VLAN When this bit is set the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets" "0: S-VLAN is disabled,1: S-VLAN is enabled"
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bitfld.long 0x00 17. "VTIM,VLAN Tag Inverse Match Enable When this bit is set this bit enables the VLAN Tag inverse matching" "0: VLAN Tag Inverse Match is disabled,1: VLAN Tag Inverse Match is enabled"
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bitfld.long 0x00 16. "ETV,Enable 12-Bit VLAN Tag Comparison for VLAN Hash Filtering When this bit is set a 12-bit VLAN identifier is used for VLAN Hash filtering instead of the complete 16-bit VLAN tag" "0: 12-Bit VLAN Tag Comparison is disabled,1: 12-Bit VLAN Tag Comparison is enabled"
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bitfld.long 0x00 2.--3. "OFS,Offset This field holds the address offset of the MAC VLAN Tag Filter Register which the application is trying to access" "0,1,2,3"
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bitfld.long 0x00 1. "CT,Command Type This bit indicates if the current register access is a read or a" "0: Write operation,1: Read operation"
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bitfld.long 0x00 0. "OB,Operation Busy This bit is set along with a read or write command for initiating the indirect access to per VLAN Tag Filter register" "0: Operation Busy is disabled,1: Operation Busy is enabled"
group.long 0x54++0x03
line.long 0x00 "MAC_VLAN_Tag_Data,This register holds the read/write data for Indirect Access of the Per VLAN Tag registers"
bitfld.long 0x00 25. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field" "0,1"
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bitfld.long 0x00 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH" "0: DMA Channel Number is disabled,1: DMA Channel Number is enabled"
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bitfld.long 0x00 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when Double VLAN Tag Enable of the Filter is set" "0: Inner VLAN tag comparison is disabled,1: Inner VLAN tag comparison is enabled"
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bitfld.long 0x00 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set" "0: Receive S-VLAN Match is disabled,1: Receive S-VLAN Match is enabled"
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bitfld.long 0x00 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set" "0: VLAN type comparison is enabled,1: VLAN type comparison is disabled"
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bitfld.long 0x00 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set" "0: 16 bit VLAN comparison,1: 12 bit VLAN comparison"
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bitfld.long 0x00 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag" "0: VLAN Tag is disabled,1: VLAN Tag is enabled"
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hexmask.long.word 0x00 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison"
group.long 0x58++0x03
line.long 0x00 "MAC_VLAN_Hash_Table,When VTHM bit of the MAC_VLAN_Tag register is set the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag"
hexmask.long.word 0x00 0.--15. 1. "VLHT,VLAN Hash Table This field contains the 16-bit VLAN Hash Table"
group.long 0x60++0x03
line.long 0x00 "MAC_VLAN_Incl,The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets"
rbitfld.long 0x00 31. "BUSY,Busy This bit indicates the status of the read/write operation of indirect access to the queue/channel specific VLAN inclusion register" "0: Busy status not detected,1: Busy status detected"
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bitfld.long 0x00 30. "RDWR,Read write control This bit controls the read or write operation for indirectly accessing the queue/channel specific VLAN Inclusion register" "0: Read operation of indirect access,1: Write operation of indirect access"
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bitfld.long 0x00 24. "ADDR,Address This field selects one of the queue/channel specific VLAN Inclusion register for read/write access" "0,1"
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bitfld.long 0x00 21. "CBTI,Channel based tag insertion When this bit is set outer VLAN tag is inserted for every packets transmitted by the MAC" "0: Channel based tag insertion is disabled,1: Channel based tag insertion is enabled"
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bitfld.long 0x00 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled"
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bitfld.long 0x00 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted or replaced,1: S-VLAN type (0x88A8) is inserted or replaced"
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bitfld.long 0x00 18. "VLP,VLAN Priority Control When this bit is set the control bits[17:16] are used for VLAN deletion insertion or replacement" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled"
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bitfld.long 0x00 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
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hexmask.long.word 0x00 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced"
group.long 0x64++0x03
line.long 0x00 "MAC_Inner_VLAN_Incl,The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet"
bitfld.long 0x00 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor" "0: VLAN Tag Input is disabled,1: VLAN Tag Input is enabled"
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bitfld.long 0x00 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 17th and 18th bytes of transmitted packets" "0: C-VLAN type (0x8100) is inserted,1: S-VLAN type (0x88A8) is inserted"
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bitfld.long 0x00 18. "VLP,VLAN Priority Control When this bit is set the VLC field is used for VLAN deletion insertion or replacement" "0: VLAN Priority Control is disabled,1: VLAN Priority Control is enabled"
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bitfld.long 0x00 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
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hexmask.long.word 0x00 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced"
group.long 0x70++0x03
line.long 0x00 "MAC_Q0_Tx_Flow_Ctrl,The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC"
hexmask.long.word 0x00 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet"
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bitfld.long 0x00 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "0: Zero-Quanta Pause packet generation is enabled,1: Zero-Quanta Pause packet generation is disabled"
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bitfld.long 0x00 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet" "0: Pause Time minus 4 Slot Times (PT -4 slot..,1: Pause Time minus 28 Slot Times (PT -28 slot..,2: Pause Time minus 36 Slot Times (PT -36 slot..,3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,?..."
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bitfld.long 0x00 1. "TFE,Transmit Flow Control Enable Full-Duplex Mode: In the full-duplex mode when this bit is set the MAC enables the flow control operation to Tx Pause packets" "0: Transmit Flow Control is disabled,1: Transmit Flow Control is enabled"
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bitfld.long 0x00 0. "FCB_BPA,Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set" "0: Flow Control Busy or Backpressure Activate is..,1: Flow Control Busy or Backpressure Activate is.."
group.long 0x90++0x03
line.long 0x00 "MAC_Rx_Flow_Ctrl,The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet"
bitfld.long 0x00 1. "UP,Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802" "0: Unicast Pause Packet Detect disabled,1: Unicast Pause Packet Detect enabled"
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bitfld.long 0x00 0. "RFE,Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex mode the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time" "0: Receive Flow Control is disabled,1: Receive Flow Control is enabled"
group.long 0x94++0x03
line.long 0x00 "MAC_RxQ_Ctrl4,The Receive Queue Control 4 register controls the routing of unicast and multicast packets that fail the Destination or Source address filter to the Rx queues"
bitfld.long 0x00 17. "VFFQ,VLAN Tag Filter Fail Packets Queue This field holds the Rx queue number to which the tagged packets failing the Destination or Source Address filter (and UFFQE/MFFQE not enabled) or failing the VLAN tag filter must be routed to" "0,1"
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bitfld.long 0x00 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable When this bit is set the tagged packets which fail the Destination or Source address filter or fail the VLAN tag filter are routed to the Rx Queue Number programmed in the VFFQ" "0: VLAN tag Filter Fail Packets Queuing is..,1: VLAN tag Filter Fail Packets Queuing is enabled"
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bitfld.long 0x00 9. "MFFQ,Multicast Address Filter Fail Packets Queue" "0,1"
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bitfld.long 0x00 8. "MFFQE,Multicast Address Filter Fail Packets Queuing Enable" "0: Multicast Address Filter Fail Packets Queuing..,1: Multicast Address Filter Fail Packets Queuing.."
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bitfld.long 0x00 1. "UFFQ,Unicast Address Filter Fail Packets Queue" "0,1"
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bitfld.long 0x00 0. "UFFQE,Unicast Address Filter Fail Packets Queuing Enable" "0: Unicast Address Filter Fail Packets Queuing..,1: Unicast Address Filter Fail Packets Queuing.."
group.long 0xA0++0x03
line.long 0x00 "MAC_RxQ_Ctrl0,The Receive Queue Control 0 register controls the queue management in the MAC Receiver"
bitfld.long 0x00 2.--3. "RXQ1EN,Receive Queue 1 Enable This field is similar to the RXQ0EN field" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
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bitfld.long 0x00 0.--1. "RXQ0EN,Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB" "0: Queue not enabled,1: Queue enabled for AV,2: Queue enabled for DCB/Generic,?..."
group.long 0xA4++0x03
line.long 0x00 "MAC_RxQ_Ctrl1,The Receive Queue Control 1 register controls the routing of multicast broadcast AV DCB and untagged packets to the Rx queues"
bitfld.long 0x00 29. "TBRQE,Type Field Based Rx Queuing Enable When this bit is set it enables Type Field based Rx Queuing where the Type field of received packet is compared with programmed TYP field in MAC_TMRQ_Regs(#i) and if a match occurs the packet is routed to the.." "0,1"
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bitfld.long 0x00 28. "OMCBCQ,Over-riding MC-BC queue priority select" "0: overriding MCBCQ priority disabled,1: overriding MCBCQ priority enabled"
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bitfld.long 0x00 24.--26. "FPRQ,Frame Preemption Residue Queue This field holds the Rx queue number to which the residual preemption frames must be forwarded" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 22.--23. "TPQC,Tagged PTP over Ethernet Packets Queuing Control" "0,1,2,3"
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bitfld.long 0x00 21. "TACPQE,Tagged AV Control Packets Queuing Enable" "0: Tagged AV Control Packets Queuing is disabled,1: Tagged AV Control Packets Queuing is enabled"
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bitfld.long 0x00 20. "MCBCQEN,Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed to Rx Queue specified in MCBCQ field" "0: Multicast and Broadcast Queue is disabled,1: Multicast and Broadcast Queue is enabled"
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bitfld.long 0x00 16.--18. "MCBCQ,Multicast and Broadcast Queue This field specifies the Rx Queue onto which Multicast or Broadcast Packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7"
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bitfld.long 0x00 12.--14. "UPQ,Untagged Packet Queue This field indicates the Rx Queue to which Untagged Packets are to be routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7"
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bitfld.long 0x00 4.--6. "PTPQ,PTP Packets Queue This field specifies the Rx queue on which the PTP packets sent over the Ethernet payload (not over IPv4 or IPv6) are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7"
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bitfld.long 0x00 0.--2. "AVCPQ,AV Untagged Control Packets Queue This field specifies the Receive queue on which the received AV tagged and untagged control packets are routed" "0: Receive Queue 0,1: Receive Queue 1,2: Receive Queue 2,3: Receive Queue 3,4: Receive Queue 4,5: Receive Queue 5,6: Receive Queue 6,7: Receive Queue 7"
group.long 0xA8++0x03
line.long 0x00 "MAC_RxQ_Ctrl2,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the RxQueues 0 to 3"
hexmask.long.byte 0x00 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1 This field decides the priorities assigned to Rx Queue 1"
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hexmask.long.byte 0x00 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0 This field decides the priorities assigned to Rx Queue 0"
rgroup.long 0xB0++0x03
line.long 0x00 "MAC_Interrupt_Status,The Interrupt Status register contains the status of interrupts"
bitfld.long 0x00 20. "MFRIS,MMC FPE Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Receive Interrupt Register" "0: MMC FPE Receive Interrupt status not active,1: MMC FPE Receive Interrupt status active"
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bitfld.long 0x00 19. "MFTIS,MMC FPE Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Transmit Interrupt Register" "0: MMC FPE Transmit Interrupt status not active,1: MMC FPE Transmit Interrupt status active"
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bitfld.long 0x00 18. "MDIOIS,MDIO Interrupt Status This bit indicates an interrupt event after the completion of MDIO operation" "0: MDIO Interrupt status not active,1: MDIO Interrupt status active"
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bitfld.long 0x00 17. "FPEIS,Frame Preemption Interrupt Status This bit indicates an interrupt event during the operation of Frame Preemption (Bits[19:16] of MAC_FPE_CTRL_STS register is set)" "0: Frame Preemption Interrupt status not active,1: Frame Preemption Interrupt status active"
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bitfld.long 0x00 14. "RXSTSIS,Receive Status Interrupt This bit indicates the status of received packets" "0: Receive Interrupt status not active,1: Receive Interrupt status active"
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bitfld.long 0x00 13. "TXSTSIS,Transmit Status Interrupt This bit indicates the status of transmitted packets" "0: Transmit Interrupt status not active,1: Transmit Interrupt status active"
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bitfld.long 0x00 12. "TSIS,Timestamp Interrupt Status If the Timestamp feature is enabled this bit is set when any of the following conditions is true: - The system time value is equal to or exceeds the value specified in the Target Time High and Low registers" "0: Timestamp Interrupt status not active,1: Timestamp Interrupt status active"
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bitfld.long 0x00 10. "MMCTXIS,MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register" "0: MMC Transmit Interrupt status not active,1: MMC Transmit Interrupt status active"
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bitfld.long 0x00 9. "MMCRXIS,MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register" "0: MMC Receive Interrupt status not active,1: MMC Receive Interrupt status active"
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bitfld.long 0x00 8. "MMCIS,MMC Interrupt Status This bit is set high when Bit 11 Bit 10 or Bit 9 is set high" "0: MMC Interrupt status not active,1: MMC Interrupt status active"
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bitfld.long 0x00 5. "LPIIS,LPI Interrupt Status When the Energy Efficient Ethernet feature is enabled this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver" "0: LPI Interrupt status not active,1: LPI Interrupt status active"
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bitfld.long 0x00 4. "PMTIS,PMT Interrupt Status This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (RWKPRCVD and MGKPRCVD bits in MAC_PMT_Control_Status register)" "0: PMT Interrupt status not active,1: PMT Interrupt status active"
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bitfld.long 0x00 3. "PHYIS,PHY Interrupt This bit is set when rising edge is detected on the phy_intr_i input" "0: PHY Interrupt not detected,1: PHY Interrupt detected"
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bitfld.long 0x00 0. "RGSMIIIS,RGMII or SMII Interrupt Status This bit is set because of any change in value of the Link Status of RGMII or SMII interface (LNKSTS bit in MAC_PHYIF_Control_Status register)" "0: RGMII or SMII Interrupt Status is not active,1: RGMII or SMII Interrupt Status is active"
group.long 0xB4++0x03
line.long 0x00 "MAC_Interrupt_Enable,The Interrupt Enable register contains the masks for generating the interrupts"
bitfld.long 0x00 18. "MDIOIE,MDIO Interrupt Enable When this bit is set it enables the assertion of the interrupt when MDIOIS field is set in the MAC_Interrupt_Status register" "0: MDIO Interrupt is disabled,1: MDIO Interrupt is enabled"
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bitfld.long 0x00 17. "FPEIE,Frame Preemption Interrupt Enable When this bit is set it enables the assertion of the interrupt when FPEIS field is set in the MAC_Interrupt_Status register" "0: Frame Preemption Interrupt is disabled,1: Frame Preemption Interrupt is enabled"
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bitfld.long 0x00 14. "RXSTSIE,Receive Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the MAC_Interrupt_Status register" "0: Receive Status Interrupt is disabled,1: Receive Status Interrupt is enabled"
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bitfld.long 0x00 13. "TXSTSIE,Transmit Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the MAC_Interrupt_Status register" "0: Timestamp Status Interrupt is disabled,1: Timestamp Status Interrupt is enabled"
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bitfld.long 0x00 12. "TSIE,Timestamp Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TSIS bit in MAC_Interrupt_Status register" "0: Timestamp Interrupt is disabled,1: Timestamp Interrupt is enabled"
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bitfld.long 0x00 5. "LPIIE,LPI Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of LPIIS bit in MAC_Interrupt_Status register" "0: LPI Interrupt is disabled,1: LPI Interrupt is enabled"
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bitfld.long 0x00 4. "PMTIE,PMT Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PMTIS bit in MAC_Interrupt_Status register" "0: PMT Interrupt is disabled,1: PMT Interrupt is enabled"
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bitfld.long 0x00 3. "PHYIE,PHY Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PHYIS bit in MAC_Interrupt_Status register" "0: PHY Interrupt is disabled,1: PHY Interrupt is enabled"
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bitfld.long 0x00 0. "RGSMIIIE,RGMII or SMII Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RGSMIIIS bit in MAC_Interrupt_Status register" "0: RGMII or SMII Interrupt is disabled,1: RGMII or SMII Interrupt is enabled"
rgroup.long 0xB8++0x03
line.long 0x00 "MAC_Rx_Tx_Status,The Receive Transmit Status register contains the Receive and Transmit Error status"
bitfld.long 0x00 8. "RWT,Receive Watchdog Timeout This bit is set when a packet with length greater than 2 048 bytes is received (10 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_Configuration register" "0: No receive watchdog timeout,1: Receive watchdog timed out"
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bitfld.long 0x00 5. "EXCOL,Excessive Collisions When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet" "0: No collision,1: Excessive collision is sensed"
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bitfld.long 0x00 4. "LCOL,Late Collision When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode 512 bytes.." "0: No collision,1: Late collision is sensed"
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bitfld.long 0x00 3. "EXDEF,Excessive Deferral When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the MAC_Configuration register this bit indicates that the transmission ended because of excessive deferral of over 24 288 bit times (155 680.." "0: No Excessive deferral,1: Excessive deferral"
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bitfld.long 0x00 2. "LCARR,Loss of Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the loss of carrier occurred during packet transmission that is the phy_crs_i signal was inactive for one or more transmission clock periods.." "0: Carrier is present,1: Loss of carrier"
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bitfld.long 0x00 1. "NCARR,No Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission" "0: Carrier is present,1: No carrier"
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bitfld.long 0x00 0. "TJT,Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2 048 bytes (10 240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_Configuration register" "0: No Transmit Jabber Timeout,1: Transmit Jabber Timeout occurred"
group.long 0xC0++0x03
line.long 0x00 "MAC_PMT_Control_Status,The PMT Control and Status Register"
bitfld.long 0x00 31. "RWKFILTRST,Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set the remote wake-up packet filter register pointer is reset to 3'b000" "0: Remote Wake-Up Packet Filter Register Pointer..,1: Remote Wake-Up Packet Filter Register Pointer.."
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rbitfld.long 0x00 24.--28. "RWKPTR,Remote Wake-up FIFO Pointer This field gives the current value (0 to 7 15 or 31 when 4 8 or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter register pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "RWKPFE,Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN the MAC receiver drops all received frames until it receives the expected Wake-up frame" "0: Remote Wake-up Packet Forwarding is disabled,1: Remote Wake-up Packet Forwarding is enabled"
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bitfld.long 0x00 9. "GLBLUCAST,Global Unicast When this bit set any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wake-up packet" "0: Global unicast is disabled,1: Global unicast is enabled"
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rbitfld.long 0x00 6. "RWKPRCVD,Remote Wake-Up Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a remote wake-up packet" "0: Remote wake-up packet is received,1: Remote wake-up packet is received"
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rbitfld.long 0x00 5. "MGKPRCVD,Magic Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a magic packet" "0: No Magic packet is received,1: Magic packet is received"
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bitfld.long 0x00 2. "RWKPKTEN,Remote Wake-Up Packet Enable When this bit is set a power management event is generated when the MAC receives a remote wake-up packet" "0: Remote wake-up packet is disabled,1: Remote wake-up packet is enabled"
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bitfld.long 0x00 1. "MGKPKTEN,Magic Packet Enable When this bit is set a power management event is generated when the MAC receives a magic packet" "0: Magic Packet is disabled,1: Magic Packet is enabled"
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bitfld.long 0x00 0. "PWRDWN,Power Down When this bit is set the MAC receiver drops all received packets until it receives the expected magic packet or remote wake-up packet" "0: Power down is disabled,1: Power down is enabled"
group.long 0xC4++0x03
line.long 0x00 "MAC_RWK_Packet_Filter,The Remote Wakeup Filter registers are implemented as 8 16 or 32 indirect access registers (wkuppktfilter_reg#i) based on whether 4 8 or 16 Remote Wakeup Filters are selected in the configuration and accessed by application through.."
hexmask.long 0x00 0.--31. 1. "WKUPFRMFTR,RWK Packet Filter This field contains the various controls of RWK Packet filter"
group.long 0xD0++0x03
line.long 0x00 "MAC_LPI_Control_Status,The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status"
bitfld.long 0x00 21. "LPITCSE,LPI Tx Clock Stop Enable When this bit is set the MAC asserts sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped" "0: LPI Tx Clock Stop is disabled,1: LPI Tx Clock Stop is enabled"
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bitfld.long 0x00 20. "LPIATE,LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state" "0: LPI Timer is disabled,1: LPI Timer is enabled"
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bitfld.long 0x00 19. "LPITXA,LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side" "0: LPI Tx Automate is disabled,1: LPI Tx Automate is enabled"
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bitfld.long 0x00 18. "PLSEN,PHY Link Status Enable This bit enables the link status received on the RGMII SGMII or SMII Receive paths to be used for activating the LPI LS TIMER" "0: PHY Link Status is disabled,1: PHY Link Status is enabled"
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bitfld.long 0x00 17. "PLS,PHY Link Status This bit indicates the link status of the PHY" "0: link is down,1: link is okay (UP)"
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bitfld.long 0x00 16. "LPIEN,LPI Enable When this bit is set it instructs the MAC Transmitter to enter the LPI state" "0: LPI state is disabled,1: LPI state is enabled"
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rbitfld.long 0x00 9. "RLPIST,Receive LPI State When this bit is set it indicates that the MAC is receiving the LPI pattern on the GMII or MII interface" "0: Receive LPI state not detected,1: Receive LPI state detected"
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rbitfld.long 0x00 8. "TLPIST,Transmit LPI State When this bit is set it indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface" "0: Transmit LPI state not detected,1: Transmit LPI state detected"
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rbitfld.long 0x00 3. "RLPIEX,Receive LPI Exit When this bit is set it indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface exited the LPI state and resumed the normal reception" "0: Receive LPI exit not detected,1: Receive LPI exit detected"
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rbitfld.long 0x00 2. "RLPIEN,Receive LPI Entry When this bit is set it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state" "0: Receive LPI entry not detected,1: Receive LPI entry detected"
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rbitfld.long 0x00 1. "TLPIEX,Transmit LPI Exit When this bit is set it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired" "0: Transmit LPI exit not detected,1: Transmit LPI exit detected"
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rbitfld.long 0x00 0. "TLPIEN,Transmit LPI Entry When this bit is set it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit" "0: Transmit LPI entry not detected,1: Transmit LPI entry detected"
group.long 0xD4++0x03
line.long 0x00 "MAC_LPI_Timers_Control,The LPI Timers Control register controls the timeout values in the LPI states"
hexmask.long.word 0x00 16.--25. 1. "LST,LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY"
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hexmask.long.word 0x00 0.--15. 1. "TWT,LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission"
group.long 0xD8++0x03
line.long 0x00 "MAC_LPI_Entry_Timer,This register controls the Tx LPI entry timer"
hexmask.long.tbyte 0x00 3.--19. 1. "LPIET,LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI mode after it has transmitted all the frames"
group.long 0xDC++0x03
line.long 0x00 "MAC_1US_Tic_Counter,This register controls the generation of the Reference time (1 microsecond tic) for all the LPI timers"
hexmask.long.word 0x00 0.--11. 1. "TIC_1US_CNTR,1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us"
group.long 0xF8++0x03
line.long 0x00 "MAC_PHYIF_Control_Status,The PHY Interface Control and Status register indicates the status signals received by the SGMII RGMII or SMII interface (selected at reset) from the PHY"
rbitfld.long 0x00 19. "LNKSTS,Link Status This bit indicates whether the link is up (1'b1) or down (1'b0)" "0: Link down,1: Link up"
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rbitfld.long 0x00 17.--18. "LNKSPEED,Link Speed This bit indicates the current speed of the link" "0: M_2500K,1: 25 MHz,2: 125 MHz,?..."
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rbitfld.long 0x00 16. "LNKMOD,Link Mode This bit indicates the current mode of operation of the link" "0: Half-duplex mode,1: Full-duplex mode"
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bitfld.long 0x00 1. "LUD,Link Up or Down This bit indicates whether the link is up or down during transmission of configuration in the RGMII SGMII or SMII interface" "0: Link down,1: Link up"
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bitfld.long 0x00 0. "TC,Transmit Configuration in RGMII SGMII or SMII When set this bit enables the transmission of duplex mode link speed and link up or down information to the PHY in the RGMII SMII or SGMII port" "0: Disable Transmit Configuration in RGMII SGMII..,1: Enable Transmit Configuration in RGMII SGMII.."
rgroup.long 0x110++0x03
line.long 0x00 "MAC_Version,The version register identifies the version of the module"
hexmask.long.byte 0x00 8.--15. 1. "CFGVER,IP configuration version"
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hexmask.long.byte 0x00 0.--7. 1. "IPVER,IP Version"
rgroup.long 0x114++0x03
line.long 0x00 "MAC_Debug,The Debug register provides the debug status of various MAC blocks"
bitfld.long 0x00 17.--18. "TFCSTS,MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module" "0: Idle state,1: Waiting for one of the following,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission"
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bitfld.long 0x00 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and it is not in the Idle state" "0: MAC GMII or MII Transmit Protocol Engine..,1: MAC GMII or MII Transmit Protocol Engine.."
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bitfld.long 0x00 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status When this bit is set this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module" "0,1,2,3"
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bitfld.long 0x00 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII receive protocol engine is actively receiving data and it is not in the Idle state" "0: MAC GMII or MII Receive Protocol Engine..,1: MAC GMII or MII Receive Protocol Engine.."
rgroup.long 0x11C++0x03
line.long 0x00 "MAC_HW_Feature0,This register indicates the presence of first set of the optional features or functions of the DWC_ether_qos"
bitfld.long 0x00 28.--30. "ACTPHYSEL,Active PHY Selected When you have multiple PHY interfaces in your configuration this field indicates the sampled value of phy_intf_sel_i during reset de-assertion" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,7: REVMIII"
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bitfld.long 0x00 27. "SAVLANINS,Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected" "0: Source Address or VLAN Insertion Enable..,1: Source Address or VLAN Insertion Enable.."
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bitfld.long 0x00 25.--26. "TSSTSSEL,Timestamp System Time Source This bit indicates the source of the Timestamp system time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: Internal,1: External,2: BOTH,?..."
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bitfld.long 0x00 24. "MACADR64SEL,MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected" "0: MAC Addresses 64-127 Select option is not..,1: MAC Addresses 64-127 Select option is selected"
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bitfld.long 0x00 23. "MACADR32SEL,MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected" "0: MAC Addresses 32-63 Select option is not..,1: MAC Addresses 32-63 Select option is selected"
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bitfld.long 0x00 18.--22. "ADDMACADRSEL,MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is selected for Enable Additional 1-31 MAC Address Registers option" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16. "RXCOESEL,Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected" "0: Receive Checksum Offload Enable option is not..,1: Receive Checksum Offload Enable option is.."
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bitfld.long 0x00 14. "TXCOESEL,Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected" "0: Transmit Checksum Offload Enable option is..,1: Transmit Checksum Offload Enable option is.."
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bitfld.long 0x00 13. "EEESEL,Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected" "0: Energy Efficient Ethernet Enable option is..,1: Energy Efficient Ethernet Enable option is.."
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bitfld.long 0x00 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected" "0: IEEE 1588-2008 Timestamp Enable option is not..,1: IEEE 1588-2008 Timestamp Enable option is.."
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bitfld.long 0x00 9. "ARPOFFSEL,ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected" "0: ARP Offload Enable option is not selected,1: ARP Offload Enable option is selected"
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bitfld.long 0x00 8. "MMCSEL,RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected" "0: RMON Module Enable option is not selected,1: RMON Module Enable option is selected"
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bitfld.long 0x00 7. "MGKSEL,PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected" "0: PMT Magic Packet Enable option is not selected,1: PMT Magic Packet Enable option is selected"
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bitfld.long 0x00 6. "RWKSEL,PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected" "0: PMT Remote Wake-up Packet Enable option is..,1: PMT Remote Wake-up Packet Enable option is.."
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bitfld.long 0x00 5. "SMASEL,SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected" "0: SMA (MDIO) Interface not selected,1: SMA (MDIO) Interface selected"
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bitfld.long 0x00 4. "VLHASH,VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected" "0: VLAN Hash Filter not selected,1: VLAN Hash Filter selected"
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bitfld.long 0x00 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface) This bit is set to 1 when the TBI SGMII or RTBI PHY interface option is selected" "0: No PCS Registers (TBI SGMII or RTBI PHY..,1: PCS Registers (TBI SGMII or RTBI PHY interface)"
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bitfld.long 0x00 2. "HDSEL,Half-duplex Support This bit is set to 1 when the half-duplex mode is selected" "0: No Half-duplex support,1: Half-duplex support"
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bitfld.long 0x00 1. "GMIISEL,1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation" "0: No 1000 Mbps support,1: 1000 Mbps support"
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bitfld.long 0x00 0. "MIISEL,10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation" "0: No 10 or 100 Mbps support,1: 10 or 100 Mbps support"
rgroup.long 0x120++0x03
line.long 0x00 "MAC_HW_Feature1,This register indicates the presence of second set of the optional features or functions of the DWC_ether_qos"
bitfld.long 0x00 27.--30. "L3L4FNUM,Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters" "0: No L3 or L4 Filter,1: 1 L3 or L4 Filter,2: 2 L3 or L4 Filters,3: 3 L3 or L4 Filters,4: 4 L3 or L4 Filters,5: 5 L3 or L4 Filters,6: 6 L3 or L4 Filters,7: 7 L3 or L4 Filters,8: 8 L3 or L4 Filters,?..."
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bitfld.long 0x00 24.--25. "HASHTBLSZ,Hash Table Size This field indicates the size of the hash table" "0: No hash table,1: M_64,2: M_128,3: M_256"
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bitfld.long 0x00 23. "POUOST,One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One step timestamp for PTP over UDP/IP feature is selected" "0: One Step for PTP over UDP/IP Feature is not..,1: One Step for PTP over UDP/IP Feature is.."
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bitfld.long 0x00 21. "RAVSEL,Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option on Rx Side Only is selected" "0: Rx Side Only AV Feature is not selected,1: Rx Side Only AV Feature is selected"
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bitfld.long 0x00 20. "AVSEL,AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected" "0: AV Feature is not selected,1: AV Feature is selected"
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bitfld.long 0x00 19. "DBGMEMA,DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected" "0: DMA Debug Registers option is not selected,1: DMA Debug Registers option is selected"
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bitfld.long 0x00 18. "TSOEN,TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected" "0: TCP Segmentation Offload Feature is not..,1: TCP Segmentation Offload Feature is selected"
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bitfld.long 0x00 17. "SPHEN,Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected" "0: Split Header Feature is not selected,1: Split Header Feature is selected"
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bitfld.long 0x00 16. "DCBEN,DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected" "0: DCB Feature is not selected,1: DCB Feature is selected"
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bitfld.long 0x00 14.--15. "ADDR64,Address Width" "0: M_32,1: M_40,2: M_48,?..."
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bitfld.long 0x00 13. "ADVTHWORD,IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected" "0: IEEE 1588 High Word Register option is not..,1: IEEE 1588 High Word Register option is selected"
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bitfld.long 0x00 12. "PTOEN,PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected" "0: PTP Offload feature is not selected,1: PTP Offload feature is selected"
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bitfld.long 0x00 11. "OSTEN,One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected" "0: One-Step Timestamping feature is not selected,1: One-Step Timestamping feature is selected"
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bitfld.long 0x00 6.--10. "TXFIFOSIZE,MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(TXFIFO_SIZE) -7" "0: 128 bytes,1: 256 bytes,2: 512 bytes,3: 1024 bytes,4: 2048 bytes,5: 4096 bytes,6: 8192 bytes,7: 16384 bytes,8: M_32KB,9: M_64KB,10: M_128KB,?..."
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bitfld.long 0x00 5. "SPRAM,Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected" "0: Single Port RAM feature is not selected,1: Single Port RAM feature is selected"
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bitfld.long 0x00 0.--4. "RXFIFOSIZE,MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(RXFIFO_SIZE) -7" "0: 128 bytes,1: 256 bytes,2: 512 bytes,3: 1024 bytes,4: 2048 bytes,5: 4096 bytes,6: 8192 bytes,7: 16384 bytes,8: M_32KB,9: M_64KB,10: M_128KB,11: M_256KB,?..."
rgroup.long 0x124++0x03
line.long 0x00 "MAC_HW_Feature2,This register indicates the presence of third set of the optional features or functions of the DWC_ether_qos"
bitfld.long 0x00 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary input,3: 3 auxiliary input,4: 4 auxiliary input,?..."
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bitfld.long 0x00 24.--26. "PPSOUTNUM,Number of PPS Outputs This field indicates the number of PPS outputs" "0: No PPS output,1: 1 PPS output,2: 2 PPS output,3: 3 PPS output,4: 4 PPS output,?..."
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bitfld.long 0x00 22.--23. "TDCSZ,Tx DMA Descriptor Cache Size in terms of 16 bytes descriptors" "0,1,2,3"
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bitfld.long 0x00 18.--21. "TXCHCNT,Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels" "0: 1 MTL Tx Channel,1: M_1TDCSZ,2: M_2TDCSZ,3: M_3TDCSZ,4: 5 MTL Tx Channels,5: 6 MTL Tx Channels,6: 7 MTL Tx Channels,7: 8 MTL Tx Channels,?..."
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bitfld.long 0x00 16.--17. "RDCSZ,Rx DMA Descriptor Cache Size in terms of 16 bytes descriptors" "0,1,2,3"
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bitfld.long 0x00 12.--15. "RXCHCNT,Number of DMA Receive Channels This field indicates the number of DMA Receive channels" "0: 1 MTL Rx Channel,1: M_1RDCSZ,2: M_2RDCSZ,3: M_3RDCSZ,4: 5 MTL Rx Channels,5: 6 MTL Rx Channels,6: 7 MTL Rx Channels,7: 8 MTL Rx Channels,?..."
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bitfld.long 0x00 6.--9. "TXQCNT,Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues" "0: 1 MTL Tx Queue,1: 2 MTL Tx Queues,2: 3 MTL Tx Queues,3: 4 MTL Tx Queues,4: 5 MTL Tx Queues,5: 6 MTL Tx Queues,6: 7 MTL Tx Queues,7: 8 MTL Tx Queues,?..."
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bitfld.long 0x00 0.--3. "RXQCNT,Number of MTL Receive Queues This field indicates the number of MTL Receive queues" "0: 1 MTL Rx Queue,1: 2 MTL Rx Queues,2: 3 MTL Rx Queues,3: 4 MTL Rx Queues,4: 5 MTL Rx Queues,5: 6 MTL Rx Queues,6: 7 MTL Rx Queues,7: 8 MTL Rx Queues,?..."
rgroup.long 0x128++0x03
line.long 0x00 "MAC_HW_Feature3,This register indicates the presence of fourth set the optional features or functions of the DWC_ether_qos"
bitfld.long 0x00 28.--29. "ASP,Automotive Safety Package Following are the encoding for the different Safety features" "0: No Safety features selected,1: Only ECC protection for external memory..,2: All the Automotive Safety features are..,3: All the Automotive Safety features are.."
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bitfld.long 0x00 27. "TBSSEL,Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected" "0: Time Based Scheduling Enable feature is not..,1: Time Based Scheduling Enable feature is.."
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bitfld.long 0x00 26. "FPESEL,Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected" "0: Frame Preemption Enable feature is not selected,1: Frame Preemption Enable feature is selected"
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bitfld.long 0x00 20.--21. "ESTWID,Width of the Time Interval field in the Gate Control List This field indicates the width of the Configured Time Interval Field" "0: Width not configured,1: WIDTH16,2: WIDTH20,3: WIDTH24"
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bitfld.long 0x00 17.--19. "ESTDEP,Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5" "0: No Depth configured,1: DEPTH64,2: DEPTH128,3: DEPTH256,4: DEPTH512,5: DEPTH1024,?..."
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bitfld.long 0x00 16. "ESTSEL,Enhancements to Scheduled Traffic Enable This bit is set to 1 when the Enable Enhancements to Scheduling Traffic feature is selected" "0: Enable Enhancements to Scheduling Traffic..,1: Enable Enhancements to Scheduling Traffic.."
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bitfld.long 0x00 13.--14. "FRPES,Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser Entries supported by Flexible Receive Parser" "0: 64 Entries,1: 128 Entries,2: 256 Entries,?..."
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bitfld.long 0x00 11.--12. "FRPBS,Flexible Receive Parser Buffer size This field indicates the supported Max Number of bytes of the packet data to be Parsed by Flexible Receive Parser" "0: M_64BYTES,1: M_128BYTES,2: M_256BYTES,?..."
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bitfld.long 0x00 10. "FRPSEL,Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible Programmable Receive Parser option is selected" "0: Flexible Receive Parser feature is not selected,1: Flexible Receive Parser feature is selected"
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bitfld.long 0x00 9. "PDUPSEL,Broadcast/Multicast Packet Duplication This bit is set to 1 when the Broadcast/Multicast Packet Duplication feature is selected" "0: Broadcast/Multicast Packet Duplication..,1: Broadcast/Multicast Packet Duplication.."
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bitfld.long 0x00 5. "DVLAN,Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected" "0: Double VLAN option is not selected,1: Double VLAN option is selected"
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bitfld.long 0x00 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected" "0: Enable Queue/Channel based VLAN tag insertion..,1: Enable Queue/Channel based VLAN tag insertion.."
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bitfld.long 0x00 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,?..."
group.long 0x140++0x03
line.long 0x00 "MAC_DPP_FSM_Interrupt_Status,This register contains the status of Automotive Safety related Data Path Parity Errors Interface Timeout Errors FSM State Parity Errors and FSM State Timeout Errors"
bitfld.long 0x00 27. "MRWCPES,MTL RWC data path Parity checker Error Status This filed when set indicates that parity error is detected on the MTL RWC data interface (or at PC12 as shown in Receive data path parity protection diagram)" "0: MTL RWC data path Parity checker Error Status..,1: MTL RWC data path Parity checker Error Status.."
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bitfld.long 0x00 26. "MTFCPES,MAC TFC data path Parity checker Error Status This filed when set indicates that parity error is detected on the MAC TFC data interface (or at PC11 as shown in Transmit data path parity protection diagram)" "0: MAC TFC data path Parity checker Error Status..,1: MAC TFC data path Parity checker Error Status.."
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bitfld.long 0x00 25. "MTBUPES,MAC TBU data path Parity checker Error Status This filed when set indicates that parity error is detected on the MAC TBU data interface (or at PC10 as shown in Transmit data path parity protection diagram)" "0: MAC TBU data path Parity checker Error Status..,1: MAC TBU data path Parity checker Error Status.."
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bitfld.long 0x00 24. "FSMPES,FSM State Parity Error Status This field when set indicates one of the FSMs State registers has a parity error detected" "0: FSM State Parity Error Status not detected,1: FSM State Parity Error Status detected"
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bitfld.long 0x00 16. "MSTTES,Master Read/Write Timeout Error Status This field when set indicates that an Application/CSR Timeout has occurred on the master (AXI/AHB/ARI/ATI) interface" "0: Master Read/Write Timeout Error Status not..,1: Master Read/Write Timeout Error Status detected"
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bitfld.long 0x00 12. "PTES,PTP FSM Timeout Error Status This field when set indicates that one of the PTP FSM Timeout has occurred" "0: PTP FSM Timeout Error Status not detected,1: PTP FSM Timeout Error Status detected"
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bitfld.long 0x00 11. "ATES,APP FSM Timeout Error Status This field when set indicates that one of the APP FSM Timeout has occurred" "0: APP FSM Timeout Error Status not detected,1: APP FSM Timeout Error Status detected"
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bitfld.long 0x00 9. "RTES,Rx FSM Timeout Error Status This field when set indicates that one of the Rx FSM Timeout has occurred" "0: Rx FSM Timeout Error Status not detected,1: Rx FSM Timeout Error Status detected"
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bitfld.long 0x00 8. "TTES,Tx FSM Timeout Error Status This field when set indicates that one of the Tx FSM Timeout has occurred" "0: Tx FSM Timeout Error Status not detected,1: Tx FSM Timeout Error Status detected"
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bitfld.long 0x00 5. "ARPES,Application Receive interface data path Parity Error Status This bit when set indicates that a parity error is detected at the following checkers based on the system configuration: - In MTL configuration (DWC_EQOS_SYS=1) parity checker (PC6 as.." "0: Application Receive interface data path..,1: Application Receive interface data path.."
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bitfld.long 0x00 4. "MTSPES,MTL TX Status data path Parity checker Error Status This filed when set indicates that parity error is detected on the MTL TX Status data on ati interface (or at PC5 as shown in Transmit data path parity protection diagram)" "0: MTL TX Status data path Parity checker Error..,1: MTL TX Status data path Parity checker Error.."
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bitfld.long 0x00 3. "MPES,MTL data path Parity checker Error Status This bit when set indicates that a parity error is detected at the MTL transmit write controller parity checker (or at PC4 as shown in Transmit data path parity protection diagram)" "0: MTL data path Parity checker Error Status not..,1: MTL data path Parity checker Error Status.."
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bitfld.long 0x00 2. "RDPES,Read Descriptor Parity checker Error Status This bit when set indicates that a parity error is detected at the DMA Read descriptor parity checker (or at PC3 as shown in Transmit data path parity protection diagram)" "0: Read Descriptor Parity checker Error Status..,1: Read Descriptor Parity checker Error Status.."
group.long 0x148++0x03
line.long 0x00 "MAC_FSM_Control,This register is used to control the FSM State parity and timeout error injection in Debug mode"
bitfld.long 0x00 28. "PLGRNML,PTP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for PTP domain else normal mode tic generation is used" "0: normal mode tic generation is used for PTP..,1: large mode tic generation is used for PTP.."
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bitfld.long 0x00 27. "ALGRNML,APP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for APP domain else normal mode tic generation is used" "0: normal mode tic generation is used for APP..,1: large mode tic generation is used for APP.."
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bitfld.long 0x00 25. "RLGRNML,Rx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Rx domain else normal mode tic generation is used" "0: normal mode tic generation is used for Rx..,1: large mode tic generation is used for Rx domain"
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bitfld.long 0x00 24. "TLGRNML,Tx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Tx domain else normal mode tic generation is used" "0: normal mode tic generation is used for Tx..,1: large mode tic generation is used for Tx domain"
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bitfld.long 0x00 20. "PPEIN,PTP FSM Parity Error Injection This field when set indicates that Error Injection for PTP FSM Parity is enabled" "0: PTP FSM Parity Error Injection is disabled,1: PTP FSM Parity Error Injection is enabled"
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bitfld.long 0x00 19. "APEIN,APP FSM Parity Error Injection This field when set indicates that Error Injection for APP FSM Parity is enabled" "0: APP FSM Parity Error Injection is disabled,1: APP FSM Parity Error Injection is enabled"
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bitfld.long 0x00 17. "RPEIN,Rx FSM Parity Error Injection This field when set indicates that Error Injection for RX FSM Parity is enabled" "0: Rx FSM Parity Error Injection is disabled,1: Rx FSM Parity Error Injection is enabled"
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bitfld.long 0x00 16. "TPEIN,Tx FSM Parity Error Injection This field when set indicates that Error Injection for TX FSM Parity is enabled" "0: Tx FSM Parity Error Injection is disabled,1: Tx FSM Parity Error Injection is enabled"
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bitfld.long 0x00 12. "PTEIN,PTP FSM Timeout Error Injection This field when set indicates that Error Injection for PTP FSM timeout is enabled" "0: PTP FSM Timeout Error Injection is disabled,1: PTP FSM Timeout Error Injection is enabled"
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bitfld.long 0x00 11. "ATEIN,APP FSM Timeout Error Injection This field when set indicates that Error Injection for APP FSM timeout is enabled" "0: APP FSM Timeout Error Injection is disabled,1: APP FSM Timeout Error Injection is enabled"
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bitfld.long 0x00 9. "RTEIN,Rx FSM Timeout Error Injection This field when set indicates that Error Injection for RX FSM timeout is enabled" "0: Rx FSM Timeout Error Injection is disabled,1: Rx FSM Timeout Error Injection is enabled"
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bitfld.long 0x00 8. "TTEIN,Tx FSM Timeout Error Injection This field when set indicates that Error Injection for TX FSM timeout is enabled" "0: Tx FSM Timeout Error Injection is disabled,1: Tx FSM Timeout Error Injection is enabled"
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bitfld.long 0x00 1. "PRTYEN,This bit when set indicates that the FSM parity feature is enabled" "0: FSM Parity feature is disabled,1: FSM Parity feature is enabled"
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bitfld.long 0x00 0. "TMOUTEN,This bit when set indicates that the FSM timeout feature is enabled" "0: FSM timeout feature is disabled,1: FSM timeout feature is enabled"
group.long 0x14C++0x03
line.long 0x00 "MAC_FSM_ACT_Timer,This register is used to select the FSM and Interface Timeout values"
bitfld.long 0x00 20.--23. "LTMRMD,Large Mode Timeout Value This field provides the mode value to be used for large mode FSM and other interface time outs" "0: Timer disabled,1: M_1MICRO_SEC,2: 1.024ms (~4ms),3: 16.384ms (~16ms),4: 65.536ms (~64ms),5: 262.144ms (~256ms),6: 1.048sec (~1sec),7: 4.194sec (~4sec),8: 16.777sec (~16sec),9: 33.554sec (~32sec),10: 67.108sec (~64sec),?..."
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bitfld.long 0x00 16.--19. "NTMRMD,Normal Mode Timeout Value This field provides the value to be used for normal mode FSM and other interface time outs" "0: Timer disabled,1: M_1MICRO_SEC,2: 1.024ms (~4ms),3: 16.384ms (~16ms),4: 65.536ms (~64ms),5: 262.144ms (~256ms),6: 1.048sec (~1sec),7: 4.194sec (~4sec),8: 16.777sec (~16sec),9: 33.554sec (~32sec),10: 67.108sec (~64sec),?..."
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hexmask.long.word 0x00 0.--9. 1. "TMR,CSR Clocks for 1us Tic This field indicates the number of CSR clocks required to generate 1us tic"
group.long 0x150++0x03
line.long 0x00 "SCS_REG1,NXP Reserved Register"
hexmask.long 0x00 0.--31. 1. "MAC_SCS1,NXP Reserved All the bits must be set to 0"
group.long 0x200++0x03
line.long 0x00 "MAC_MDIO_Address,The MDIO Address register controls the management cycles to external PHY through a management interface"
bitfld.long 0x00 27. "PSE,Preamble Suppression Enable When this bit is set the SMA suppresses the 32-bit preamble and transmits MDIO frames with only 1 preamble bit" "0: Preamble Suppression disabled,1: Preamble Suppression enabled"
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bitfld.long 0x00 26. "BTB,Back to Back transactions When this bit is set and the NTC has value greater than 0 then the MAC informs the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted)" "0: Back to Back transactions disabled,1: Back to Back transactions enabled"
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bitfld.long 0x00 21.--25. "PA,Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. "RDA,Register/Device Address These bits select the PHY register in selected Clause 22 PHY device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--14. "NTC,Number of Trailing Clocks This field controls the number of trailing clock cycles generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "CR,CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design" "0: CSR clock = 60-100 MHz MDC clock = CSR clock/42,1: CSR clock = 100-150 MHz MDC clock = CSR..,2: CSR clock = 20-35 MHz MDC clock = CSR clock/16,3: CSR clock = 35-60 MHz MDC clock = CSR clock/26,4: CSR clock = 150-250 MHz MDC clock = CSR..,5: CSR clock = 250-300 MHz MDC clock = CSR..,6: CSR clock = 300-500 MHz MDC clock = CSR..,7: CSR clock = 500-800 MHz MDC clock = CSR,?,?,?,11: 0) ensures that the MDC clock is approximately,?..."
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bitfld.long 0x00 4. "SKAP,Skip Address Packet When this bit is set the SMA does not send the address packets before read write or post-read increment address packets" "0: Skip Address Packet is disabled,1: Skip Address Packet is enabled"
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bitfld.long 0x00 3. "GOC_1,GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or RevMII GOC_1 and GOC_O is encoded as follows" "0: GMII Operation Command 1 is disabled,1: GMII Operation Command 1 is enabled"
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bitfld.long 0x00 2. "GOC_0,GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII" "0: GMII Operation Command 0 is disabled,1: GMII Operation Command 0 is enabled"
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bitfld.long 0x00 1. "C45E,Clause 45 PHY Enable When this bit is set Clause 45 capable PHY is connected to MDIO" "0: Clause 45 PHY is disabled,1: Clause 45 PHY is enabled"
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bitfld.long 0x00 0. "GB,GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave" "0: GMII Busy is disabled,1: GMII Busy is enabled"
group.long 0x204++0x03
line.long 0x00 "MAC_MDIO_Data,The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in MAC_MDIO_Address"
hexmask.long.word 0x00 16.--31. 1. "RA,Register Address This field is valid only when C45E is set"
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hexmask.long.word 0x00 0.--15. 1. "GD,GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation"
group.long 0x210++0x03
line.long 0x00 "MAC_ARP_Address,The ARP Address register contains the IPv4 Destination Address of the MAC"
hexmask.long 0x00 0.--31. 1. "ARPPA,ARP Protocol Address This field contains the IPv4 Destination Address of the MAC"
group.long 0x230++0x03
line.long 0x00 "MAC_CSR_SW_Ctrl,This register contains software programmable controls for changing the CSR access response and status bits clearing"
bitfld.long 0x00 8. "SEEN,Slave Error Response Enable When this bit is set the MAC responds with Slave Error for accesses to reserved registers in CSR space" "0: Slave Error Response is disabled,1: Slave Error Response is enabled"
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bitfld.long 0x00 0. "RCWE,Register Clear on Write 1 Enable When this bit is set the access mode of some register fields changes to Clear on Write 1 the application needs to set that respective bit to 1 to clear it" "0: Register Clear on Write 1 is disabled,1: Register Clear on Write 1 is enabled"
group.long 0x234++0x03
line.long 0x00 "MAC_FPE_CTRL_STS,This register controls the operation of Frame Preemption"
bitfld.long 0x00 19. "TRSP,Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field)" "0: Not transmitted Respond Frame,1: transmitted Respond Frame"
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bitfld.long 0x00 18. "TVER,Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field)" "0: Not transmitted Verify Frame,1: transmitted Verify Frame"
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bitfld.long 0x00 17. "RRSP,Received Respond Frame Set when a Respond mPacket is received" "0: Not received Respond Frame,1: Received Respond Frame"
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bitfld.long 0x00 16. "RVER,Received Verify Frame Set when a Verify mPacket is received" "0: Not received Verify Frame,1: Received Verify Frame"
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bitfld.long 0x00 3. "S1_SET_0,NXP Reserved Must be set to 0" "0,1"
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bitfld.long 0x00 2. "SRSP,Send Respond mPacket When set indicates hardware to send a Respond mPacket" "0: Send Respond mPacket is disabled,1: Send Respond mPacket is enabled"
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bitfld.long 0x00 1. "SVER,Send Verify mPacket When set indicates hardware to send a verify mPacket" "0: Send Verify mPacket is disabled,1: Send Verify mPacket is enabled"
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bitfld.long 0x00 0. "EFPE,Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled" "0: Tx Frame Preemption is disabled,1: Tx Frame Preemption is enabled"
group.long 0x238++0x03
line.long 0x00 "MAC_Ext_Cfg1,This register contains Split mode control field and offset field for Split Header feature"
bitfld.long 0x00 24. "SAVE,Split AV Enable - When this bit is set to 1 and the received packet is an AV Type packet the header is split at SAVO bytes from the beginning of Length/Type field of the packet for L2 Split" "0,1"
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hexmask.long.byte 0x00 16.--22. 1. "SAVO,Split AV Offset When SAVE bit is set to 1 and the received packet is an AV Type packet these bits indicate the value of the offset from the beginning of Length/Type field at which header should be split when appropriate SPLM is selected"
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bitfld.long 0x00 8.--9. "SPLM,Split Mode These bits indicate the mode of splitting the incoming Rx packets" "0: Split at L3/L4 header,1: Split at L2 header with an offset,2: Combination mode,?..."
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hexmask.long.byte 0x00 0.--6. 1. "SPLOFST,Split Offset These bits indicate the value of offset from the beginning of Length/Type field at which header split should take place when the appropriate SPLM is selected"
rgroup.long 0x240++0x03
line.long 0x00 "MAC_Presn_Time_ns,This register contains the 32-bit binary rollover equivalent time of the PTP System Time in ns Exists when DWC_EQOS_FLEXI_PPS_OUT_EN is configured"
hexmask.long 0x00 0.--31. 1. "MPTN,MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary rollover equivalent time of the PTP System Time in ns"
group.long 0x244++0x03
line.long 0x00 "MAC_Presn_Time_Updt,This field holds the 32-bit value of MAC 1722 Presentation Time in ns that should be added to the Current Presentation Time Counter value"
hexmask.long 0x00 0.--31. 1. "MPTU,MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time"
group.long 0x300++0x03
line.long 0x00 "MAC_Address0_High,The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station"
rbitfld.long 0x00 31. "AE,Address Enable This bit is always set to 1" "0: INVALID,1: This bit is always set to 1"
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bitfld.long 0x00 16.--17. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address0 content is routed" "0,1,2,3"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address"
group.long 0x304++0x03
line.long 0x00 "MAC_Address0_Low,The MAC Address0 Low register holds the lower 32 bits of the 6-byte first MAC address of the station"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address0[31:0] This field contains the lower 32 bits of the first 6-byte MAC address"
group.long 0x308++0x03
line.long 0x00 "MAC_Address1_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--17. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x30C++0x03
line.long 0x00 "MAC_Address1_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x310++0x03
line.long 0x00 "MAC_Address2_High,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station"
bitfld.long 0x00 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering" "0: Address is ignored,1: Address is enabled"
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bitfld.long 0x00 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet" "0: Compare with Destination Address,1: Compare with Source Address"
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bitfld.long 0x00 24.--29. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--17. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed" "0,1,2,3"
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hexmask.long.word 0x00 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address"
group.long 0x314++0x03
line.long 0x00 "MAC_Address2_Low,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station"
hexmask.long 0x00 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address"
group.long 0x700++0x03
line.long 0x00 "MMC_Control,This register establishes the operating mode of MMC"
bitfld.long 0x00 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit" "0: Update MMC Counters for Dropped Broadcast..,1: Update MMC Counters for Dropped Broadcast.."
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bitfld.long 0x00 5. "CNTPRSTLVL,Full-Half Preset When this bit is low and the CNTPRST bit is set all MMC counters get preset to almost-half value" "0: Full-Half Preset is disabled,1: Full-Half Preset is enabled"
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bitfld.long 0x00 4. "CNTPRST,Counters Preset When this bit is set all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit" "0: Counters Preset is disabled,1: Counters Preset is enabled"
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bitfld.long 0x00 3. "CNTFREEZ,MMC Counter Freeze When this bit is set it freezes all MMC counters to their current value" "0: MMC Counter Freeze is disabled,1: MMC Counter Freeze is enabled"
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bitfld.long 0x00 2. "RSTONRD,Reset on Read When this bit is set the MMC counters are reset to zero after Read (self-clearing after reset)" "0: Reset on Read is disabled,1: Reset on Read is enabled"
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bitfld.long 0x00 1. "CNTSTOPRO,Counter Stop Rollover When this bit is set the counter does not roll over to zero after reaching the maximum value" "0: Counter Stop Rollover is disabled,1: Counter Stop Rollover is enabled"
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bitfld.long 0x00 0. "CNTRST,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset"
rgroup.long 0x704++0x03
line.long 0x00 "MMC_Rx_Interrupt,This register maintains the interrupts generated from all Receive statistics counters"
bitfld.long 0x00 27. "RXLPITRCIS,MMC Receive LPI transition counter interrupt status This bit is set when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI transition Counter Interrupt..,1: MMC Receive LPI transition Counter Interrupt.."
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bitfld.long 0x00 26. "RXLPIUSCIS,MMC Receive LPI microsecond counter interrupt status This bit is set when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI microsecond Counter Interrupt..,1: MMC Receive LPI microsecond Counter Interrupt.."
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bitfld.long 0x00 25. "RXCTRLPIS,MMC Receive Control Packet Counter Interrupt Status This bit is set when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.."
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bitfld.long 0x00 24. "RXRCVERRPIS,MMC Receive Error Packet Counter Interrupt Status This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt..,1: MMC Receive Error Packet Counter Interrupt.."
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bitfld.long 0x00 23. "RXWDOGPIS,MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.."
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bitfld.long 0x00 22. "RXVLANGBPIS,MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.."
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bitfld.long 0x00 21. "RXFOVPIS,MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.."
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bitfld.long 0x00 20. "RXPAUSPIS,MMC Receive Pause Packet Counter Interrupt Status This bit is set when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt..,1: MMC Receive Pause Packet Counter Interrupt.."
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bitfld.long 0x00 19. "RXORANGEPIS,MMC Receive Out Of Range Error Packet Counter Interrupt Status" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.."
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bitfld.long 0x00 18. "RXLENERPIS,MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.."
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bitfld.long 0x00 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.."
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bitfld.long 0x00 16. "RX1024TMAXOCTGBPIS,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.."
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bitfld.long 0x00 15. "RX512T1023OCTGBPIS,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.."
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bitfld.long 0x00 14. "RX256T511OCTGBPIS,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.."
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bitfld.long 0x00 13. "RX128T255OCTGBPIS,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.."
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bitfld.long 0x00 12. "RX65T127OCTGBPIS,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.."
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bitfld.long 0x00 11. "RX64OCTGBPIS,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.."
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bitfld.long 0x00 10. "RXOSIZEGPIS,MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.."
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bitfld.long 0x00 9. "RXUSIZEGPIS,MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.."
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bitfld.long 0x00 8. "RXJABERPIS,MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.."
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bitfld.long 0x00 7. "RXRUNTPIS,MMC Receive Runt Packet Counter Interrupt Status This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt..,1: MMC Receive Runt Packet Counter Interrupt.."
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bitfld.long 0x00 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.."
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bitfld.long 0x00 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter..,1: MMC Receive CRC Error Packet Counter.."
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bitfld.long 0x00 4. "RXMCGPIS,MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.."
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bitfld.long 0x00 3. "RXBCGPIS,MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.."
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bitfld.long 0x00 2. "RXGOCTIS,MMC Receive Good Octet Counter Interrupt Status This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt..,1: MMC Receive Good Octet Counter Interrupt.."
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bitfld.long 0x00 1. "RXGBOCTIS,MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.."
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bitfld.long 0x00 0. "RXGBPKTIS,MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.."
rgroup.long 0x708++0x03
line.long 0x00 "MMC_Tx_Interrupt,This register maintains the interrupts generated from all Transmit statistics counters"
bitfld.long 0x00 27. "TXLPITRCIS,MMC Transmit LPI transition counter interrupt status This bit is set when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI transition Counter Interrupt..,1: MMC Transmit LPI transition Counter Interrupt.."
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bitfld.long 0x00 26. "TXLPIUSCIS,MMC Transmit LPI microsecond counter interrupt status This bit is set when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI microsecond Counter..,1: MMC Transmit LPI microsecond Counter.."
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bitfld.long 0x00 25. "TXOSIZEGPIS,MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.."
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bitfld.long 0x00 24. "TXVLANGPIS,MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter..,1: MMC Transmit VLAN Good Packet Counter.."
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bitfld.long 0x00 23. "TXPAUSPIS,MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the txpausepacketserror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt..,1: MMC Transmit Pause Packet Counter Interrupt.."
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bitfld.long 0x00 22. "TXEXDEFPIS,MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet..,1: MMC Transmit Excessive Deferral Packet.."
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bitfld.long 0x00 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt..,1: MMC Transmit Good Packet Counter Interrupt.."
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bitfld.long 0x00 20. "TXGOCTIS,MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt..,1: MMC Transmit Good Octet Counter Interrupt.."
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bitfld.long 0x00 19. "TXCARERPIS,MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.."
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bitfld.long 0x00 18. "TXEXCOLPIS,MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet..,1: MMC Transmit Excessive Collision Packet.."
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bitfld.long 0x00 17. "TXLATCOLPIS,MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.."
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bitfld.long 0x00 16. "TXDEFPIS,MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter..,1: MMC Transmit Deferred Packet Counter.."
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bitfld.long 0x00 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.."
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bitfld.long 0x00 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.."
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bitfld.long 0x00 13. "TXUFLOWERPIS,MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.."
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bitfld.long 0x00 12. "TXBCGBPIS,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet..,1: MMC Transmit Broadcast Good Bad Packet.."
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bitfld.long 0x00 11. "TXMCGBPIS,MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet..,1: MMC Transmit Multicast Good Bad Packet.."
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bitfld.long 0x00 10. "TXUCGBPIS,MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.."
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bitfld.long 0x00 9. "TX1024TMAXOCTGBPIS,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.."
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bitfld.long 0x00 8. "TX512T1023OCTGBPIS,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad..,1: MMC Transmit 512 to 1023 Octet Good Bad.."
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bitfld.long 0x00 7. "TX256T511OCTGBPIS,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.."
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bitfld.long 0x00 6. "TX128T255OCTGBPIS,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.."
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bitfld.long 0x00 5. "TX65T127OCTGBPIS,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half the maximum value and also when it reaches the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.."
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bitfld.long 0x00 4. "TX64OCTGBPIS,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.."
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bitfld.long 0x00 3. "TXMCGPIS,MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.."
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bitfld.long 0x00 2. "TXBCGPIS,MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.."
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bitfld.long 0x00 1. "TXGBPKTIS,MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter..,1: MMC Transmit Good Bad Packet Counter.."
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bitfld.long 0x00 0. "TXGBOCTIS,MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.."
group.long 0x70C++0x03
line.long 0x00 "MMC_Rx_Interrupt_Mask,This register maintains the masks for interrupts generated from all Receive statistics counters"
bitfld.long 0x00 27. "RXLPITRCIM,MMC Receive LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI transition counter interrupt..,1: MMC Receive LPI transition counter interrupt.."
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bitfld.long 0x00 26. "RXLPIUSCIM,MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Receive LPI microsecond counter interrupt..,1: MMC Receive LPI microsecond counter interrupt.."
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bitfld.long 0x00 25. "RXCTRLPIM,MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Control Packet Counter Interrupt..,1: MMC Receive Control Packet Counter Interrupt.."
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bitfld.long 0x00 24. "RXRCVERRPIM,MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Error Packet Counter Interrupt..,1: MMC Receive Error Packet Counter Interrupt.."
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bitfld.long 0x00 23. "RXWDOGPIM,MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value" "0: MMC Receive Watchdog Error Packet Counter..,1: MMC Receive Watchdog Error Packet Counter.."
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bitfld.long 0x00 22. "RXVLANGBPIM,MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive VLAN Good Bad Packet Counter..,1: MMC Receive VLAN Good Bad Packet Counter.."
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bitfld.long 0x00 21. "RXFOVPIM,MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value" "0: MMC Receive FIFO Overflow Packet Counter..,1: MMC Receive FIFO Overflow Packet Counter.."
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bitfld.long 0x00 20. "RXPAUSPIM,MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Receive Pause Packet Counter Interrupt..,1: MMC Receive Pause Packet Counter Interrupt.."
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bitfld.long 0x00 19. "RXORANGEPIM,MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value" "0: MMC Receive Out Of Range Error Packet Counter..,1: MMC Receive Out Of Range Error Packet Counter.."
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bitfld.long 0x00 18. "RXLENERPIM,MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Length Error Packet Counter..,1: MMC Receive Length Error Packet Counter.."
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bitfld.long 0x00 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Unicast Good Packet Counter..,1: MMC Receive Unicast Good Packet Counter.."
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bitfld.long 0x00 16. "RX1024TMAXOCTGBPIM,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask" "0: MMC Receive 1024 to Maximum Octet Good Bad..,1: MMC Receive 1024 to Maximum Octet Good Bad.."
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bitfld.long 0x00 15. "RX512T1023OCTGBPIM,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 512 to 1023 Octet Good Bad Packet..,1: MMC Receive 512 to 1023 Octet Good Bad Packet.."
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bitfld.long 0x00 14. "RX256T511OCTGBPIM,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 256 to 511 Octet Good Bad Packet..,1: MMC Receive 256 to 511 Octet Good Bad Packet.."
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bitfld.long 0x00 13. "RX128T255OCTGBPIM,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 128 to 255 Octet Good Bad Packet..,1: MMC Receive 128 to 255 Octet Good Bad Packet.."
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bitfld.long 0x00 12. "RX65T127OCTGBPIM,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 65 to 127 Octet Good Bad Packet..,1: MMC Receive 65 to 127 Octet Good Bad Packet.."
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bitfld.long 0x00 11. "RX64OCTGBPIM,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive 64 Octet Good Bad Packet Counter..,1: MMC Receive 64 Octet Good Bad Packet Counter.."
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bitfld.long 0x00 10. "RXOSIZEGPIM,MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Oversize Good Packet Counter..,1: MMC Receive Oversize Good Packet Counter.."
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bitfld.long 0x00 9. "RXUSIZEGPIM,MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Undersize Good Packet Counter..,1: MMC Receive Undersize Good Packet Counter.."
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bitfld.long 0x00 8. "RXJABERPIM,MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Jabber Error Packet Counter..,1: MMC Receive Jabber Error Packet Counter.."
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bitfld.long 0x00 7. "RXRUNTPIM,MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Runt Packet Counter Interrupt..,1: MMC Receive Runt Packet Counter Interrupt.."
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bitfld.long 0x00 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value" "0: MMC Receive Alignment Error Packet Counter..,1: MMC Receive Alignment Error Packet Counter.."
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bitfld.long 0x00 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value" "0: MMC Receive CRC Error Packet Counter..,1: MMC Receive CRC Error Packet Counter.."
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bitfld.long 0x00 4. "RXMCGPIM,MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Multicast Good Packet Counter..,1: MMC Receive Multicast Good Packet Counter.."
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bitfld.long 0x00 3. "RXBCGPIM,MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Broadcast Good Packet Counter..,1: MMC Receive Broadcast Good Packet Counter.."
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bitfld.long 0x00 2. "RXGOCTIM,MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Octet Counter Interrupt Mask..,1: MMC Receive Good Octet Counter Interrupt Mask.."
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bitfld.long 0x00 1. "RXGBOCTIM,MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Octet Counter Interrupt..,1: MMC Receive Good Bad Octet Counter Interrupt.."
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bitfld.long 0x00 0. "RXGBPKTIM,MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Receive Good Bad Packet Counter Interrupt..,1: MMC Receive Good Bad Packet Counter Interrupt.."
group.long 0x710++0x03
line.long 0x00 "MMC_Tx_Interrupt_Mask,This register maintains the masks for interrupts generated from all Transmit statistics counters"
bitfld.long 0x00 27. "TXLPITRCIM,MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI transition counter interrupt..,1: MMC Transmit LPI transition counter interrupt.."
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bitfld.long 0x00 26. "TXLPIUSCIM,MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit LPI microsecond counter..,1: MMC Transmit LPI microsecond counter.."
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bitfld.long 0x00 25. "TXOSIZEGPIM,MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Oversize Good Packet Counter..,1: MMC Transmit Oversize Good Packet Counter.."
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bitfld.long 0x00 24. "TXVLANGPIM,MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit VLAN Good Packet Counter..,1: MMC Transmit VLAN Good Packet Counter.."
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bitfld.long 0x00 23. "TXPAUSPIM,MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Pause Packet Counter Interrupt..,1: MMC Transmit Pause Packet Counter Interrupt.."
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bitfld.long 0x00 22. "TXEXDEFPIM,MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Deferral Packet..,1: MMC Transmit Excessive Deferral Packet.."
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bitfld.long 0x00 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Packet Counter Interrupt..,1: MMC Transmit Good Packet Counter Interrupt.."
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bitfld.long 0x00 20. "TXGOCTIM,MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Octet Counter Interrupt..,1: MMC Transmit Good Octet Counter Interrupt.."
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bitfld.long 0x00 19. "TXCARERPIM,MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Carrier Error Packet Counter..,1: MMC Transmit Carrier Error Packet Counter.."
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bitfld.long 0x00 18. "TXEXCOLPIM,MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Excessive Collision Packet..,1: MMC Transmit Excessive Collision Packet.."
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bitfld.long 0x00 17. "TXLATCOLPIM,MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Late Collision Packet Counter..,1: MMC Transmit Late Collision Packet Counter.."
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bitfld.long 0x00 16. "TXDEFPIM,MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Deferred Packet Counter..,1: MMC Transmit Deferred Packet Counter.."
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bitfld.long 0x00 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multiple Collision Good Packet..,1: MMC Transmit Multiple Collision Good Packet.."
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bitfld.long 0x00 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Single Collision Good Packet..,1: MMC Transmit Single Collision Good Packet.."
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bitfld.long 0x00 13. "TXUFLOWERPIM,MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Underflow Error Packet Counter..,1: MMC Transmit Underflow Error Packet Counter.."
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bitfld.long 0x00 12. "TXBCGBPIM,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Bad Packet..,1: MMC Transmit Broadcast Good Bad Packet.."
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bitfld.long 0x00 11. "TXMCGBPIM,MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Bad Packet..,1: MMC Transmit Multicast Good Bad Packet.."
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bitfld.long 0x00 10. "TXUCGBPIM,MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Unicast Good Bad Packet Counter..,1: MMC Transmit Unicast Good Bad Packet Counter.."
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bitfld.long 0x00 9. "TX1024TMAXOCTGBPIM,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 1024 to Maximum Octet Good Bad..,1: MMC Transmit 1024 to Maximum Octet Good Bad.."
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bitfld.long 0x00 8. "TX512T1023OCTGBPIM,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 512 to 1023 Octet Good Bad..,1: MMC Transmit 512 to 1023 Octet Good Bad.."
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bitfld.long 0x00 7. "TX256T511OCTGBPIM,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 256 to 511 Octet Good Bad Packet..,1: MMC Transmit 256 to 511 Octet Good Bad Packet.."
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bitfld.long 0x00 6. "TX128T255OCTGBPIM,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 128 to 255 Octet Good Bad Packet..,1: MMC Transmit 128 to 255 Octet Good Bad Packet.."
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bitfld.long 0x00 5. "TX65T127OCTGBPIM,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 65 to 127 Octet Good Bad Packet..,1: MMC Transmit 65 to 127 Octet Good Bad Packet.."
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bitfld.long 0x00 4. "TX64OCTGBPIM,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit 64 Octet Good Bad Packet Counter..,1: MMC Transmit 64 Octet Good Bad Packet Counter.."
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bitfld.long 0x00 3. "TXMCGPIM,MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Multicast Good Packet Counter..,1: MMC Transmit Multicast Good Packet Counter.."
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bitfld.long 0x00 2. "TXBCGPIM,MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Broadcast Good Packet Counter..,1: MMC Transmit Broadcast Good Packet Counter.."
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bitfld.long 0x00 1. "TXGBPKTIM,MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Packet Counter..,1: MMC Transmit Good Bad Packet Counter.."
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bitfld.long 0x00 0. "TXGBOCTIM,MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Good Bad Octet Counter Interrupt..,1: MMC Transmit Good Bad Octet Counter Interrupt.."
rgroup.long 0x714++0x03
line.long 0x00 "Tx_Octet_Count_Good_Bad,This register provides the number of bytes transmitted by the DWC_ether_qos exclusive of preamble and retried bytes in good and bad packets"
hexmask.long 0x00 0.--31. 1. "TXOCTGB,Tx Octet Count Good Bad This field indicates the number of bytes transmitted exclusive of preamble and retried bytes in good and bad packets"
rgroup.long 0x718++0x03
line.long 0x00 "Tx_Packet_Count_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos exclusive of retried packets"
hexmask.long 0x00 0.--31. 1. "TXPKTGB,Tx Packet Count Good Bad This field indicates the number of good and bad packets transmitted exclusive of retried packets"
rgroup.long 0x71C++0x03
line.long 0x00 "Tx_Broadcast_Packets_Good,This register provides the number of good broadcast packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXBCASTG,Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted"
rgroup.long 0x720++0x03
line.long 0x00 "Tx_Multicast_Packets_Good,This register provides the number of good multicast packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXMCASTG,Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted"
rgroup.long 0x724++0x03
line.long 0x00 "Tx_64Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 64 bytes exclusive of preamble and retried packets"
hexmask.long 0x00 0.--31. 1. "TX64OCTGB,Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets transmitted with length 64 bytes exclusive of preamble and retried packets"
rgroup.long 0x728++0x03
line.long 0x00 "Tx_65To127Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried packets"
hexmask.long 0x00 0.--31. 1. "TX65_127OCTGB,Tx 65To127Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x72C++0x03
line.long 0x00 "Tx_128To255Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 128 to 255 (inclusive) bytes exclusive of preamble and retried packets"
hexmask.long 0x00 0.--31. 1. "TX128_255OCTGB,Tx 128To255Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 128 and 255 (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x730++0x03
line.long 0x00 "Tx_256To511Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 256 to 511 (inclusive) bytes exclusive of preamble and retried packets"
hexmask.long 0x00 0.--31. 1. "TX256_511OCTGB,Tx 256To511Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 256 and 511 (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x734++0x03
line.long 0x00 "Tx_512To1023Octets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 512 to 1023 (inclusive) bytes exclusive of preamble and retried packets"
hexmask.long 0x00 0.--31. 1. "TX512_1023OCTGB,Tx 512To1023Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 512 and 1023 (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x738++0x03
line.long 0x00 "Tx_1024ToMaxOctets_Packets_Good_Bad,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 1024 to maxsize (inclusive) bytes exclusive of preamble and retried packets"
hexmask.long 0x00 0.--31. 1. "TX1024_MAXOCTGB,Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes exclusive of preamble and retried packets"
rgroup.long 0x73C++0x03
line.long 0x00 "Tx_Unicast_Packets_Good_Bad,This register provides the number of good and bad unicast packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXUCASTGB,Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted"
rgroup.long 0x740++0x03
line.long 0x00 "Tx_Multicast_Packets_Good_Bad,This register provides the number of good and bad multicast packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXMCASTGB,Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted"
rgroup.long 0x744++0x03
line.long 0x00 "Tx_Broadcast_Packets_Good_Bad,This register provides the number of good and bad broadcast packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXBCASTGB,Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted"
rgroup.long 0x748++0x03
line.long 0x00 "Tx_Underflow_Error_Packets,This register provides the number of packets aborted by DWC_ether_qos because of packets underflow error"
hexmask.long 0x00 0.--31. 1. "TXUNDRFLW,Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error"
rgroup.long 0x74C++0x03
line.long 0x00 "Tx_Single_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_ether_qos after a single collision in the half-duplex mode"
hexmask.long 0x00 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode"
rgroup.long 0x750++0x03
line.long 0x00 "Tx_Multiple_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_ether_qos after multiple collisions in the half-duplex mode"
hexmask.long 0x00 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode"
rgroup.long 0x754++0x03
line.long 0x00 "Tx_Deferred_Packets,This register provides the number of successfully transmitted by DWC_ether_qos after a deferral in the half-duplex mode"
hexmask.long 0x00 0.--31. 1. "TXDEFRD,Tx Deferred Packets This field indicates the number of successfully transmitted after a deferral in the half-duplex mode"
rgroup.long 0x758++0x03
line.long 0x00 "Tx_Late_Collision_Packets,This register provides the number of packets aborted by DWC_ether_qos because of late collision error"
hexmask.long 0x00 0.--31. 1. "TXLATECOL,Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error"
rgroup.long 0x75C++0x03
line.long 0x00 "Tx_Excessive_Collision_Packets,This register provides the number of packets aborted by DWC_ether_qos because of excessive (16) collision errors"
hexmask.long 0x00 0.--31. 1. "TXEXSCOL,Tx Excessive Collision Packets This field indicates the number of packets aborted because of excessive (16) collision errors"
rgroup.long 0x760++0x03
line.long 0x00 "Tx_Carrier_Error_Packets,This register provides the number of packets aborted by DWC_ether_qos because of carrier sense error (no carrier or loss of carrier)"
hexmask.long 0x00 0.--31. 1. "TXCARR,Tx Carrier Error Packets This field indicates the number of packets aborted because of carrier sense error (no carrier or loss of carrier)"
rgroup.long 0x764++0x03
line.long 0x00 "Tx_Octet_Count_Good,This register provides the number of bytes transmitted by DWC_ether_qos exclusive of preamble only in good packets"
hexmask.long 0x00 0.--31. 1. "TXOCTG,Tx Octet Count Good This field indicates the number of bytes transmitted exclusive of preamble only in good packets"
rgroup.long 0x768++0x03
line.long 0x00 "Tx_Packet_Count_Good,This register provides the number of good packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXPKTG,Tx Packet Count Good This field indicates the number of good packets transmitted"
rgroup.long 0x76C++0x03
line.long 0x00 "Tx_Excessive_Deferral_Error,This register provides the number of packets aborted by DWC_ether_qos because of excessive deferral error (deferred for more than two max-sized packet times)"
hexmask.long 0x00 0.--31. 1. "TXEXSDEF,Tx Excessive Deferral Error This field indicates the number of packets aborted because of excessive deferral error (deferred for more than two max-sized packet times)"
rgroup.long 0x770++0x03
line.long 0x00 "Tx_Pause_Packets,This register provides the number of good Pause packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXPAUSE,Tx Pause Packets This field indicates the number of good Pause packets transmitted"
rgroup.long 0x774++0x03
line.long 0x00 "Tx_VLAN_Packets_Good,This register provides the number of good VLAN packets transmitted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXVLANG,Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted"
rgroup.long 0x778++0x03
line.long 0x00 "Tx_OSize_Packets_Good,This register provides the number of packets transmitted by DWC_ether_qos without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged packets 2000 bytes if enabled in S2KP bit of the.."
hexmask.long 0x00 0.--31. 1. "TXOSIZG,Tx OSize Packets Good This field indicates the number of packets transmitted without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged packets 2000 bytes if enabled in S2KP bit of the MAC_Configuration register)"
rgroup.long 0x780++0x03
line.long 0x00 "Rx_Packets_Count_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXPKTGB,Rx Packets Count Good Bad This field indicates the number of good and bad packets received"
rgroup.long 0x784++0x03
line.long 0x00 "Rx_Octet_Count_Good_Bad,This register provides the number of bytes received by DWC_ther_qos exclusive of preamble in good and bad packets"
hexmask.long 0x00 0.--31. 1. "RXOCTGB,Rx Octet Count Good Bad This field indicates the number of bytes received exclusive of preamble in good and bad packets"
rgroup.long 0x788++0x03
line.long 0x00 "Rx_Octet_Count_Good,This register provides the number of bytes received by DWC_ether_qos exclusive of preamble only in good packets"
hexmask.long 0x00 0.--31. 1. "RXOCTG,Rx Octet Count Good This field indicates the number of bytes received exclusive of preamble only in good packets"
rgroup.long 0x78C++0x03
line.long 0x00 "Rx_Broadcast_Packets_Good,This register provides the number of good broadcast packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXBCASTG,Rx Broadcast Packets Good This field indicates the number of good broadcast packets received"
rgroup.long 0x790++0x03
line.long 0x00 "Rx_Multicast_Packets_Good,This register provides the number of good multicast packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXMCASTG,Rx Multicast Packets Good This field indicates the number of good multicast packets received"
rgroup.long 0x794++0x03
line.long 0x00 "Rx_CRC_Error_Packets,This register provides the number of packets received by DWC_ether_qos with CRC error"
hexmask.long 0x00 0.--31. 1. "RXCRCERR,Rx CRC Error Packets This field indicates the number of packets received with CRC error"
rgroup.long 0x798++0x03
line.long 0x00 "Rx_Alignment_Error_Packets,This register provides the number of packets received by DWC_ether_qos with alignment (dribble) error"
hexmask.long 0x00 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error"
rgroup.long 0x79C++0x03
line.long 0x00 "Rx_Runt_Error_Packets,This register provides the number of packets received by DWC_ether_qos with runt (length less than 64 bytes and CRC error) error"
hexmask.long 0x00 0.--31. 1. "RXRUNTERR,Rx Runt Error Packets This field indicates the number of packets received with runt (length less than 64 bytes and CRC error) error"
rgroup.long 0x7A0++0x03
line.long 0x00 "Rx_Jabber_Error_Packets,This register provides the number of giant packets received by DWC_ether_qos with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error"
hexmask.long 0x00 0.--31. 1. "RXJABERR,Rx Jabber Error Packets This field indicates the number of giant packets received with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error"
rgroup.long 0x7A4++0x03
line.long 0x00 "Rx_Undersize_Packets_Good,This register provides the number of packets received by DWC_ether_qos with length less than 64 bytes without any errors"
hexmask.long 0x00 0.--31. 1. "RXUNDERSZG,Rx Undersize Packets Good This field indicates the number of packets received with length less than 64 bytes without any errors"
rgroup.long 0x7A8++0x03
line.long 0x00 "Rx_Oversize_Packets_Good,This register provides the number of packets received by DWC_ether_qos without errors with length greater than the maxsize (1 518 bytes or 1 522 bytes for VLAN tagged packets 2000 bytes if enabled in the S2KP bit of the.."
hexmask.long 0x00 0.--31. 1. "RXOVERSZG,Rx Oversize Packets Good This field indicates the number of packets received without errors with length greater than the maxsize (1 518 bytes or 1 522 bytes for VLAN tagged packets 2000 bytes if enabled in the S2KP bit of the MAC_Configuration.."
rgroup.long 0x7AC++0x03
line.long 0x00 "Rx_64Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length 64 bytes exclusive of the preamble"
hexmask.long 0x00 0.--31. 1. "RX64OCTGB,Rx 64 Octets Packets Good Bad This field indicates the number of good and bad packets received with length 64 bytes exclusive of the preamble"
rgroup.long 0x7B0++0x03
line.long 0x00 "Rx_65To127Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 65 and 127 (inclusive) bytes exclusive of the preamble"
hexmask.long 0x00 0.--31. 1. "RX65_127OCTGB,Rx 65-127 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 65 and 127 (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7B4++0x03
line.long 0x00 "Rx_128To255Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 128 and 255 (inclusive) bytes exclusive of the preamble"
hexmask.long 0x00 0.--31. 1. "RX128_255OCTGB,Rx 128-255 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 128 and 255 (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7B8++0x03
line.long 0x00 "Rx_256To511Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 256 and 511 (inclusive) bytes exclusive of the preamble"
hexmask.long 0x00 0.--31. 1. "RX256_511OCTGB,Rx 256-511 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 256 and 511 (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7BC++0x03
line.long 0x00 "Rx_512To1023Octets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 512 and 1023 (inclusive) bytes exclusive of the preamble"
hexmask.long 0x00 0.--31. 1. "RX512_1023OCTGB,RX 512-1023 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 512 and 1023 (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7C0++0x03
line.long 0x00 "Rx_1024ToMaxOctets_Packets_Good_Bad,This register provides the number of good and bad packets received by DWC_ether_qos with length between 1024 and maxsize (inclusive) bytes exclusive of the preamble"
hexmask.long 0x00 0.--31. 1. "RX1024_MAXOCTGB,Rx 1024-Max Octets Good Bad This field indicates the number of good and bad packets received with length between 1024 and maxsize (inclusive) bytes exclusive of the preamble"
rgroup.long 0x7C4++0x03
line.long 0x00 "Rx_Unicast_Packets_Good,This register provides the number of good unicast packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good This field indicates the number of good unicast packets received"
rgroup.long 0x7C8++0x03
line.long 0x00 "Rx_Length_Error_Packets,This register provides the number of packets received by DWC_ether_qos with length error (Length Type field not equal to packet size) for all packets with valid length field"
hexmask.long 0x00 0.--31. 1. "RXLENERR,Rx Length Error Packets This field indicates the number of packets received with length error (Length Type field not equal to packet size) for all packets with valid length field"
rgroup.long 0x7CC++0x03
line.long 0x00 "Rx_Out_Of_Range_Type_Packets,This register provides the number of packets received by DWC_ether_qos with length field not equal to the valid packet size (greater than 1 500 but less than 1 536)"
hexmask.long 0x00 0.--31. 1. "RXOUTOFRNG,Rx Out of Range Type Packet This field indicates the number of packets received with length field not equal to the valid packet size (greater than 1 500 but less than 1 536)"
rgroup.long 0x7D0++0x03
line.long 0x00 "Rx_Pause_Packets,This register provides the number of good and valid Pause packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXPAUSEPKT,Rx Pause Packets This field indicates the number of good and valid Pause packets received"
rgroup.long 0x7D4++0x03
line.long 0x00 "Rx_FIFO_Overflow_Packets,This register provides the number of missed received packets because of FIFO overflow in DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXFIFOOVFL,Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow"
rgroup.long 0x7D8++0x03
line.long 0x00 "Rx_VLAN_Packets_Good_Bad,This register provides the number of good and bad VLAN packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXVLANPKTGB,Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received"
rgroup.long 0x7DC++0x03
line.long 0x00 "Rx_Watchdog_Error_Packets,This register provides the number of packets received by DWC_ether_qos with error because of watchdog timeout error (packets with a data load larger than 2 048 bytes (when JE and WD bits are reset in MAC_Configuration register).."
hexmask.long 0x00 0.--31. 1. "RXWDGERR,Rx Watchdog Error Packets This field indicates the number of packets received with error because of watchdog timeout error (packets with a data load larger than 2 048 bytes (when JE and WD bits are reset in MAC_Configuration register) 10 240.."
rgroup.long 0x7E0++0x03
line.long 0x00 "Rx_Receive_Error_Packets,This register provides the number of packets received by DWC_ether_qos with Receive error or Packet Extension error on the GMII or MII interface"
hexmask.long 0x00 0.--31. 1. "RXRCVERR,Rx Receive Error Packets This field indicates the number of packets received with Receive error or Packet Extension error on the GMII or MII interface"
rgroup.long 0x7E4++0x03
line.long 0x00 "Rx_Control_Packets_Good,This register provides the number of good control packets received by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXCTRLG,Rx Control Packets Good This field indicates the number of good control packets received"
rgroup.long 0x7EC++0x03
line.long 0x00 "Tx_LPI_USEC_Cntr,This register provides the number of microseconds Tx LPI is asserted by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "TXLPIUSC,Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted"
rgroup.long 0x7F0++0x03
line.long 0x00 "Tx_LPI_Tran_Cntr,This register provides the number of times DWC_ether_qos has entered Tx LPI"
hexmask.long 0x00 0.--31. 1. "TXLPITRC,Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred"
rgroup.long 0x7F4++0x03
line.long 0x00 "Rx_LPI_USEC_Cntr,This register provides the number of microseconds Rx LPI is sampled by DWC_ether_qos"
hexmask.long 0x00 0.--31. 1. "RXLPIUSC,Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted"
rgroup.long 0x7F8++0x03
line.long 0x00 "Rx_LPI_Tran_Cntr,This register provides the number of times DWC_ether_qos has entered Rx LPI"
hexmask.long 0x00 0.--31. 1. "RXLPITRC,Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred"
rgroup.long 0x8A0++0x03
line.long 0x00 "MMC_FPE_Tx_Interrupt,This register maintains the interrupts generated from all FPE related Transmit statistics counters"
bitfld.long 0x00 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx Hold Request Counter Interrupt Status..,1: MMC Tx Hold Request Counter Interrupt Status.."
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bitfld.long 0x00 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status This bit is set when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Tx FPE Fragment Counter Interrupt status..,1: MMC Tx FPE Fragment Counter Interrupt status.."
group.long 0x8A4++0x03
line.long 0x00 "MMC_FPE_Tx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Transmit statistics counters"
bitfld.long 0x00 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Hold Request Counter Interrupt..,1: MMC Transmit Hold Request Counter Interrupt.."
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bitfld.long 0x00 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Transmit Fragment Counter Interrupt Mask..,1: MMC Transmit Fragment Counter Interrupt Mask.."
rgroup.long 0x8A8++0x03
line.long 0x00 "MMC_Tx_FPE_Fragment_Cntr,This register provides the number of additional mPackets transmitted due to preemption"
hexmask.long 0x00 0.--31. 1. "TXFFC,Tx FPE Fragment counter This field indicates the number of additional mPackets that has been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled during FPE Enabled configuration"
rgroup.long 0x8AC++0x03
line.long 0x00 "MMC_Tx_Hold_Req_Cntr,This register provides the count of number of times a hold request is given to MAC"
hexmask.long 0x00 0.--31. 1. "TXHRC,Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC"
rgroup.long 0x8C0++0x03
line.long 0x00 "MMC_FPE_Rx_Interrupt,This register maintains the interrupts generated from all FPE related Receive statistics counters"
bitfld.long 0x00 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Status..,1: MMC Rx FPE Fragment Counter Interrupt Status.."
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bitfld.long 0x00 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt..,1: MMC Rx Packet Assembly OK Counter Interrupt.."
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bitfld.long 0x00 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt..,1: MMC Rx Packet SMD Error Counter Interrupt.."
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bitfld.long 0x00 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter..,1: MMC Rx Packet Assembly Error Counter.."
group.long 0x8C4++0x03
line.long 0x00 "MMC_FPE_Rx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Receive statistics counters"
bitfld.long 0x00 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx FPE Fragment Counter Interrupt Mask is..,1: MMC Rx FPE Fragment Counter Interrupt Mask is.."
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bitfld.long 0x00 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly OK Counter Interrupt..,1: MMC Rx Packet Assembly OK Counter Interrupt.."
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bitfld.long 0x00 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet SMD Error Counter Interrupt..,1: MMC Rx Packet SMD Error Counter Interrupt.."
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bitfld.long 0x00 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value" "0: MMC Rx Packet Assembly Error Counter..,1: MMC Rx Packet Assembly Error Counter.."
rgroup.long 0x8C8++0x03
line.long 0x00 "MMC_Rx_Packet_Assembly_Err_Cntr,This register provides the number of MAC frames with reassembly errors on the Receiver due to mismatch in the Fragment Count value"
hexmask.long 0x00 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter This field indicates the number of MAC frames with reassembly errors on the Receiver due to mismatch in the Fragment Count value"
rgroup.long 0x8CC++0x03
line.long 0x00 "MMC_Rx_Packet_SMD_Err_Cntr,This register provides the number of received MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame"
hexmask.long 0x00 0.--31. 1. "PSEC,Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame"
rgroup.long 0x8D0++0x03
line.long 0x00 "MMC_Rx_Packet_Assembly_OK_Cntr,This register provides the number of MAC frames that were successfully reassembled and delivered to MAC"
hexmask.long 0x00 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were successfully reassembled and delivered to MAC"
rgroup.long 0x8D4++0x03
line.long 0x00 "MMC_Rx_FPE_Fragment_Cntr,This register provides the number of additional mPackets received due to preemption"
hexmask.long 0x00 0.--31. 1. "FFC,Rx FPE Fragment Counter This field indicates the number of additional mPackets received due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE Enabled configuration"
group.long 0x900++0x03
line.long 0x00 "MAC_L3_L4_Control0,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4"
bitfld.long 0x00 28. "DMCHEN0,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
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bitfld.long 0x00 24. "DMCHN0,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1"
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bitfld.long 0x00 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
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bitfld.long 0x00 20. "L4DPM0,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
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bitfld.long 0x00 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
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bitfld.long 0x00 18. "L4SPM0,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
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bitfld.long 0x00 16. "L4PEN0,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
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bitfld.long 0x00 11.--15. "L3HDBM0,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--10. "L3HSBM0,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
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bitfld.long 0x00 4. "L3DAM0,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
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bitfld.long 0x00 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
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bitfld.long 0x00 2. "L3SAM0,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
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bitfld.long 0x00 0. "L3PEN0,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x904++0x03
line.long 0x00 "MAC_Layer4_Address0,The MAC_Layer4_Address(#i) MAC_L3_L4_Control(#i) MAC_Layer3_Addr0_Reg(#i) MAC_Layer3_Addr1_Reg(#i) MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.."
hexmask.long.word 0x00 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
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hexmask.long.word 0x00 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0x910++0x03
line.long 0x00 "MAC_Layer3_Addr0_Reg0,For IPv4 packets the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field"
hexmask.long 0x00 0.--31. 1. "L3A00,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0x914++0x03
line.long 0x00 "MAC_Layer3_Addr1_Reg0,For IPv4 packets the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field"
hexmask.long 0x00 0.--31. 1. "L3A10,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0x918++0x03
line.long 0x00 "MAC_Layer3_Addr2_Reg0,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A20,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0x91C++0x03
line.long 0x00 "MAC_Layer3_Addr3_Reg0,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A30,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0x930++0x03
line.long 0x00 "MAC_L3_L4_Control1,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4"
bitfld.long 0x00 28. "DMCHEN1,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
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bitfld.long 0x00 24. "DMCHN1,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1"
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bitfld.long 0x00 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
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bitfld.long 0x00 20. "L4DPM1,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
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bitfld.long 0x00 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
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bitfld.long 0x00 18. "L4SPM1,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
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bitfld.long 0x00 16. "L4PEN1,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
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bitfld.long 0x00 11.--15. "L3HDBM1,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--10. "L3HSBM1,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
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bitfld.long 0x00 4. "L3DAM1,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
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bitfld.long 0x00 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
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bitfld.long 0x00 2. "L3SAM1,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
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bitfld.long 0x00 0. "L3PEN1,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x934++0x03
line.long 0x00 "MAC_Layer4_Address1,The MAC_Layer4_Address(#i) MAC_L3_L4_Control(#i) MAC_Layer3_Addr0_Reg(#i) MAC_Layer3_Addr1_Reg(#i) MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.."
hexmask.long.word 0x00 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
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hexmask.long.word 0x00 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0x940++0x03
line.long 0x00 "MAC_Layer3_Addr0_Reg1,For IPv4 packets the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field"
hexmask.long 0x00 0.--31. 1. "L3A01,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0x944++0x03
line.long 0x00 "MAC_Layer3_Addr1_Reg1,For IPv4 packets the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field"
hexmask.long 0x00 0.--31. 1. "L3A11,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0x948++0x03
line.long 0x00 "MAC_Layer3_Addr2_Reg1,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A21,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0x94C++0x03
line.long 0x00 "MAC_Layer3_Addr3_Reg1,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A31,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0x960++0x03
line.long 0x00 "MAC_L3_L4_Control2,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4"
bitfld.long 0x00 28. "DMCHEN2,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
newline
bitfld.long 0x00 24. "DMCHN2,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1"
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bitfld.long 0x00 21. "L4DPIM2,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
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bitfld.long 0x00 20. "L4DPM2,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
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bitfld.long 0x00 19. "L4SPIM2,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
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bitfld.long 0x00 18. "L4SPM2,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
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bitfld.long 0x00 16. "L4PEN2,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
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bitfld.long 0x00 11.--15. "L3HDBM2,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--10. "L3HSBM2,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "L3DAIM2,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
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bitfld.long 0x00 4. "L3DAM2,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
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bitfld.long 0x00 3. "L3SAIM2,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
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bitfld.long 0x00 2. "L3SAM2,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
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bitfld.long 0x00 0. "L3PEN2,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x964++0x03
line.long 0x00 "MAC_Layer4_Address2,The MAC_Layer4_Address(#i) MAC_L3_L4_Control(#i) MAC_Layer3_Addr0_Reg(#i) MAC_Layer3_Addr1_Reg(#i) MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.."
hexmask.long.word 0x00 16.--31. 1. "L4DP2,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
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hexmask.long.word 0x00 0.--15. 1. "L4SP2,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0x970++0x03
line.long 0x00 "MAC_Layer3_Addr0_Reg2,For IPv4 packets the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field"
hexmask.long 0x00 0.--31. 1. "L3A02,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0x974++0x03
line.long 0x00 "MAC_Layer3_Addr1_Reg2,For IPv4 packets the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field"
hexmask.long 0x00 0.--31. 1. "L3A12,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0x978++0x03
line.long 0x00 "MAC_Layer3_Addr2_Reg2,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A22,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0x97C++0x03
line.long 0x00 "MAC_Layer3_Addr3_Reg2,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A32,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0x990++0x03
line.long 0x00 "MAC_L3_L4_Control3,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4"
bitfld.long 0x00 28. "DMCHEN3,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter" "0: DMA Channel Select is disabled,1: DMA Channel Select is enabled"
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bitfld.long 0x00 24. "DMCHN3,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed" "0,1"
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bitfld.long 0x00 21. "L4DPIM3,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching" "0: Layer 4 Destination Port Inverse Match is..,1: Layer 4 Destination Port Inverse Match is.."
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bitfld.long 0x00 20. "L4DPM3,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching" "0: Layer 4 Destination Port Match is disabled,1: Layer 4 Destination Port Match is enabled"
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bitfld.long 0x00 19. "L4SPIM3,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching" "0: Layer 4 Source Port Inverse Match is disabled,1: Layer 4 Source Port Inverse Match is enabled"
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bitfld.long 0x00 18. "L4SPM3,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching" "0: Layer 4 Source Port Match is disabled,1: Layer 4 Source Port Match is enabled"
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bitfld.long 0x00 16. "L4PEN3,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching" "0: Layer 4 Protocol is disabled,1: Layer 4 Protocol is enabled"
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bitfld.long 0x00 11.--15. "L3HDBM3,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--10. "L3HSBM3,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "L3DAIM3,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching" "0: Layer 3 IP DA Inverse Match is disabled,1: Layer 3 IP DA Inverse Match is enabled"
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bitfld.long 0x00 4. "L3DAM3,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching" "0: Layer 3 IP DA Match is disabled,1: Layer 3 IP DA Match is enabled"
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bitfld.long 0x00 3. "L3SAIM3,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching" "0: Layer 3 IP SA Inverse Match is disabled,1: Layer 3 IP SA Inverse Match is enabled"
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bitfld.long 0x00 2. "L3SAM3,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching" "0: Layer 3 IP SA Match is disabled,1: Layer 3 IP SA Match is enabled"
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bitfld.long 0x00 0. "L3PEN3,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets" "0: Layer 3 Protocol is disabled,1: Layer 3 Protocol is enabled"
group.long 0x994++0x03
line.long 0x00 "MAC_Layer4_Address3,The MAC_Layer4_Address(#i) MAC_L3_L4_Control(#i) MAC_Layer3_Addr0_Reg(#i) MAC_Layer3_Addr1_Reg(#i) MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.."
hexmask.long.word 0x00 16.--31. 1. "L4DP3,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets"
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hexmask.long.word 0x00 0.--15. 1. "L4SP3,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets"
group.long 0x9A0++0x03
line.long 0x00 "MAC_Layer3_Addr0_Reg3,For IPv4 packets the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field"
hexmask.long 0x00 0.--31. 1. "L3A03,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets"
group.long 0x9A4++0x03
line.long 0x00 "MAC_Layer3_Addr1_Reg3,For IPv4 packets the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field"
hexmask.long 0x00 0.--31. 1. "L3A13,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets"
group.long 0x9A8++0x03
line.long 0x00 "MAC_Layer3_Addr2_Reg3,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A23,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets"
group.long 0x9AC++0x03
line.long 0x00 "MAC_Layer3_Addr3_Reg3,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets"
hexmask.long 0x00 0.--31. 1. "L3A33,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets"
group.long 0xA70++0x03
line.long 0x00 "MAC_Indir_Access_Ctrl,This register provides the Indirect Access control and status for MAC_<MSEl>_<AOFF> registers"
bitfld.long 0x00 16.--19. "MSEL,Mode Select This field is used in indirect access of MAC_<MSEL>_<AOFF>" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 8.--15. 1. "AOFF,Address Offset This field is used in indirect access of MAC_<MSEL>_<AOFF>"
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bitfld.long 0x00 5. "AUTO,Auto increment" "0,1"
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bitfld.long 0x00 1. "COM,Command type This bit indicates the register access type" "0: Write operation,1: Read operation"
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bitfld.long 0x00 0. "OB,Operation Busy" "0,1"
group.long 0xA74++0x03
line.long 0x00 "MAC_Indir_Access_Data,This register holds the read/write data for Indirect Access of MAC_<MSEL_<AOFF> registers"
hexmask.long 0x00 0.--31. 1. "DATA,This field contains data to read/write for Indirect address access associated with MAC_Indir_Access_Ctrl register"
group.long 0xB00++0x03
line.long 0x00 "MAC_Timestamp_Control,This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver"
bitfld.long 0x00 28. "AV8021ASMEN,AV 802" "0: AV 802.1AS Mode is disabled,1: AV 802.1AS Mode is enabled"
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bitfld.long 0x00 24. "TXTSSTSM,Transmit Timestamp Status Mode When this bit is set the MAC overwrites the earlier transmit timestamp status even if it is not read by the software" "0: Transmit Timestamp Status Mode is disabled,1: Transmit Timestamp Status Mode is enabled"
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bitfld.long 0x00 20. "ESTI,External System Time Input When this bit is set the MAC uses the external 64-bit reference System Time input for the following: - To take the timestamp provided as status - To insert the timestamp in transmit PTP packets when One-step Timestamp or.." "0: External System Time Input is disabled,1: External System Time Input is enabled"
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bitfld.long 0x00 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering When this bit is set the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet" "0: MAC Address for PTP Packet Filtering is..,1: MAC Address for PTP Packet Filtering is enabled"
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bitfld.long 0x00 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken" "0,1,2,3"
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bitfld.long 0x00 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master When this bit is set the snapshot is taken only for the messages that are relevant to the master node" "0: Snapshot for Messages Relevant to Master is..,1: Snapshot for Messages Relevant to Master is.."
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bitfld.long 0x00 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages When this bit is set the timestamp snapshot is taken only for event messages (SYNC Delay_Req Pdelay_Req or Pdelay_Resp)" "0: Timestamp Snapshot for Event Messages is..,1: Timestamp Snapshot for Event Messages is.."
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bitfld.long 0x00 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets" "0: Processing of PTP Packets Sent over IPv4-UDP..,1: Processing of PTP Packets Sent over IPv4-UDP.."
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bitfld.long 0x00 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets" "0: Processing of PTP Packets Sent over IPv6-UDP..,1: Processing of PTP Packets Sent over IPv6-UDP.."
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bitfld.long 0x00 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets When this bit is set the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets" "0: Processing of PTP over Ethernet Packets is..,1: Processing of PTP over Ethernet Packets is.."
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bitfld.long 0x00 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format When this bit is set the IEEE 1588 version 2 format is used to process the PTP packets" "0: PTP Packet Processing for Version 2 Format is..,1: PTP Packet Processing for Version 2 Format is.."
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bitfld.long 0x00 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control When this bit is set the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is 1 nanosecond accuracy) and increments the timestamp (High) seconds" "0: Timestamp Digital or Binary Rollover Control..,1: Timestamp Digital or Binary Rollover Control.."
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bitfld.long 0x00 8. "TSENALL,Enable Timestamp for All Packets When this bit is set the timestamp snapshot is enabled for all packets received by the MAC" "0: Timestamp for All Packets disabled,1: Timestamp for All Packets enabled"
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bitfld.long 0x00 6. "PTGE,Presentation Time Generation Enable When this bit is set the Presentation Time generation is enabled" "0: Presentation Time Generation is disabled,1: Presentation Time Generation is enabled"
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bitfld.long 0x00 5. "TSADDREG,Update Addend Register When this bit is set the content of the Timestamp Addend register is updated in the PTP block for fine correction" "0: Addend Register is not updated,1: Addend Register is updated"
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bitfld.long 0x00 3. "TSUPDT,Update Timestamp When this bit is set the system time is updated (added or subtracted) with the value specified in MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not updated,1: Timestamp is updated"
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bitfld.long 0x00 2. "TSINIT,Initialize Timestamp When this bit is set the system time is initialized (overwritten) with the value specified in the MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers" "0: Timestamp is not initialized,1: Timestamp is initialized"
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bitfld.long 0x00 1. "TSCFUPDT,Fine or Coarse Timestamp Update When this bit is set the Fine method is used to update system timestamp" "0: Coarse method is used to update system..,1: Fine method is used to update system timestamp"
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bitfld.long 0x00 0. "TSENA,Enable Timestamp When this bit is set the timestamp is added for Transmit and Receive packets" "0: Timestamp is disabled,1: Timestamp is enabled"
group.long 0xB04++0x03
line.long 0x00 "MAC_Sub_Second_Increment,This register specifies the value to be added to the internal system time register every cycle of clk_ptp_ref_i clock"
hexmask.long.byte 0x00 16.--23. 1. "SSINC,Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register"
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hexmask.long.byte 0x00 8.--15. 1. "SNSINC,Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value represented in nanoseconds multiplied by 2^8"
rgroup.long 0xB08++0x03
line.long 0x00 "MAC_System_Time_Seconds,The System Time Seconds register along with System Time Nanoseconds register indicates the current value of the system time maintained by the MAC"
hexmask.long 0x00 0.--31. 1. "TSS,Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC"
rgroup.long 0xB0C++0x03
line.long 0x00 "MAC_System_Time_Nanoseconds,The System Time Nanoseconds register along with System Time Seconds register indicates the current value of the system time maintained by the MAC"
hexmask.long 0x00 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field has the sub-second representation of time with an accuracy of 0"
group.long 0xB10++0x03
line.long 0x00 "MAC_System_Time_Seconds_Update,The System Time Seconds Update register along with the System Time Nanoseconds Update register initializes or updates the system time maintained by the MAC"
hexmask.long 0x00 0.--31. 1. "TSS,Timestamp Seconds The value in this field is the seconds part of the update"
group.long 0xB14++0x03
line.long 0x00 "MAC_System_Time_Nanoseconds_Update,MAC System Time Nanoseconds Update register"
bitfld.long 0x00 31. "ADDSUB,Add or Subtract Time When this bit is set the time value is subtracted with the contents of the update register" "0: Add time,1: Subtract time"
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hexmask.long 0x00 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field is the sub-seconds part of the update"
group.long 0xB18++0x03
line.long 0x00 "MAC_Timestamp_Addend,Timestamp Addend register"
hexmask.long 0x00 0.--31. 1. "TSAR,Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization"
group.long 0xB1C++0x03
line.long 0x00 "MAC_System_Time_Higher_Word_Seconds,System Time - Higher Word Seconds register"
hexmask.long.word 0x00 0.--15. 1. "TSHWR,Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value"
rgroup.long 0xB20++0x03
line.long 0x00 "MAC_Timestamp_Status,Timestamp Status register"
bitfld.long 0x00 25.--29. "ATSNS,Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set" "0: Auxiliary Timestamp Snapshot Trigger Missed..,1: Auxiliary Timestamp Snapshot Trigger Missed.."
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bitfld.long 0x00 16.--19. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "TXTSSIS,Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop transmit status is enabled in MTL this bit is set when the captured transmit timestamp is updated in the MAC_Tx_Timestamp_Status_Nanoseconds and.." "0: Tx Timestamp Status Interrupt status not..,1: Tx Timestamp Status Interrupt status detected"
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bitfld.long 0x00 9. "TSTRGTERR3,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
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bitfld.long 0x00 8. "TSTARGT3,Timestamp Target Time Reached for Target Time PPS3 When this bit is set and MCGREN3 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the.." "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.."
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bitfld.long 0x00 7. "TSTRGTERR2,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
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bitfld.long 0x00 6. "TSTARGT2,Timestamp Target Time Reached for Target Time PPS2 When this bit is set and MCGREN2 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the.." "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.."
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bitfld.long 0x00 5. "TSTRGTERR1,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
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bitfld.long 0x00 4. "TSTARGT1,Timestamp Target Time Reached for Target Time PPS1 When this bit is set and MCGREN1 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the.." "0: Timestamp Target Time Reached for Target Time..,1: Timestamp Target Time Reached for Target Time.."
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bitfld.long 0x00 3. "TSTRGTERR0,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses" "0: Timestamp Target Time Error status not detected,1: Timestamp Target Time Error status detected"
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bitfld.long 0x00 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO" "0: Auxiliary Timestamp Trigger Snapshot status..,1: Auxiliary Timestamp Trigger Snapshot status.."
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bitfld.long 0x00 1. "TSTARGT0,Timestamp Target Time Reached When this bit is set and MCGREN0 of MAC_PPS_Control register is reset it indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and.." "0: Timestamp Target Time Reached status not..,1: Timestamp Target Time Reached status detected"
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bitfld.long 0x00 0. "TSSOVF,Timestamp Seconds Overflow When this bit is set it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF" "0: Timestamp Seconds Overflow status not detected,1: Timestamp Seconds Overflow status detected"
rgroup.long 0xB30++0x03
line.long 0x00 "MAC_Tx_Timestamp_Status_Nanoseconds,This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled"
bitfld.long 0x00 31. "TXTSSMIS,Transmit Timestamp Status Missed When this bit is set it indicates one of the following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the MAC_Timestamp_Control register is reset - The timestamp of the previous packet is.." "0: Transmit Timestamp Status Missed status not..,1: Transmit Timestamp Status Missed status.."
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hexmask.long 0x00 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp"
rgroup.long 0xB34++0x03
line.long 0x00 "MAC_Tx_Timestamp_Status_Seconds,The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted"
hexmask.long 0x00 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp"
group.long 0xB40++0x03
line.long 0x00 "MAC_Auxiliary_Control,The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot"
bitfld.long 0x00 7. "ATSEN3,Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
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bitfld.long 0x00 6. "ATSEN2,Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
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bitfld.long 0x00 5. "ATSEN1,Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
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bitfld.long 0x00 4. "ATSEN0,Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0" "0: Auxiliary Snapshot i is disabled,1: Auxiliary Snapshot i is enabled"
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bitfld.long 0x00 0. "ATSFC,Auxiliary Snapshot FIFO Clear When set this bit resets the pointers of the Auxiliary Snapshot FIFO" "0: Auxiliary Snapshot FIFO Clear is disabled,1: Auxiliary Snapshot FIFO Clear is enabled"
rgroup.long 0xB48++0x03
line.long 0x00 "MAC_Auxiliary_Timestamp_Nanoseconds,The Auxiliary Timestamp Nanoseconds register along with MAC_Auxiliary_Timestamp_Seconds gives the 64-bit timestamp stored as auxiliary snapshot"
hexmask.long 0x00 0.--30. 1. "AUXTSLO,Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp"
rgroup.long 0xB4C++0x03
line.long 0x00 "MAC_Auxiliary_Timestamp_Seconds,The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register"
hexmask.long 0x00 0.--31. 1. "AUXTSHI,Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp"
group.long 0xB50++0x03
line.long 0x00 "MAC_Timestamp_Ingress_Asym_Corr,The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages"
hexmask.long 0x00 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet"
group.long 0xB54++0x03
line.long 0x00 "MAC_Timestamp_Egress_Asym_Corr,The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages"
hexmask.long 0x00 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet"
group.long 0xB58++0x03
line.long 0x00 "MAC_Timestamp_Ingress_Corr_Nanosecond,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path"
hexmask.long 0x00 0.--31. 1. "TSIC,Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression"
group.long 0xB5C++0x03
line.long 0x00 "MAC_Timestamp_Egress_Corr_Nanosecond,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path"
hexmask.long 0x00 0.--31. 1. "TSEC,Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression"
group.long 0xB60++0x03
line.long 0x00 "MAC_Timestamp_Ingress_Corr_Subnanosec,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value for ingress direction"
hexmask.long.byte 0x00 8.--15. 1. "TSICSNS,Timestamp Ingress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the ingress path correction value as defined by the Ingress Correction expression"
group.long 0xB64++0x03
line.long 0x00 "MAC_Timestamp_Egress_Corr_Subnanosec,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value for egress direction"
hexmask.long.byte 0x00 8.--15. 1. "TSECSNS,Timestamp Egress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the egress path correction value as defined by the Egress Correction expression"
rgroup.long 0xB68++0x03
line.long 0x00 "MAC_Timestamp_Ingress_Latency,This register holds the Ingress MAC latency"
hexmask.long.word 0x00 16.--27. 1. "ITLNS,Ingress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken"
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hexmask.long.byte 0x00 8.--15. 1. "ITLSNS,Ingress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken"
rgroup.long 0xB6C++0x03
line.long 0x00 "MAC_Timestamp_Egress_Latency,This register holds the Egress MAC latency"
hexmask.long.word 0x00 16.--27. 1. "ETLNS,Egress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC"
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hexmask.long.byte 0x00 8.--15. 1. "ETLSNS,Egress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC"
group.long 0xB70++0x03
line.long 0x00 "MAC_PPS_Control,PPS Control register"
bitfld.long 0x00 31. "MCGREN3,MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode" "0,1"
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bitfld.long 0x00 29.--30. "TRGTMODSEL3,Target Time Register Mode for PPS3 Output This field indicates the Target Time registers (MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds) mode for PPS3 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
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bitfld.long 0x00 28. "TIMESEL,Time Select When this bit is set 64 bit PTP time is used to capture time at MCGR trigger[0] input When this bit is reset presentation time is used to capture time at trigger input maintaining backward compatibility" "0,1"
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bitfld.long 0x00 24.--27. "PPSCMD3,Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "MCGREN2,MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode" "0: 2nd PPS instance is disabled to operate in..,1: 2nd PPS instance is enabled to operate in PPS.."
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bitfld.long 0x00 21.--22. "TRGTMODSEL2,Target Time Register Mode for PPS2 Output This field indicates the Target Time registers (MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds) mode for PPS2 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
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bitfld.long 0x00 16.--19. "PPSCMD2,Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "MCGREN1,MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode" "0: 1st PPS instance is disabled to operate in..,1: 1st PPS instance is enabled to operate in PPS.."
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bitfld.long 0x00 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS1 Output This field indicates the Target Time registers (MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds) mode for PPS1 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
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bitfld.long 0x00 8.--11. "PPSCMD1,Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "MCGREN0,MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode" "0: 0th PPS instance is enabled to operate in PPS..,1: 0th PPS instance is enabled to operate in.."
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bitfld.long 0x00 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output This field indicates the Target Time registers (MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds) mode for PPS0 output signal" "0: Target Time registers are programmed only for..,1: Enables MCGR Interrupt whose status bit is..,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.."
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bitfld.long 0x00 4. "PPSEN0,Flexible PPS Output Mode Enable When this bit is" "0: Flexible PPS Output Mode is disabled,1: Flexible PPS Output Mode is enabled"
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bitfld.long 0x00 0.--3. "PPSCTRL_PPSCMD,PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xB80++0x03
line.long 0x00 "MAC_PPS0_Target_Time_Seconds,The PPS Target Time Seconds register along with PPS Target Time Nanoseconds register is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers"
hexmask.long 0x00 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register This field stores the time in seconds"
group.long 0xB84++0x03
line.long 0x00 "MAC_PPS0_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register"
bitfld.long 0x00 31. "TRGTBUSY0,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
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hexmask.long 0x00 0.--30. 1. "TTSL0,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
group.long 0xB88++0x03
line.long 0x00 "MAC_PPS0_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSINT0,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
group.long 0xB8C++0x03
line.long 0x00 "MAC_PPS0_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
group.long 0xB90++0x03
line.long 0x00 "MAC_PPS1_Target_Time_Seconds,The PPS Target Time Seconds register along with PPS Target Time Nanoseconds register is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers"
hexmask.long 0x00 0.--31. 1. "TSTRH1,PPS Target Time Seconds Register This field stores the time in seconds"
group.long 0xB94++0x03
line.long 0x00 "MAC_PPS1_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register"
bitfld.long 0x00 31. "TRGTBUSY1,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
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hexmask.long 0x00 0.--30. 1. "TTSL1,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
group.long 0xB98++0x03
line.long 0x00 "MAC_PPS1_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSINT1,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
group.long 0xB9C++0x03
line.long 0x00 "MAC_PPS1_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSWIDTH1,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
group.long 0xBA0++0x03
line.long 0x00 "MAC_PPS2_Target_Time_Seconds,The PPS Target Time Seconds register along with PPS Target Time Nanoseconds register is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers"
hexmask.long 0x00 0.--31. 1. "TSTRH2,PPS Target Time Seconds Register This field stores the time in seconds"
group.long 0xBA4++0x03
line.long 0x00 "MAC_PPS2_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register"
bitfld.long 0x00 31. "TRGTBUSY2,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
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hexmask.long 0x00 0.--30. 1. "TTSL2,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
group.long 0xBA8++0x03
line.long 0x00 "MAC_PPS2_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSINT2,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
group.long 0xBAC++0x03
line.long 0x00 "MAC_PPS2_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSWIDTH2,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
group.long 0xBB0++0x03
line.long 0x00 "MAC_PPS3_Target_Time_Seconds,The PPS Target Time Seconds register along with PPS Target Time Nanoseconds register is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers"
hexmask.long 0x00 0.--31. 1. "TSTRH3,PPS Target Time Seconds Register This field stores the time in seconds"
group.long 0xBB4++0x03
line.long 0x00 "MAC_PPS3_Target_Time_Nanoseconds,PPS0 Target Time Nanoseconds register"
bitfld.long 0x00 31. "TRGTBUSY3,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011" "0: PPS Target Time Register Busy status is not..,1: PPS Target Time Register Busy is detected"
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hexmask.long 0x00 0.--30. 1. "TTSL3,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds"
group.long 0xBB8++0x03
line.long 0x00 "MAC_PPS3_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSINT3,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output"
group.long 0xBBC++0x03
line.long 0x00 "MAC_PPS3_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])"
hexmask.long 0x00 0.--31. 1. "PPSWIDTH3,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output"
group.long 0xC00++0x03
line.long 0x00 "MTL_Operation_Mode,The Operation Mode register establishes the Transmit and Receive operating modes and commands"
bitfld.long 0x00 15. "FRPE,Flexible Rx parser Enable" "0: Flexible Rx parser is disabled,1: Flexible Rx parser is enabled"
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bitfld.long 0x00 14. "RXPED,RxParser Software Error/Incomplete Parsing Packet Drop Enable when this bit is set to 0 packets encountering software programming errors (NPE/NVE/frame offset overflow errors) or incomplete parsing are forwarded to application with the.." "0: Flexible Rx parser packet drop in case..,1: Flexible Rx parser packet drop in case.."
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bitfld.long 0x00 9. "CNTCLR,Counters Reset When this bit is set all counters are reset" "0: Counters are not reset,1: All counters are reset"
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bitfld.long 0x00 8. "CNTPRST,Counters Preset When this bit is set - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0" "0: Counters Preset is disabled,1: Counters Preset is enabled"
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bitfld.long 0x00 5.--6. "SCHALG,Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling" "0: WRR algorithm,1: WFQ algorithm when DCB feature is..,2: DWRR algorithm when DCB feature is..,3: Strict priority algorithm"
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bitfld.long 0x00 2. "RAA,Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side" "0: Strict priority (SP),1: Weighted Strict Priority (WSP)"
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bitfld.long 0x00 1. "DTXSTS,Drop Transmit Status" "0: Drop Transmit Status is disabled,1: Drop Transmit Status is enabled"
group.long 0xC08++0x03
line.long 0x00 "MTL_DBG_CTL,The FIFO Debug Access Control and Status register controls the operation mode of FIFO debug access"
bitfld.long 0x00 18. "EIEC,ECC Inject Error Control for Tx Rx TSO and DCACHE memories When EIEE or EIAEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: insert 2 bit errors"
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bitfld.long 0x00 17. "EIAEE,ECC Inject Address Error for Tx Rx TSO and DCACHE memories" "0: Disables the ECC address error injection,1: Enables the ECC address error injection"
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bitfld.long 0x00 16. "EIEE,ECC Inject Error Enable for Tx Rx TSO and DCACHE memories" "0: ECC Inject Error for Tx Rx TSO and DCACHE..,1: ECC Inject Error for Tx Rx TSO and DCACHE.."
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bitfld.long 0x00 15. "STSIE,Transmit Status Available Interrupt Status Enable When this bit is set an interrupt is generated when Transmit status is available in slave mode" "0: Transmit Packet Available Interrupt Status is..,1: Transmit Packet Available Interrupt Status is.."
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bitfld.long 0x00 14. "PKTIE,Receive Packet Available Interrupt Status Enable When this bit is set an interrupt is generated when EOP of received packet is written to the Rx FIFO" "0: Receive Packet Available Interrupt Status is..,1: Receive Packet Available Interrupt Status is.."
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bitfld.long 0x00 12.--13. "FIFOSEL,FIFO Selected for Access This field indicates the FIFO selected for debug access" "0: Tx FIFO,1: Tx Status FIFO (only read access when SLVMOD..,2: TSO FIFO (cannot be accessed when SLVMOD is..,3: Rx FIFO"
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bitfld.long 0x00 11. "FIFOWREN,FIFO Write Enable When this bit is set it enables the Write operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Write is disabled,1: FIFO Write is enabled"
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bitfld.long 0x00 10. "FIFORDEN,FIFO Read Enable When this bit is set it enables the Read operation on selected FIFO when FIFO Debug Access is enabled" "0: FIFO Read is disabled,1: FIFO Read is enabled"
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bitfld.long 0x00 9. "RSTSEL,Reset Pointers of Selected FIFO When this bit is set the pointers of the currently-selected FIFO are reset when FIFO Debug Access is enabled" "0: Reset Pointers of Selected FIFO is disabled,1: Reset Pointers of Selected FIFO is enabled"
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bitfld.long 0x00 8. "RSTALL,Reset All Pointers When this bit is set the pointers of all FIFOs are reset when FIFO Debug Access is enabled" "0: Reset All Pointers is disabled,1: Reset All Pointers is enabled"
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bitfld.long 0x00 5.--6. "PKTSTATE,Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP"
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bitfld.long 0x00 2.--3. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Write operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid"
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bitfld.long 0x00 1. "DBGMOD,Debug Mode Access to FIFO" "0: Debug Mode Access to FIFO is disabled,1: Debug Mode Access to FIFO is enabled"
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bitfld.long 0x00 0. "FDBGEN,FIFO Debug Access Enable" "0: FIFO Debug Access is disabled,1: FIFO Debug Access is enabled"
group.long 0xC0C++0x03
line.long 0x00 "MTL_DBG_STS,The FIFO Debug Status register contains the status of FIFO debug access"
hexmask.long.tbyte 0x00 15.--31. 1. "LOCR,Remaining Locations in the FIFO - Slave Access Mode: This field indicates the space available in the selected FIFO"
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bitfld.long 0x00 9. "STSI,Transmit Status Available Interrupt Status When set this bit indicates that the Slave mode Tx packet is transmitted and the status is available in Tx Status FIFO" "0: Transmit Status Available Interrupt Status..,1: Transmit Status Available Interrupt Status.."
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bitfld.long 0x00 8. "PKTI,Receive Packet Available Interrupt Status When set this bit indicates that MAC layer has written the EOP of received packet to the Rx FIFO" "0: Receive Packet Available Interrupt Status not..,1: Receive Packet Available Interrupt Status.."
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rbitfld.long 0x00 3.--4. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Read operation" "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,2: Byte 0 Byte 1 and Byte 2 are valid,3: All four bytes are valid"
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rbitfld.long 0x00 1.--2. "PKTSTATE,Encoded Packet State This field is used to get the control or status information of the selected FIFO" "0: Packet Data,1: Control Word/Normal Status,2: SOP Data/Last Status,3: EOP Data/EOP"
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rbitfld.long 0x00 0. "FIFOBUSY,FIFO Busy When set this bit indicates that a FIFO operation is in progress in the MAC and content of the following fields is not valid: - All other fields of this register - All fields of the MTL_FIFO_Debug_Data register" "0: FIFO Busy not detected,1: FIFO Busy detected"
group.long 0xC10++0x03
line.long 0x00 "MTL_FIFO_Debug_Data,The FIFO Debug Data register contains the data to be written to or read from the FIFOs"
hexmask.long 0x00 0.--31. 1. "FDBGDATA,FIFO Debug Data During debug or slave access write operation this field contains the data to be written to the Tx FIFO Rx FIFO or TSO FIFO"
rgroup.long 0xC20++0x03
line.long 0x00 "MTL_Interrupt_Status,The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC"
bitfld.long 0x00 23. "MTLPIS,MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block" "0: MTL Rx Parser Interrupt status not detected,1: MTL Rx Parser Interrupt status detected"
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bitfld.long 0x00 18. "ESTIS,EST (TAS- 802" "0: EST (TAS- 802.1Qbv) Interrupt status not..,1: EST (TAS- 802.1Qbv) Interrupt status detected"
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bitfld.long 0x00 17. "DBGIS,Debug Interrupt status This bit indicates an interrupt event during the slave access" "0: Debug Interrupt status not detected,1: Debug Interrupt status detected"
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bitfld.long 0x00 1. "Q1IS,Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1" "0: Queue 1 Interrupt status not detected,1: Queue 1 Interrupt status detected"
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bitfld.long 0x00 0. "Q0IS,Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0" "0: Queue 0 Interrupt status not detected,1: Queue 0 Interrupt status detected"
group.long 0xC30++0x03
line.long 0x00 "MTL_RxQ_DMA_Map0,The Receive Queue and DMA Channel Mapping 0 register is reserved in EQOS-CORE and EQOS-MTL configurations"
bitfld.long 0x00 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 1 disabled for DA-based DMA Channel..,1: Queue 1 enabled for DA-based DMA Channel.."
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bitfld.long 0x00 8. "Q1MDMACH,Queue 1 Mapped to DMA Channel This field controls the routing of the received packet in Queue 1 to the DMA channel" "0: DMA Channel,1: DMA Channel"
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bitfld.long 0x00 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "0: Queue 0 disabled for DA-based DMA Channel..,1: Queue 0 enabled for DA-based DMA Channel.."
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bitfld.long 0x00 0. "Q0MDMACH,Queue 0 Mapped to DMA Channel This field controls the routing of the packet received in Queue 0 to the DMA channel" "0: DMA Channel,1: DMA Channel"
group.long 0xC40++0x03
line.long 0x00 "MTL_TBS_CTRL,This register controls the operation of Time Based Scheduling"
hexmask.long.tbyte 0x00 8.--31. 1. "LEOS,Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the Launch time to compute the Launch Expiry time"
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bitfld.long 0x00 4.--6. "LEGOS,Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1. "LEOV,Launch Expiry Offset Valid When set indicates the LEOS field is valid" "0: LEOS field is invalid,1: LEOS field is valid"
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bitfld.long 0x00 0. "ESTM,EST offset Mode When this bit is set the Launch Time value used in Time Based Scheduling is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the current list" "0: EST offset Mode is disabled,1: EST offset Mode is enabled"
group.long 0xC50++0x03
line.long 0x00 "MTL_EST_Control,This register controls the operation of Enhancements to Scheduled Transmission (IEEE802.1Qbv)"
hexmask.long.byte 0x00 24.--31. 1. "PTOV,PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds"
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hexmask.long.word 0x00 12.--23. 1. "CTOV,Current Time Offset Value Provides a 12 bit time offset value in nanosecond that is added to the current time to compensate for all the implementation pipeline delays such as the CDC sync delay buffering delays data path delays and so on"
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bitfld.long 0x00 8.--10. "TILS,Time Interval Left Shift Amount This field provides the left shift amount for the programmed Time Interval values used in the Gate Control Lists" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "LCSE,Loop Count to report Scheduling Error Programmable number of GCL list iterations before reporting an HLBS error defined in EST_Status register" "0: 4 iterations,1: 8 iterations,2: 16 iterations,3: 32 iterations"
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bitfld.long 0x00 5. "DFBS,Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due to not getting scheduled (HLBS field of EST_Status register) after 4 8 16 32 (based on LCSE field of this register) GCL iterations are dropped" "0: Do not Drop Frames causing Scheduling Error,1: Drop Frames causing Scheduling Error"
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bitfld.long 0x00 4. "DDBF,Do not Drop frames during Frame Size Error When set frames are not be dropped during Head-of-Line blocking due to Frame Size Error (HLBF field of EST_Status register)" "0: Drop frames during Frame Size Error,1: Do not Drop frames during Frame Size Error"
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bitfld.long 0x00 3. "QHLBF,Quick Assertion of HLBF Error When set Time Window for Head-of-Line blocking due to Frame Size Error is 1 to 2 loop count of GCL list" "0: Disable Quick assertion of HLBF error,1: Quick Assertion of HLBF Error"
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bitfld.long 0x00 1. "SSWL,Switch to S/W owned list When set indicates that the software has programmed that list that it currently owns (SWOL) and the hardware should switch to the new list based on the new BTR" "0: Switch to S/W owned list is disabled,1: Switch to S/W owned list is enabled"
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bitfld.long 0x00 0. "EEST,Enable EST When reset the gate control list processing is halted and all gates are assumed to be in Open state" "0: EST is disabled,1: EST is enabled"
group.long 0xC54++0x03
line.long 0x00 "MTL_EST_Ext_Control,This register indicates the number of Overhead bytes for EST related scheduling"
bitfld.long 0x00 0.--5. "OVHD,Overhead Bytes Value This field indicates the fixed overhead for every packet to account for EST Scheduler Delay IPG or EIPG and Preamble bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC58++0x03
line.long 0x00 "MTL_EST_Status,This register provides Status related to Enhancements to Scheduled Transmission (IEEE802.1Qbv)"
rbitfld.long 0x00 16.--19. "CGSN,Current GCL Slot Number Indicates the slot number of the GCL list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 8.--15. 1. "BTRL,BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + (N * New Cycle Time) becomes true"
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rbitfld.long 0x00 7. "SWOL,S/W owned list When '0' indicates Gate control list number 0 is owned by software and when 1 indicates the Gate Control list 1 is owned by the software" "0: Gate control list number 0 is owned by software,1: Gate control list number 1 is owned by software"
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bitfld.long 0x00 4. "CGCE,Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the Cycle Time (CTR) is less than or equal to the programmed Time Interval (TI) value after the optional Left Shifting" "0: Constant Gate Control Error not detected,1: Constant Gate Control Error detected"
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rbitfld.long 0x00 3. "HLBS,Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration and get scheduled even after 4 iterations of the GCL" "0: Head-Of-Line Blocking due to Scheduling not..,1: Head-Of-Line Blocking due to Scheduling.."
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rbitfld.long 0x00 2. "HLBF,Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or equal to the duration needed for frame size (or frame fragment.." "0: Head-Of-Line Blocking due to Frame Size not..,1: Head-Of-Line Blocking due to Frame Size.."
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bitfld.long 0x00 1. "BTRE,BTR Error When 1 indicates a programming error in the BTR of SWOL where the programmed value is less than current time" "0: BTR Error not detected,1: BTR Error detected"
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bitfld.long 0x00 0. "SWLC,Switch to S/W owned list Complete When 1 indicates the hardware has successfully switched to the SWOL and the SWOL bit has been updated to that effect" "0: Switch to S/W owned list Complete not detected,1: Switch to S/W owned list Complete detected"
group.long 0xC60++0x03
line.long 0x00 "MTL_EST_Sch_Error,This register provides the One Hot encoded Queue Numbers that are having the Scheduling related error (timeout)"
bitfld.long 0x00 0.--1. "SEQN,Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced error/timeout described in HLBS field of status register" "0,1,2,3"
group.long 0xC64++0x03
line.long 0x00 "MTL_EST_Frm_Size_Error,This register provides the One Hot encoded Queue Numbers that are having the Frame Size related error"
bitfld.long 0x00 0.--1. "FEQN,Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced error described in HLBF field of status register" "0,1,2,3"
rgroup.long 0xC68++0x03
line.long 0x00 "MTL_EST_Frm_Size_Capture,This register captures the Frame Size and Queue Number of the first occurrence of the Frame Size related error"
bitfld.long 0x00 16. "HBFQ,Queue Number of HLBF Captures the binary value of the of the first Queue (number) experiencing HLBF error (see HLBF field of status register)" "0,1"
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hexmask.long.word 0x00 0.--14. 1. "HBFS,Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number indicated in HBFQ field of this register"
group.long 0xC70++0x03
line.long 0x00 "MTL_EST_Intr_Enable,This register implements the Interrupt Enable bits for the various events that generate an interrupt"
bitfld.long 0x00 4. "CGCE,Interrupt Enable for CGCE When set generates interrupt when the Constant Gate Control Error occurs and is indicated in the status" "0: Interrupt for CGCE is disabled,1: Interrupt for CGCE is enabled"
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bitfld.long 0x00 3. "IEHS,Interrupt Enable for HLBS When set generates interrupt when the Head-of-Line Blocking due to Scheduling issue and is indicated in the status" "0: Interrupt for HLBS is disabled,1: Interrupt for HLBS is enabled"
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bitfld.long 0x00 2. "IEHF,Interrupt Enable for HLBF When set generates interrupt when the Head-of-Line Blocking due to Frame Size error occurs and is indicated in the status" "0: Interrupt for HLBF is disabled,1: Interrupt for HLBF is enabled"
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bitfld.long 0x00 1. "IEBE,Interrupt Enable for BTR Error When set generates interrupt when the BTR Error occurs and is indicated in the status" "0: Interrupt for BTR Error is disabled,1: Interrupt for BTR Error is enabled"
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bitfld.long 0x00 0. "IECC,Interrupt Enable for Switch List When set generates interrupt when the configuration change is successful and the hardware has switched to the new list" "0: Interrupt for Switch List is disabled,1: Interrupt for Switch List is enabled"
group.long 0xC80++0x03
line.long 0x00 "MTL_EST_GCL_Control,This register provides the control information for reading/writing to the Gate Control lists"
bitfld.long 0x00 23. "ESTEIEC,ECC Inject Error Control for EST Memory When ESTEIEE or ESTEIAEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: Insert 2 bit errors"
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bitfld.long 0x00 22. "ESTEIAEE,EST ECC Inject Address Error Enable When set along with EEST bit of MTL_EST_Control register enables the ECC address error injection feature" "0: EST ECC Inject Address Error is disabled,1: EST ECC Inject Address Error is enabled"
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bitfld.long 0x00 21. "ESTEIEE,EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_Control register enables the ECC error injection feature" "0: EST ECC Inject Error is disabled,1: EST ECC Inject Error is enabled"
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hexmask.long.byte 0x00 8.--15. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is 0 )"
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bitfld.long 0x00 5. "DBGB,Debug Mode Bank Select When set to 0 indicates R/W in debug mode should be directed to Bank 0 (GCL0 and corresponding Time related registers)" "0: R/W in debug mode should be directed to Bank 0,1: R/W in debug mode should be directed to Bank 1"
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bitfld.long 0x00 4. "DBGM,Debug Mode When set to 1 indicates R/W in debug mode where the memory bank (for GCL and Time related registers) is explicitly provided by DBGB value when set to 0 SWOL bit is used to determine which bank to use" "0: Debug Mode is disabled,1: Debug Mode is enabled"
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bitfld.long 0x00 2. "GCRR,Gate Control Related Registers When set to 1 indicates the R/W access is for the GCL related registers (BTR CTR TER LLR) whose address is provided by GCRA" "0: Gate Control Related Registers are disabled,1: Gate Control Related Registers are enabled"
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bitfld.long 0x00 1. "R1W0,Read '1' Write '0'" "0: Write Operation,1: Read Operation"
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bitfld.long 0x00 0. "SRWO,Start Read/Write Op" "0: Start Read/Write Op disabled,1: Start Read/Write Op enabled"
group.long 0xC84++0x03
line.long 0x00 "MTL_EST_GCL_Data,This register holds the read data or write data in case of reads and writes respectively"
hexmask.long 0x00 0.--31. 1. "GCD,Gate Control Data The data corresponding to the address selected in the GCL_Control register"
group.long 0xC90++0x03
line.long 0x00 "MTL_FPE_CTRL_STS,This register controls the operation of and provides status for Frame Preemption (IEEE802.1Qbu/802.3br)"
rbitfld.long 0x00 28. "HRS,Hold/Release Status" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was.."
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bitfld.long 0x00 8.--9. "PEC,Preemption Classification When set indicates the corresponding Queue must be classified as preemptable when '0' Queue is classified as express" "0,1,2,3"
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bitfld.long 0x00 0.--1. "AFSZ,Additional Fragment Size used to indicate in units of 64 bytes the minimum number of bytes over 64 bytes required in non-final fragments of preempted frames" "0,1,2,3"
group.long 0xC94++0x03
line.long 0x00 "MTL_FPE_Advance,This register holds the Hold and Release Advance time"
hexmask.long.word 0x00 16.--31. 1. "RADV,Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE to the MAC and the MAC being ready to resume transmission of preemptable frames in the absence of there being any express frames available for transmission"
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hexmask.long.word 0x00 0.--15. 1. "HADV,Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of transmission or any preemptable frames that are queued for transmission"
group.long 0xCA0++0x03
line.long 0x00 "MTL_RXP_Control_Status,The MTL_RXP_Control_Status register establishes the operating mode of Rx Parser and provides some status"
rbitfld.long 0x00 31. "RXPI,RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State and waiting for a new packet for processing" "0: RX Parser not in Idle state,1: RX Parser in Idle state"
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bitfld.long 0x00 30. "ELIRS,Enable Last Instruction in RX Status When this bit is set RDES2[31:16] indicates the index of the last instruction executed in Rx Parse when set to 0 indicates MAC filter status" "0,1"
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bitfld.long 0x00 16.--21. "NPE,Number of parsable entries in the Instruction table This control indicates the number of parsable entries in the Instruction Memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "NVE,Number of valid entry address/index in the Instruction table This control indicates the number of valid entries address/index in the Instruction Memory (i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xCA4++0x03
line.long 0x00 "MTL_RXP_Interrupt_Control_Status,The MTL_RXP_Interrupt_Control_Status registers provides enable control for the interrupts and provides interrupt status"
bitfld.long 0x00 19. "PDRFIE,Packet Drop due to RF Interrupt Enable When this bit is set the PDRFIS interrupt is enabled" "0: Packet Drop due to RF Interrupt is disabled,1: Packet Drop due to RF Interrupt is enabled"
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bitfld.long 0x00 18. "FOOVIE,Frame Offset Overflow Interrupt Enable When this bit is set the FOOVIS interrupt is enabled" "0: Frame Offset Overflow Interrupt is disabled,1: Frame Offset Overflow Interrupt is enabled"
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bitfld.long 0x00 17. "NPEOVIE,Number of Parsable Entries Overflow Interrupt Enable When this bit is set the NPEOVIS interrupt is enabled" "0: Number of Parsable Entries Overflow Interrupt..,1: Number of Parsable Entries Overflow Interrupt.."
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bitfld.long 0x00 16. "NVEOVIE,Number of Valid Entries Overflow Interrupt Enable When this bit is set the NVEOVIS interrupt is enabled" "0: Number of Valid Entries Overflow Interrupt is..,1: Number of Valid Entries Overflow Interrupt is.."
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bitfld.long 0x00 3. "PDRFIS,Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the packet by setting RF=1 in the instruction memory then this bit is set to 1" "0: Packet Dropped due to RF Interrupt Status not..,1: Packet Dropped due to RF Interrupt Status.."
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bitfld.long 0x00 2. "FOOVIS,Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's 'Frame Offset' found to be more than EOF offset then then this bit is set" "0: Frame Offset Overflow Interrupt Status not..,1: Frame Offset Overflow Interrupt Status detected"
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bitfld.long 0x00 1. "NPEOVIS,Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the number of parsed entries found to be more than NPE[] (Number of Parseable Entries in MTL_RXP_Control register) then this bit is set to 1" "0: Number of Parsable Entries Overflow Interrupt..,1: Number of Parsable Entries Overflow Interrupt.."
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bitfld.long 0x00 0. "NVEOVIS,Number of Valid Entry Address/Index Overflow Interrupt Status While parsing if the Instruction address found to be more than NVE (Number of Valid Entry Address/index in MTL_RXP_Control register) then this bit is set to 1" "0: Number of Valid Entries Overflow Interrupt..,1: Number of Valid Entries Overflow Interrupt.."
rgroup.long 0xCA8++0x03
line.long 0x00 "MTL_RXP_Drop_Cnt,The MTL_RXP_Drop_Cnt register provides the drop count of Rx Parser initiated drops"
bitfld.long 0x00 31. "RXPDCOVF,Rx Parser Drop Counter Overflow Bit When set this bit indicates that the MTL_RXP_Drop_cnt (RXPDC) Counter field crossed the maximum limit" "0: Rx Parser Drop count overflow not occurred,1: Rx Parser Drop count overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPDC,Rx Parser Drop count This 31-bit counter is implemented when a Rx Parser Drops a packet due to RF =1"
rgroup.long 0xCAC++0x03
line.long 0x00 "MTL_RXP_Error_Cnt,The MTL_RXP_Error_Cnt register provides the Rx Parser related error occurrence count"
bitfld.long 0x00 31. "RXPECOVF,Rx Parser Error Counter Overflow Bit When set this bit indicates that the MTL_RXP_Error_cnt (RXPEC) Counter field crossed the maximum limit" "0: Rx Parser Error count overflow not occurred,1: Rx Parser Error count overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPEC,Rx Parser Error count This 31-bit counter is implemented when a Rx Parser encounters following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry address > EOF data entry address The counter is cleared when the.."
group.long 0xCB0++0x03
line.long 0x00 "MTL_RXP_Indirect_Acc_Control_Status,The MTL_RXP_Indirect_Acc_Control_Status register provides the Indirect Access control and status for Rx Parser memory"
bitfld.long 0x00 31. "STARTBUSY,FRP Instruction Table Access Busy - Set to 1 by the software indicates to start the Read/Write operation from/to the Rx Parser Memory" "0: hardware not busy,1: hardware is busy (Read/Write operation.."
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bitfld.long 0x00 22. "RXPEIEC,ECC Inject Error Control for Rx Parser Memory When RXPEIEE or RXPEIAEE bit of this register is set following are the errors inserted based on the value encoded in this field" "0: Insert 1 bit error,1: Insert 2 bit errors"
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bitfld.long 0x00 21. "RXPEIAEE,ECC Inject Address Error Enable for Rx Parser Memory" "0: ECC Inject Address Error for Rx Parser Memory..,1: ECC Inject Address Error for Rx Parser Memory.."
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bitfld.long 0x00 20. "RXPEIEE,ECC Inject Error Enable for Rx Parser Memory" "0: ECC Inject Error for Rx Parser Memory is..,1: ECC Inject Error for Rx Parser Memory is.."
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bitfld.long 0x00 16. "WRRDN,Read Write Control" "0: Read operation to the Rx Parser Memory,1: Write operation to the Rx Parser Memory"
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hexmask.long.byte 0x00 0.--7. 1. "ADDR,FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table"
rgroup.long 0xCB4++0x03
line.long 0x00 "MTL_RXP_Indirect_Acc_Data,The MTL_RXP_Indirect_Acc_Data registers holds the data associated to Indirect Access to Rx Parser memory"
hexmask.long 0x00 0.--31. 1. "DATA,FRP Instruction Table Write/Read Data Software should write this register before issuing any write command"
rgroup.long 0xCB8++0x03
line.long 0x00 "MTL_RXP_Bypass_Cnt,The MTL_RXP_Bypass_Cnt register provides the bypass count of Rx Parser"
bitfld.long 0x00 31. "RXPBCOF,Rx Parser bypass Counter Overflow Bit When set this bit indicates that the MTL_RXP_Bypass_cnt (RXPBC) Counter field crossed the maximum limit" "0: Rx Parser Bypass count overflow not occurred,1: Rx Parser Bypass count overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPBC,Rx Parser Bypass count This 31-bit counter is implemented when a Rx Parser bypass a packet due to AF=1 and RF =1"
group.long 0xCC0++0x03
line.long 0x00 "MTL_ECC_Control,The MTL_ECC_Control register establishes the operating mode of ECC related to MTL memories"
bitfld.long 0x00 8. "MEEAO,MTL ECC Error Address Status Over-ride" "0: MTL ECC Error Address Status Over-ride is..,1: MTL ECC Error Address Status Over-ride is.."
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bitfld.long 0x00 3. "MRXPEE,MTL Rx Parser ECC Enable" "0: MTL Rx Parser ECC is disabled,1: MTL Rx Parser ECC is enabled"
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bitfld.long 0x00 2. "MESTEE,MTL EST ECC Enable" "0: MTL EST ECC is disabled,1: MTL EST ECC is enabled"
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bitfld.long 0x00 1. "MRXEE,MTL Rx FIFO ECC Enable" "0: MTL Rx FIFO ECC is disabled,1: MTL Rx FIFO ECC is enabled"
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bitfld.long 0x00 0. "MTXEE,MTL Tx FIFO ECC Enable" "0: MTL Tx FIFO ECC is disabled,1: MTL Tx FIFO ECC is enabled"
rgroup.long 0xCC4++0x03
line.long 0x00 "MTL_Safety_Interrupt_Status,The MTL_Safety_Interrupt_Status registers provides Safety interrupt status"
bitfld.long 0x00 1. "MEUIS,MTL ECC Uncorrectable error Interrupt Status This bit indicates that an uncorrectable error interrupt event in the MTL ECC safety feature" "0: MTL ECC Uncorrectable error Interrupt Status..,1: MTL ECC Uncorrectable error Interrupt Status.."
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bitfld.long 0x00 0. "MECIS,MTL ECC Correctable error Interrupt Status This bit indicates that a correctable error interrupt event in the MTL ECC safety feature" "0: MTL ECC Correctable error Interrupt Status..,1: MTL ECC Correctable error Interrupt Status.."
group.long 0xCC8++0x03
line.long 0x00 "MTL_ECC_Interrupt_Enable,The MTL_ECC_Interrupt_Enable register provides enable bits for the ECC interrupts"
bitfld.long 0x00 12. "RPCEIE,Rx Parser memory Correctable Error Interrupt Enable When set generates an interrupt when an uncorrectable error is detected at the Rx Parser memory interface" "0: Rx Parser memory Correctable Error Interrupt..,1: Rx Parser memory Correctable Error Interrupt.."
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bitfld.long 0x00 8. "ECEIE,EST memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL EST memory interface" "0: EST memory Correctable Error Interrupt is..,1: EST memory Correctable Error Interrupt is.."
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bitfld.long 0x00 4. "RXCEIE,Rx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Rx memory interface" "0: Rx memory Correctable Error Interrupt is..,1: Rx memory Correctable Error Interrupt is.."
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bitfld.long 0x00 0. "TXCEIE,Tx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Tx memory interface" "0: Tx memory Correctable Error Interrupt is..,1: Tx memory Correctable Error Interrupt is.."
group.long 0xCCC++0x03
line.long 0x00 "MTL_ECC_Interrupt_Status,The MTL_ECC_Interrupt_Status register provides MTL ECC Interrupt Status"
bitfld.long 0x00 14. "RPUES,Rx Parser memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at Rx Parser memory interface" "0: Rx Parser memory Uncorrectable Error Status..,1: Rx Parser memory Uncorrectable Error Status.."
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bitfld.long 0x00 13. "RPAMS,MTL Rx Parser memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of Rx Parser memory" "0: MTL Rx Parser memory Address Mismatch Status..,1: MTL Rx Parser memory Address Mismatch Status.."
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bitfld.long 0x00 12. "RPCES,MTL Rx Parser memory Correctable Error Status This bit when set indicates that correctable error is detected at RX Parser memory interface" "0: MTL Rx Parser memory Correctable Error Status..,1: MTL Rx Parser memory Correctable Error Status.."
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bitfld.long 0x00 10. "EUES,MTL EST memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at MTL EST memory interface" "0: MTL EST memory Uncorrectable Error Status not..,1: MTL EST memory Uncorrectable Error Status.."
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bitfld.long 0x00 9. "EAMS,MTL EST memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of MTL EST memory" "0: MTL EST memory Address Mismatch Status not..,1: MTL EST memory Address Mismatch Status detected"
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bitfld.long 0x00 8. "ECES,MTL EST memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL EST memory" "0: MTL EST memory Correctable Error Status not..,1: MTL EST memory Correctable Error Status.."
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bitfld.long 0x00 6. "RXUES,MTL Rx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL Rx memory interface" "0: MTL Rx memory Uncorrectable Error Status not..,1: MTL Rx memory Uncorrectable Error Status.."
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bitfld.long 0x00 5. "RXAMS,MTL Rx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Rx memory" "0: MTL Rx memory Address Mismatch Status not..,1: MTL Rx memory Address Mismatch Status detected"
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bitfld.long 0x00 4. "RXCES,MTL Rx memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL Rx memory" "0: MTL Rx memory correctable Error Status not..,1: MTL Rx memory correctable Error Status detected"
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bitfld.long 0x00 2. "TXUES,MTL Tx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL TX memory interface" "0: MTL Tx memory Uncorrectable Error Status not..,1: MTL Tx memory Uncorrectable Error Status.."
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bitfld.long 0x00 1. "TXAMS,MTL Tx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Tx memory" "0: MTL Tx memory Address Mismatch Status not..,1: MTL Tx memory Address Mismatch Status detected"
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bitfld.long 0x00 0. "TXCES,MTL Tx memory Correctable Error Status This bit when set indicates that a correctable error is detected at the MTL Tx memory" "0: MTL Tx memory Correctable Error Status not..,1: MTL Tx memory Correctable Error Status detected"
group.long 0xCD0++0x03
line.long 0x00 "MTL_ECC_Err_Sts_Rctl,The MTL_ECC_Err_Sts_Rctl register establishes the control for ECC Error status capture"
bitfld.long 0x00 5. "CUES,Clear Uncorrectable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's uncorrectable error address and uncorrectable error count values are cleared upon reading" "0: Clear Uncorrectable Error Status not detected,1: Clear Uncorrectable Error Status detected"
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bitfld.long 0x00 4. "CCES,Clear Correctable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's correctable error address and correctable error count values are cleared upon reading" "0: Clear Correctable Error Status not detected,1: Clear Correctable Error Status detected"
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bitfld.long 0x00 1.--3. "EMS,MTL ECC Memory Selection When EESRE bit of this register is set this field indicates which memory's error status value to be read" "0: MTL Tx memory,1: MTL Rx memory,2: MTL EST memory,3: MTL Rx Parser memory,4: DMA TSO memory,5: DMA DCACHE memory,?..."
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bitfld.long 0x00 0. "EESRE,MTL ECC Error Status Read Enable When this bit is set based on the EMS field of this register the respective memory's error status values are captured as described: - The correctable and uncorrectable error count values are captured into.." "0: MTL ECC Error Status Read is disabled,1: MTL ECC Error Status Read is enabled"
rgroup.long 0xCD4++0x03
line.long 0x00 "MTL_ECC_Err_Addr_Status,The MTL_ECC_Err_Addr_Status register provides the memory addresses for the correctable and uncorrectable errors"
hexmask.long.word 0x00 16.--31. 1. "EUEAS,MTL ECC Uncorrectable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which an uncorrectable error or address mismatch is detected"
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hexmask.long.word 0x00 0.--15. 1. "ECEAS,MTL ECC Correctable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which a correctable error is detected"
rgroup.long 0xCD8++0x03
line.long 0x00 "MTL_ECC_Err_Cntr_Status,The MTL_ECC_Err_Cntr_Status register provides ECC Error count for Correctable and uncorrectable errors"
bitfld.long 0x00 16.--19. "EUECS,MTL ECC Uncorrectable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's uncorrectable error count value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "ECECS,MTL ECC Correctable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's correctable error count value"
group.long 0xCE0++0x03
line.long 0x00 "MTL_DPP_Control,The MTL_DPP_Control establishes the operating mode of Data Parity protection and error injection"
bitfld.long 0x00 15. "IPEMRWC,IPEMRWC" "0: Insert Parity error in MTL RWC data parity..,1: Insert Parity error in MTL RWC data parity.."
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bitfld.long 0x00 14. "IPEMTFC,Insert Parity error in MAC TFC data parity checker When set to 1 parity/data bit of first valid input parity/data of the MAC TFC data parity checker (or at PC11 as shown in Transmit Data path parity protection diagram) is flipped" "0: Insert Parity error in MAC TFC data parity..,1: Insert Parity error in MAC TFC data parity.."
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bitfld.long 0x00 13. "IPEMTBU,Insert Parity error in MTL RWC data parity checker When set to 1 parity/data bit of first valid input parity/data of the MTL RWC data parity checker (or at PC12 as shown in Receive data path parity protection diagram) is flipped" "0: Insert Parity error in MAC TBU data parity..,1: Insert Parity error in MAC TBU data parity.."
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bitfld.long 0x00 9. "IPERID,Insert Parity Error in RX Interface Data parity checker When set to 1 parity/data bit of first valid input parity/data of the RX Interface Data parity checker is (or at PC6 as shown in Receive data path parity protection diagram) flipped" "0: Insert Parity Error in Rx Interface Data..,1: Insert Parity Error in Rx Interface Data.."
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bitfld.long 0x00 8. "IPEMTS,Insert Parity Error in MTL Tx Status FIFO parity checker When set to 1 parity/data bit of first valid input parity/data of the MTL Tx Status FIFO parity checker (or at PC5 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in MTL TX Status FIFO..,1: Insert Parity Error in MTL TX Status FIFO.."
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bitfld.long 0x00 7. "IPEMTF,Insert Parity Error in MTL Tx FIFO write data parity checker When set to 1 parity/data bit of first valid input parity/data of the MTL Tx FIFO write data parity checker (or at PC4 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in MTL Tx FIFO write data..,1: Insert Parity Error in MTL Tx FIFO write data.."
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bitfld.long 0x00 6. "IPETRD,Insert Parity Error in DMA Tx/Rx Descriptor parity checker When set to 1 parity/data bit of first valid input parity/data of the DMA Tx/Rx Descriptor parity checker (or at PC3 as shown in Transmit data path parity protection diagram) is flipped" "0: Insert Parity Error in DMA Tx/Rx Descriptor..,1: Insert Parity Error in DMA Tx/Rx Descriptor.."
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rbitfld.long 0x00 1. "OPE,Odd Parity Enable When set to 1 enables odd parity protection on all the external interfaces and when set to 0 enables even parity protection on all the external interfaces" "0: Odd Parity is disabled,1: Odd Parity is enabled"
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bitfld.long 0x00 0. "EDPP,Enable Data path Parity Protection When set to 1 enables the parity protection for EQOS datapath by generating and checking the parity on EQOS datapath" "0: Data path Parity Protection is disabled,1: Data path Parity Protection is enabled"
group.long 0xCE4++0x03
line.long 0x00 "MTL_DPP_ECC_EIC,The MTL_DPP_ECC_EIC establishes the operating mode of ECC/DPP error injection"
bitfld.long 0x00 16. "EIM,Error Injection Mode When it set to 0 indicate error injection on data When it set to 1 indicate error injection on ECC/Parity bits(need to check the address error injection mode is disabled)" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "BLEI,Bit Location of error injection This field indicates the bit location of DPP/ECC error injection determination of error in Parity/ECC bits or Data (being protected) depends on the Error Injection Mode(EIM field)"
group.long 0xD00++0x03
line.long 0x00 "MTL_TxQ0_Operation_Mode,The Queue 0 Transmit Operation Mode register establishes the Transmit queue operating modes and commands"
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: M_32BYTES,1: M_64BYTES,2: M_96BYTES,3: M_128BYTES,4: M_192BYTES,5: M_256BYTES,6: M_384BYTES,7: M_512BYTES"
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bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
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bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
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bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
rgroup.long 0xD04++0x03
line.long 0x00 "MTL_TxQ0_Underflow,The Queue 0 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush"
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
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hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
rgroup.long 0xD08++0x03
line.long 0x00 "MTL_TxQ0_Debug,The Queue 0 Transmit Debug register gives the debug status of various blocks related to the Transmit queue"
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
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bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
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bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
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bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
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bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
rgroup.long 0xD14++0x03
line.long 0x00 "MTL_TxQ0_ETS_Status,The Queue 0 ETS Status register provides the average traffic transmitted in Queue 0"
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
group.long 0xD18++0x03
line.long 0x00 "MTL_TxQ0_Quantum_Weight,The Queue 0 Quantum or Weights register contains the quantum value for Deficit Weighted Round Robin (DWRR) weights for the Weighted Round Robin (WRR) and Weighted Fair Queuing (WFQ) for Queue 0"
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0 traffic this field contains the quantum value in bytes to be added to credit during every queue scanning cycle"
group.long 0xD2C++0x03
line.long 0x00 "MTL_Q0_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 0 interrupts"
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
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bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
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bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
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bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
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bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
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bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
group.long 0xD30++0x03
line.long 0x00 "MTL_RxQ0_Operation_Mode,The Queue 0 Receive Operation Mode register establishes the Receive queue operating modes and command"
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
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bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
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bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
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bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
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bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
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bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
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bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: M_64BYTE,1: M_32BYTE,2: M_96BYTE,3: M_128BYTE"
rgroup.long 0xD34++0x03
line.long 0x00 "MTL_RxQ0_Missed_Packet_Overflow_Cnt,The Queue 0 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow"
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
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hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
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bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
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hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
rgroup.long 0xD38++0x03
line.long 0x00 "MTL_RxQ0_Debug,The Queue 0 Receive Debug register gives the debug status of various blocks related to the Receive queue"
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
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bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
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bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
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bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
group.long 0xD3C++0x03
line.long 0x00 "MTL_RxQ0_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application"
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
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bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
group.long 0xD40++0x03
line.long 0x00 "MTL_TxQ1_Operation_Mode,The Queue 1 Transmit Operation Mode register establishes the Transmit queue operating modes and commands"
bitfld.long 0x00 16.--20. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue" "0: M_32BYTES,1: M_64BYTES,2: M_96BYTES,3: M_128BYTES,4: M_192BYTES,5: M_256BYTES,6: M_384BYTES,7: M_512BYTES"
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bitfld.long 0x00 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0" "0: Not enabled,1: Enable in AV mode (Reserved in non-AV),2: Enabled,?..."
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bitfld.long 0x00 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue" "0: Transmit Store and Forward is disabled,1: Transmit Store and Forward is enabled"
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bitfld.long 0x00 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values" "0: Flush Transmit Queue is disabled,1: Flush Transmit Queue is enabled"
rgroup.long 0xD44++0x03
line.long 0x00 "MTL_TxQ1_Underflow,The Queue 1 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush"
bitfld.long 0x00 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count" "0: Overflow not detected for Underflow Packet..,1: Overflow detected for Underflow Packet Counter"
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hexmask.long.word 0x00 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow"
rgroup.long 0xD48++0x03
line.long 0x00 "MTL_TxQ1_Debug,The Queue 1 Transmit Debug register gives the debug status of various blocks related to the Transmit queue"
bitfld.long 0x00 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full" "0: MTL Tx Status FIFO Full status is not detected,1: MTL Tx Status FIFO Full status is detected"
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bitfld.long 0x00 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission" "0: MTL Tx Queue Not Empty status is not detected,1: MTL Tx Queue Not Empty status is detected"
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bitfld.long 0x00 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue" "0: MTL Tx Queue Write Controller status is not..,1: MTL Tx Queue Write Controller status is.."
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bitfld.long 0x00 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
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bitfld.long 0x00 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "0: Transmit Queue in Pause status is not detected,1: Transmit Queue in Pause status is detected"
group.long 0xD50++0x03
line.long 0x00 "MTL_TxQ1_ETS_Control,The Queue ETS Control register controls the enhanced transmission selection operation"
bitfld.long 0x00 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH(#i)_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "0: M_1_SLOT,1: M_2_SLOT,2: M_4_SLOT,3: M_8_SLOT,4: M_16_SLOT,?..."
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bitfld.long 0x00 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1" "0: Credit Control is disabled,1: Credit Control is enabled"
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bitfld.long 0x00 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic" "0: CBS Algorithm is disabled,1: CBS Algorithm is enabled"
rgroup.long 0xD54++0x03
line.long 0x00 "MTL_TxQ1_ETS_Status,The Queue 1 ETS Status register provides the average traffic transmitted in Queue 1"
hexmask.long.tbyte 0x00 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot"
group.long 0xD58++0x03
line.long 0x00 "MTL_TxQ1_Quantum_Weight,The Queue 1 idleSlopeCredit Quantum or Weights register provides the average traffic transmitted in Queue 1"
hexmask.long.tbyte 0x00 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1"
group.long 0xD5C++0x03
line.long 0x00 "MTL_TxQ1_SendSlopeCredit,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue"
hexmask.long.word 0x00 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1"
group.long 0xD60++0x03
line.long 0x00 "MTL_TxQ1_HiCredit,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue"
hexmask.long 0x00 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm"
group.long 0xD64++0x03
line.long 0x00 "MTL_TxQ1_LoCredit,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue"
hexmask.long 0x00 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm"
group.long 0xD6C++0x03
line.long 0x00 "MTL_Q1_Interrupt_Control_Status,This register contains the interrupt enable and status bits for the queue 1 interrupts"
bitfld.long 0x00 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled" "0: Receive Queue Overflow Interrupt is disabled,1: Receive Queue Overflow Interrupt is enabled"
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bitfld.long 0x00 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet" "0: Receive Queue Overflow Interrupt Status not..,1: Receive Queue Overflow Interrupt Status.."
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bitfld.long 0x00 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated" "0: Average Bits Per Slot Interrupt is disabled,1: Average Bits Per Slot Interrupt is enabled"
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bitfld.long 0x00 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled" "0: Transmit Queue Underflow Interrupt Status is..,1: Transmit Queue Underflow Interrupt Status is.."
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bitfld.long 0x00 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value" "0: Average Bits Per Slot Interrupt Status not..,1: Average Bits Per Slot Interrupt Status detected"
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bitfld.long 0x00 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet" "0: Transmit Queue Underflow Interrupt Status not..,1: Transmit Queue Underflow Interrupt Status.."
group.long 0xD70++0x03
line.long 0x00 "MTL_RxQ1_Operation_Mode,The Queue 1 Receive Operation Mode register establishes the Receive queue operating modes and command"
bitfld.long 0x00 20.--24. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--17. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation" "0: Full minus 1 KB that is FULL 1 KB,1: Full minus 1,?..."
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bitfld.long 0x00 8.--11. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled" "0: Hardware Flow Control is disabled,1: Hardware Flow Control is enabled"
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bitfld.long 0x00 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine" "0: Dropping of TCP/IP Checksum Error Packets is..,1: Dropping of TCP/IP Checksum Error Packets is.."
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bitfld.long 0x00 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register" "0: Receive Queue Store and Forward is disabled,1: Receive Queue Store and Forward is enabled"
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bitfld.long 0x00 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow)" "0: Forward Error Packets is disabled,1: Forward Error Packets is enabled"
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bitfld.long 0x00 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC" "0: Forward Undersized Good Packets is disabled,1: Forward Undersized Good Packets is enabled"
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bitfld.long 0x00 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold" "0: M_64BYTE,1: M_32BYTE,2: M_96BYTE,3: M_128BYTE"
rgroup.long 0xD74++0x03
line.long 0x00 "MTL_RxQ1_Missed_Packet_Overflow_Cnt,The Queue 1 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow"
bitfld.long 0x00 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit" "0: Missed Packet Counter overflow not detected,1: Missed Packet Counter overflow detected"
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hexmask.long.word 0x00 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue"
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bitfld.long 0x00 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit" "0: Overflow Counter overflow not detected,1: Overflow Counter overflow detected"
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hexmask.long.word 0x00 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow"
rgroup.long 0xD78++0x03
line.long 0x00 "MTL_RxQ1_Debug,The Queue 1 Receive Debug register gives the debug status of various blocks related to the Receive queue"
hexmask.long.word 0x00 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue"
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bitfld.long 0x00 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue" "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control..,3: Rx Queue full"
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bitfld.long 0x00 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status"
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bitfld.long 0x00 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue" "0: MTL Rx Queue Write Controller Active Status..,1: MTL Rx Queue Write Controller Active Status.."
group.long 0xD7C++0x03
line.long 0x00 "MTL_RxQ1_Control,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application"
bitfld.long 0x00 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue" "0: Receive Queue Packet Arbitration is disabled,1: Receive Queue Packet Arbitration is enabled"
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bitfld.long 0x00 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0" "0,1,2,3,4,5,6,7"
group.long 0x1000++0x03
line.long 0x00 "DMA_Mode,The Bus Mode register establishes the bus operating modes for the DMA"
bitfld.long 0x00 16.--17. "INTM,Interrupt Mode This field defines the interrupt mode of DWC_ether_qos" "0: See above description,1: See above description,2: See above description,?..."
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bitfld.long 0x00 11. "TXPR,Transmit Priority When set this bit indicates that the Tx DMA has higher priority than the Rx DMA during arbitration for the system-side bus or Descriptor reads from DCACHE memory when DWC_EQOS_DCEXT is enabled" "0: Transmit Priority is disabled,1: Transmit Priority is enabled"
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bitfld.long 0x00 8. "DSPW,Descriptor Posted Write When this bit is set to" "0: Descriptor Posted Write is disabled,1: Descriptor Posted Write is enabled"
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bitfld.long 0x00 2.--4. "TAA,Transmit Arbitration Algorithm This field is used to select the arbitration algorithm for the Transmit side when multiple Tx DMAs are selected" "0: Fixed priority (Channel 0 has the lowest..,1: Weighted Strict Priority (WSP),2: Weighted Round-Robin (WRR),?..."
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bitfld.long 0x00 0. "SWR,Software Reset When this bit is set the MAC and the DMA controller reset the logic and all internal registers of the DMA MTL and MAC" "0: Software Reset is disabled,1: Software Reset is enabled"
group.long 0x1004++0x03
line.long 0x00 "DMA_SysBus_Mode,The System Bus mode register controls the behavior of the AHB or AXI master"
bitfld.long 0x00 31. "EN_LPI,Enable Low Power Interface (LPI) When set to" "0: Low Power Interface (LPI) is disabled,1: Low Power Interface (LPI) is enabled"
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bitfld.long 0x00 30. "LPI_XIT_PKT,Unlock on Magic Packet or Remote Wake-Up Packet When set to 1 this bit enables the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet is received" "0: Unlock on Magic Packet or Remote Wake-Up..,1: Unlock on Magic Packet or Remote Wake-Up.."
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bitfld.long 0x00 24.--26. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit This value limits the maximum outstanding request on the AXI write interface" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 13. "ONEKBBE,1 KB Boundary Crossing Enable for the EQOS-AXI Master" "0: 1 KB Boundary Crossing for the EQOS-AXI..,1: 1 KB Boundary Crossing for the EQOS-AXI.."
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bitfld.long 0x00 12. "AAL,Address-Aligned Beats When this bit is set to 1 the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels" "0: Address-Aligned Beats is disabled,1: Address-Aligned Beats is enabled"
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bitfld.long 0x00 10. "AALE,Automatic AXI LPI enable When set to 1 enables the AXI master to enter into LPI state when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in the LPIEI field of AXI_LPI_Entry_Interval register" "0: Automatic AXI LPI is disabled,1: Automatic AXI LPI is enabled"
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bitfld.long 0x00 7. "BLEN256,AXI Burst Length 256 When set to" "0: No effect,1: AXI Burst Length 256"
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bitfld.long 0x00 6. "BLEN128,AXI Burst Length 128 When set to" "0: No effect,1: AXI Burst Length 128"
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bitfld.long 0x00 5. "BLEN64,AXI Burst Length 64 When set to" "0: No effect,1: AXI Burst Length 64"
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bitfld.long 0x00 4. "BLEN32,AXI Burst Length 32 When set to" "0: No effect,1: AXI Burst Length 32"
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bitfld.long 0x00 3. "BLEN16,AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 1 the EQOS-AXI master can select a burst length of 16 on the AXI interface" "0: No effect,1: AXI Burst Length 16"
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bitfld.long 0x00 2. "BLEN8,AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 1 the EQOS-AXI master can select a burst length of 8 on the AXI interface" "0: No effect,1: AXI Burst Length 8"
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bitfld.long 0x00 1. "BLEN4,AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 1 the EQOS-AXI master can select a burst length of 4 on the AXI interface" "0: No effect,1: AXI Burst Length 4"
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bitfld.long 0x00 0. "FB,Fixed Burst Length" "0: Fixed Burst Length is disabled,1: Fixed Burst Length is enabled"
rgroup.long 0x1008++0x03
line.long 0x00 "DMA_Interrupt_Status,The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels MTL queues and the MAC"
bitfld.long 0x00 17. "MACIS,MAC Interrupt Status This bit indicates an interrupt event in the MAC" "0: MAC Interrupt Status not detected,1: MAC Interrupt Status detected"
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bitfld.long 0x00 16. "MTLIS,MTL Interrupt Status This bit indicates an interrupt event in the MTL" "0: MTL Interrupt Status not detected,1: MTL Interrupt Status detected"
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bitfld.long 0x00 1. "DC1IS,DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1" "0: DMA Channel 1 Interrupt Status not detected,1: DMA Channel 1 Interrupt Status detected"
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bitfld.long 0x00 0. "DC0IS,DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0" "0: DMA Channel 0 Interrupt Status not detected,1: DMA Channel 0 Interrupt Status detected"
rgroup.long 0x100C++0x03
line.long 0x00 "DMA_Debug_Status0,The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0-Channel 2 for debugging purpose"
bitfld.long 0x00 20.--23. "TPS1,DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
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bitfld.long 0x00 16.--19. "RPS1,DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
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bitfld.long 0x00 12.--15. "TPS0,DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0" "0: Stopped (Reset or Stop Transmit Command issued),1: Running (Fetching Tx Transfer Descriptor),2: Running (Waiting for status),3: Running (Reading Data from system memory..,4: Timestamp write state,?,6: Suspended (Tx Descriptor Unavailable or Tx..,7: Running (Closing Tx Descriptor),?..."
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bitfld.long 0x00 8.--11. "RPS0,DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0" "0: Stopped (Reset or Stop Receive Command issued),1: Running (Fetching Rx Transfer Descriptor),?,3: Running (Waiting for Rx packet),4: Suspended (Rx Descriptor Unavailable),5: Running (Closing the Rx Descriptor),6: Timestamp write state,7: Running (Transferring the received packet..,?..."
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bitfld.long 0x00 1. "AXRHSTS,AXI Master Read Channel Status When high this bit indicates that the read channel of the AXI master is active and it is transferring the data" "0: AXI Master Read Channel Status not detected,1: AXI Master Read Channel Status detected"
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bitfld.long 0x00 0. "AXWHSTS,AXI Master Write Channel When high this bit indicates that the write channel of the AXI master is active and it is transferring data" "0: AXI Master Write Channel or AHB Master Status..,1: AXI Master Write Channel or AHB Master Status.."
group.long 0x1020++0x03
line.long 0x00 "AXI4_Tx_AR_ACE_Control,This register is used to control the AXI4 Cache Coherency Signals for read transactions by all the Transmit DMA channels"
bitfld.long 0x00 20.--21. "THD,Transmit DMA First Packet Buffer This field is used to drive ardomain_o[1:0] signal when Transmit DMA is accessing First Buffer of the Packet (First valid buffer with FD being set in the TDES3 of the Descriptor)" "0,1,2,3"
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bitfld.long 0x00 16.--19. "THC,Transmit DMA First Packet Buffer This field is used to drive arcache_o[3:0] signal when Transmit DMA is accessing First Buffer of the Packet (First valid buffer with FD being set in the TDES3 of the Descriptor)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--13. "TED,Transmit DMA Extended Packet Buffer This field is used to drive ardomain_o[1:0] signal when Transmit DMA is accessing the extended buffers (when packet is distributed across multiple buffers)" "0,1,2,3"
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bitfld.long 0x00 8.--11. "TEC,Transmit DMA Extended Packet Buffer This field is used to drive arcache_o[3:0] signal when Transmit DMA is accessing the extended buffers (when packet is distributed across multiple buffers)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--5. "TDRD,Transmit DMA Read Descriptor Domain Control This field is used to drive ardomain_o[1:0] signal when Transmit DMA engines access the Descriptor" "0,1,2,3"
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bitfld.long 0x00 0.--3. "TDRC,Transmit DMA Read Descriptor Cache Control This field is used to drive arcache_o[3:0] signal when Transmit DMA engines access the Descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1024++0x03
line.long 0x00 "AXI4_Rx_AW_ACE_Control,This register is used to control the AXI4 Cache Coherency Signals for write transactions by all the Receive DMA channels"
bitfld.long 0x00 28.--29. "RDD,Receive DMA Buffer Domain Control This field is used to drive the awdomain_o[1:0] signal when Receive DMA is accessing the Buffer when Header and payload are NOT separated" "0,1,2,3"
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bitfld.long 0x00 24.--27. "RDC,Receive DMA Buffer Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Buffer when Header and payload are NOT separated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--21. "RHD,Receive DMA Header Domain Control This field is used to drive awdomain_o[1:0] and signal when Receive DMA is accessing the header Buffer when Header and payload are separated" "0,1,2,3"
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bitfld.long 0x00 16.--19. "RHC,Receive DMA Header Cache Control This field is used to drive awcache_o[3:0] and signal when Receive DMA is accessing the header Buffer when Header and payload are separated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--13. "RPD,Receive DMA Payload Domain Control This field is used to drive awdomain_o[1:0] signal when Receive DMA is accessing the Payload Buffer when Header and payload are separated" "0,1,2,3"
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bitfld.long 0x00 8.--11. "RPC,Receive DMA Payload Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Payload Buffer when Header and payload are separated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--5. "RDWD,Receive DMA Write Descriptor Domain Control This field is used to drive awdomain_o[1:0] signal when Receive DMA accesses the Descriptor" "0,1,2,3"
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bitfld.long 0x00 0.--3. "RDWC,Receive DMA Write Descriptor Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA accesses the Descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1028++0x03
line.long 0x00 "AXI4_TxRx_AWAR_ACE_Control,This register is used to control the AXI4 Cache Coherency Signals for Descriptor write transactions by all the TxDMA channels and Descriptor read transactions by all the RxDMA channels"
bitfld.long 0x00 20.--22. "WRP,DMA Write Protection control This field is used to drive awprot_m_o[2:0] signal on the AXI Write Channel" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. "RDP,DMA Read Protection control This field is used to drive arprot_m_o[2:0] signal during all read requests" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 12.--13. "RDRD,Receive DMA Read Descriptor Domain control This field is used to drive ardomain_o[1:0] signal when Receive DMA engines read the Descriptor" "0,1,2,3"
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bitfld.long 0x00 8.--11. "RDRC,Receive DMA Read Descriptor Cache control This field is used to drive arcache_o[3:0] signal when Receive DMA engines read the Descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--5. "TDWD,Transmit DMA Write Descriptor Domain control This field is used to drive awdomain_o[1:0] signal when Transmit DMA write to the Descriptor" "0,1,2,3"
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bitfld.long 0x00 0.--3. "TDWC,Transmit DMA Write Descriptor Cache control This field is used to drive awcache_o[3:0] signal when Transmit DMA writes to the Descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1040++0x03
line.long 0x00 "AXI_LPI_Entry_Interval,This register is used to control the AXI LPI entry interval"
bitfld.long 0x00 0.--3. "LPIEI,LPI Entry Interval Contains the number of system clock cycles multiplied by 64 to wait for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1050++0x03
line.long 0x00 "DMA_TBS_CTRL0,This register is used to control the TBS attributes"
hexmask.long.tbyte 0x00 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time"
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bitfld.long 0x00 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid" "0: Fetch Time Offset is invalid,1: Fetch Time Offset is valid"
rgroup.long 0x1080++0x03
line.long 0x00 "DMA_Safety_Interrupt_Status,This register indicates summary (whether error occurred in DMA/MTL/MAC and correctable/uncorrectable) of the Automotive Safety related error interrupts"
bitfld.long 0x00 31. "MCSIS,MAC Safety Uncorrectable Interrupt Status Indicates a uncorrectable Safety related Interrupt is set in the MAC module" "0: MAC Safety Uncorrectable Interrupt Status not..,1: MAC Safety Uncorrectable Interrupt Status.."
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bitfld.long 0x00 29. "MSUIS,MTL Safety Uncorrectable error Interrupt Status This bit indicates an uncorrectable error interrupt event in MTL" "0: MTL Safety Uncorrectable error Interrupt..,1: MTL Safety Uncorrectable error Interrupt.."
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bitfld.long 0x00 28. "MSCIS,MTL Safety Correctable error Interrupt Status This bit indicates a correctable error interrupt event in MTL" "0: MTL Safety Correctable error Interrupt Status..,1: MTL Safety Correctable error Interrupt Status.."
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bitfld.long 0x00 1. "DEUIS,DMA ECC Uncorrectable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature" "0: DMA ECC Uncorrectable error Interrupt Status..,1: DMA ECC Uncorrectable error Interrupt Status.."
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bitfld.long 0x00 0. "DECIS,DMA ECC Correctable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature" "0: DMA ECC Correctable error Interrupt Status..,1: DMA ECC Correctable error Interrupt Status.."
group.long 0x1100++0x03
line.long 0x00 "DMA_CH0_Control,The DMA Channeli Control register specifies the MSS value for segmentation length to skip between two descriptors and also the features such as header splitting and 8xPBL mode"
bitfld.long 0x00 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled"
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bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
group.long 0x1104++0x03
line.long 0x00 "DMA_CH0_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL TCP segmentation and Tx Channel weights"
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
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bitfld.long 0x00 24.--27. "TQOS,Transmit QOS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled"
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bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
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bitfld.long 0x00 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
group.long 0x1108++0x03
line.long 0x00 "DMA_CH0_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL buffer size and extended status"
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
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bitfld.long 0x00 24.--27. "RQOS,Rx AXI4 QOS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
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rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
group.long 0x1114++0x03
line.long 0x00 "DMA_CH0_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list"
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
group.long 0x111C++0x03
line.long 0x00 "DMA_CH0_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list"
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
group.long 0x1120++0x03
line.long 0x00 "DMA_CH0_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor"
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
group.long 0x1128++0x03
line.long 0x00 "DMA_CH0_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor"
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
group.long 0x112C++0x03
line.long 0x00 "DMA_CH0_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring"
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
group.long 0x1130++0x03
line.long 0x00 "DMA_CH0_Rx_Control2,The Channeli Receive Control register controls the Rx features such as Rx Descriptor Ring Length and Alternate Rx Buffer Size"
hexmask.long.byte 0x00 17.--23. 1. "ARBS,Alternate Receive Buffer Size Indicates size in bytes for Buffer 1 when ARBS is programmed to a non-zero value (when split header feature is not enabled)"
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hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
group.long 0x1134++0x03
line.long 0x00 "DMA_CH0_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register"
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
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bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
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bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
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bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
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bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
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bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
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bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
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bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
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bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
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bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
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bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
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bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
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bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
group.long 0x1138++0x03
line.long 0x00 "DMA_CH0_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA"
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
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hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
group.long 0x113C++0x03
line.long 0x00 "DMA_CH0_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path"
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
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bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
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bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
rgroup.long 0x1144++0x03
line.long 0x00 "DMA_CH0_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x114C++0x03
line.long 0x00 "DMA_CH0_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
rgroup.long 0x1154++0x03
line.long 0x00 "DMA_CH0_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x115C++0x03
line.long 0x00 "DMA_CH0_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
group.long 0x1160++0x03
line.long 0x00 "DMA_CH0_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA"
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
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bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
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bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
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bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
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bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
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bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
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bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
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bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
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bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
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bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
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bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
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bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
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bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
rgroup.long 0x1164++0x03
line.long 0x00 "DMA_CH0_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register"
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
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hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register"
rgroup.long 0x1168++0x03
line.long 0x00 "DMA_CH0_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser"
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented when a Rx Parser Accept a packet due to AF =1"
group.long 0x1180++0x03
line.long 0x00 "DMA_CH1_Control,The DMA Channeli Control register specifies the MSS value for segmentation length to skip between two descriptors and also the features such as header splitting and 8xPBL mode"
bitfld.long 0x00 24. "SPH,Split Headers When this bit is set the DMA splits the header and payload in the Receive path" "0: Split Headers feature is disabled,1: Split Headers feature is enabled"
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bitfld.long 0x00 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "PBLx8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH(#i)_Tx_Control and Bits[21:16] in DMA_CH(#i)_Rx_Control is multiplied by eight times" "0: 8xPBL mode is disabled,1: 8xPBL mode is enabled"
group.long 0x1184++0x03
line.long 0x00 "DMA_CH1_Tx_Control,The DMA Channeli Transmit Control register controls the Tx features such as PBL TCP segmentation and Tx Channel weights"
bitfld.long 0x00 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors" "0: Enhanced Descriptor is disabled,1: Enhanced Descriptor is enabled"
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bitfld.long 0x00 24.--27. "TQOS,Transmit QOS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--21. "TxPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer" "0: Ignore PBL Requirement is disabled,1: Ignore PBL Requirement is enabled"
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bitfld.long 0x00 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained" "0: Operate on Second Packet disabled,1: Operate on Second Packet enabled"
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bitfld.long 0x00 1.--3. "TCW,Transmit Channel Weight This field indicates the weight assigned to the corresponding Transmit channel" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state" "0: Stop Transmission Command,1: Start Transmission Command"
group.long 0x1188++0x03
line.long 0x00 "DMA_CH1_Rx_Control,The DMA Channeli Receive Control register controls the Rx features such as PBL buffer size and extended status"
bitfld.long 0x00 31. "RPF,Rx Packet Flush" "0: Rx Packet Flush is disabled,1: Rx Packet Flush is enabled"
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bitfld.long 0x00 24.--27. "RQOS,Rx AXI4 QOS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--21. "RxPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 4.--14. 1. "RBSZ_13_y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0"
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rbitfld.long 0x00 1.--3. "RBSZ_x_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets" "0: Stop Receive,1: Start Receive"
group.long 0x1194++0x03
line.long 0x00 "DMA_CH1_TxDesc_List_Address,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list"
hexmask.long 0x00 3.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list"
group.long 0x119C++0x03
line.long 0x00 "DMA_CH1_RxDesc_List_Address,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list"
hexmask.long 0x00 3.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list"
group.long 0x11A0++0x03
line.long 0x00 "DMA_CH1_TxDesc_Tail_Pointer,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor"
hexmask.long 0x00 3.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring"
group.long 0x11A8++0x03
line.long 0x00 "DMA_CH1_RxDesc_Tail_Pointer,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor"
hexmask.long 0x00 3.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring"
group.long 0x11AC++0x03
line.long 0x00 "DMA_CH1_TxDesc_Ring_Length,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring"
hexmask.long.word 0x00 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring"
group.long 0x11B0++0x03
line.long 0x00 "DMA_CH1_Rx_Control2,The Channeli Receive Control register controls the Rx features such as Rx Descriptor Ring Length and Alternate Rx Buffer Size"
hexmask.long.byte 0x00 17.--23. 1. "ARBS,Alternate Receive Buffer Size Indicates size in bytes for Buffer 1 when ARBS is programmed to a non-zero value (when split header feature is not enabled)"
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hexmask.long.word 0x00 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring"
group.long 0x11B4++0x03
line.long 0x00 "DMA_CH1_Interrupt_Enable,The Channeli Interrupt Enable register enables the interrupts reported by the Status register"
bitfld.long 0x00 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled" "0: Normal Interrupt Summary is disabled,1: Normal Interrupt Summary is enabled"
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bitfld.long 0x00 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled" "0: Abnormal Interrupt Summary is disabled,1: Abnormal Interrupt Summary is enabled"
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bitfld.long 0x00 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled" "0: Context Descriptor Error is disabled,1: Context Descriptor Error is enabled"
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bitfld.long 0x00 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled" "0: Fatal Bus Error is disabled,1: Fatal Bus Error is enabled"
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bitfld.long 0x00 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled" "0: Early Receive Interrupt is disabled,1: Early Receive Interrupt is enabled"
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bitfld.long 0x00 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled" "0: Early Transmit Interrupt is disabled,1: Early Transmit Interrupt is enabled"
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bitfld.long 0x00 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled" "0: Receive Watchdog Timeout is disabled,1: Receive Watchdog Timeout is enabled"
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bitfld.long 0x00 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled" "0: Receive Stopped is disabled,1: Receive Stopped is enabled"
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bitfld.long 0x00 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled" "0: Receive Buffer Unavailable is disabled,1: Receive Buffer Unavailable is enabled"
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bitfld.long 0x00 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled" "0: Receive Interrupt is disabled,1: Receive Interrupt is enabled"
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bitfld.long 0x00 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled" "0: Transmit Buffer Unavailable is disabled,1: Transmit Buffer Unavailable is enabled"
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bitfld.long 0x00 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled" "0: Transmit Stopped is disabled,1: Transmit Stopped is enabled"
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bitfld.long 0x00 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled" "0: Transmit Interrupt is disabled,1: Transmit Interrupt is enabled"
group.long 0x11B8++0x03
line.long 0x00 "DMA_CH1_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA"
bitfld.long 0x00 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field" "0,1,2,3"
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hexmask.long.byte 0x00 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set"
group.long 0x11BC++0x03
line.long 0x00 "DMA_CH1_Slot_Function_Control_Status,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path"
rbitfld.long 0x00 16.--19. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets"
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bitfld.long 0x00 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "0: Advance Slot Check is disabled,1: Advance Slot Check is enabled"
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bitfld.long 0x00 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field" "0: Slot Comparison is disabled,1: Slot Comparison is enabled"
rgroup.long 0x11C4++0x03
line.long 0x00 "DMA_CH1_Current_App_TxDesc,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x11CC++0x03
line.long 0x00 "DMA_CH1_Current_App_RxDesc,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation"
rgroup.long 0x11D4++0x03
line.long 0x00 "DMA_CH1_Current_App_TxBuffer,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation"
rgroup.long 0x11DC++0x03
line.long 0x00 "DMA_CH1_Current_App_RxBuffer,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA"
hexmask.long 0x00 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation"
group.long 0x11E0++0x03
line.long 0x00 "DMA_CH1_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA"
rbitfld.long 0x00 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit" "0: Normal Interrupt Summary status not detected,1: Normal Interrupt Summary status detected"
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bitfld.long 0x00 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit" "0: Abnormal Interrupt Summary status not detected,1: Abnormal Interrupt Summary status detected"
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bitfld.long 0x00 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "0: Context Descriptor Error status not detected,1: Context Descriptor Error status detected"
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bitfld.long 0x00 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field)" "0: Fatal Bus Error status not detected,1: Fatal Bus Error status detected"
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bitfld.long 0x00 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory" "0: Early Receive Interrupt status not detected,1: Early Receive Interrupt status detected"
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bitfld.long 0x00 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory" "0: Early Transmit Interrupt status not detected,1: Early Transmit Interrupt status detected"
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bitfld.long 0x00 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received" "0: Receive Watchdog Timeout status not detected,1: Receive Watchdog Timeout status detected"
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bitfld.long 0x00 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state" "0: Receive Process Stopped status not detected,1: Receive Process Stopped status detected"
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bitfld.long 0x00 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it" "0: Receive Buffer Unavailable status not detected,1: Receive Buffer Unavailable status detected"
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bitfld.long 0x00 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete" "0: Receive Interrupt status not detected,1: Receive Interrupt status detected"
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bitfld.long 0x00 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it" "0: Transmit Buffer Unavailable status not detected,1: Transmit Buffer Unavailable status detected"
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bitfld.long 0x00 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped" "0: Transmit Process Stopped status not detected,1: Transmit Process Stopped status detected"
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bitfld.long 0x00 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete" "0: Transmit Interrupt status not detected,1: Transmit Interrupt status detected"
rgroup.long 0x11E4++0x03
line.long 0x00 "DMA_CH1_Miss_Frame_Cnt,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register"
bitfld.long 0x00 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further" "0: Miss Frame Counter overflow not occurred,1: Miss Frame Counter overflow occurred"
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hexmask.long.word 0x00 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register"
rgroup.long 0x11E8++0x03
line.long 0x00 "DMA_CH1_RXP_Accept_Cnt,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser"
bitfld.long 0x00 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit" "0: Rx Parser Accept Counter overflow not occurred,1: Rx Parser Accept Counter overflow occurred"
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hexmask.long 0x00 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented when a Rx Parser Accept a packet due to AF =1"
tree.end
tree.end
tree "I2C (Inter-Integrated Circuit)"
repeat 2. (list 0. 1.) (list ad:0x40298000 ad:0x40498000)
tree "I2C_$1"
base $2
group.byte 0x00++0x00
line.byte 0x00 "IBAD,I2C Bus Address"
hexmask.byte 0x00 1.--7. 1. "ADR,Slave Address"
group.byte 0x01++0x00
line.byte 0x00 "IBFD,I2C Bus Frequency Divider"
hexmask.byte 0x00 0.--7. 1. "IBC,I-Bus Clock Rate"
group.byte 0x02++0x00
line.byte 0x00 "IBCR,I2C Bus Control"
bitfld.byte 0x00 7. "MDIS,Module Disable" "0: The module is enabled,1: The module is reset and disabled"
bitfld.byte 0x00 6. "IBIE,Bus Interrupt Enable" "0: Interrupts from I2C are disabled,1: Interrupts from I2C are enabled"
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bitfld.byte 0x00 5. "MSSL,Master/Slave Mode Select" "0: SLAVE_MODE,1: MASTER_MODE"
bitfld.byte 0x00 4. "TXRX,Transmit/Receive Mode Select" "0: Receive,1: Transmit"
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bitfld.byte 0x00 3. "NOACK,Data Acknowledge Disable" "0: Send an acknowledge signal to the bus at the..,1: Do not send an acknowledge-signal response.."
bitfld.byte 0x00 2. "RSTA,Repeat START" "0: NO_REP_START,1: Generate repeated START condition"
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bitfld.byte 0x00 1. "DMAEN,DMA Enable" "0: Disable the DMA TX/RX request signals,1: Enable the DMA TX/RX request signals"
group.byte 0x03++0x00
line.byte 0x00 "IBSR,I2C Bus Status"
rbitfld.byte 0x00 7. "TCF,Transfer Complete" "0: XFER_IN_PROGRESS,1: XFER_COMPLETE"
rbitfld.byte 0x00 6. "IAAS,Addressed As A Slave" "0: ADDR_AS_SLV_NO,1: Addressed as a slave"
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rbitfld.byte 0x00 5. "IBB,Bus Busy" "0: BUS_IDLE,1: BUS_BUSY"
eventfld.byte 0x00 4. "IBAL,Arbitration Lost" "0,1"
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rbitfld.byte 0x00 2. "SRW,Slave Read/" "0: Slave receive master writing to slave,1: Slave transmit master reading from slave"
eventfld.byte 0x00 1. "IBIF,Bus Interrupt Flag" "0,1"
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rbitfld.byte 0x00 0. "RXAK,Received Acknowledge" "0: Acknowledge received,1: No acknowledge received"
group.byte 0x04++0x00
line.byte 0x00 "IBDR,I2C Bus Data I/O"
hexmask.byte 0x00 0.--7. 1. "DATA,Data transmitted or received"
group.byte 0x05++0x00
line.byte 0x00 "IBIC,I2C Bus Interrupt Configuration"
bitfld.byte 0x00 7. "BIIE,Bus Idle Interrupt Enable" "0: BI_INT_DISABLED,1: BI_INT_ENABLED"
bitfld.byte 0x00 6. "BYTERXIE,Byte Receive Interrupt Enable" "0,1"
group.byte 0x06++0x00
line.byte 0x00 "IBDBG,I2C Bus Debug"
bitfld.byte 0x00 3. "GLFLT_EN,Glitch Filter Enable" "0: The I2C module allows all pulses on the SCL..,1: The I2C module filters out any pulse (rising.."
eventfld.byte 0x00 2. "BYTE_RX,Byte Receive" "0,1"
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rbitfld.byte 0x00 1. "IPG_DEBUG_HALTED,Debug Halted" "0: Still executing a transaction,1: Entered DEBUG mode"
bitfld.byte 0x00 0. "IPG_DEBUG_EN,Debug Enable" "0: Normal operation the bus idle interrupts are..,1: In DEBUG mode"
tree.end
repeat.end
tree.end
tree "JDC"
base ad:0x400E4000
group.long 0x00++0x03
line.long 0x00 "MCR,Module Configuration Register"
bitfld.long 0x00 16. "JIN_IEN,JIN Interrupt Enable" "0: Setting MSR[JIN_INT] bit does not assert the..,1: Setting MSR[JIN_INT] bit asserts the JIN.."
bitfld.long 0x00 0. "JOUT_IEN,JOUT Interrupt Enable" "0: Setting MSR[JOUT_INT] bit does not assert the..,1: Setting MSR[JOUT_INT] bit asserts the JOUT.."
group.long 0x04++0x03
line.long 0x00 "MSR,Module Status Register"
rbitfld.long 0x00 18. "JIN_RDY,JIN Ready (read only)" "0: Cleared upon software read of JIN_IPS..,1: Set when new data is written to the JIN_IPS.."
eventfld.long 0x00 16. "JIN_INT,JIN Interrupt" "0: Cleared by writing logic 1,1: Set when new data is written to the JIN_IPS.."
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rbitfld.long 0x00 2. "JOUT_RDY,JOUT Ready (read only)" "0: Cleared upon tool read of JOUT register via..,1: Set when new data is written to the JOUT_IPS.."
eventfld.long 0x00 0. "JOUT_INT,JOUT Interrupt" "0: Cleared by writing logic 1,1: Set when JOUT_RDY bit is cleared by tool.."
group.long 0x08++0x03
line.long 0x00 "JOUT_IPS,JTAG Output Data Register"
hexmask.long 0x00 0.--31. 1. "Data,JOUT_IPS Data"
rgroup.long 0x0C++0x03
line.long 0x00 "JIN_IPS,JTAG Input Data Register"
hexmask.long 0x00 0.--31. 1. "Data,JIN_IPS data"
tree.end
tree "LINFLEXD"
base ad:0x4048C000
group.long 0x00++0x03
line.long 0x00 "LINCR1,LIN Control Register 1"
bitfld.long 0x00 16. "NLSE,LIN State Capture Enable on Bit Error Enables capture of LIN state LINSR[LINS] whenever bit error flag occur that is LINESR[BEF] set to 1" "0: LIN state LINSR[LINS] shows the current LIN..,1: LIN state LINSR[LINS] is captured whenever.."
bitfld.long 0x00 15. "CCD,Checksum Calculation Disable You can read this field at any time and write to it only in Initialization mode" "0: Hardware performs the checksum calculation,1: Checksum calculation disabled"
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bitfld.long 0x00 14. "CFD,Checksum Field Disable You can read this field at any time and write to it only in Initialization mode" "0: Checksum field is sent after the required..,1: No checksum field is sent in the frame"
bitfld.long 0x00 12. "AUTOWU,Auto Wakeup You can read this field at any time and write to it only in Initialization mode" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever.."
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bitfld.long 0x00 8.--11. "MBL,Master Break Length Chooses the length of the Sync break that the master generates" "0: 10-bit break length,1: 11-bit break length,2: 12-bit break length,3: 13-bit break length,4: 14-bit break length,5: 15-bit break length,6: 16-bit break length,7: 17-bit break length,8: 18-bit break length,9: 19-bit break length,10: 20-bit break length,11: 21-bit break length,12: 22-bit break length,13: 23-bit break length,14: 36-bit break length,15: 50-bit break length"
bitfld.long 0x00 5. "LBKM,Loop Back mode See Loop back mode in" "0: Loop Back mode disabled,1: Loop Back mode enabled"
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bitfld.long 0x00 4. "MME,Master Mode Enable You can read this field at any time and write to it only in Initialization mode" "0: Slave mode,1: Master mode"
bitfld.long 0x00 3. "SSBL,Slave Mode Sync Break Length You can read this field at any time and write to it only in Initialization mode" "0: 11-bit break length,1: 10-bit break length"
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bitfld.long 0x00 2. "RBLM,Receiver Buffer Locked mode You can read this field at any time and write to it only in Initialization mode" "0: Receiver buffer not locked,1: Receiver buffer locked against overrun"
bitfld.long 0x00 1. "SLEEP,Sleep Mode Request Write a 1 to this field to request LINFlexD to enter Sleep mode" "0,1"
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bitfld.long 0x00 0. "INIT,Initialization Mode Request Write a 1 to this field to request LINFlexD to enter Initialization mode" "0,1"
group.long 0x04++0x03
line.long 0x00 "LINIER,LIN Interrupt Enable Register"
bitfld.long 0x00 15. "SZIE,Stuck at Zero Interrupt Enable An interrupt is generated if this bit is set and the Stuck at Zero Flag (SZF) in LINESR or UARTSR is set" "0: No interrupt,1: Interrupt enabled"
bitfld.long 0x00 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.."
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bitfld.long 0x00 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is.."
bitfld.long 0x00 12. "CEIE,Checksum Error Interrupt Enable An interrupt is generated if this bit is set and the Checksum Error Flag (CEF) is set in LINESR" "0: No interrupt,1: Interrupt enabled"
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bitfld.long 0x00 11. "HEIE,Header Error Interrupt Enable An interrupt is generated when this bit is set and either of the following flags are set: SFEF SDEF or IDPEF" "0: No interrupt,1: Interrupt enabled"
bitfld.long 0x00 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).."
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bitfld.long 0x00 7. "BOIE,Buffer Overrun Error Interrupt Enable An interrupt is generated if this bit is set and the Buffer Overrun Flag (BOF) is set in LINESR or UARTSR" "0: No interrupt,1: Interrupt enabled"
bitfld.long 0x00 6. "LSIE,LIN State Interrupt Enable Interrupt is generated only when entering the above fields" "0: No interrupt,1: Interrupt generated when entering the.."
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bitfld.long 0x00 5. "WUIE,Wakeup Interrupt Enable If WUIE=1 and the WUF in LINSR or UARTSR is set then an interrupt is generated" "0: No interrupt,1: Interrupt enabled"
bitfld.long 0x00 3. "TOIE,Timeout Interrupt Enable An interrupt is generated if this bit is set and UARTSR[TO]=1 (in UART mode)" "0: No interrupt,1: Interrupt enabled"
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bitfld.long 0x00 2. "DRIE,Data Reception Complete Interrupt Enable An interrupt is generated when this bit is set and Data Received flag (DRF) in LINSR or UARTSR is set" "0: No interrupt,1: Interrupt enabled"
bitfld.long 0x00 1. "DTIE,Data Transmitted Interrupt enable An interrupt is generated when this bit is set and Data Transmitted flag (DTF) in LINSR or UARTSR is set" "0: No interrupt,1: Interrupt enabled"
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bitfld.long 0x00 0. "HRIE,Header Received Interrupt An interrupt is generated when this bit is set and the Header Received flag (HRF) in LINSR is set" "0: No interrupt,1: Interrupt enabled"
group.long 0x08++0x03
line.long 0x00 "LINSR,LIN Status Register"
rbitfld.long 0x00 16.--18. "RDC,Receive Data Byte Count Contains the number of entries (bytes) in the Receive data buffer in LIN mode" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes"
bitfld.long 0x00 12.--15. "LINS,LIN State" "0: Sleep mode,1: Init mode,2: Idle mode,3: Sync break,4: Sync Del,5: Sync Field,6: Identifier Field,7: Header Reception/Transmission,8: Data Reception/Data Transmission,9: Checksum,?..."
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eventfld.long 0x00 9. "RMB,Release Message Buffer" "0: Buffer data is free and is reset by hardware..,1: Buffer data ready to be read by software"
eventfld.long 0x00 8. "DRBNE,Data Reception Buffer Not Empty LINFlexD writes a 1 to this field as soon as the first byte of response has been received and stored in BDRL (when there is at least one data byte in reception buffer)" "0,1"
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rbitfld.long 0x00 7. "RXBUSY,Receiver Busy In Slave mode after header reception if DIR bit is reset and reception starts then this bit is set" "0: Receiver idle,1: Reception ongoing"
rbitfld.long 0x00 6. "RDI,Receiver Data Input Reflects the current status of the Rx pin After reset is released RDI reflects the actual value of Rx pin" "0,1"
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eventfld.long 0x00 5. "WUF,Wakeup flag This bit is set by hardware when a falling edge is detected on the Rx pin" "0,1"
eventfld.long 0x00 2. "DRF,Data Reception Completed Flag This bit is set by hardware and indicates that data reception completed" "0,1"
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eventfld.long 0x00 1. "DTF,Data Transmission Completed Flag This bit is set by hardware and indicates that data transmission completed" "0,1"
eventfld.long 0x00 0. "HRF,Header Received flag This bit is set when the header reception is completed" "0,1"
group.long 0x0C++0x03
line.long 0x00 "LINESR,LIN Error Status Register"
eventfld.long 0x00 15. "SZF,Stuck At Zero Flag This bit is set when there is a stuck-at-zero timeout error" "0,1"
eventfld.long 0x00 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: In master mode LINESR[OCF] flag is set when.."
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eventfld.long 0x00 13. "BEF,Bit Error Flag LINFlexD writes a 1 to this field when a bit error occurs" "0,1"
eventfld.long 0x00 12. "CEF,Checksum Error Flag LINFlexD writes a 1 to this field if the received checksum does not match the hardware-calculated checksum" "0,1"
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eventfld.long 0x00 11. "SFEF,Sync Field Error Flag LINFlexD writes a 1 to this field when the received Sync Field is inconsistent" "0,1"
eventfld.long 0x00 10. "SDEF,Sync Delimiter Error Flag TLINFlexD writes a 1 to this field when the delimiter is too short (in other words less than one bit time)" "0,1"
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eventfld.long 0x00 9. "IDPEF,ID Parity Error Flag TLINFlexD writes a 1 to this field when an error in the ID parity occurs" "0,1"
eventfld.long 0x00 8. "FEF,Framing Error Flag LINFlexD writes a 1 to this field when a framing error (invalid stop bit) occurs" "0,1"
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eventfld.long 0x00 7. "BOF,Buffer Overrun Flag This bit is set by hardware when there is a new byte received and RMB bit is not cleared" "0,1"
eventfld.long 0x00 0. "NF,Noise Flag This bit is set by hardware when noise is detected in the received character" "0,1"
group.long 0x10++0x03
line.long 0x00 "UARTCR,UART Mode Control Register"
bitfld.long 0x00 31. "MIS,Monitor Idle State Controls what UARTCTO monitors" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the.."
bitfld.long 0x00 28.--30. "CSP,Configurable Sample Point Decides the sample point during reduced oversampling" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--27. "OSR,Over Sampling Rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times,1: OSR determines the oversampling rate"
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bitfld.long 0x00 20.--22. "NEF,Number of expected frames" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.."
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bitfld.long 0x00 17.--18. "SBUR,Stop Bits In UART Reception Mode When the UART is used for transmission and reception you need to set the same number of stop bits in GCR and SBUR" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?..."
bitfld.long 0x00 16. "WLS,Special Word Length in UART mode If this bit is set setting WL and PCE bits has no effect in UART reception although parity check is enabled by default in this mode and PC0/1 bits can be used to select the parity control" "0: This bit is disabled,1: This bit enables 12-bit + parity bit in.."
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bitfld.long 0x00 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter TDFL defines the number of bytes to be transmitted in UART buffer mode (TFBM = 0)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter RDFL defines the number of bytes to be received in UART buffer mode (RFBM = 0)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9. "RFBM,Rx FIFO/Buffer Mode Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled (mandatory in DMA Rx mode)"
bitfld.long 0x00 8. "TFBM,Tx FIFO/Buffer Mode Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled (mandatory in DMA Tx mode)"
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bitfld.long 0x00 7. "WL1,Word Length In UART Mode Works with WL0 to configure word length as shown in the following table" "0,1"
bitfld.long 0x00 6. "PC1,Parity Control Works with PC0 to configure parity as shown in the following table" "0,1"
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bitfld.long 0x00 5. "RxEn,Receiver Enable This bit can be programmed only when the UART bit is set" "0: Receiver disabled,1: Receiver enabled"
bitfld.long 0x00 4. "TxEn,Transmitter Enable This bit can be programmed only when UART bit is set" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.."
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bitfld.long 0x00 3. "PC0,Parity Control Works with PC1 to configure parity" "0,1"
bitfld.long 0x00 2. "PCE,Parity Control Enable Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Parity transmit/check disabled,1: Parity transmit/check enabled"
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bitfld.long 0x00 1. "WL0,Word Length in UART mode Works with WL1 to configure word length" "0,1"
bitfld.long 0x00 0. "UART,UART Mode Register bit can be read in any mode written only in initialization mode" "0: LIN mode,1: UART mode"
group.long 0x14++0x03
line.long 0x00 "UARTSR,UART Mode Status Register"
eventfld.long 0x00 15. "SZF,Stuck At Zero Flag LINFlexD writes a 1 to this field when LINFlexD detects 100 dominant bits" "0,1"
eventfld.long 0x00 14. "OCF,Output Compare Flag An interrupt will be generated if the OCIE bit in LINIER is set" "0: No output compare event occurred,1: The content of the counter has matched the.."
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eventfld.long 0x00 10.--13. "PE,Parity Error Flag Indicates whether a parity error occurred in the corresponding byte" "0: No parity error,1: Parity error in the corresponding received byte,?..."
eventfld.long 0x00 9. "RMB,Release Message Buffer This bit must be cleared by software" "0: Buffer data is free,1: Buffer data ready for software to"
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eventfld.long 0x00 8. "FEF,Framing Error Flag LINFlexD writes a 1 to this field when a framing error (invalid stop bit) occurs" "0: No framing error,1: Framing error occurs"
eventfld.long 0x00 7. "BOF,FIFO/Buffer overrun flag This bit is set by hardware when there is a new byte received and the RMB bit is not cleared in UART buffer mode" "0,1"
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rbitfld.long 0x00 6. "RDI,Receiver Data Input signal This bit reflects the current status of the RX pin when UART bit is set" "0,1"
eventfld.long 0x00 5. "WUF,Wakeup flag This bit is set by hardware when a falling edge is detected on the RX pin in sleep mode" "0,1"
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rbitfld.long 0x00 4. "RFNE,Receive FIFO Not Empty RFNE bit is set by hardware in UART FIFO mode (RFBM = 1) when there is at least one data byte present in the receive FIFO" "0,1"
eventfld.long 0x00 3. "TO,Timeout This bit is set by hardware when a UART timeout occurs - in other words the value of UARTCTO becomes equal to the preset value of the timeout (UARTPTO register setting)" "0,1"
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eventfld.long 0x00 2. "DRFRFE,Data Reception Completed Flag /Rx FIFO Empty Flag DRF is set by hardware in UART buffer mode (RFBM = 0) and indicates that the number of bytes programmed in RDFL have been received" "0,1"
eventfld.long 0x00 1. "DTFTFF,Data Transmission Completed Flag/ TX FIFO Full Flag DTF is set by hardware in UART buffer mode (TFBM = 0) and indicates that data transmission is completed" "0,1"
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eventfld.long 0x00 0. "NF,Noise flag This bit is set by hardware when noise is detected in the received character" "0,1"
group.long 0x18++0x03
line.long 0x00 "LINTCSR,LIN Time-Out Control Status Register"
bitfld.long 0x00 10. "MODE,Time-out counter mode This bit can be configured only during initialization" "0: LIN mode,1: Output compare mode"
bitfld.long 0x00 9. "IOT,Idle on timeout Register bit can be read in any mode written only in initialization mode" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout.."
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bitfld.long 0x00 8. "TOCE,Time-out counter enable TOCE is always configurable by software in Initialization mode" "0: Time-out counter disable,1: Time-out counter enable"
hexmask.long.byte 0x00 0.--7. 1. "CNT,Counter Value These bits reflect the value of a counter used for timeout"
group.long 0x1C++0x03
line.long 0x00 "LINOCR,LIN Output Compare Register"
hexmask.long.byte 0x00 8.--15. 1. "OC2,Output compare value 2"
hexmask.long.byte 0x00 0.--7. 1. "OC1,Output compare value 1"
group.long 0x20++0x03
line.long 0x00 "LINTOCR,LIN Time-Out Control Register"
bitfld.long 0x00 8.--11. "RTO,Response timeout value This is the response timeout duration (in bit time) for 1 byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--6. 1. "HTO,Header timeout value This register contains the header timeout duration (in bit time)"
group.long 0x24++0x03
line.long 0x00 "LINFBRR,LIN Fractional Baud Rate Register"
bitfld.long 0x00 0.--3. "FBR,Fractional Baud rates Register bit can be read in any mode written only in initialization mode" "0: Fraction(LDIV) = 0,1: Fraction(LDIV) = 1/16,2: Fraction(LDIV) = 2/16,3: Fraction(LDIV) = 3/16,4: Fraction(LDIV) = 4/16,5: Fraction(LDIV) = 5/16,6: Fraction(LDIV) = 6/16,7: Fraction(LDIV) = 7/16,8: Fraction(LDIV) = 8/16,9: Fraction(LDIV) = 9/16,10: Fraction(LDIV) = 10/16,11: Fraction(LDIV) = 11/16,12: Fraction(LDIV) = 12/16,13: Fraction(LDIV) = 13/16,14: Fraction(LDIV) = 14/16,15: Fraction(LDIV) = 15/16"
group.long 0x28++0x03
line.long 0x00 "LINIBRR,LIN Integer Baud Rate Register"
hexmask.long.tbyte 0x00 0.--19. 1. "IBR,Integer Baud rates These bits along with the fractional baud rate bits decide the LIN baud rate"
group.long 0x2C++0x03
line.long 0x00 "LINCFR,LIN Checksum Field Register"
hexmask.long.byte 0x00 0.--7. 1. "CF,Checksum bits When the CCD bit is reset these bits are read-only and are calculated by hardware"
group.long 0x30++0x03
line.long 0x00 "LINCR2,LIN Control Register 2"
bitfld.long 0x00 15. "TBDE,Two Bit delimiter bit This bit can be set in Initialization mode only" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits"
bitfld.long 0x00 14. "IOBE,Idle on Bit Error This bit can be set in Initialization mode only" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine"
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bitfld.long 0x00 13. "IOPE,Idle on Identifier Parity Error This bit can be set in Initialization mode only" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine"
bitfld.long 0x00 12. "WURQ,Wakeup Generate Request Setting this bit will generate a wakeup pulse" "0,1"
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bitfld.long 0x00 11. "DDRQ,Data Discard request Set by software to stop data reception if the frame does not concern the node" "0,1"
bitfld.long 0x00 10. "DTRQ,Data Transmission Request Set by software in slave mode to request the transmission of the LIN Data field stored in the Buffer data register" "0,1"
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bitfld.long 0x00 9. "ABRQ,Abort Request Set by software to abort the current transmission" "0,1"
bitfld.long 0x00 8. "HTRQ,Header Transmission Request Set by software to request the transmission of the LIN Header" "0,1"
group.long 0x34++0x03
line.long 0x00 "BIDR,Buffer Identifier Register"
bitfld.long 0x00 10.--12. "DFL,Data Field Length Number of data bytes in the response part of the frame" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "DIR,Direction This bit controls the direction of the data field" "0: LINFlexD receives the data and copy them in..,1: LINFlexD transmits the data from the BDR.."
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bitfld.long 0x00 8. "CCS,Classic Checksum This bit controls the type of checksum applied on the current message" "0: Enhanced Checksum covering Identifier and..,1: Classic Checksum covering Data filed only"
bitfld.long 0x00 0.--5. "ID,Identifier Identifier part of the identifier field without the identifier parity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x38++0x03
line.long 0x00 "BDRL,Buffer Data Register Least Significant"
hexmask.long.byte 0x00 24.--31. 1. "DATA3,Data Byte 3 Data byte 3 of the data field"
hexmask.long.byte 0x00 16.--23. 1. "DATA2,Data Byte 2 Data byte 2 of the data field"
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hexmask.long.byte 0x00 8.--15. 1. "DATA1,Data Byte 1 Data byte 1of the data field"
hexmask.long.byte 0x00 0.--7. 1. "DATA0,Data Byte 0 Data byte 0 of the data field"
group.long 0x3C++0x03
line.long 0x00 "BDRM,Buffer Data Register Most Significant"
hexmask.long.byte 0x00 24.--31. 1. "DATA7,Data Byte 7 Data byte 7 of the data field"
hexmask.long.byte 0x00 16.--23. 1. "DATA6,Data Byte 6 Data byte 6 of the data field"
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hexmask.long.byte 0x00 8.--15. 1. "DATA5,Data Byte 5 Data byte 5 of the data field"
hexmask.long.byte 0x00 0.--7. 1. "DATA4,Data Byte 4 Data byte 4 of the data field"
group.long 0x4C++0x03
line.long 0x00 "GCR,Global Control Register"
bitfld.long 0x00 5. "TDFBM,Transmit data first bit MSB This bit controls the first bit of transmit data (payload only) as MSB/LSB in both UART and LIN modes" "0: The first bit of transmitted data is LSB - in..,1: The first bit of transmitted data is MSB - in.."
bitfld.long 0x00 4. "RDFBM,Received data first bit MSB This bit controls the first bit of received data (payload only) as MSB/LSB both in UART and LIN modes" "0: The first bit of received data is LSB - in..,1: The first bit of received data is MSB - in.."
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bitfld.long 0x00 3. "TDLIS,Transmit data level inversion selection This bit controls the data inversion of transmitted data (payload only) in both UART and LIN modes" "0: Transmitted data is not inverted,1: Transmitted data is inverted"
bitfld.long 0x00 2. "RDLIS,Received data level inversion selection This bit controls the data inversion of received data (payload only) in both UART and LIN modes" "0: Received data is not inverted,1: Received data is inverted"
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bitfld.long 0x00 1. "STOP,1/2 stop bit configuration This bit controls the number of stop bit transmitted data in both UART and LIN modes" "0: 1 stop bit,1: 2 stop bits"
bitfld.long 0x00 0. "SR,Soft reset SR executes a soft reset of the LINFlexD controller (FSMs FIFO pointers counters timers status and error registers) without modifying the configuration registers when a 1 write operation is performed" "0,1"
group.long 0x50++0x03
line.long 0x00 "UARTPTO,UART Preset Timeout Register"
hexmask.long.word 0x00 0.--11. 1. "PTO,Preset Timeout PTO defines the preset value of timeout counter"
rgroup.long 0x54++0x03
line.long 0x00 "UARTCTO,UART Current Timeout Register"
hexmask.long.word 0x00 0.--11. 1. "CTO,Current Timeout CTO defines the current value of the timeout counter"
group.long 0x58++0x03
line.long 0x00 "DMATXE,DMA Tx Enable Register"
bitfld.long 0x00 0. "DTE0,DMA Tx channel enable" "0: nth DMA Tx channel disabled,1: nth DMA Tx channel enabled"
group.long 0x5C++0x03
line.long 0x00 "DMARXE,DMA Rx Enable Register"
bitfld.long 0x00 0. "DRE0,DMA Rx channel enable The number of DRE bits varies and is equal to DMA_RX_CH_NUM" "0: nth DMA Rx channel disabled,1: nth DMA Rx channel enabled"
tree.end
tree "MC_CGM"
tree "MC_CGM_0"
base ad:0x400C8000
group.long 0x300++0x03
line.long 0x00 "MUX_0_CSC,Clock Mux 0 Select Control Register"
bitfld.long 0x00 24.--28. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,10: CORE_PLL_PHI6_CLK,?,?,?,?,?,?,?,18: PERIPH_PLL_PHI0_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x304++0x03
line.long 0x00 "MUX_0_CSS,Clock Mux 0 Select Status Register"
bitfld.long 0x00 24.--28. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,10: CORE_PLL_PHI6_CLK,?,?,?,?,?,?,?,18: PERIPH_PLL_PHI0_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x340++0x03
line.long 0x00 "MUX_1_CSC,Clock Mux 1 Select Control Register"
bitfld.long 0x00 24.--29. "SELCTL,Clock source selection control" "?,?,2: clk_src_2,?,?,?,?,?,?,9: CORE_PLL_PHI5_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: PERIPH_PLL_PHI6_CLK,?,?,27: PERIPH_DFS2_CLK,?..."
bitfld.long 0x00 3. "FCG,Force clock gate" "0,1"
newline
bitfld.long 0x00 2. "CG,Clock gate" "0,1"
rgroup.long 0x344++0x03
line.long 0x00 "MUX_1_CSS,Clock Mux 1 Select Status Register"
bitfld.long 0x00 24.--29. "SELSTAT,Clock source selection status" "?,?,2: clk_src_2,?,?,?,?,?,?,9: CORE_PLL_PHI5_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: PERIPH_PLL_PHI6_CLK,?,?,27: PERIPH_DFS2_CLK,?..."
bitfld.long 0x00 17. "CS,Clock status" "0: Clock is gated to logic-0 at output of clock..,1: Clock mux is transparent"
newline
bitfld.long 0x00 16. "GRIP,Gating request is in progress" "0: Clock source gating or ungating has completed,1: Clock source gating or ungating is in progress"
group.long 0x348++0x03
line.long 0x00 "MUX_1_DC_0,Clock Mux 1 Divider 0 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
rgroup.long 0x37C++0x03
line.long 0x00 "MUX_1_DIV_UPD_STAT,Clock Mux 1 Divider Update Status Register"
bitfld.long 0x00 0. "DIV_STAT,Divider status for clock mux 1" "0: No divider configuration update is pending,1: Divider configuration update on at least one.."
group.long 0x380++0x03
line.long 0x00 "MUX_2_CSC,Clock Mux 2 Select Control Register"
bitfld.long 0x00 24.--29. "SELCTL,Clock source selection control" "?,?,2: clk_src_2,?,?,?,?,?,?,9: CORE_PLL_PHI5_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: PERIPH_PLL_PHI6_CLK,?,?,27: PERIPH_DFS2_CLK,?..."
bitfld.long 0x00 3. "FCG,Force clock gate" "0,1"
newline
bitfld.long 0x00 2. "CG,Clock gate" "0,1"
rgroup.long 0x384++0x03
line.long 0x00 "MUX_2_CSS,Clock Mux 2 Select Status Register"
bitfld.long 0x00 24.--29. "SELSTAT,Clock source selection status" "?,?,2: clk_src_2,?,?,?,?,?,?,9: CORE_PLL_PHI5_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: PERIPH_PLL_PHI6_CLK,?,?,27: PERIPH_DFS2_CLK,?..."
bitfld.long 0x00 17. "CS,Clock status" "0: Clock is gated to logic-0 at output of clock..,1: Clock mux is transparent"
newline
bitfld.long 0x00 16. "GRIP,Gating request is in progress" "0: Clock source gating or ungating has completed,1: Clock source gating or ungating is in progress"
group.long 0x388++0x03
line.long 0x00 "MUX_2_DC_0,Clock Mux 2 Divider 0 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
rgroup.long 0x3BC++0x03
line.long 0x00 "MUX_2_DIV_UPD_STAT,Clock Mux 2 Divider Update Status Register"
bitfld.long 0x00 0. "DIV_STAT,Divider status for clock mux 2" "0: No divider configuration update is pending,1: Divider configuration update on at least one.."
group.long 0x3C0++0x03
line.long 0x00 "MUX_3_CSC,Clock Mux 3 Select Control Register"
bitfld.long 0x00 24.--28. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,19: PERIPH_PLL_PHI1_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x3C4++0x03
line.long 0x00 "MUX_3_CSS,Clock Mux 3 Select Status Register"
bitfld.long 0x00 24.--28. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,19: PERIPH_PLL_PHI1_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x400++0x03
line.long 0x00 "MUX_4_CSC,Clock Mux 4 Select Control Register"
bitfld.long 0x00 24.--28. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,25: PERIPH_PLL_PHI7_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x404++0x03
line.long 0x00 "MUX_4_CSS,Clock Mux 4 Select Status Register"
bitfld.long 0x00 24.--28. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,25: PERIPH_PLL_PHI7_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x440++0x03
line.long 0x00 "MUX_5_CSC,Clock Mux 5 Select Control Register"
bitfld.long 0x00 24.--28. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: PERIPH_PLL_PHI9_CLK,?,?,?,?,?,?,?,?,?,26: PERIPH_DFS1_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x444++0x03
line.long 0x00 "MUX_5_CSS,Clock Mux 5 Select Status Register"
bitfld.long 0x00 24.--28. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,16: PERIPH_PLL_PHI9_CLK,?,?,?,?,?,?,?,?,?,26: PERIPH_DFS1_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x448++0x03
line.long 0x00 "MUX_5_DC_0,Clock Mux 5 Divider 0 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
rgroup.long 0x47C++0x03
line.long 0x00 "MUX_5_DIV_UPD_STAT,Clock Mux 5 Divider Update Status Register"
bitfld.long 0x00 0. "DIV_STAT,Divider status for clock mux 5" "0: No divider configuration update is pending,1: Divider configuration update on at least one.."
group.long 0x480++0x03
line.long 0x00 "MUX_6_CSC,Clock Mux 6 Select Control Register"
bitfld.long 0x00 24.--28. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,23: PERIPH_PLL_PHI5_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x484++0x03
line.long 0x00 "MUX_6_CSS,Clock Mux 6 Select Status Register"
bitfld.long 0x00 24.--28. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,23: PERIPH_PLL_PHI5_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x488++0x03
line.long 0x00 "MUX_6_DC_0,Clock Mux 6 Divider 0 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
group.long 0x48C++0x03
line.long 0x00 "MUX_6_DC_1,Clock Mux 6 Divider 1 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
group.long 0x490++0x03
line.long 0x00 "MUX_6_DC_2,Clock Mux 6 Divider 2 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
group.long 0x494++0x03
line.long 0x00 "MUX_6_DC_3,Clock Mux 6 Divider 3 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
group.long 0x498++0x03
line.long 0x00 "MUX_6_DC_4,Clock Mux 6 Divider 4 Control Register"
rbitfld.long 0x00 31. "DE,Divider enable" "0: DISABLED,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
rgroup.long 0x4BC++0x03
line.long 0x00 "MUX_6_DIV_UPD_STAT,Clock Mux 6 Divider Update Status Register"
bitfld.long 0x00 0. "DIV_STAT,Divider status for clock mux 6" "0: No divider configuration update is pending,1: Divider configuration update on at least one.."
group.long 0x4C0++0x03
line.long 0x00 "MUX_7_CSC,Clock Mux 7 Select Control Register"
bitfld.long 0x00 24.--28. "SELCTL,Clock source selection control" "0: clk_src_0,?,2: clk_src_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,20: PERIPH_PLL_PHI2_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x4C4++0x03
line.long 0x00 "MUX_7_CSS,Clock Mux 7 Select Status Register"
bitfld.long 0x00 24.--28. "SELSTAT,Clock source selection status" "0: clk_src_0,?,2: clk_src_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,20: PERIPH_PLL_PHI2_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x500++0x03
line.long 0x00 "MUX_8_CSC,Clock Mux 8 Select Control Register"
bitfld.long 0x00 24.--28. "SELCTL,Clock source selection control" "0: clk_src_0,?,2: clk_src_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,21: PERIPH_PLL_PHI3_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x504++0x03
line.long 0x00 "MUX_8_CSS,Clock Mux 8 Select Status Register"
bitfld.long 0x00 24.--28. "SELSTAT,Clock source selection status" "0: clk_src_0,?,2: clk_src_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,21: PERIPH_PLL_PHI3_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
tree.end
tree "MC_CGM_1"
base ad:0x440C8000
group.long 0x00++0x03
line.long 0x00 "PCFS_SDUR,PCFS Step Duration"
hexmask.long.word 0x00 0.--15. 1. "SDUR,Step duration"
group.long 0x28++0x03
line.long 0x00 "PCFS_DIVC4,PCFS Divider Change 4 Register"
hexmask.long.word 0x00 16.--31. 1. "INIT,Divider change initial value"
hexmask.long.byte 0x00 0.--7. 1. "RATE,Divider change rate"
group.long 0x2C++0x03
line.long 0x00 "PCFS_DIVE4,PCFS Divider End 4 Register"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVE,Divider end value"
group.long 0x30++0x03
line.long 0x00 "PCFS_DIVS4,PCFS Divider Start 4 Register"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVS,Divider start value"
group.long 0x34++0x03
line.long 0x00 "PCFS_DIVC5,PCFS Divider Change 5 Register"
hexmask.long.word 0x00 16.--31. 1. "INIT,Divider change initial value"
hexmask.long.byte 0x00 0.--7. 1. "RATE,Divider change rate"
group.long 0x38++0x03
line.long 0x00 "PCFS_DIVE5,PCFS Divider End 5 Register"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVE,Divider end value"
group.long 0x3C++0x03
line.long 0x00 "PCFS_DIVS5,PCFS Divider Start 5 Register"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVS,Divider start value"
group.long 0x40++0x03
line.long 0x00 "PCFS_DIVC6,PCFS Divider Change 6 Register"
hexmask.long.word 0x00 16.--31. 1. "INIT,Divider change initial value"
hexmask.long.byte 0x00 0.--7. 1. "RATE,Divider change rate"
group.long 0x44++0x03
line.long 0x00 "PCFS_DIVE6,PCFS Divider End 6 Register"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVE,Divider end value"
group.long 0x48++0x03
line.long 0x00 "PCFS_DIVS6,PCFS Divider Start 6 Register"
hexmask.long.tbyte 0x00 0.--19. 1. "DIVS,Divider start value"
group.long 0x300++0x03
line.long 0x00 "MUX_0_CSC,Clock Mux 0 Select Control Register"
bitfld.long 0x00 24.--26. "SELCTL,Clock source selection control" "0: clk_src_0,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
bitfld.long 0x00 1. "RAMPDOWN,PCFS ramp-down" "0,1"
newline
bitfld.long 0x00 0. "RAMPUP,PCFS ramp-up" "0,1"
rgroup.long 0x304++0x03
line.long 0x00 "MUX_0_CSS,Clock Mux 0 Select Status Register"
bitfld.long 0x00 24.--26. "SELSTAT,Clock source selection status" "0: clk_src_0,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
bitfld.long 0x00 1. "RAMPDOWN,PCFS ramp-down" "0: No ramp-down operation was requested,1: Ramp-down operation was requested"
newline
bitfld.long 0x00 0. "RAMPUP,PCFS ramp-up" "0: No ramp-up operation was requested,1: Ramp-up operation was requested"
group.long 0x340++0x03
line.long 0x00 "MUX_1_CSC,Clock Mux 1 Select Control Register"
bitfld.long 0x00 24.--26. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,5: CORE_PLL_PHI1_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
bitfld.long 0x00 1. "RAMPDOWN,PCFS ramp-down" "0,1"
newline
bitfld.long 0x00 0. "RAMPUP,PCFS ramp-up" "0,1"
rgroup.long 0x344++0x03
line.long 0x00 "MUX_1_CSS,Clock Mux 1 Select Status Register"
bitfld.long 0x00 24.--26. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,5: CORE_PLL_PHI1_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
bitfld.long 0x00 1. "RAMPDOWN,PCFS ramp-down" "0: No ramp-down operation was requested,1: Ramp-down operation was requested"
newline
bitfld.long 0x00 0. "RAMPUP,PCFS ramp-up" "0: No ramp-up operation was requested,1: Ramp-up operation was requested"
group.long 0x380++0x03
line.long 0x00 "MUX_2_CSC,Clock Mux 2 Select Control Register"
bitfld.long 0x00 24.--26. "SELCTL,Clock source selection control" "0: clk_src_0,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
bitfld.long 0x00 1. "RAMPDOWN,PCFS ramp-down" "0,1"
newline
bitfld.long 0x00 0. "RAMPUP,PCFS ramp-up" "0,1"
rgroup.long 0x384++0x03
line.long 0x00 "MUX_2_CSS,Clock Mux 2 Select Status Register"
bitfld.long 0x00 24.--26. "SELSTAT,Clock source selection status" "0: clk_src_0,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
bitfld.long 0x00 1. "RAMPDOWN,PCFS ramp-down" "0: No ramp-down operation was requested,1: Ramp-down operation was requested"
newline
bitfld.long 0x00 0. "RAMPUP,PCFS ramp-up" "0: No ramp-up operation was requested,1: Ramp-up operation was requested"
group.long 0x3C0++0x03
line.long 0x00 "MUX_3_CSC,Clock Mux 3 Select Control Register"
bitfld.long 0x00 24.--26. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,7: CORE_PLL_PHI3_CLK"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x3C4++0x03
line.long 0x00 "MUX_3_CSS,Clock Mux 3 Select Status Register"
bitfld.long 0x00 24.--26. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,7: CORE_PLL_PHI3_CLK"
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x400++0x03
line.long 0x00 "MUX_4_CSC,Clock Mux 4 Select Control Register"
bitfld.long 0x00 24.--27. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,8: PERIPH_PLL_PHI4_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x404++0x03
line.long 0x00 "MUX_4_CSS,Clock Mux 4 Select Status Register"
bitfld.long 0x00 24.--27. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,8: PERIPH_PLL_PHI4_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x408++0x03
line.long 0x00 "MUX_4_DC_0,Clock Mux 4 Divider 0 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
group.long 0x40C++0x03
line.long 0x00 "MUX_4_DC_1,Clock Mux 4 Divider 1 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
rgroup.long 0x43C++0x03
line.long 0x00 "MUX_4_DIV_UPD_STAT,Clock Mux 4 Divider Update Status Register"
bitfld.long 0x00 0. "DIV_STAT,Divider status for clock mux 4" "0: No divider configuration update is pending,1: Divider configuration update on at least one.."
group.long 0x440++0x03
line.long 0x00 "MUX_5_CSC,Clock Mux 5 Select Control Register"
bitfld.long 0x00 24.--28. "SELCTL,Clock source selection control" "0: clk_src_0,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
bitfld.long 0x00 1. "RAMPDOWN,PCFS ramp-down" "0,1"
newline
bitfld.long 0x00 0. "RAMPUP,PCFS ramp-up" "0,1"
rgroup.long 0x444++0x03
line.long 0x00 "MUX_5_CSS,Clock Mux 5 Select Status Register"
bitfld.long 0x00 24.--28. "SELSTAT,Clock source selection status" "0: clk_src_0,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
bitfld.long 0x00 1. "RAMPDOWN,PCFS ramp-down" "0: No ramp-down operation was requested,1: Ramp-down operation was requested"
newline
bitfld.long 0x00 0. "RAMPUP,PCFS ramp-up" "0: No ramp-up operation was requested,1: Ramp-up operation was requested"
group.long 0x480++0x03
line.long 0x00 "MUX_6_CSC,Clock Mux 6 Select Control Register"
bitfld.long 0x00 24.--27. "SELCTL,Clock source selection control" "0: clk_src_0,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
bitfld.long 0x00 1. "RAMPDOWN,PCFS ramp-down" "0,1"
newline
bitfld.long 0x00 0. "RAMPUP,PCFS ramp-up" "0,1"
rgroup.long 0x484++0x03
line.long 0x00 "MUX_6_CSS,Clock Mux 6 Select Status Register"
bitfld.long 0x00 24.--27. "SELSTAT,Clock source selection status" "0: clk_src_0,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
bitfld.long 0x00 1. "RAMPDOWN,PCFS ramp-down" "0: No ramp-down operation was requested,1: Ramp-down operation was requested"
newline
bitfld.long 0x00 0. "RAMPUP,PCFS ramp-up" "0: No ramp-up operation was requested,1: Ramp-up operation was requested"
group.long 0x488++0x03
line.long 0x00 "MUX_6_DC_0,Clock Mux 6 Divider 0 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
rgroup.long 0x4BC++0x03
line.long 0x00 "MUX_6_DIV_UPD_STAT,Clock Mux 6 Divider Update Status Register"
bitfld.long 0x00 0. "DIV_STAT,Divider status for clock mux 6" "0: No divider configuration update is pending,1: Divider configuration update on at least one.."
tree.end
tree "MC_CGM_2"
base ad:0x44084000
group.long 0x340++0x03
line.long 0x00 "MUX_1_CSC,Clock Mux 1 Select Control Register"
bitfld.long 0x00 24.--29. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,22: PERIPH_PLL_PHI4_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,55: GMAC_1_EXT_TS_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x344++0x03
line.long 0x00 "MUX_1_CSS,Clock Mux 1 Select Status Register"
bitfld.long 0x00 24.--29. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,22: PERIPH_PLL_PHI4_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,55: GMAC_1_EXT_TS_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x348++0x03
line.long 0x00 "MUX_1_DC_0,Clock Mux 1 Divider 0 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
rgroup.long 0x37C++0x03
line.long 0x00 "MUX_1_DIV_UPD_STAT,Clock Mux 1 Divider Update Status Register"
bitfld.long 0x00 0. "DIV_STAT,Divider status for clock mux 1" "0: No divider configuration update is pending,1: Divider configuration update on at least one.."
group.long 0x380++0x03
line.long 0x00 "MUX_2_CSC,Clock Mux 2 Select Control Register"
bitfld.long 0x00 24.--29. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,23: PERIPH_PLL_PHI5_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,54: GMAC_1_REF_DIV_CLK,?,56: GMAC_1_EXT_TX_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x384++0x03
line.long 0x00 "MUX_2_CSS,Clock Mux 2 Select Status Register"
bitfld.long 0x00 24.--29. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,23: PERIPH_PLL_PHI5_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,54: GMAC_1_REF_DIV_CLK,?,56: GMAC_1_EXT_TX_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x388++0x03
line.long 0x00 "MUX_2_DC_0,Clock Mux 2 Divider 0 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
rgroup.long 0x3BC++0x03
line.long 0x00 "MUX_2_DIV_UPD_STAT,Clock Mux 2 Divider Update Status Register"
bitfld.long 0x00 0. "DIV_STAT,Divider status for clock mux 2" "0: No divider configuration update is pending,1: Divider configuration update on at least one.."
group.long 0x3C0++0x03
line.long 0x00 "MUX_3_CSC,Clock Mux 3 Select Control Register"
bitfld.long 0x00 24.--29. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,58: GMAC_1_EXT_REF_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x3C4++0x03
line.long 0x00 "MUX_3_CSS,Clock Mux 3 Select Status Register"
bitfld.long 0x00 24.--29. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,58: GMAC_1_EXT_REF_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x3C8++0x03
line.long 0x00 "MUX_3_DC_0,Clock Mux 3 Divider 0 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
rgroup.long 0x3FC++0x03
line.long 0x00 "MUX_3_DIV_UPD_STAT,Clock Mux 3 Divider Update Status Register"
bitfld.long 0x00 0. "DIV_STAT,Divider status for clock mux 3" "0: No divider configuration update is pending,1: Divider configuration update on at least one.."
group.long 0x400++0x03
line.long 0x00 "MUX_4_CSC,Clock Mux 4 Select Control Register"
bitfld.long 0x00 24.--29. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,54: GMAC_1_REF_DIV_CLK,?,?,57: GMAC_1_EXT_RX_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x404++0x03
line.long 0x00 "MUX_4_CSS,Clock Mux 4 Select Status Register"
bitfld.long 0x00 24.--29. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,54: GMAC_1_REF_DIV_CLK,?,?,57: GMAC_1_EXT_RX_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
tree.end
tree "MC_CGM_3"
base ad:0x400FC000
group.long 0x300++0x03
line.long 0x00 "MUX_0_CSC,Clock Mux 0 Select Control Register"
bitfld.long 0x00 24.--29. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,19: PERIPH_PLL_PHI1_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,34: FTM_0_EXT_REF_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x304++0x03
line.long 0x00 "MUX_0_CSS,Clock Mux 0 Select Status Register"
bitfld.long 0x00 24.--29. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,19: PERIPH_PLL_PHI1_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,34: FTM_0_EXT_REF_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x308++0x03
line.long 0x00 "MUX_0_DC_0,Clock Mux 0 Divider 0 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
rgroup.long 0x33C++0x03
line.long 0x00 "MUX_0_DIV_UPD_STAT,Clock Mux 0 Divider Update Status Register"
bitfld.long 0x00 0. "DIV_STAT,Divider status for clock mux 0" "0: No divider configuration update is pending,1: Divider configuration update on at least one.."
group.long 0x340++0x03
line.long 0x00 "MUX_1_CSC,Clock Mux 1 Select Control Register"
bitfld.long 0x00 24.--29. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,22: PERIPH_PLL_PHI4_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,44: GMAC_0_EXT_TS_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x344++0x03
line.long 0x00 "MUX_1_CSS,Clock Mux 1 Select Status Register"
bitfld.long 0x00 24.--29. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,22: PERIPH_PLL_PHI4_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,44: GMAC_0_EXT_TS_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x348++0x03
line.long 0x00 "MUX_1_DC_0,Clock Mux 1 Divider 0 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
rgroup.long 0x37C++0x03
line.long 0x00 "MUX_1_DIV_UPD_STAT,Clock Mux 1 Divider Update Status Register"
bitfld.long 0x00 0. "DIV_STAT,Divider status for clock mux 1" "0: No divider configuration update is pending,1: Divider configuration update on at least one.."
group.long 0x380++0x03
line.long 0x00 "MUX_2_CSC,Clock Mux 2 Select Control Register"
bitfld.long 0x00 24.--29. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,37: GMAC_0_EXT_TX_CLK,?,?,?,?,?,?,?,45: GMAC_0_REF_DIV_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x384++0x03
line.long 0x00 "MUX_2_CSS,Clock Mux 2 Select Status Register"
bitfld.long 0x00 24.--29. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,37: GMAC_0_EXT_TX_CLK,?,?,?,?,?,?,?,45: GMAC_0_REF_DIV_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x3C0++0x03
line.long 0x00 "MUX_3_CSC,Clock Mux 3 Select Control Register"
bitfld.long 0x00 24.--29. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: PERIPH_PLL_PHI6_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,39: GMAC_0_EXT_REF_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x3C4++0x03
line.long 0x00 "MUX_3_CSS,Clock Mux 3 Select Status Register"
bitfld.long 0x00 24.--29. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,24: PERIPH_PLL_PHI6_CLK,?,?,?,?,?,?,?,?,?,?,?,?,?,?,39: GMAC_0_EXT_REF_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
group.long 0x3C8++0x03
line.long 0x00 "MUX_3_DC_0,Clock Mux 3 Divider 0 Control Register"
bitfld.long 0x00 31. "DE,Divider enable" "0: Divider is disabled,1: Divider is enabled"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division value"
rgroup.long 0x3FC++0x03
line.long 0x00 "MUX_3_DIV_UPD_STAT,Clock Mux 3 Divider Update Status Register"
bitfld.long 0x00 0. "DIV_STAT,Divider status for clock mux 3" "0: No divider configuration update is pending,1: Divider configuration update on at least one.."
group.long 0x400++0x03
line.long 0x00 "MUX_4_CSC,Clock Mux 4 Select Control Register"
bitfld.long 0x00 24.--29. "SELCTL,Clock source selection control" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,38: GMAC_0_EXT_RX_CLK,?,?,?,?,?,?,45: GMAC_0_REF_DIV_CLK,?..."
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0,1"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0,1"
rgroup.long 0x404++0x03
line.long 0x00 "MUX_4_CSS,Clock Mux 4 Select Status Register"
bitfld.long 0x00 24.--29. "SELSTAT,Clock source selection status" "0: clk_src_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,38: GMAC_0_EXT_RX_CLK,?,?,?,?,?,?,45: GMAC_0_REF_DIV_CLK,?..."
bitfld.long 0x00 17.--19. "SWTRG,Switch trigger cause" "?,1: Switch after request succeeded,2: Switch after the request failed because of an..,3: Switch after the request failed because of an..,4: Switch to FIRC_CLK because of a safe clock..,5: Switch to FIRC_CLK because of a safe clock..,?..."
newline
bitfld.long 0x00 16. "SWIP,Switch in progress" "0: Clock source switching is complete,1: Clock source switching is in progress"
bitfld.long 0x00 3. "SAFE_SW,Safe clock request" "0: No safe clock switch operation was requested,1: Safe clock switch operation was requested"
newline
bitfld.long 0x00 2. "CLK_SW,Clock switch" "0: No clock switch operation was requested,1: Clock switch operation was requested"
tree.end
tree.end
tree "MC_ME"
base ad:0x400D0000
group.long 0x00++0x03
line.long 0x00 "CTL_KEY,Control Key Register"
hexmask.long.word 0x00 0.--15. 1. "KEY,Control key"
group.long 0x04++0x03
line.long 0x00 "MODE_CONF,Mode Configuration Register"
bitfld.long 0x00 1. "FUNC_RST,Functional reset request" "0,1"
bitfld.long 0x00 0. "DEST_RST,Destructive reset request" "0,1"
group.long 0x08++0x03
line.long 0x00 "MODE_UPD,Mode Update Register"
bitfld.long 0x00 0. "MODE_UPD,Mode update" "0,1"
group.long 0x100++0x03
line.long 0x00 "PRTN0_PCONF,Partition 0 Process Configuration Register"
bitfld.long 0x00 0. "PCE,Partition clock enable" "0: Disable the clock to IPs,1: Enable the clock to IPs"
group.long 0x104++0x03
line.long 0x00 "PRTN0_PUPD,Partition 0 Process Update Register"
bitfld.long 0x00 0. "PCUD,Partition clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process"
rgroup.long 0x108++0x03
line.long 0x00 "PRTN0_STAT,Partition 0 Status Register"
bitfld.long 0x00 0. "PCS,Partition clock status" "0: Clock is inactive,1: Clock is active"
group.long 0x140++0x03
line.long 0x00 "PRTN0_CORE0_PCONF,Partition 0 Core 0 Process Configuration Register"
bitfld.long 0x00 0. "CCE,Core 0 clock enable" "0: Disable the core clock,1: Enable the core clock"
group.long 0x144++0x03
line.long 0x00 "PRTN0_CORE0_PUPD,Partition 0 Core 0 Process Update Register"
bitfld.long 0x00 0. "CCUPD,Core 0 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process"
rgroup.long 0x148++0x03
line.long 0x00 "PRTN0_CORE0_STAT,Partition 0 Core 0 Status Register"
bitfld.long 0x00 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed"
bitfld.long 0x00 0. "CCS,Core 0 clock process status" "0: Clock is inactive,1: Clock is active"
group.long 0x14C++0x03
line.long 0x00 "PRTN0_CORE0_ADDR,Partition 0 Core 0 Address Register"
hexmask.long 0x00 2.--31. 1. "ADDR,Address"
group.long 0x160++0x03
line.long 0x00 "PRTN0_CORE1_PCONF,Partition 0 Core 1 Process Configuration Register"
bitfld.long 0x00 0. "CCE,Core 1 clock enable" "0: Disable the core clock,1: Enable the core clock"
group.long 0x164++0x03
line.long 0x00 "PRTN0_CORE1_PUPD,Partition 0 Core 1 Process Update Register"
bitfld.long 0x00 0. "CCUPD,Core 1 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process"
rgroup.long 0x168++0x03
line.long 0x00 "PRTN0_CORE1_STAT,Partition 0 Core 1 Status Register"
bitfld.long 0x00 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed"
bitfld.long 0x00 0. "CCS,Core 1 clock process status" "0: Clock is inactive,1: Clock is active"
group.long 0x16C++0x03
line.long 0x00 "PRTN0_CORE1_ADDR,Partition 0 Core 1 Address Register"
hexmask.long 0x00 2.--31. 1. "ADDR,Address"
group.long 0x300++0x03
line.long 0x00 "PRTN1_PCONF,Partition 1 Process Configuration Register"
bitfld.long 0x00 2. "OSSE,Output safe stating enable" "0: Disable output safe stating,1: Enable output safe stating"
bitfld.long 0x00 0. "PCE,Partition clock enable" "0: Disable the clock to IPs,1: Enable the clock to IPs"
group.long 0x304++0x03
line.long 0x00 "PRTN1_PUPD,Partition 1 Process Update Register"
bitfld.long 0x00 2. "OSSUD,Output safe stating update" "0: Do not trigger the hardware process,1: Trigger the hardware process"
bitfld.long 0x00 0. "PCUD,Partition clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process"
rgroup.long 0x308++0x03
line.long 0x00 "PRTN1_STAT,Partition 1 Status Register"
bitfld.long 0x00 2. "OSSS,Output safe stating status" "0: Output safe stating is inactive,1: Output safe stating is active"
bitfld.long 0x00 0. "PCS,Partition clock status" "0: Clock is inactive,1: Clock is active"
rgroup.long 0x310++0x03
line.long 0x00 "PRTN1_COFB0_STAT,Partition 1 COFB Set 0 Clock Status Register"
bitfld.long 0x00 2. "BLOCK2,IP block status" "0: Clock is not running,1: Clock is running"
bitfld.long 0x00 1. "BLOCK1,IP block status" "0: Clock is not running,1: Clock is running"
bitfld.long 0x00 0. "BLOCK0,IP block status" "0: Clock is not running,1: Clock is running"
group.long 0x330++0x03
line.long 0x00 "PRTN1_COFB0_CLKEN,Partition 1 COFB Set 0 Clock Enable Register"
bitfld.long 0x00 2. "REQ2,Clock enable" "0: Clock is turned off,1: Clock is turned on"
bitfld.long 0x00 1. "REQ1,Clock enable" "0: Clock is turned off,1: Clock is turned on"
bitfld.long 0x00 0. "REQ0,Clock enable" "0: Clock is turned off,1: Clock is turned on"
group.long 0x340++0x03
line.long 0x00 "PRTN1_CORE0_PCONF,Partition 1 Core 0 Process Configuration Register"
bitfld.long 0x00 0. "CCE,Core 0 clock enable" "0: Disable the core clock,1: Enable the core clock"
group.long 0x344++0x03
line.long 0x00 "PRTN1_CORE0_PUPD,Partition 1 Core 0 Process Update Register"
bitfld.long 0x00 0. "CCUPD,Core 0 clock update" "0: Do not trigger the hardware process,1: Trigger the hardware process"
rgroup.long 0x348++0x03
line.long 0x00 "PRTN1_CORE0_STAT,Partition 1 Core 0 Status Register"
bitfld.long 0x00 31. "WFI,Wait for interrupt status" "0: No WFI executed,1: WFI executed"
bitfld.long 0x00 0. "CCS,Core 0 clock process status" "0: Clock is inactive,1: Clock is active"
group.long 0x34C++0x03
line.long 0x00 "PRTN1_CORE0_ADDR,Partition 1 Core 0 Address Register"
hexmask.long 0x00 2.--31. 1. "ADDR,Address"
tree.end
tree "MC_RGM"
base ad:0x400CC000
group.long 0x00++0x03
line.long 0x00 "DES,Destructive Event Status Register"
eventfld.long 0x00 31. "DEBUG_DEST,Flag for 'Destructive' Reset DEBUG_DEST" "0: 'Destructive' reset event DEBUG_DEST has not..,1: 'Destructive' reset event DEBUG_DEST has.."
newline
eventfld.long 0x00 30. "SW_DEST,Flag for 'Destructive' Reset SW_DEST" "0: 'Destructive' reset event SW_DEST has not..,1: 'Destructive' reset event SW_DEST has occurred"
newline
eventfld.long 0x00 22. "F_DR_22,Flag for 'Destructive' Reset F_DR_22" "0: 'Destructive' reset event F_DR_22 has not..,1: 'Destructive' reset event F_DR_22 has occurred"
newline
eventfld.long 0x00 20. "ACCEL_XBAR_DIV8_CLK_FAIL,Flag for 'Destructive' Reset ACCEL_XBAR_DIV8_CLK_FAIL" "0: 'Destructive' reset event..,1: 'Destructive' reset event.."
newline
eventfld.long 0x00 19. "SYS_DIV8_CLK_FAIL,Flag for 'Destructive' Reset SYS_DIV8_CLK_FAIL" "0: 'Destructive' reset event SYS_DIV8_CLK_FAIL..,1: 'Destructive' reset event SYS_DIV8_CLK_FAIL.."
newline
eventfld.long 0x00 18. "HSE_Reset_Source3,Flag for 'Destructive' Reset HSE_Reset_Source3" "0: 'Destructive' reset event HSE_Reset_Source3..,1: 'Destructive' reset event HSE_Reset_Source3.."
newline
eventfld.long 0x00 17. "HSE_Reset_Source2,Flag for 'Destructive' Reset HSE_Reset_Source2" "0: 'Destructive' reset event HSE_Reset_Source2..,1: 'Destructive' reset event HSE_Reset_Source2.."
newline
eventfld.long 0x00 16. "HSE_Reset_Source1,Flag for 'Destructive' Reset HSE_Reset_Source1" "0: 'Destructive' reset event HSE_Reset_Source1..,1: 'Destructive' reset event HSE_Reset_Source1.."
newline
eventfld.long 0x00 13. "STCU_CLK_FAIL,Flag for 'Destructive' Reset STCU_CLK_FAIL" "0: 'Destructive' reset event STCU_CLK_FAIL has..,1: 'Destructive' reset event STCU_CLK_FAIL has.."
newline
eventfld.long 0x00 11. "MC_RGM_FRTO,Flag for 'Destructive' Reset MC_RGM_FRTO" "0: 'Destructive' reset event MC_RGM_FRTO has not..,1: 'Destructive' reset event MC_RGM_FRTO has.."
newline
eventfld.long 0x00 10. "PERIPH_LOL,Flag for 'Destructive' Reset PERIPH_LOL" "0: 'Destructive' reset event PERIPH_LOL has not..,1: 'Destructive' reset event PERIPH_LOL has.."
newline
eventfld.long 0x00 9. "CORE_LOL,Flag for 'Destructive' Reset CORE_LOL" "0: 'Destructive' reset event CORE_LOL has not..,1: 'Destructive' reset event CORE_LOL has occurred"
newline
eventfld.long 0x00 8. "FXOSC_FAIL,Flag for 'Destructive' Reset FXOSC_FAIL" "0: 'Destructive' reset event FXOSC_FAIL has not..,1: 'Destructive' reset event FXOSC_FAIL has.."
newline
eventfld.long 0x00 6. "MC_RGM_FRE,Flag for 'Destructive' Reset MC_RGM_FRE" "0: 'Destructive' reset event MC_RGM_FRE has not..,1: 'Destructive' reset event MC_RGM_FRE has.."
newline
eventfld.long 0x00 4. "STCU_URF,Flag for 'Destructive' Reset STCU_URF" "0: 'Destructive' reset event STCU_URF has not..,1: 'Destructive' reset event STCU_URF has occurred"
newline
eventfld.long 0x00 3. "FCCU_FTR,Flag for 'Destructive' Reset FCCU_FTR" "0: 'Destructive' reset event FCCU_FTR has not..,1: 'Destructive' reset event FCCU_FTR has occurred"
newline
eventfld.long 0x00 1. "NC_SPD_RST,Flag for 'Destructive' Reset NC_SPD_RST" "0: 'Destructive' reset event NC_SPD_RST has not..,1: 'Destructive' reset event NC_SPD_RST has.."
newline
eventfld.long 0x00 0. "F_POR,Flag for power-on reset" "0: No power-on event has occurred since the last..,1: A power-on event has occurred"
group.long 0x08++0x03
line.long 0x00 "FES,Functional /External Reset Status Register"
eventfld.long 0x00 31. "DEBUG_FUNC,Flag for 'Functional' Reset DEBUG_FUNC" "0: 'Functional' reset event DEBUG_FUNC has not..,1: 'Functional' reset event DEBUG_FUNC has.."
newline
eventfld.long 0x00 30. "SW_FUNC,Flag for 'Functional' Reset SW_FUNC" "0: 'Functional' reset event SW_FUNC has not..,1: 'Functional' reset event SW_FUNC has occurred"
newline
eventfld.long 0x00 21. "HSE_Reset_Source7,Flag for 'Functional' Reset HSE_Reset_Source7" "0: 'Functional' reset event HSE_Reset_Source7..,1: 'Functional' reset event HSE_Reset_Source7.."
newline
eventfld.long 0x00 20. "HSE_Reset_Source6,Flag for 'Functional' Reset HSE_Reset_Source6" "0: 'Functional' reset event HSE_Reset_Source6..,1: 'Functional' reset event HSE_Reset_Source6.."
newline
eventfld.long 0x00 19. "HSE_Reset_Source5,Flag for 'Functional' Reset HSE_Reset_Source5" "0: 'Functional' reset event HSE_Reset_Source5..,1: 'Functional' reset event HSE_Reset_Source5.."
newline
eventfld.long 0x00 18. "HSE_Reset_Source4,Flag for 'Functional' Reset HSE_Reset_Source4" "0: 'Functional' reset event HSE_Reset_Source4..,1: 'Functional' reset event HSE_Reset_Source4.."
newline
eventfld.long 0x00 6. "SWT0_RST,Flag for 'Functional' Reset SWT0_RST" "0: 'Functional' reset event SWT0_RST has not..,1: 'Functional' reset event SWT0_RST has occurred"
newline
eventfld.long 0x00 4. "ST_DONE,Flag for 'Functional' Reset ST_DONE" "0: 'Functional' reset event ST_DONE has not..,1: 'Functional' reset event ST_DONE has occurred"
newline
eventfld.long 0x00 3. "FCCU_RST,Flag for 'Functional' Reset FCCU_RST" "0: 'Functional' reset event FCCU_RST has not..,1: 'Functional' reset event FCCU_RST has occurred"
newline
eventfld.long 0x00 0. "F_EXR,Flag for External Reset" "0: No external reset event has occurred since..,1: An external reset event has occurred"
group.long 0x0C++0x03
line.long 0x00 "FERD,Functional Event Reset Disable Register"
bitfld.long 0x00 31. "D_DEBUG_FUNC,DEBUG_FUNC Disable Control" "0: Functional reset event DEBUG_FUNC triggers a..,1: Functional reset event DEBUG_FUNC generates.."
newline
bitfld.long 0x00 0. "D_EXR,External Reset event demote to interrupt" "0: 'External' reset event triggers a reset..,1: 'External' reset event generates an interrupt.."
rgroup.long 0x10++0x03
line.long 0x00 "FBRE,Functional Bidirectional Reset Enable Register"
bitfld.long 0x00 31. "BE_DEBUG_FUNC,Bidirectional Reset Enables for 'Functional' Reset DEBUG_FUNC" "0: External reset pin is asserted on a..,1: External reset pin is not asserted on a.."
newline
bitfld.long 0x00 30. "BE_SW_FUNC,Bidirectional Reset Enables for 'Functional' Reset SW_FUNC" "0: External reset pin is asserted on a..,1: External reset pin is not asserted on a.."
newline
bitfld.long 0x00 21. "BE_HSE_Reset_Source7,Bidirectional Reset Enables for 'Functional' Reset HSE_Reset_Source7" "0: External reset pin is asserted on a..,1: External reset pin is not asserted on a.."
newline
bitfld.long 0x00 20. "BE_HSE_Reset_Source6,Bidirectional Reset Enables for 'Functional' Reset HSE_Reset_Source6" "0: External reset pin is asserted on a..,1: External reset pin is not asserted on a.."
newline
bitfld.long 0x00 19. "BE_HSE_Reset_Source5,Bidirectional Reset Enables for 'Functional' Reset HSE_Reset_Source5" "0: External reset pin is asserted on a..,1: External reset pin is not asserted on a.."
newline
bitfld.long 0x00 18. "BE_HSE_Reset_Source4,Bidirectional Reset Enables for 'Functional' Reset HSE_Reset_Source4" "0: External reset pin is asserted on a..,1: External reset pin is not asserted on a.."
newline
bitfld.long 0x00 6. "BE_SWT0_RST,Bidirectional Reset Enables for 'Functional' Reset SWT0_RST" "0: External reset pin is asserted on a..,1: External reset pin is not asserted on a.."
newline
bitfld.long 0x00 4. "BE_ST_DONE,Bidirectional Reset Enables for 'Functional' Reset ST_DONE" "0: External reset pin is asserted on a..,1: External reset pin is not asserted on a.."
newline
bitfld.long 0x00 3. "BE_FCCU_RST,Bidirectional Reset Enables for 'Functional' Reset FCCU_RST" "0: External reset pin is asserted on a..,1: External reset pin is not asserted on a.."
newline
bitfld.long 0x00 0. "BE_EXR,Bidirectional Reset Enable for External Reset" "0: External reset pin is asserted on an external..,1: External reset pin is not asserted on an.."
group.long 0x14++0x03
line.long 0x00 "FREC,Functional Reset Escalation Counter Register"
eventfld.long 0x00 0.--3. "FREC,Functional' Reset Escalation Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x03
line.long 0x00 "FRET,Functional Reset Escalation Threshold Register"
bitfld.long 0x00 0.--3. "FRET,'Functional' Reset Escalation Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x03
line.long 0x00 "DRET,Destructive Reset Escalation Threshold Register"
bitfld.long 0x00 0.--3. "DRET,'Destructive' Reset Escalation Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "ERCTRL,External Reset Control Register"
bitfld.long 0x00 0. "ERASSERT,ERASSERT" "0: NO_CHANGE,1: External reset is asserted"
group.long 0x28++0x03
line.long 0x00 "FRENTC,Functional Reset Entry Timeout Control Register"
hexmask.long 0x00 1.--31. 1. "FRET_TIMEOUT,Functional Reset Entry Timer Value"
newline
bitfld.long 0x00 0. "FRET_EN,Functional Reset Entry Timer Enable/Disable" "0: Functional reset entry timer is disabled,1: Functional reset entry timer is enabled"
group.long 0x40++0x03
line.long 0x00 "PRST0_0,Peripheral Reset"
bitfld.long 0x00 31. "PERIPH_31_RST,Reset Control value for peripheral PERIPH_31_RST" "0: No forced reset on PERIPH_31_RST,1: Forced Reset on PERIPH_31_RST"
newline
bitfld.long 0x00 30. "PERIPH_30_RST,Reset Control value for peripheral PERIPH_30_RST" "0: No forced reset on PERIPH_30_RST,1: Forced Reset on PERIPH_30_RST"
newline
bitfld.long 0x00 29. "PERIPH_29_RST,Reset Control value for peripheral PERIPH_29_RST" "0: No forced reset on PERIPH_29_RST,1: Forced Reset on PERIPH_29_RST"
newline
bitfld.long 0x00 28. "PERIPH_28_RST,Reset Control value for peripheral PERIPH_28_RST" "0: No forced reset on PERIPH_28_RST,1: Forced Reset on PERIPH_28_RST"
newline
bitfld.long 0x00 27. "PERIPH_27_RST,Reset Control value for peripheral PERIPH_27_RST" "0: No forced reset on PERIPH_27_RST,1: Forced Reset on PERIPH_27_RST"
newline
bitfld.long 0x00 26. "PERIPH_26_RST,Reset Control value for peripheral PERIPH_26_RST" "0: No forced reset on PERIPH_26_RST,1: Forced Reset on PERIPH_26_RST"
newline
bitfld.long 0x00 25. "PERIPH_25_RST,Reset Control value for peripheral PERIPH_25_RST" "0: No forced reset on PERIPH_25_RST,1: Forced Reset on PERIPH_25_RST"
newline
bitfld.long 0x00 24. "PERIPH_24_RST,Reset Control value for peripheral PERIPH_24_RST" "0: No forced reset on PERIPH_24_RST,1: Forced Reset on PERIPH_24_RST"
newline
bitfld.long 0x00 23. "PERIPH_23_RST,Reset Control value for peripheral PERIPH_23_RST" "0: No forced reset on PERIPH_23_RST,1: Forced Reset on PERIPH_23_RST"
newline
bitfld.long 0x00 22. "PERIPH_22_RST,Reset Control value for peripheral PERIPH_22_RST" "0: No forced reset on PERIPH_22_RST,1: Forced Reset on PERIPH_22_RST"
newline
bitfld.long 0x00 21. "PERIPH_21_RST,Reset Control value for peripheral PERIPH_21_RST" "0: No forced reset on PERIPH_21_RST,1: Forced Reset on PERIPH_21_RST"
newline
bitfld.long 0x00 20. "PERIPH_20_RST,Reset Control value for peripheral PERIPH_20_RST" "0: No forced reset on PERIPH_20_RST,1: Forced Reset on PERIPH_20_RST"
newline
bitfld.long 0x00 19. "PERIPH_19_RST,Reset Control value for peripheral PERIPH_19_RST" "0: No forced reset on PERIPH_19_RST,1: Forced Reset on PERIPH_19_RST"
newline
bitfld.long 0x00 18. "PERIPH_18_RST,Reset Control value for peripheral PERIPH_18_RST" "0: No forced reset on PERIPH_18_RST,1: Forced Reset on PERIPH_18_RST"
newline
bitfld.long 0x00 17. "PERIPH_17_RST,Reset Control value for peripheral PERIPH_17_RST" "0: No forced reset on PERIPH_17_RST,1: Forced Reset on PERIPH_17_RST"
newline
bitfld.long 0x00 16. "PERIPH_16_RST,Reset Control value for peripheral PERIPH_16_RST" "0: No forced reset on PERIPH_16_RST,1: Forced Reset on PERIPH_16_RST"
newline
bitfld.long 0x00 15. "PERIPH_15_RST,Reset Control value for peripheral PERIPH_15_RST" "0: No forced reset on PERIPH_15_RST,1: Forced Reset on PERIPH_15_RST"
newline
bitfld.long 0x00 14. "PERIPH_14_RST,Reset Control value for peripheral PERIPH_14_RST" "0: No forced reset on PERIPH_14_RST,1: Forced Reset on PERIPH_14_RST"
newline
bitfld.long 0x00 13. "PERIPH_13_RST,Reset Control value for peripheral PERIPH_13_RST" "0: No forced reset on PERIPH_13_RST,1: Forced Reset on PERIPH_13_RST"
newline
bitfld.long 0x00 12. "PERIPH_12_RST,Reset Control value for peripheral PERIPH_12_RST" "0: No forced reset on PERIPH_12_RST,1: Forced Reset on PERIPH_12_RST"
newline
bitfld.long 0x00 11. "PERIPH_11_RST,Reset Control value for peripheral PERIPH_11_RST" "0: No forced reset on PERIPH_11_RST,1: Forced Reset on PERIPH_11_RST"
newline
bitfld.long 0x00 10. "PERIPH_10_RST,Reset Control value for peripheral PERIPH_10_RST" "0: No forced reset on PERIPH_10_RST,1: Forced Reset on PERIPH_10_RST"
newline
bitfld.long 0x00 9. "PERIPH_9_RST,Reset Control value for peripheral PERIPH_9_RST" "0: No forced reset on PERIPH_9_RST,1: Forced Reset on PERIPH_9_RST"
newline
bitfld.long 0x00 8. "PERIPH_8_RST,Reset Control value for peripheral PERIPH_8_RST" "0: No forced reset on PERIPH_8_RST,1: Forced Reset on PERIPH_8_RST"
newline
bitfld.long 0x00 7. "PERIPH_7_RST,Reset Control value for peripheral PERIPH_7_RST" "0: No forced reset on PERIPH_7_RST,1: Forced Reset on PERIPH_7_RST"
newline
bitfld.long 0x00 6. "PERIPH_6_RST,Reset Control value for peripheral PERIPH_6_RST" "0: No forced reset on PERIPH_6_RST,1: Forced Reset on PERIPH_6_RST"
newline
bitfld.long 0x00 5. "PERIPH_5_RST,Reset Control value for peripheral PERIPH_5_RST" "0: No forced reset on PERIPH_5_RST,1: Forced Reset on PERIPH_5_RST"
newline
bitfld.long 0x00 4. "PERIPH_4_RST,Reset Control value for peripheral PERIPH_4_RST" "0: No forced reset on PERIPH_4_RST,1: Forced Reset on PERIPH_4_RST"
newline
bitfld.long 0x00 3. "PERIPH_3_RST,Reset Control value for peripheral PERIPH_3_RST" "0: No forced reset on PERIPH_3_RST,1: Forced Reset on PERIPH_3_RST"
newline
bitfld.long 0x00 2. "PERIPH_2_RST,Reset Control value for peripheral PERIPH_2_RST" "0: No forced reset on PERIPH_2_RST,1: Forced Reset on PERIPH_2_RST"
newline
bitfld.long 0x00 1. "PERIPH_1_RST,Reset Control value for peripheral CM7_Cluster_1_RST" "0: No forced reset on CM7_Cluster_1_RST,1: Forced Reset on CM7_Cluster_1_RST"
newline
bitfld.long 0x00 0. "PERIPH_0_RST,Reset Control value for peripheral CM7_Cluster_0_RST" "0: No forced reset on CM7_Cluster_0_RST,1: Forced Reset on CM7_Cluster_0_RST"
group.long 0x44++0x03
line.long 0x00 "PRST0_1,Peripheral Reset"
bitfld.long 0x00 31. "PERIPH_63_RST,Reset Control value for peripheral PERIPH_63_RST" "0: No forced reset on PERIPH_63_RST,1: Forced Reset on PERIPH_63_RST"
newline
bitfld.long 0x00 30. "PERIPH_62_RST,Reset Control value for peripheral PERIPH_62_RST" "0: No forced reset on PERIPH_62_RST,1: Forced Reset on PERIPH_62_RST"
newline
bitfld.long 0x00 29. "PERIPH_61_RST,Reset Control value for peripheral PERIPH_61_RST" "0: No forced reset on PERIPH_61_RST,1: Forced Reset on PERIPH_61_RST"
newline
bitfld.long 0x00 28. "PERIPH_60_RST,Reset Control value for peripheral PERIPH_60_RST" "0: No forced reset on PERIPH_60_RST,1: Forced Reset on PERIPH_60_RST"
newline
bitfld.long 0x00 27. "PERIPH_59_RST,Reset Control value for peripheral PERIPH_59_RST" "0: No forced reset on PERIPH_59_RST,1: Forced Reset on PERIPH_59_RST"
newline
bitfld.long 0x00 26. "PERIPH_58_RST,Reset Control value for peripheral PERIPH_58_RST" "0: No forced reset on PERIPH_58_RST,1: Forced Reset on PERIPH_58_RST"
newline
bitfld.long 0x00 25. "PERIPH_57_RST,Reset Control value for peripheral PERIPH_57_RST" "0: No forced reset on PERIPH_57_RST,1: Forced Reset on PERIPH_57_RST"
newline
bitfld.long 0x00 24. "PERIPH_56_RST,Reset Control value for peripheral PERIPH_56_RST" "0: No forced reset on PERIPH_56_RST,1: Forced Reset on PERIPH_56_RST"
newline
bitfld.long 0x00 23. "PERIPH_55_RST,Reset Control value for peripheral PERIPH_55_RST" "0: No forced reset on PERIPH_55_RST,1: Forced Reset on PERIPH_55_RST"
newline
bitfld.long 0x00 22. "PERIPH_54_RST,Reset Control value for peripheral PERIPH_54_RST" "0: No forced reset on PERIPH_54_RST,1: Forced Reset on PERIPH_54_RST"
newline
bitfld.long 0x00 21. "PERIPH_53_RST,Reset Control value for peripheral PERIPH_53_RST" "0: No forced reset on PERIPH_53_RST,1: Forced Reset on PERIPH_53_RST"
newline
bitfld.long 0x00 20. "PERIPH_52_RST,Reset Control value for peripheral PERIPH_52_RST" "0: No forced reset on PERIPH_52_RST,1: Forced Reset on PERIPH_52_RST"
newline
bitfld.long 0x00 19. "PERIPH_51_RST,Reset Control value for peripheral PERIPH_51_RST" "0: No forced reset on PERIPH_51_RST,1: Forced Reset on PERIPH_51_RST"
newline
bitfld.long 0x00 18. "PERIPH_50_RST,Reset Control value for peripheral PERIPH_50_RST" "0: No forced reset on PERIPH_50_RST,1: Forced Reset on PERIPH_50_RST"
newline
bitfld.long 0x00 17. "PERIPH_49_RST,Reset Control value for peripheral PERIPH_49_RST" "0: No forced reset on PERIPH_49_RST,1: Forced Reset on PERIPH_49_RST"
newline
bitfld.long 0x00 16. "PERIPH_48_RST,Reset Control value for peripheral PERIPH_48_RST" "0: No forced reset on PERIPH_48_RST,1: Forced Reset on PERIPH_48_RST"
newline
bitfld.long 0x00 15. "PERIPH_47_RST,Reset Control value for peripheral PERIPH_47_RST" "0: No forced reset on PERIPH_47_RST,1: Forced Reset on PERIPH_47_RST"
newline
bitfld.long 0x00 14. "PERIPH_46_RST,Reset Control value for peripheral PERIPH_46_RST" "0: No forced reset on PERIPH_46_RST,1: Forced Reset on PERIPH_46_RST"
newline
bitfld.long 0x00 13. "PERIPH_45_RST,Reset Control value for peripheral PERIPH_45_RST" "0: No forced reset on PERIPH_45_RST,1: Forced Reset on PERIPH_45_RST"
newline
bitfld.long 0x00 12. "PERIPH_44_RST,Reset Control value for peripheral PERIPH_44_RST" "0: No forced reset on PERIPH_44_RST,1: Forced Reset on PERIPH_44_RST"
newline
bitfld.long 0x00 11. "PERIPH_43_RST,Reset Control value for peripheral PERIPH_43_RST" "0: No forced reset on PERIPH_43_RST,1: Forced Reset on PERIPH_43_RST"
newline
bitfld.long 0x00 10. "PERIPH_42_RST,Reset Control value for peripheral PERIPH_42_RST" "0: No forced reset on PERIPH_42_RST,1: Forced Reset on PERIPH_42_RST"
newline
bitfld.long 0x00 9. "PERIPH_41_RST,Reset Control value for peripheral PERIPH_41_RST" "0: No forced reset on PERIPH_41_RST,1: Forced Reset on PERIPH_41_RST"
newline
bitfld.long 0x00 8. "PERIPH_40_RST,Reset Control value for peripheral PERIPH_40_RST" "0: No forced reset on PERIPH_40_RST,1: Forced Reset on PERIPH_40_RST"
newline
bitfld.long 0x00 7. "PERIPH_39_RST,Reset Control value for peripheral PERIPH_39_RST" "0: No forced reset on PERIPH_39_RST,1: Forced Reset on PERIPH_39_RST"
newline
bitfld.long 0x00 6. "PERIPH_38_RST,Reset Control value for peripheral PERIPH_38_RST" "0: No forced reset on PERIPH_38_RST,1: Forced Reset on PERIPH_38_RST"
newline
bitfld.long 0x00 5. "PERIPH_37_RST,Reset Control value for peripheral PERIPH_37_RST" "0: No forced reset on PERIPH_37_RST,1: Forced Reset on PERIPH_37_RST"
newline
bitfld.long 0x00 4. "PERIPH_36_RST,Reset Control value for peripheral PERIPH_36_RST" "0: No forced reset on PERIPH_36_RST,1: Forced Reset on PERIPH_36_RST"
newline
bitfld.long 0x00 3. "PERIPH_35_RST,Reset Control value for peripheral PERIPH_35_RST" "0: No forced reset on PERIPH_35_RST,1: Forced Reset on PERIPH_35_RST"
newline
bitfld.long 0x00 2. "PERIPH_34_RST,Reset Control value for peripheral PERIPH_34_RST" "0: No forced reset on PERIPH_34_RST,1: Forced Reset on PERIPH_34_RST"
newline
bitfld.long 0x00 1. "PERIPH_33_RST,Reset Control value for peripheral PERIPH_33_RST" "0: No forced reset on PERIPH_33_RST,1: Forced Reset on PERIPH_33_RST"
newline
bitfld.long 0x00 0. "PERIPH_32_RST,Reset Control value for peripheral PERIPH_32_RST" "0: No forced reset on PERIPH_32_RST,1: Forced Reset on PERIPH_32_RST"
group.long 0x48++0x03
line.long 0x00 "PRST1_0,Peripheral Reset"
bitfld.long 0x00 31. "PERIPH_95_RST,Reset Control value for peripheral PERIPH_95_RST" "0: No forced reset on PERIPH_95_RST,1: Forced Reset on PERIPH_95_RST"
newline
bitfld.long 0x00 30. "PERIPH_94_RST,Reset Control value for peripheral PERIPH_94_RST" "0: No forced reset on PERIPH_94_RST,1: Forced Reset on PERIPH_94_RST"
newline
bitfld.long 0x00 29. "PERIPH_93_RST,Reset Control value for peripheral PERIPH_93_RST" "0: No forced reset on PERIPH_93_RST,1: Forced Reset on PERIPH_93_RST"
newline
bitfld.long 0x00 28. "PERIPH_92_RST,Reset Control value for peripheral PERIPH_92_RST" "0: No forced reset on PERIPH_92_RST,1: Forced Reset on PERIPH_92_RST"
newline
bitfld.long 0x00 27. "PERIPH_91_RST,Reset Control value for peripheral PERIPH_91_RST" "0: No forced reset on PERIPH_91_RST,1: Forced Reset on PERIPH_91_RST"
newline
bitfld.long 0x00 26. "PERIPH_90_RST,Reset Control value for peripheral PERIPH_90_RST" "0: No forced reset on PERIPH_90_RST,1: Forced Reset on PERIPH_90_RST"
newline
bitfld.long 0x00 25. "PERIPH_89_RST,Reset Control value for peripheral PERIPH_89_RST" "0: No forced reset on PERIPH_89_RST,1: Forced Reset on PERIPH_89_RST"
newline
bitfld.long 0x00 24. "PERIPH_88_RST,Reset Control value for peripheral PERIPH_88_RST" "0: No forced reset on PERIPH_88_RST,1: Forced Reset on PERIPH_88_RST"
newline
bitfld.long 0x00 23. "PERIPH_87_RST,Reset Control value for peripheral PERIPH_87_RST" "0: No forced reset on PERIPH_87_RST,1: Forced Reset on PERIPH_87_RST"
newline
bitfld.long 0x00 22. "PERIPH_86_RST,Reset Control value for peripheral PERIPH_86_RST" "0: No forced reset on PERIPH_86_RST,1: Forced Reset on PERIPH_86_RST"
newline
bitfld.long 0x00 21. "PERIPH_85_RST,Reset Control value for peripheral PERIPH_85_RST" "0: No forced reset on PERIPH_85_RST,1: Forced Reset on PERIPH_85_RST"
newline
bitfld.long 0x00 20. "PERIPH_84_RST,Reset Control value for peripheral PERIPH_84_RST" "0: No forced reset on PERIPH_84_RST,1: Forced Reset on PERIPH_84_RST"
newline
bitfld.long 0x00 19. "PERIPH_83_RST,Reset Control value for peripheral PERIPH_83_RST" "0: No forced reset on PERIPH_83_RST,1: Forced Reset on PERIPH_83_RST"
newline
bitfld.long 0x00 18. "PERIPH_82_RST,Reset Control value for peripheral PERIPH_82_RST" "0: No forced reset on PERIPH_82_RST,1: Forced Reset on PERIPH_82_RST"
newline
bitfld.long 0x00 17. "PERIPH_81_RST,Reset Control value for peripheral PERIPH_81_RST" "0: No forced reset on PERIPH_81_RST,1: Forced Reset on PERIPH_81_RST"
newline
bitfld.long 0x00 16. "PERIPH_80_RST,Reset Control value for peripheral PERIPH_80_RST" "0: No forced reset on PERIPH_80_RST,1: Forced Reset on PERIPH_80_RST"
newline
bitfld.long 0x00 15. "PERIPH_79_RST,Reset Control value for peripheral PERIPH_79_RST" "0: No forced reset on PERIPH_79_RST,1: Forced Reset on PERIPH_79_RST"
newline
bitfld.long 0x00 14. "PERIPH_78_RST,Reset Control value for peripheral PERIPH_78_RST" "0: No forced reset on PERIPH_78_RST,1: Forced Reset on PERIPH_78_RST"
newline
bitfld.long 0x00 13. "PERIPH_77_RST,Reset Control value for peripheral PERIPH_77_RST" "0: No forced reset on PERIPH_77_RST,1: Forced Reset on PERIPH_77_RST"
newline
bitfld.long 0x00 12. "PERIPH_76_RST,Reset Control value for peripheral PERIPH_76_RST" "0: No forced reset on PERIPH_76_RST,1: Forced Reset on PERIPH_76_RST"
newline
bitfld.long 0x00 11. "PERIPH_75_RST,Reset Control value for peripheral PERIPH_75_RST" "0: No forced reset on PERIPH_75_RST,1: Forced Reset on PERIPH_75_RST"
newline
bitfld.long 0x00 10. "PERIPH_74_RST,Reset Control value for peripheral PERIPH_74_RST" "0: No forced reset on PERIPH_74_RST,1: Forced Reset on PERIPH_74_RST"
newline
bitfld.long 0x00 9. "PERIPH_73_RST,Reset Control value for peripheral PERIPH_73_RST" "0: No forced reset on PERIPH_73_RST,1: Forced Reset on PERIPH_73_RST"
newline
bitfld.long 0x00 8. "PERIPH_72_RST,Reset Control value for peripheral PERIPH_72_RST" "0: No forced reset on PERIPH_72_RST,1: Forced Reset on PERIPH_72_RST"
newline
bitfld.long 0x00 7. "PERIPH_71_RST,Reset Control value for peripheral PERIPH_71_RST" "0: No forced reset on PERIPH_71_RST,1: Forced Reset on PERIPH_71_RST"
newline
bitfld.long 0x00 6. "PERIPH_70_RST,Reset Control value for peripheral PERIPH_70_RST" "0: No forced reset on PERIPH_70_RST,1: Forced Reset on PERIPH_70_RST"
newline
bitfld.long 0x00 5. "PERIPH_69_RST,Reset Control value for peripheral PERIPH_69_RST" "0: No forced reset on PERIPH_69_RST,1: Forced Reset on PERIPH_69_RST"
newline
bitfld.long 0x00 4. "PERIPH_68_RST,Reset Control value for peripheral PERIPH_68_RST" "0: No forced reset on PERIPH_68_RST,1: Forced Reset on PERIPH_68_RST"
newline
bitfld.long 0x00 3. "PERIPH_67_RST,Reset Control value for peripheral PERIPH_67_RST" "0: No forced reset on PERIPH_67_RST,1: Forced Reset on PERIPH_67_RST"
newline
bitfld.long 0x00 2. "PERIPH_66_RST,Reset Control value for peripheral PERIPH_66_RST" "0: No forced reset on PERIPH_66_RST,1: Forced Reset on PERIPH_66_RST"
newline
bitfld.long 0x00 1. "PERIPH_65_RST,Reset Control value for peripheral CA53_CORE_0_RST" "0: No forced reset on CA53_CORE_0_RST,1: Forced Reset on CA53_CORE_0_RST"
newline
bitfld.long 0x00 0. "PERIPH_64_RST,Reset Control value for peripheral A53_Cluster_RST" "0: No forced reset on A53_Cluster_RST,1: Forced Reset on A53_Cluster_RST"
group.long 0x4C++0x03
line.long 0x00 "PRST1_1,Peripheral Reset"
bitfld.long 0x00 31. "PERIPH_127_RST,Reset Control value for peripheral PERIPH_127_RST" "0: No forced reset on PERIPH_127_RST,1: Forced Reset on PERIPH_127_RST"
newline
bitfld.long 0x00 30. "PERIPH_126_RST,Reset Control value for peripheral PERIPH_126_RST" "0: No forced reset on PERIPH_126_RST,1: Forced Reset on PERIPH_126_RST"
newline
bitfld.long 0x00 29. "PERIPH_125_RST,Reset Control value for peripheral PERIPH_125_RST" "0: No forced reset on PERIPH_125_RST,1: Forced Reset on PERIPH_125_RST"
newline
bitfld.long 0x00 28. "PERIPH_124_RST,Reset Control value for peripheral PERIPH_124_RST" "0: No forced reset on PERIPH_124_RST,1: Forced Reset on PERIPH_124_RST"
newline
bitfld.long 0x00 27. "PERIPH_123_RST,Reset Control value for peripheral PERIPH_123_RST" "0: No forced reset on PERIPH_123_RST,1: Forced Reset on PERIPH_123_RST"
newline
bitfld.long 0x00 26. "PERIPH_122_RST,Reset Control value for peripheral PERIPH_122_RST" "0: No forced reset on PERIPH_122_RST,1: Forced Reset on PERIPH_122_RST"
newline
bitfld.long 0x00 25. "PERIPH_121_RST,Reset Control value for peripheral PERIPH_121_RST" "0: No forced reset on PERIPH_121_RST,1: Forced Reset on PERIPH_121_RST"
newline
bitfld.long 0x00 24. "PERIPH_120_RST,Reset Control value for peripheral PERIPH_120_RST" "0: No forced reset on PERIPH_120_RST,1: Forced Reset on PERIPH_120_RST"
newline
bitfld.long 0x00 23. "PERIPH_119_RST,Reset Control value for peripheral PERIPH_119_RST" "0: No forced reset on PERIPH_119_RST,1: Forced Reset on PERIPH_119_RST"
newline
bitfld.long 0x00 22. "PERIPH_118_RST,Reset Control value for peripheral PERIPH_118_RST" "0: No forced reset on PERIPH_118_RST,1: Forced Reset on PERIPH_118_RST"
newline
bitfld.long 0x00 21. "PERIPH_117_RST,Reset Control value for peripheral PERIPH_117_RST" "0: No forced reset on PERIPH_117_RST,1: Forced Reset on PERIPH_117_RST"
newline
bitfld.long 0x00 20. "PERIPH_116_RST,Reset Control value for peripheral PERIPH_116_RST" "0: No forced reset on PERIPH_116_RST,1: Forced Reset on PERIPH_116_RST"
newline
bitfld.long 0x00 19. "PERIPH_115_RST,Reset Control value for peripheral PERIPH_115_RST" "0: No forced reset on PERIPH_115_RST,1: Forced Reset on PERIPH_115_RST"
newline
bitfld.long 0x00 18. "PERIPH_114_RST,Reset Control value for peripheral PERIPH_114_RST" "0: No forced reset on PERIPH_114_RST,1: Forced Reset on PERIPH_114_RST"
newline
bitfld.long 0x00 17. "PERIPH_113_RST,Reset Control value for peripheral PERIPH_113_RST" "0: No forced reset on PERIPH_113_RST,1: Forced Reset on PERIPH_113_RST"
newline
bitfld.long 0x00 16. "PERIPH_112_RST,Reset Control value for peripheral PERIPH_112_RST" "0: No forced reset on PERIPH_112_RST,1: Forced Reset on PERIPH_112_RST"
newline
bitfld.long 0x00 15. "PERIPH_111_RST,Reset Control value for peripheral PERIPH_111_RST" "0: No forced reset on PERIPH_111_RST,1: Forced Reset on PERIPH_111_RST"
newline
bitfld.long 0x00 14. "PERIPH_110_RST,Reset Control value for peripheral PERIPH_110_RST" "0: No forced reset on PERIPH_110_RST,1: Forced Reset on PERIPH_110_RST"
newline
bitfld.long 0x00 13. "PERIPH_109_RST,Reset Control value for peripheral PERIPH_109_RST" "0: No forced reset on PERIPH_109_RST,1: Forced Reset on PERIPH_109_RST"
newline
bitfld.long 0x00 12. "PERIPH_108_RST,Reset Control value for peripheral PERIPH_108_RST" "0: No forced reset on PERIPH_108_RST,1: Forced Reset on PERIPH_108_RST"
newline
bitfld.long 0x00 11. "PERIPH_107_RST,Reset Control value for peripheral PERIPH_107_RST" "0: No forced reset on PERIPH_107_RST,1: Forced Reset on PERIPH_107_RST"
newline
bitfld.long 0x00 10. "PERIPH_106_RST,Reset Control value for peripheral PERIPH_106_RST" "0: No forced reset on PERIPH_106_RST,1: Forced Reset on PERIPH_106_RST"
newline
bitfld.long 0x00 9. "PERIPH_105_RST,Reset Control value for peripheral PERIPH_105_RST" "0: No forced reset on PERIPH_105_RST,1: Forced Reset on PERIPH_105_RST"
newline
bitfld.long 0x00 8. "PERIPH_104_RST,Reset Control value for peripheral PERIPH_104_RST" "0: No forced reset on PERIPH_104_RST,1: Forced Reset on PERIPH_104_RST"
newline
bitfld.long 0x00 7. "PERIPH_103_RST,Reset Control value for peripheral PERIPH_103_RST" "0: No forced reset on PERIPH_103_RST,1: Forced Reset on PERIPH_103_RST"
newline
bitfld.long 0x00 6. "PERIPH_102_RST,Reset Control value for peripheral PERIPH_102_RST" "0: No forced reset on PERIPH_102_RST,1: Forced Reset on PERIPH_102_RST"
newline
bitfld.long 0x00 5. "PERIPH_101_RST,Reset Control value for peripheral PERIPH_101_RST" "0: No forced reset on PERIPH_101_RST,1: Forced Reset on PERIPH_101_RST"
newline
bitfld.long 0x00 4. "PERIPH_100_RST,Reset Control value for peripheral PERIPH_100_RST" "0: No forced reset on PERIPH_100_RST,1: Forced Reset on PERIPH_100_RST"
newline
bitfld.long 0x00 3. "PERIPH_99_RST,Reset Control value for peripheral PERIPH_99_RST" "0: No forced reset on PERIPH_99_RST,1: Forced Reset on PERIPH_99_RST"
newline
bitfld.long 0x00 2. "PERIPH_98_RST,Reset Control value for peripheral PERIPH_98_RST" "0: No forced reset on PERIPH_98_RST,1: Forced Reset on PERIPH_98_RST"
newline
bitfld.long 0x00 1. "PERIPH_97_RST,Reset Control value for peripheral PERIPH_97_RST" "0: No forced reset on PERIPH_97_RST,1: Forced Reset on PERIPH_97_RST"
newline
bitfld.long 0x00 0. "PERIPH_96_RST,Reset Control value for peripheral PERIPH_96_RST" "0: No forced reset on PERIPH_96_RST,1: Forced Reset on PERIPH_96_RST"
group.long 0x50++0x03
line.long 0x00 "PRST2_0,Peripheral Reset"
bitfld.long 0x00 31. "PERIPH_159_RST,Reset Control value for peripheral PERIPH_159_RST" "0: No forced reset on PERIPH_159_RST,1: Forced Reset on PERIPH_159_RST"
newline
bitfld.long 0x00 30. "PERIPH_158_RST,Reset Control value for peripheral PERIPH_158_RST" "0: No forced reset on PERIPH_158_RST,1: Forced Reset on PERIPH_158_RST"
newline
bitfld.long 0x00 29. "PERIPH_157_RST,Reset Control value for peripheral PERIPH_157_RST" "0: No forced reset on PERIPH_157_RST,1: Forced Reset on PERIPH_157_RST"
newline
bitfld.long 0x00 28. "PERIPH_156_RST,Reset Control value for peripheral PERIPH_156_RST" "0: No forced reset on PERIPH_156_RST,1: Forced Reset on PERIPH_156_RST"
newline
bitfld.long 0x00 27. "PERIPH_155_RST,Reset Control value for peripheral PERIPH_155_RST" "0: No forced reset on PERIPH_155_RST,1: Forced Reset on PERIPH_155_RST"
newline
bitfld.long 0x00 26. "PERIPH_154_RST,Reset Control value for peripheral PERIPH_154_RST" "0: No forced reset on PERIPH_154_RST,1: Forced Reset on PERIPH_154_RST"
newline
bitfld.long 0x00 25. "PERIPH_153_RST,Reset Control value for peripheral PERIPH_153_RST" "0: No forced reset on PERIPH_153_RST,1: Forced Reset on PERIPH_153_RST"
newline
bitfld.long 0x00 24. "PERIPH_152_RST,Reset Control value for peripheral PERIPH_152_RST" "0: No forced reset on PERIPH_152_RST,1: Forced Reset on PERIPH_152_RST"
newline
bitfld.long 0x00 23. "PERIPH_151_RST,Reset Control value for peripheral PERIPH_151_RST" "0: No forced reset on PERIPH_151_RST,1: Forced Reset on PERIPH_151_RST"
newline
bitfld.long 0x00 22. "PERIPH_150_RST,Reset Control value for peripheral PERIPH_150_RST" "0: No forced reset on PERIPH_150_RST,1: Forced Reset on PERIPH_150_RST"
newline
bitfld.long 0x00 21. "PERIPH_149_RST,Reset Control value for peripheral PERIPH_149_RST" "0: No forced reset on PERIPH_149_RST,1: Forced Reset on PERIPH_149_RST"
newline
bitfld.long 0x00 20. "PERIPH_148_RST,Reset Control value for peripheral PERIPH_148_RST" "0: No forced reset on PERIPH_148_RST,1: Forced Reset on PERIPH_148_RST"
newline
bitfld.long 0x00 19. "PERIPH_147_RST,Reset Control value for peripheral PERIPH_147_RST" "0: No forced reset on PERIPH_147_RST,1: Forced Reset on PERIPH_147_RST"
newline
bitfld.long 0x00 18. "PERIPH_146_RST,Reset Control value for peripheral PERIPH_146_RST" "0: No forced reset on PERIPH_146_RST,1: Forced Reset on PERIPH_146_RST"
newline
bitfld.long 0x00 17. "PERIPH_145_RST,Reset Control value for peripheral PERIPH_145_RST" "0: No forced reset on PERIPH_145_RST,1: Forced Reset on PERIPH_145_RST"
newline
bitfld.long 0x00 16. "PERIPH_144_RST,Reset Control value for peripheral PERIPH_144_RST" "0: No forced reset on PERIPH_144_RST,1: Forced Reset on PERIPH_144_RST"
newline
bitfld.long 0x00 15. "PERIPH_143_RST,Reset Control value for peripheral PERIPH_143_RST" "0: No forced reset on PERIPH_143_RST,1: Forced Reset on PERIPH_143_RST"
newline
bitfld.long 0x00 14. "PERIPH_142_RST,Reset Control value for peripheral PERIPH_142_RST" "0: No forced reset on PERIPH_142_RST,1: Forced Reset on PERIPH_142_RST"
newline
bitfld.long 0x00 13. "PERIPH_141_RST,Reset Control value for peripheral PERIPH_141_RST" "0: No forced reset on PERIPH_141_RST,1: Forced Reset on PERIPH_141_RST"
newline
bitfld.long 0x00 12. "PERIPH_140_RST,Reset Control value for peripheral PERIPH_140_RST" "0: No forced reset on PERIPH_140_RST,1: Forced Reset on PERIPH_140_RST"
newline
bitfld.long 0x00 11. "PERIPH_139_RST,Reset Control value for peripheral PERIPH_139_RST" "0: No forced reset on PERIPH_139_RST,1: Forced Reset on PERIPH_139_RST"
newline
bitfld.long 0x00 10. "PERIPH_138_RST,Reset Control value for peripheral PERIPH_138_RST" "0: No forced reset on PERIPH_138_RST,1: Forced Reset on PERIPH_138_RST"
newline
bitfld.long 0x00 9. "PERIPH_137_RST,Reset Control value for peripheral PERIPH_137_RST" "0: No forced reset on PERIPH_137_RST,1: Forced Reset on PERIPH_137_RST"
newline
bitfld.long 0x00 8. "PERIPH_136_RST,Reset Control value for peripheral PERIPH_136_RST" "0: No forced reset on PERIPH_136_RST,1: Forced Reset on PERIPH_136_RST"
newline
bitfld.long 0x00 7. "PERIPH_135_RST,Reset Control value for peripheral PERIPH_135_RST" "0: No forced reset on PERIPH_135_RST,1: Forced Reset on PERIPH_135_RST"
newline
bitfld.long 0x00 6. "PERIPH_134_RST,Reset Control value for peripheral PERIPH_134_RST" "0: No forced reset on PERIPH_134_RST,1: Forced Reset on PERIPH_134_RST"
newline
bitfld.long 0x00 5. "PERIPH_133_RST,Reset Control value for peripheral PERIPH_133_RST" "0: No forced reset on PERIPH_133_RST,1: Forced Reset on PERIPH_133_RST"
newline
bitfld.long 0x00 4. "PERIPH_132_RST,Reset Control value for peripheral PERIPH_132_RST" "0: No forced reset on PERIPH_132_RST,1: Forced Reset on PERIPH_132_RST"
newline
bitfld.long 0x00 3. "PERIPH_131_RST,Reset Control value for peripheral PERIPH_131_RST" "0: No forced reset on PERIPH_131_RST,1: Forced Reset on PERIPH_131_RST"
newline
bitfld.long 0x00 2. "PERIPH_130_RST,Reset Control value for peripheral PERIPH_130_RST" "0: No forced reset on PERIPH_130_RST,1: Forced Reset on PERIPH_130_RST"
newline
bitfld.long 0x00 1. "PERIPH_129_RST,Reset Control value for peripheral PERIPH_129_RST" "0: No forced reset on PERIPH_129_RST,1: Forced Reset on PERIPH_129_RST"
newline
bitfld.long 0x00 0. "PERIPH_128_RST,Reset Control value for peripheral PERIPH_128_RST" "0: No forced reset on PERIPH_128_RST,1: Forced Reset on PERIPH_128_RST"
group.long 0x54++0x03
line.long 0x00 "PRST2_1,Peripheral Reset"
bitfld.long 0x00 31. "PERIPH_191_RST,Reset Control value for peripheral PERIPH_191_RST" "0: No forced reset on PERIPH_191_RST,1: Forced Reset on PERIPH_191_RST"
newline
bitfld.long 0x00 30. "PERIPH_190_RST,Reset Control value for peripheral PERIPH_190_RST" "0: No forced reset on PERIPH_190_RST,1: Forced Reset on PERIPH_190_RST"
newline
bitfld.long 0x00 29. "PERIPH_189_RST,Reset Control value for peripheral PERIPH_189_RST" "0: No forced reset on PERIPH_189_RST,1: Forced Reset on PERIPH_189_RST"
newline
bitfld.long 0x00 28. "PERIPH_188_RST,Reset Control value for peripheral PERIPH_188_RST" "0: No forced reset on PERIPH_188_RST,1: Forced Reset on PERIPH_188_RST"
newline
bitfld.long 0x00 27. "PERIPH_187_RST,Reset Control value for peripheral PERIPH_187_RST" "0: No forced reset on PERIPH_187_RST,1: Forced Reset on PERIPH_187_RST"
newline
bitfld.long 0x00 26. "PERIPH_186_RST,Reset Control value for peripheral PERIPH_186_RST" "0: No forced reset on PERIPH_186_RST,1: Forced Reset on PERIPH_186_RST"
newline
bitfld.long 0x00 25. "PERIPH_185_RST,Reset Control value for peripheral PERIPH_185_RST" "0: No forced reset on PERIPH_185_RST,1: Forced Reset on PERIPH_185_RST"
newline
bitfld.long 0x00 24. "PERIPH_184_RST,Reset Control value for peripheral PERIPH_184_RST" "0: No forced reset on PERIPH_184_RST,1: Forced Reset on PERIPH_184_RST"
newline
bitfld.long 0x00 23. "PERIPH_183_RST,Reset Control value for peripheral PERIPH_183_RST" "0: No forced reset on PERIPH_183_RST,1: Forced Reset on PERIPH_183_RST"
newline
bitfld.long 0x00 22. "PERIPH_182_RST,Reset Control value for peripheral PERIPH_182_RST" "0: No forced reset on PERIPH_182_RST,1: Forced Reset on PERIPH_182_RST"
newline
bitfld.long 0x00 21. "PERIPH_181_RST,Reset Control value for peripheral PERIPH_181_RST" "0: No forced reset on PERIPH_181_RST,1: Forced Reset on PERIPH_181_RST"
newline
bitfld.long 0x00 20. "PERIPH_180_RST,Reset Control value for peripheral PERIPH_180_RST" "0: No forced reset on PERIPH_180_RST,1: Forced Reset on PERIPH_180_RST"
newline
bitfld.long 0x00 19. "PERIPH_179_RST,Reset Control value for peripheral PERIPH_179_RST" "0: No forced reset on PERIPH_179_RST,1: Forced Reset on PERIPH_179_RST"
newline
bitfld.long 0x00 18. "PERIPH_178_RST,Reset Control value for peripheral PERIPH_178_RST" "0: No forced reset on PERIPH_178_RST,1: Forced Reset on PERIPH_178_RST"
newline
bitfld.long 0x00 17. "PERIPH_177_RST,Reset Control value for peripheral PERIPH_177_RST" "0: No forced reset on PERIPH_177_RST,1: Forced Reset on PERIPH_177_RST"
newline
bitfld.long 0x00 16. "PERIPH_176_RST,Reset Control value for peripheral PERIPH_176_RST" "0: No forced reset on PERIPH_176_RST,1: Forced Reset on PERIPH_176_RST"
newline
bitfld.long 0x00 15. "PERIPH_175_RST,Reset Control value for peripheral PERIPH_175_RST" "0: No forced reset on PERIPH_175_RST,1: Forced Reset on PERIPH_175_RST"
newline
bitfld.long 0x00 14. "PERIPH_174_RST,Reset Control value for peripheral PERIPH_174_RST" "0: No forced reset on PERIPH_174_RST,1: Forced Reset on PERIPH_174_RST"
newline
bitfld.long 0x00 13. "PERIPH_173_RST,Reset Control value for peripheral PERIPH_173_RST" "0: No forced reset on PERIPH_173_RST,1: Forced Reset on PERIPH_173_RST"
newline
bitfld.long 0x00 12. "PERIPH_172_RST,Reset Control value for peripheral PERIPH_172_RST" "0: No forced reset on PERIPH_172_RST,1: Forced Reset on PERIPH_172_RST"
newline
bitfld.long 0x00 11. "PERIPH_171_RST,Reset Control value for peripheral PERIPH_171_RST" "0: No forced reset on PERIPH_171_RST,1: Forced Reset on PERIPH_171_RST"
newline
bitfld.long 0x00 10. "PERIPH_170_RST,Reset Control value for peripheral PERIPH_170_RST" "0: No forced reset on PERIPH_170_RST,1: Forced Reset on PERIPH_170_RST"
newline
bitfld.long 0x00 9. "PERIPH_169_RST,Reset Control value for peripheral PERIPH_169_RST" "0: No forced reset on PERIPH_169_RST,1: Forced Reset on PERIPH_169_RST"
newline
bitfld.long 0x00 8. "PERIPH_168_RST,Reset Control value for peripheral PERIPH_168_RST" "0: No forced reset on PERIPH_168_RST,1: Forced Reset on PERIPH_168_RST"
newline
bitfld.long 0x00 7. "PERIPH_167_RST,Reset Control value for peripheral PERIPH_167_RST" "0: No forced reset on PERIPH_167_RST,1: Forced Reset on PERIPH_167_RST"
newline
bitfld.long 0x00 6. "PERIPH_166_RST,Reset Control value for peripheral PERIPH_166_RST" "0: No forced reset on PERIPH_166_RST,1: Forced Reset on PERIPH_166_RST"
newline
bitfld.long 0x00 5. "PERIPH_165_RST,Reset Control value for peripheral PERIPH_165_RST" "0: No forced reset on PERIPH_165_RST,1: Forced Reset on PERIPH_165_RST"
newline
bitfld.long 0x00 4. "PERIPH_164_RST,Reset Control value for peripheral PERIPH_164_RST" "0: No forced reset on PERIPH_164_RST,1: Forced Reset on PERIPH_164_RST"
newline
bitfld.long 0x00 3. "PERIPH_163_RST,Reset Control value for peripheral PERIPH_163_RST" "0: No forced reset on PERIPH_163_RST,1: Forced Reset on PERIPH_163_RST"
newline
bitfld.long 0x00 2. "PERIPH_162_RST,Reset Control value for peripheral PERIPH_162_RST" "0: No forced reset on PERIPH_162_RST,1: Forced Reset on PERIPH_162_RST"
newline
bitfld.long 0x00 1. "PERIPH_161_RST,Reset Control value for peripheral PERIPH_161_RST" "0: No forced reset on PERIPH_161_RST,1: Forced Reset on PERIPH_161_RST"
newline
bitfld.long 0x00 0. "PERIPH_160_RST,Reset Control value for peripheral PERIPH_160_RST" "0: No forced reset on PERIPH_160_RST,1: Forced Reset on PERIPH_160_RST"
group.long 0x58++0x03
line.long 0x00 "PRST3_0,Peripheral Reset"
bitfld.long 0x00 31. "PERIPH_223_RST,Reset Control value for peripheral PERIPH_223_RST" "0: No forced reset on PERIPH_223_RST,1: Forced Reset on PERIPH_223_RST"
newline
bitfld.long 0x00 30. "PERIPH_222_RST,Reset Control value for peripheral PERIPH_222_RST" "0: No forced reset on PERIPH_222_RST,1: Forced Reset on PERIPH_222_RST"
newline
bitfld.long 0x00 29. "PERIPH_221_RST,Reset Control value for peripheral PERIPH_221_RST" "0: No forced reset on PERIPH_221_RST,1: Forced Reset on PERIPH_221_RST"
newline
bitfld.long 0x00 28. "PERIPH_220_RST,Reset Control value for peripheral PERIPH_220_RST" "0: No forced reset on PERIPH_220_RST,1: Forced Reset on PERIPH_220_RST"
newline
bitfld.long 0x00 27. "PERIPH_219_RST,Reset Control value for peripheral PERIPH_219_RST" "0: No forced reset on PERIPH_219_RST,1: Forced Reset on PERIPH_219_RST"
newline
bitfld.long 0x00 26. "PERIPH_218_RST,Reset Control value for peripheral PERIPH_218_RST" "0: No forced reset on PERIPH_218_RST,1: Forced Reset on PERIPH_218_RST"
newline
bitfld.long 0x00 25. "PERIPH_217_RST,Reset Control value for peripheral PERIPH_217_RST" "0: No forced reset on PERIPH_217_RST,1: Forced Reset on PERIPH_217_RST"
newline
bitfld.long 0x00 24. "PERIPH_216_RST,Reset Control value for peripheral PERIPH_216_RST" "0: No forced reset on PERIPH_216_RST,1: Forced Reset on PERIPH_216_RST"
newline
bitfld.long 0x00 23. "PERIPH_215_RST,Reset Control value for peripheral PERIPH_215_RST" "0: No forced reset on PERIPH_215_RST,1: Forced Reset on PERIPH_215_RST"
newline
bitfld.long 0x00 22. "PERIPH_214_RST,Reset Control value for peripheral PERIPH_214_RST" "0: No forced reset on PERIPH_214_RST,1: Forced Reset on PERIPH_214_RST"
newline
bitfld.long 0x00 21. "PERIPH_213_RST,Reset Control value for peripheral PERIPH_213_RST" "0: No forced reset on PERIPH_213_RST,1: Forced Reset on PERIPH_213_RST"
newline
bitfld.long 0x00 20. "PERIPH_212_RST,Reset Control value for peripheral PERIPH_212_RST" "0: No forced reset on PERIPH_212_RST,1: Forced Reset on PERIPH_212_RST"
newline
bitfld.long 0x00 19. "PERIPH_211_RST,Reset Control value for peripheral PERIPH_211_RST" "0: No forced reset on PERIPH_211_RST,1: Forced Reset on PERIPH_211_RST"
newline
bitfld.long 0x00 18. "PERIPH_210_RST,Reset Control value for peripheral PERIPH_210_RST" "0: No forced reset on PERIPH_210_RST,1: Forced Reset on PERIPH_210_RST"
newline
bitfld.long 0x00 17. "PERIPH_209_RST,Reset Control value for peripheral PERIPH_209_RST" "0: No forced reset on PERIPH_209_RST,1: Forced Reset on PERIPH_209_RST"
newline
bitfld.long 0x00 16. "PERIPH_208_RST,Reset Control value for peripheral PERIPH_208_RST" "0: No forced reset on PERIPH_208_RST,1: Forced Reset on PERIPH_208_RST"
newline
bitfld.long 0x00 15. "PERIPH_207_RST,Reset Control value for peripheral PERIPH_207_RST" "0: No forced reset on PERIPH_207_RST,1: Forced Reset on PERIPH_207_RST"
newline
bitfld.long 0x00 14. "PERIPH_206_RST,Reset Control value for peripheral PERIPH_206_RST" "0: No forced reset on PERIPH_206_RST,1: Forced Reset on PERIPH_206_RST"
newline
bitfld.long 0x00 13. "PERIPH_205_RST,Reset Control value for peripheral PERIPH_205_RST" "0: No forced reset on PERIPH_205_RST,1: Forced Reset on PERIPH_205_RST"
newline
bitfld.long 0x00 12. "PERIPH_204_RST,Reset Control value for peripheral PERIPH_204_RST" "0: No forced reset on PERIPH_204_RST,1: Forced Reset on PERIPH_204_RST"
newline
bitfld.long 0x00 11. "PERIPH_203_RST,Reset Control value for peripheral PERIPH_203_RST" "0: No forced reset on PERIPH_203_RST,1: Forced Reset on PERIPH_203_RST"
newline
bitfld.long 0x00 10. "PERIPH_202_RST,Reset Control value for peripheral PERIPH_202_RST" "0: No forced reset on PERIPH_202_RST,1: Forced Reset on PERIPH_202_RST"
newline
bitfld.long 0x00 9. "PERIPH_201_RST,Reset Control value for peripheral PERIPH_201_RST" "0: No forced reset on PERIPH_201_RST,1: Forced Reset on PERIPH_201_RST"
newline
bitfld.long 0x00 8. "PERIPH_200_RST,Reset Control value for peripheral PERIPH_200_RST" "0: No forced reset on PERIPH_200_RST,1: Forced Reset on PERIPH_200_RST"
newline
bitfld.long 0x00 7. "PERIPH_199_RST,Reset Control value for peripheral PERIPH_199_RST" "0: No forced reset on PERIPH_199_RST,1: Forced Reset on PERIPH_199_RST"
newline
bitfld.long 0x00 6. "PERIPH_198_RST,Reset Control value for peripheral PERIPH_198_RST" "0: No forced reset on PERIPH_198_RST,1: Forced Reset on PERIPH_198_RST"
newline
bitfld.long 0x00 5. "PERIPH_197_RST,Reset Control value for peripheral PERIPH_197_RST" "0: No forced reset on PERIPH_197_RST,1: Forced Reset on PERIPH_197_RST"
newline
bitfld.long 0x00 4. "PERIPH_196_RST,Reset Control value for peripheral PERIPH_196_RST" "0: No forced reset on PERIPH_196_RST,1: Forced Reset on PERIPH_196_RST"
newline
bitfld.long 0x00 3. "PERIPH_195_RST,Reset Control value for peripheral PERIPH_195_RST" "0: No forced reset on PERIPH_195_RST,1: Forced Reset on PERIPH_195_RST"
newline
bitfld.long 0x00 2. "PERIPH_194_RST,Reset Control value for peripheral PERIPH_194_RST" "0: No forced reset on PERIPH_194_RST,1: Forced Reset on PERIPH_194_RST"
newline
bitfld.long 0x00 1. "PERIPH_193_RST,Reset Control value for peripheral PERIPH_193_RST" "0: No forced reset on PERIPH_193_RST,1: Forced Reset on PERIPH_193_RST"
newline
bitfld.long 0x00 0. "PERIPH_192_RST,Reset Control value for peripheral RADAR_SS_RST" "0: No forced reset on RADAR_SS_RST,1: Forced Reset on RADAR_SS_RST"
group.long 0x5C++0x03
line.long 0x00 "PRST3_1,Peripheral Reset"
bitfld.long 0x00 31. "PERIPH_255_RST,Reset Control value for peripheral PERIPH_255_RST" "0: No forced reset on PERIPH_255_RST,1: Forced Reset on PERIPH_255_RST"
newline
bitfld.long 0x00 30. "PERIPH_254_RST,Reset Control value for peripheral PERIPH_254_RST" "0: No forced reset on PERIPH_254_RST,1: Forced Reset on PERIPH_254_RST"
newline
bitfld.long 0x00 29. "PERIPH_253_RST,Reset Control value for peripheral PERIPH_253_RST" "0: No forced reset on PERIPH_253_RST,1: Forced Reset on PERIPH_253_RST"
newline
bitfld.long 0x00 28. "PERIPH_252_RST,Reset Control value for peripheral PERIPH_252_RST" "0: No forced reset on PERIPH_252_RST,1: Forced Reset on PERIPH_252_RST"
newline
bitfld.long 0x00 27. "PERIPH_251_RST,Reset Control value for peripheral PERIPH_251_RST" "0: No forced reset on PERIPH_251_RST,1: Forced Reset on PERIPH_251_RST"
newline
bitfld.long 0x00 26. "PERIPH_250_RST,Reset Control value for peripheral PERIPH_250_RST" "0: No forced reset on PERIPH_250_RST,1: Forced Reset on PERIPH_250_RST"
newline
bitfld.long 0x00 25. "PERIPH_249_RST,Reset Control value for peripheral PERIPH_249_RST" "0: No forced reset on PERIPH_249_RST,1: Forced Reset on PERIPH_249_RST"
newline
bitfld.long 0x00 24. "PERIPH_248_RST,Reset Control value for peripheral PERIPH_248_RST" "0: No forced reset on PERIPH_248_RST,1: Forced Reset on PERIPH_248_RST"
newline
bitfld.long 0x00 23. "PERIPH_247_RST,Reset Control value for peripheral PERIPH_247_RST" "0: No forced reset on PERIPH_247_RST,1: Forced Reset on PERIPH_247_RST"
newline
bitfld.long 0x00 22. "PERIPH_246_RST,Reset Control value for peripheral PERIPH_246_RST" "0: No forced reset on PERIPH_246_RST,1: Forced Reset on PERIPH_246_RST"
newline
bitfld.long 0x00 21. "PERIPH_245_RST,Reset Control value for peripheral PERIPH_245_RST" "0: No forced reset on PERIPH_245_RST,1: Forced Reset on PERIPH_245_RST"
newline
bitfld.long 0x00 20. "PERIPH_244_RST,Reset Control value for peripheral PERIPH_244_RST" "0: No forced reset on PERIPH_244_RST,1: Forced Reset on PERIPH_244_RST"
newline
bitfld.long 0x00 19. "PERIPH_243_RST,Reset Control value for peripheral PERIPH_243_RST" "0: No forced reset on PERIPH_243_RST,1: Forced Reset on PERIPH_243_RST"
newline
bitfld.long 0x00 18. "PERIPH_242_RST,Reset Control value for peripheral PERIPH_242_RST" "0: No forced reset on PERIPH_242_RST,1: Forced Reset on PERIPH_242_RST"
newline
bitfld.long 0x00 17. "PERIPH_241_RST,Reset Control value for peripheral PERIPH_241_RST" "0: No forced reset on PERIPH_241_RST,1: Forced Reset on PERIPH_241_RST"
newline
bitfld.long 0x00 16. "PERIPH_240_RST,Reset Control value for peripheral PERIPH_240_RST" "0: No forced reset on PERIPH_240_RST,1: Forced Reset on PERIPH_240_RST"
newline
bitfld.long 0x00 15. "PERIPH_239_RST,Reset Control value for peripheral PERIPH_239_RST" "0: No forced reset on PERIPH_239_RST,1: Forced Reset on PERIPH_239_RST"
newline
bitfld.long 0x00 14. "PERIPH_238_RST,Reset Control value for peripheral PERIPH_238_RST" "0: No forced reset on PERIPH_238_RST,1: Forced Reset on PERIPH_238_RST"
newline
bitfld.long 0x00 13. "PERIPH_237_RST,Reset Control value for peripheral PERIPH_237_RST" "0: No forced reset on PERIPH_237_RST,1: Forced Reset on PERIPH_237_RST"
newline
bitfld.long 0x00 12. "PERIPH_236_RST,Reset Control value for peripheral PERIPH_236_RST" "0: No forced reset on PERIPH_236_RST,1: Forced Reset on PERIPH_236_RST"
newline
bitfld.long 0x00 11. "PERIPH_235_RST,Reset Control value for peripheral PERIPH_235_RST" "0: No forced reset on PERIPH_235_RST,1: Forced Reset on PERIPH_235_RST"
newline
bitfld.long 0x00 10. "PERIPH_234_RST,Reset Control value for peripheral PERIPH_234_RST" "0: No forced reset on PERIPH_234_RST,1: Forced Reset on PERIPH_234_RST"
newline
bitfld.long 0x00 9. "PERIPH_233_RST,Reset Control value for peripheral PERIPH_233_RST" "0: No forced reset on PERIPH_233_RST,1: Forced Reset on PERIPH_233_RST"
newline
bitfld.long 0x00 8. "PERIPH_232_RST,Reset Control value for peripheral PERIPH_232_RST" "0: No forced reset on PERIPH_232_RST,1: Forced Reset on PERIPH_232_RST"
newline
bitfld.long 0x00 7. "PERIPH_231_RST,Reset Control value for peripheral PERIPH_231_RST" "0: No forced reset on PERIPH_231_RST,1: Forced Reset on PERIPH_231_RST"
newline
bitfld.long 0x00 6. "PERIPH_230_RST,Reset Control value for peripheral PERIPH_230_RST" "0: No forced reset on PERIPH_230_RST,1: Forced Reset on PERIPH_230_RST"
newline
bitfld.long 0x00 5. "PERIPH_229_RST,Reset Control value for peripheral PERIPH_229_RST" "0: No forced reset on PERIPH_229_RST,1: Forced Reset on PERIPH_229_RST"
newline
bitfld.long 0x00 4. "PERIPH_228_RST,Reset Control value for peripheral PERIPH_228_RST" "0: No forced reset on PERIPH_228_RST,1: Forced Reset on PERIPH_228_RST"
newline
bitfld.long 0x00 3. "PERIPH_227_RST,Reset Control value for peripheral PERIPH_227_RST" "0: No forced reset on PERIPH_227_RST,1: Forced Reset on PERIPH_227_RST"
newline
bitfld.long 0x00 2. "PERIPH_226_RST,Reset Control value for peripheral PERIPH_226_RST" "0: No forced reset on PERIPH_226_RST,1: Forced Reset on PERIPH_226_RST"
newline
bitfld.long 0x00 1. "PERIPH_225_RST,Reset Control value for peripheral PERIPH_225_RST" "0: No forced reset on PERIPH_225_RST,1: Forced Reset on PERIPH_225_RST"
newline
bitfld.long 0x00 0. "PERIPH_224_RST,Reset Control value for peripheral PERIPH_224_RST" "0: No forced reset on PERIPH_224_RST,1: Forced Reset on PERIPH_224_RST"
group.long 0x60++0x03
line.long 0x00 "PRST4_0,Peripheral Reset"
bitfld.long 0x00 31. "PERIPH_287_RST,Reset Control value for peripheral PERIPH_287_RST" "0: No forced reset on PERIPH_287_RST,1: Forced Reset on PERIPH_287_RST"
newline
bitfld.long 0x00 30. "PERIPH_286_RST,Reset Control value for peripheral PERIPH_286_RST" "0: No forced reset on PERIPH_286_RST,1: Forced Reset on PERIPH_286_RST"
newline
bitfld.long 0x00 29. "PERIPH_285_RST,Reset Control value for peripheral PERIPH_285_RST" "0: No forced reset on PERIPH_285_RST,1: Forced Reset on PERIPH_285_RST"
newline
bitfld.long 0x00 28. "PERIPH_284_RST,Reset Control value for peripheral PERIPH_284_RST" "0: No forced reset on PERIPH_284_RST,1: Forced Reset on PERIPH_284_RST"
newline
bitfld.long 0x00 27. "PERIPH_283_RST,Reset Control value for peripheral PERIPH_283_RST" "0: No forced reset on PERIPH_283_RST,1: Forced Reset on PERIPH_283_RST"
newline
bitfld.long 0x00 26. "PERIPH_282_RST,Reset Control value for peripheral PERIPH_282_RST" "0: No forced reset on PERIPH_282_RST,1: Forced Reset on PERIPH_282_RST"
newline
bitfld.long 0x00 25. "PERIPH_281_RST,Reset Control value for peripheral PERIPH_281_RST" "0: No forced reset on PERIPH_281_RST,1: Forced Reset on PERIPH_281_RST"
newline
bitfld.long 0x00 24. "PERIPH_280_RST,Reset Control value for peripheral PERIPH_280_RST" "0: No forced reset on PERIPH_280_RST,1: Forced Reset on PERIPH_280_RST"
newline
bitfld.long 0x00 23. "PERIPH_279_RST,Reset Control value for peripheral PERIPH_279_RST" "0: No forced reset on PERIPH_279_RST,1: Forced Reset on PERIPH_279_RST"
newline
bitfld.long 0x00 22. "PERIPH_278_RST,Reset Control value for peripheral PERIPH_278_RST" "0: No forced reset on PERIPH_278_RST,1: Forced Reset on PERIPH_278_RST"
newline
bitfld.long 0x00 21. "PERIPH_277_RST,Reset Control value for peripheral PERIPH_277_RST" "0: No forced reset on PERIPH_277_RST,1: Forced Reset on PERIPH_277_RST"
newline
bitfld.long 0x00 20. "PERIPH_276_RST,Reset Control value for peripheral PERIPH_276_RST" "0: No forced reset on PERIPH_276_RST,1: Forced Reset on PERIPH_276_RST"
newline
bitfld.long 0x00 19. "PERIPH_275_RST,Reset Control value for peripheral PERIPH_275_RST" "0: No forced reset on PERIPH_275_RST,1: Forced Reset on PERIPH_275_RST"
newline
bitfld.long 0x00 18. "PERIPH_274_RST,Reset Control value for peripheral PERIPH_274_RST" "0: No forced reset on PERIPH_274_RST,1: Forced Reset on PERIPH_274_RST"
newline
bitfld.long 0x00 17. "PERIPH_273_RST,Reset Control value for peripheral PERIPH_273_RST" "0: No forced reset on PERIPH_273_RST,1: Forced Reset on PERIPH_273_RST"
newline
bitfld.long 0x00 16. "PERIPH_272_RST,Reset Control value for peripheral PERIPH_272_RST" "0: No forced reset on PERIPH_272_RST,1: Forced Reset on PERIPH_272_RST"
newline
bitfld.long 0x00 15. "PERIPH_271_RST,Reset Control value for peripheral PERIPH_271_RST" "0: No forced reset on PERIPH_271_RST,1: Forced Reset on PERIPH_271_RST"
newline
bitfld.long 0x00 14. "PERIPH_270_RST,Reset Control value for peripheral PERIPH_270_RST" "0: No forced reset on PERIPH_270_RST,1: Forced Reset on PERIPH_270_RST"
newline
bitfld.long 0x00 13. "PERIPH_269_RST,Reset Control value for peripheral PERIPH_269_RST" "0: No forced reset on PERIPH_269_RST,1: Forced Reset on PERIPH_269_RST"
newline
bitfld.long 0x00 12. "PERIPH_268_RST,Reset Control value for peripheral PERIPH_268_RST" "0: No forced reset on PERIPH_268_RST,1: Forced Reset on PERIPH_268_RST"
newline
bitfld.long 0x00 11. "PERIPH_267_RST,Reset Control value for peripheral PERIPH_267_RST" "0: No forced reset on PERIPH_267_RST,1: Forced Reset on PERIPH_267_RST"
newline
bitfld.long 0x00 10. "PERIPH_266_RST,Reset Control value for peripheral PERIPH_266_RST" "0: No forced reset on PERIPH_266_RST,1: Forced Reset on PERIPH_266_RST"
newline
bitfld.long 0x00 9. "PERIPH_265_RST,Reset Control value for peripheral PERIPH_265_RST" "0: No forced reset on PERIPH_265_RST,1: Forced Reset on PERIPH_265_RST"
newline
bitfld.long 0x00 8. "PERIPH_264_RST,Reset Control value for peripheral PERIPH_264_RST" "0: No forced reset on PERIPH_264_RST,1: Forced Reset on PERIPH_264_RST"
newline
bitfld.long 0x00 7. "PERIPH_263_RST,Reset Control value for peripheral PERIPH_263_RST" "0: No forced reset on PERIPH_263_RST,1: Forced Reset on PERIPH_263_RST"
newline
bitfld.long 0x00 6. "PERIPH_262_RST,Reset Control value for peripheral PERIPH_262_RST" "0: No forced reset on PERIPH_262_RST,1: Forced Reset on PERIPH_262_RST"
newline
bitfld.long 0x00 5. "PERIPH_261_RST,Reset Control value for peripheral PERIPH_261_RST" "0: No forced reset on PERIPH_261_RST,1: Forced Reset on PERIPH_261_RST"
newline
bitfld.long 0x00 4. "PERIPH_260_RST,Reset Control value for peripheral PERIPH_260_RST" "0: No forced reset on PERIPH_260_RST,1: Forced Reset on PERIPH_260_RST"
newline
bitfld.long 0x00 3. "PERIPH_259_RST,Reset Control value for peripheral PERIPH_259_RST" "0: No forced reset on PERIPH_259_RST,1: Forced Reset on PERIPH_259_RST"
newline
bitfld.long 0x00 2. "PERIPH_258_RST,Reset Control value for peripheral PERIPH_258_RST" "0: No forced reset on PERIPH_258_RST,1: Forced Reset on PERIPH_258_RST"
newline
bitfld.long 0x00 1. "PERIPH_257_RST,Reset Control value for peripheral PERIPH_257_RST" "0: No forced reset on PERIPH_257_RST,1: Forced Reset on PERIPH_257_RST"
newline
bitfld.long 0x00 0. "PERIPH_256_RST,Reset Control value for peripheral PERIPH_256_RST" "0: No forced reset on PERIPH_256_RST,1: Forced Reset on PERIPH_256_RST"
group.long 0x64++0x03
line.long 0x00 "PRST4_1,Peripheral Reset"
bitfld.long 0x00 31. "PERIPH_319_RST,Reset Control value for peripheral PERIPH_319_RST" "0: No forced reset on PERIPH_319_RST,1: Forced Reset on PERIPH_319_RST"
newline
bitfld.long 0x00 30. "PERIPH_318_RST,Reset Control value for peripheral PERIPH_318_RST" "0: No forced reset on PERIPH_318_RST,1: Forced Reset on PERIPH_318_RST"
newline
bitfld.long 0x00 29. "PERIPH_317_RST,Reset Control value for peripheral PERIPH_317_RST" "0: No forced reset on PERIPH_317_RST,1: Forced Reset on PERIPH_317_RST"
newline
bitfld.long 0x00 28. "PERIPH_316_RST,Reset Control value for peripheral PERIPH_316_RST" "0: No forced reset on PERIPH_316_RST,1: Forced Reset on PERIPH_316_RST"
newline
bitfld.long 0x00 27. "PERIPH_315_RST,Reset Control value for peripheral PERIPH_315_RST" "0: No forced reset on PERIPH_315_RST,1: Forced Reset on PERIPH_315_RST"
newline
bitfld.long 0x00 26. "PERIPH_314_RST,Reset Control value for peripheral PERIPH_314_RST" "0: No forced reset on PERIPH_314_RST,1: Forced Reset on PERIPH_314_RST"
newline
bitfld.long 0x00 25. "PERIPH_313_RST,Reset Control value for peripheral PERIPH_313_RST" "0: No forced reset on PERIPH_313_RST,1: Forced Reset on PERIPH_313_RST"
newline
bitfld.long 0x00 24. "PERIPH_312_RST,Reset Control value for peripheral PERIPH_312_RST" "0: No forced reset on PERIPH_312_RST,1: Forced Reset on PERIPH_312_RST"
newline
bitfld.long 0x00 23. "PERIPH_311_RST,Reset Control value for peripheral PERIPH_311_RST" "0: No forced reset on PERIPH_311_RST,1: Forced Reset on PERIPH_311_RST"
newline
bitfld.long 0x00 22. "PERIPH_310_RST,Reset Control value for peripheral PERIPH_310_RST" "0: No forced reset on PERIPH_310_RST,1: Forced Reset on PERIPH_310_RST"
newline
bitfld.long 0x00 21. "PERIPH_309_RST,Reset Control value for peripheral PERIPH_309_RST" "0: No forced reset on PERIPH_309_RST,1: Forced Reset on PERIPH_309_RST"
newline
bitfld.long 0x00 20. "PERIPH_308_RST,Reset Control value for peripheral PERIPH_308_RST" "0: No forced reset on PERIPH_308_RST,1: Forced Reset on PERIPH_308_RST"
newline
bitfld.long 0x00 19. "PERIPH_307_RST,Reset Control value for peripheral PERIPH_307_RST" "0: No forced reset on PERIPH_307_RST,1: Forced Reset on PERIPH_307_RST"
newline
bitfld.long 0x00 18. "PERIPH_306_RST,Reset Control value for peripheral PERIPH_306_RST" "0: No forced reset on PERIPH_306_RST,1: Forced Reset on PERIPH_306_RST"
newline
bitfld.long 0x00 17. "PERIPH_305_RST,Reset Control value for peripheral PERIPH_305_RST" "0: No forced reset on PERIPH_305_RST,1: Forced Reset on PERIPH_305_RST"
newline
bitfld.long 0x00 16. "PERIPH_304_RST,Reset Control value for peripheral PERIPH_304_RST" "0: No forced reset on PERIPH_304_RST,1: Forced Reset on PERIPH_304_RST"
newline
bitfld.long 0x00 15. "PERIPH_303_RST,Reset Control value for peripheral PERIPH_303_RST" "0: No forced reset on PERIPH_303_RST,1: Forced Reset on PERIPH_303_RST"
newline
bitfld.long 0x00 14. "PERIPH_302_RST,Reset Control value for peripheral PERIPH_302_RST" "0: No forced reset on PERIPH_302_RST,1: Forced Reset on PERIPH_302_RST"
newline
bitfld.long 0x00 13. "PERIPH_301_RST,Reset Control value for peripheral PERIPH_301_RST" "0: No forced reset on PERIPH_301_RST,1: Forced Reset on PERIPH_301_RST"
newline
bitfld.long 0x00 12. "PERIPH_300_RST,Reset Control value for peripheral PERIPH_300_RST" "0: No forced reset on PERIPH_300_RST,1: Forced Reset on PERIPH_300_RST"
newline
bitfld.long 0x00 11. "PERIPH_299_RST,Reset Control value for peripheral PERIPH_299_RST" "0: No forced reset on PERIPH_299_RST,1: Forced Reset on PERIPH_299_RST"
newline
bitfld.long 0x00 10. "PERIPH_298_RST,Reset Control value for peripheral PERIPH_298_RST" "0: No forced reset on PERIPH_298_RST,1: Forced Reset on PERIPH_298_RST"
newline
bitfld.long 0x00 9. "PERIPH_297_RST,Reset Control value for peripheral PERIPH_297_RST" "0: No forced reset on PERIPH_297_RST,1: Forced Reset on PERIPH_297_RST"
newline
bitfld.long 0x00 8. "PERIPH_296_RST,Reset Control value for peripheral PERIPH_296_RST" "0: No forced reset on PERIPH_296_RST,1: Forced Reset on PERIPH_296_RST"
newline
bitfld.long 0x00 7. "PERIPH_295_RST,Reset Control value for peripheral PERIPH_295_RST" "0: No forced reset on PERIPH_295_RST,1: Forced Reset on PERIPH_295_RST"
newline
bitfld.long 0x00 6. "PERIPH_294_RST,Reset Control value for peripheral PERIPH_294_RST" "0: No forced reset on PERIPH_294_RST,1: Forced Reset on PERIPH_294_RST"
newline
bitfld.long 0x00 5. "PERIPH_293_RST,Reset Control value for peripheral PERIPH_293_RST" "0: No forced reset on PERIPH_293_RST,1: Forced Reset on PERIPH_293_RST"
newline
bitfld.long 0x00 4. "PERIPH_292_RST,Reset Control value for peripheral PERIPH_292_RST" "0: No forced reset on PERIPH_292_RST,1: Forced Reset on PERIPH_292_RST"
newline
bitfld.long 0x00 3. "PERIPH_291_RST,Reset Control value for peripheral PERIPH_291_RST" "0: No forced reset on PERIPH_291_RST,1: Forced Reset on PERIPH_291_RST"
newline
bitfld.long 0x00 2. "PERIPH_290_RST,Reset Control value for peripheral PERIPH_290_RST" "0: No forced reset on PERIPH_290_RST,1: Forced Reset on PERIPH_290_RST"
newline
bitfld.long 0x00 1. "PERIPH_289_RST,Reset Control value for peripheral PERIPH_289_RST" "0: No forced reset on PERIPH_289_RST,1: Forced Reset on PERIPH_289_RST"
newline
bitfld.long 0x00 0. "PERIPH_288_RST,Reset Control value for peripheral PERIPH_288_RST" "0: No forced reset on PERIPH_288_RST,1: Forced Reset on PERIPH_288_RST"
rgroup.long 0x140++0x03
line.long 0x00 "PSTAT0_0,Peripheral Reset Status Register"
bitfld.long 0x00 31. "PERIPH_31_STAT,Reset Status for peripheral PERIPH_31_STAT" "0: Peripheral PERIPH_31_STAT is not in reset,1: Peripheral PERIPH_31_STAT is in reset"
newline
bitfld.long 0x00 30. "PERIPH_30_STAT,Reset Status for peripheral PERIPH_30_STAT" "0: Peripheral PERIPH_30_STAT is not in reset,1: Peripheral PERIPH_30_STAT is in reset"
newline
bitfld.long 0x00 29. "PERIPH_29_STAT,Reset Status for peripheral PERIPH_29_STAT" "0: Peripheral PERIPH_29_STAT is not in reset,1: Peripheral PERIPH_29_STAT is in reset"
newline
bitfld.long 0x00 28. "PERIPH_28_STAT,Reset Status for peripheral PERIPH_28_STAT" "0: Peripheral PERIPH_28_STAT is not in reset,1: Peripheral PERIPH_28_STAT is in reset"
newline
bitfld.long 0x00 27. "PERIPH_27_STAT,Reset Status for peripheral PERIPH_27_STAT" "0: Peripheral PERIPH_27_STAT is not in reset,1: Peripheral PERIPH_27_STAT is in reset"
newline
bitfld.long 0x00 26. "PERIPH_26_STAT,Reset Status for peripheral PERIPH_26_STAT" "0: Peripheral PERIPH_26_STAT is not in reset,1: Peripheral PERIPH_26_STAT is in reset"
newline
bitfld.long 0x00 25. "PERIPH_25_STAT,Reset Status for peripheral PERIPH_25_STAT" "0: Peripheral PERIPH_25_STAT is not in reset,1: Peripheral PERIPH_25_STAT is in reset"
newline
bitfld.long 0x00 24. "PERIPH_24_STAT,Reset Status for peripheral PERIPH_24_STAT" "0: Peripheral PERIPH_24_STAT is not in reset,1: Peripheral PERIPH_24_STAT is in reset"
newline
bitfld.long 0x00 23. "PERIPH_23_STAT,Reset Status for peripheral PERIPH_23_STAT" "0: Peripheral PERIPH_23_STAT is not in reset,1: Peripheral PERIPH_23_STAT is in reset"
newline
bitfld.long 0x00 22. "PERIPH_22_STAT,Reset Status for peripheral PERIPH_22_STAT" "0: Peripheral PERIPH_22_STAT is not in reset,1: Peripheral PERIPH_22_STAT is in reset"
newline
bitfld.long 0x00 21. "PERIPH_21_STAT,Reset Status for peripheral PERIPH_21_STAT" "0: Peripheral PERIPH_21_STAT is not in reset,1: Peripheral PERIPH_21_STAT is in reset"
newline
bitfld.long 0x00 20. "PERIPH_20_STAT,Reset Status for peripheral PERIPH_20_STAT" "0: Peripheral PERIPH_20_STAT is not in reset,1: Peripheral PERIPH_20_STAT is in reset"
newline
bitfld.long 0x00 19. "PERIPH_19_STAT,Reset Status for peripheral PERIPH_19_STAT" "0: Peripheral PERIPH_19_STAT is not in reset,1: Peripheral PERIPH_19_STAT is in reset"
newline
bitfld.long 0x00 18. "PERIPH_18_STAT,Reset Status for peripheral PERIPH_18_STAT" "0: Peripheral PERIPH_18_STAT is not in reset,1: Peripheral PERIPH_18_STAT is in reset"
newline
bitfld.long 0x00 17. "PERIPH_17_STAT,Reset Status for peripheral PERIPH_17_STAT" "0: Peripheral PERIPH_17_STAT is not in reset,1: Peripheral PERIPH_17_STAT is in reset"
newline
bitfld.long 0x00 16. "PERIPH_16_STAT,Reset Status for peripheral PERIPH_16_STAT" "0: Peripheral PERIPH_16_STAT is not in reset,1: Peripheral PERIPH_16_STAT is in reset"
newline
bitfld.long 0x00 15. "PERIPH_15_STAT,Reset Status for peripheral PERIPH_15_STAT" "0: Peripheral PERIPH_15_STAT is not in reset,1: Peripheral PERIPH_15_STAT is in reset"
newline
bitfld.long 0x00 14. "PERIPH_14_STAT,Reset Status for peripheral PERIPH_14_STAT" "0: Peripheral PERIPH_14_STAT is not in reset,1: Peripheral PERIPH_14_STAT is in reset"
newline
bitfld.long 0x00 13. "PERIPH_13_STAT,Reset Status for peripheral PERIPH_13_STAT" "0: Peripheral PERIPH_13_STAT is not in reset,1: Peripheral PERIPH_13_STAT is in reset"
newline
bitfld.long 0x00 12. "PERIPH_12_STAT,Reset Status for peripheral PERIPH_12_STAT" "0: Peripheral PERIPH_12_STAT is not in reset,1: Peripheral PERIPH_12_STAT is in reset"
newline
bitfld.long 0x00 11. "PERIPH_11_STAT,Reset Status for peripheral PERIPH_11_STAT" "0: Peripheral PERIPH_11_STAT is not in reset,1: Peripheral PERIPH_11_STAT is in reset"
newline
bitfld.long 0x00 10. "PERIPH_10_STAT,Reset Status for peripheral PERIPH_10_STAT" "0: Peripheral PERIPH_10_STAT is not in reset,1: Peripheral PERIPH_10_STAT is in reset"
newline
bitfld.long 0x00 9. "PERIPH_9_STAT,Reset Status for peripheral PERIPH_9_STAT" "0: Peripheral PERIPH_9_STAT is not in reset,1: Peripheral PERIPH_9_STAT is in reset"
newline
bitfld.long 0x00 8. "PERIPH_8_STAT,Reset Status for peripheral PERIPH_8_STAT" "0: Peripheral PERIPH_8_STAT is not in reset,1: Peripheral PERIPH_8_STAT is in reset"
newline
bitfld.long 0x00 7. "PERIPH_7_STAT,Reset Status for peripheral PERIPH_7_STAT" "0: Peripheral PERIPH_7_STAT is not in reset,1: Peripheral PERIPH_7_STAT is in reset"
newline
bitfld.long 0x00 6. "PERIPH_6_STAT,Reset Status for peripheral PERIPH_6_STAT" "0: Peripheral PERIPH_6_STAT is not in reset,1: Peripheral PERIPH_6_STAT is in reset"
newline
bitfld.long 0x00 5. "PERIPH_5_STAT,Reset Status for peripheral PERIPH_5_STAT" "0: Peripheral PERIPH_5_STAT is not in reset,1: Peripheral PERIPH_5_STAT is in reset"
newline
bitfld.long 0x00 4. "PERIPH_4_STAT,Reset Status for peripheral PERIPH_4_STAT" "0: Peripheral PERIPH_4_STAT is not in reset,1: Peripheral PERIPH_4_STAT is in reset"
newline
bitfld.long 0x00 3. "PERIPH_3_STAT,Reset Status for peripheral PERIPH_3_STAT" "0: Peripheral PERIPH_3_STAT is not in reset,1: Peripheral PERIPH_3_STAT is in reset"
newline
bitfld.long 0x00 2. "PERIPH_2_STAT,Reset Status for peripheral PERIPH_2_STAT" "0: Peripheral PERIPH_2_STAT is not in reset,1: Peripheral PERIPH_2_STAT is in reset"
newline
bitfld.long 0x00 1. "PERIPH_1_STAT,Reset Status for peripheral CM7_Cluster_1_STAT" "0: Peripheral CM7_Cluster_1_STAT is not in reset,1: Peripheral CM7_Cluster_1_STAT is in reset"
newline
bitfld.long 0x00 0. "PERIPH_0_STAT,Reset Status for peripheral CM7_Cluster_0_STAT" "0: Peripheral CM7_Cluster_0_STAT is not in reset,1: Peripheral CM7_Cluster_0_STAT is in reset"
rgroup.long 0x144++0x03
line.long 0x00 "PSTAT0_1,Peripheral Reset Status Register"
bitfld.long 0x00 31. "PERIPH_63_STAT,Reset Status for peripheral PERIPH_63_STAT" "0: Peripheral PERIPH_63_STAT is not in reset,1: Peripheral PERIPH_63_STAT is in reset"
newline
bitfld.long 0x00 30. "PERIPH_62_STAT,Reset Status for peripheral PERIPH_62_STAT" "0: Peripheral PERIPH_62_STAT is not in reset,1: Peripheral PERIPH_62_STAT is in reset"
newline
bitfld.long 0x00 29. "PERIPH_61_STAT,Reset Status for peripheral PERIPH_61_STAT" "0: Peripheral PERIPH_61_STAT is not in reset,1: Peripheral PERIPH_61_STAT is in reset"
newline
bitfld.long 0x00 28. "PERIPH_60_STAT,Reset Status for peripheral PERIPH_60_STAT" "0: Peripheral PERIPH_60_STAT is not in reset,1: Peripheral PERIPH_60_STAT is in reset"
newline
bitfld.long 0x00 27. "PERIPH_59_STAT,Reset Status for peripheral PERIPH_59_STAT" "0: Peripheral PERIPH_59_STAT is not in reset,1: Peripheral PERIPH_59_STAT is in reset"
newline
bitfld.long 0x00 26. "PERIPH_58_STAT,Reset Status for peripheral PERIPH_58_STAT" "0: Peripheral PERIPH_58_STAT is not in reset,1: Peripheral PERIPH_58_STAT is in reset"
newline
bitfld.long 0x00 25. "PERIPH_57_STAT,Reset Status for peripheral PERIPH_57_STAT" "0: Peripheral PERIPH_57_STAT is not in reset,1: Peripheral PERIPH_57_STAT is in reset"
newline
bitfld.long 0x00 24. "PERIPH_56_STAT,Reset Status for peripheral PERIPH_56_STAT" "0: Peripheral PERIPH_56_STAT is not in reset,1: Peripheral PERIPH_56_STAT is in reset"
newline
bitfld.long 0x00 23. "PERIPH_55_STAT,Reset Status for peripheral PERIPH_55_STAT" "0: Peripheral PERIPH_55_STAT is not in reset,1: Peripheral PERIPH_55_STAT is in reset"
newline
bitfld.long 0x00 22. "PERIPH_54_STAT,Reset Status for peripheral PERIPH_54_STAT" "0: Peripheral PERIPH_54_STAT is not in reset,1: Peripheral PERIPH_54_STAT is in reset"
newline
bitfld.long 0x00 21. "PERIPH_53_STAT,Reset Status for peripheral PERIPH_53_STAT" "0: Peripheral PERIPH_53_STAT is not in reset,1: Peripheral PERIPH_53_STAT is in reset"
newline
bitfld.long 0x00 20. "PERIPH_52_STAT,Reset Status for peripheral PERIPH_52_STAT" "0: Peripheral PERIPH_52_STAT is not in reset,1: Peripheral PERIPH_52_STAT is in reset"
newline
bitfld.long 0x00 19. "PERIPH_51_STAT,Reset Status for peripheral PERIPH_51_STAT" "0: Peripheral PERIPH_51_STAT is not in reset,1: Peripheral PERIPH_51_STAT is in reset"
newline
bitfld.long 0x00 18. "PERIPH_50_STAT,Reset Status for peripheral PERIPH_50_STAT" "0: Peripheral PERIPH_50_STAT is not in reset,1: Peripheral PERIPH_50_STAT is in reset"
newline
bitfld.long 0x00 17. "PERIPH_49_STAT,Reset Status for peripheral PERIPH_49_STAT" "0: Peripheral PERIPH_49_STAT is not in reset,1: Peripheral PERIPH_49_STAT is in reset"
newline
bitfld.long 0x00 16. "PERIPH_48_STAT,Reset Status for peripheral PERIPH_48_STAT" "0: Peripheral PERIPH_48_STAT is not in reset,1: Peripheral PERIPH_48_STAT is in reset"
newline
bitfld.long 0x00 15. "PERIPH_47_STAT,Reset Status for peripheral PERIPH_47_STAT" "0: Peripheral PERIPH_47_STAT is not in reset,1: Peripheral PERIPH_47_STAT is in reset"
newline
bitfld.long 0x00 14. "PERIPH_46_STAT,Reset Status for peripheral PERIPH_46_STAT" "0: Peripheral PERIPH_46_STAT is not in reset,1: Peripheral PERIPH_46_STAT is in reset"
newline
bitfld.long 0x00 13. "PERIPH_45_STAT,Reset Status for peripheral PERIPH_45_STAT" "0: Peripheral PERIPH_45_STAT is not in reset,1: Peripheral PERIPH_45_STAT is in reset"
newline
bitfld.long 0x00 12. "PERIPH_44_STAT,Reset Status for peripheral PERIPH_44_STAT" "0: Peripheral PERIPH_44_STAT is not in reset,1: Peripheral PERIPH_44_STAT is in reset"
newline
bitfld.long 0x00 11. "PERIPH_43_STAT,Reset Status for peripheral PERIPH_43_STAT" "0: Peripheral PERIPH_43_STAT is not in reset,1: Peripheral PERIPH_43_STAT is in reset"
newline
bitfld.long 0x00 10. "PERIPH_42_STAT,Reset Status for peripheral PERIPH_42_STAT" "0: Peripheral PERIPH_42_STAT is not in reset,1: Peripheral PERIPH_42_STAT is in reset"
newline
bitfld.long 0x00 9. "PERIPH_41_STAT,Reset Status for peripheral PERIPH_41_STAT" "0: Peripheral PERIPH_41_STAT is not in reset,1: Peripheral PERIPH_41_STAT is in reset"
newline
bitfld.long 0x00 8. "PERIPH_40_STAT,Reset Status for peripheral PERIPH_40_STAT" "0: Peripheral PERIPH_40_STAT is not in reset,1: Peripheral PERIPH_40_STAT is in reset"
newline
bitfld.long 0x00 7. "PERIPH_39_STAT,Reset Status for peripheral PERIPH_39_STAT" "0: Peripheral PERIPH_39_STAT is not in reset,1: Peripheral PERIPH_39_STAT is in reset"
newline
bitfld.long 0x00 6. "PERIPH_38_STAT,Reset Status for peripheral PERIPH_38_STAT" "0: Peripheral PERIPH_38_STAT is not in reset,1: Peripheral PERIPH_38_STAT is in reset"
newline
bitfld.long 0x00 5. "PERIPH_37_STAT,Reset Status for peripheral PERIPH_37_STAT" "0: Peripheral PERIPH_37_STAT is not in reset,1: Peripheral PERIPH_37_STAT is in reset"
newline
bitfld.long 0x00 4. "PERIPH_36_STAT,Reset Status for peripheral PERIPH_36_STAT" "0: Peripheral PERIPH_36_STAT is not in reset,1: Peripheral PERIPH_36_STAT is in reset"
newline
bitfld.long 0x00 3. "PERIPH_35_STAT,Reset Status for peripheral PERIPH_35_STAT" "0: Peripheral PERIPH_35_STAT is not in reset,1: Peripheral PERIPH_35_STAT is in reset"
newline
bitfld.long 0x00 2. "PERIPH_34_STAT,Reset Status for peripheral PERIPH_34_STAT" "0: Peripheral PERIPH_34_STAT is not in reset,1: Peripheral PERIPH_34_STAT is in reset"
newline
bitfld.long 0x00 1. "PERIPH_33_STAT,Reset Status for peripheral PERIPH_33_STAT" "0: Peripheral PERIPH_33_STAT is not in reset,1: Peripheral PERIPH_33_STAT is in reset"
newline
bitfld.long 0x00 0. "PERIPH_32_STAT,Reset Status for peripheral PERIPH_32_STAT" "0: Peripheral PERIPH_32_STAT is not in reset,1: Peripheral PERIPH_32_STAT is in reset"
rgroup.long 0x148++0x03
line.long 0x00 "PSTAT1_0,Peripheral Reset Status Register"
bitfld.long 0x00 31. "PERIPH_95_STAT,Reset Status for peripheral PERIPH_95_STAT" "0: Peripheral PERIPH_95_STAT is not in reset,1: Peripheral PERIPH_95_STAT is in reset"
newline
bitfld.long 0x00 30. "PERIPH_94_STAT,Reset Status for peripheral PERIPH_94_STAT" "0: Peripheral PERIPH_94_STAT is not in reset,1: Peripheral PERIPH_94_STAT is in reset"
newline
bitfld.long 0x00 29. "PERIPH_93_STAT,Reset Status for peripheral PERIPH_93_STAT" "0: Peripheral PERIPH_93_STAT is not in reset,1: Peripheral PERIPH_93_STAT is in reset"
newline
bitfld.long 0x00 28. "PERIPH_92_STAT,Reset Status for peripheral PERIPH_92_STAT" "0: Peripheral PERIPH_92_STAT is not in reset,1: Peripheral PERIPH_92_STAT is in reset"
newline
bitfld.long 0x00 27. "PERIPH_91_STAT,Reset Status for peripheral PERIPH_91_STAT" "0: Peripheral PERIPH_91_STAT is not in reset,1: Peripheral PERIPH_91_STAT is in reset"
newline
bitfld.long 0x00 26. "PERIPH_90_STAT,Reset Status for peripheral PERIPH_90_STAT" "0: Peripheral PERIPH_90_STAT is not in reset,1: Peripheral PERIPH_90_STAT is in reset"
newline
bitfld.long 0x00 25. "PERIPH_89_STAT,Reset Status for peripheral PERIPH_89_STAT" "0: Peripheral PERIPH_89_STAT is not in reset,1: Peripheral PERIPH_89_STAT is in reset"
newline
bitfld.long 0x00 24. "PERIPH_88_STAT,Reset Status for peripheral PERIPH_88_STAT" "0: Peripheral PERIPH_88_STAT is not in reset,1: Peripheral PERIPH_88_STAT is in reset"
newline
bitfld.long 0x00 23. "PERIPH_87_STAT,Reset Status for peripheral PERIPH_87_STAT" "0: Peripheral PERIPH_87_STAT is not in reset,1: Peripheral PERIPH_87_STAT is in reset"
newline
bitfld.long 0x00 22. "PERIPH_86_STAT,Reset Status for peripheral PERIPH_86_STAT" "0: Peripheral PERIPH_86_STAT is not in reset,1: Peripheral PERIPH_86_STAT is in reset"
newline
bitfld.long 0x00 21. "PERIPH_85_STAT,Reset Status for peripheral PERIPH_85_STAT" "0: Peripheral PERIPH_85_STAT is not in reset,1: Peripheral PERIPH_85_STAT is in reset"
newline
bitfld.long 0x00 20. "PERIPH_84_STAT,Reset Status for peripheral PERIPH_84_STAT" "0: Peripheral PERIPH_84_STAT is not in reset,1: Peripheral PERIPH_84_STAT is in reset"
newline
bitfld.long 0x00 19. "PERIPH_83_STAT,Reset Status for peripheral PERIPH_83_STAT" "0: Peripheral PERIPH_83_STAT is not in reset,1: Peripheral PERIPH_83_STAT is in reset"
newline
bitfld.long 0x00 18. "PERIPH_82_STAT,Reset Status for peripheral PERIPH_82_STAT" "0: Peripheral PERIPH_82_STAT is not in reset,1: Peripheral PERIPH_82_STAT is in reset"
newline
bitfld.long 0x00 17. "PERIPH_81_STAT,Reset Status for peripheral PERIPH_81_STAT" "0: Peripheral PERIPH_81_STAT is not in reset,1: Peripheral PERIPH_81_STAT is in reset"
newline
bitfld.long 0x00 16. "PERIPH_80_STAT,Reset Status for peripheral PERIPH_80_STAT" "0: Peripheral PERIPH_80_STAT is not in reset,1: Peripheral PERIPH_80_STAT is in reset"
newline
bitfld.long 0x00 15. "PERIPH_79_STAT,Reset Status for peripheral PERIPH_79_STAT" "0: Peripheral PERIPH_79_STAT is not in reset,1: Peripheral PERIPH_79_STAT is in reset"
newline
bitfld.long 0x00 14. "PERIPH_78_STAT,Reset Status for peripheral PERIPH_78_STAT" "0: Peripheral PERIPH_78_STAT is not in reset,1: Peripheral PERIPH_78_STAT is in reset"
newline
bitfld.long 0x00 13. "PERIPH_77_STAT,Reset Status for peripheral PERIPH_77_STAT" "0: Peripheral PERIPH_77_STAT is not in reset,1: Peripheral PERIPH_77_STAT is in reset"
newline
bitfld.long 0x00 12. "PERIPH_76_STAT,Reset Status for peripheral PERIPH_76_STAT" "0: Peripheral PERIPH_76_STAT is not in reset,1: Peripheral PERIPH_76_STAT is in reset"
newline
bitfld.long 0x00 11. "PERIPH_75_STAT,Reset Status for peripheral PERIPH_75_STAT" "0: Peripheral PERIPH_75_STAT is not in reset,1: Peripheral PERIPH_75_STAT is in reset"
newline
bitfld.long 0x00 10. "PERIPH_74_STAT,Reset Status for peripheral PERIPH_74_STAT" "0: Peripheral PERIPH_74_STAT is not in reset,1: Peripheral PERIPH_74_STAT is in reset"
newline
bitfld.long 0x00 9. "PERIPH_73_STAT,Reset Status for peripheral PERIPH_73_STAT" "0: Peripheral PERIPH_73_STAT is not in reset,1: Peripheral PERIPH_73_STAT is in reset"
newline
bitfld.long 0x00 8. "PERIPH_72_STAT,Reset Status for peripheral PERIPH_72_STAT" "0: Peripheral PERIPH_72_STAT is not in reset,1: Peripheral PERIPH_72_STAT is in reset"
newline
bitfld.long 0x00 7. "PERIPH_71_STAT,Reset Status for peripheral PERIPH_71_STAT" "0: Peripheral PERIPH_71_STAT is not in reset,1: Peripheral PERIPH_71_STAT is in reset"
newline
bitfld.long 0x00 6. "PERIPH_70_STAT,Reset Status for peripheral PERIPH_70_STAT" "0: Peripheral PERIPH_70_STAT is not in reset,1: Peripheral PERIPH_70_STAT is in reset"
newline
bitfld.long 0x00 5. "PERIPH_69_STAT,Reset Status for peripheral PERIPH_69_STAT" "0: Peripheral PERIPH_69_STAT is not in reset,1: Peripheral PERIPH_69_STAT is in reset"
newline
bitfld.long 0x00 4. "PERIPH_68_STAT,Reset Status for peripheral PERIPH_68_STAT" "0: Peripheral PERIPH_68_STAT is not in reset,1: Peripheral PERIPH_68_STAT is in reset"
newline
bitfld.long 0x00 3. "PERIPH_67_STAT,Reset Status for peripheral PERIPH_67_STAT" "0: Peripheral PERIPH_67_STAT is not in reset,1: Peripheral PERIPH_67_STAT is in reset"
newline
bitfld.long 0x00 2. "PERIPH_66_STAT,Reset Status for peripheral PERIPH_66_STAT" "0: Peripheral PERIPH_66_STAT is not in reset,1: Peripheral PERIPH_66_STAT is in reset"
newline
bitfld.long 0x00 1. "PERIPH_65_STAT,Reset Status for peripheral CA53_CORE_0_STAT" "0: Peripheral CA53_CORE_0_STAT is not in reset,1: Peripheral CA53_CORE_0_STAT is in reset"
newline
bitfld.long 0x00 0. "PERIPH_64_STAT,Reset Status for peripheral A53_Cluster_STAT" "0: Peripheral A53_Cluster_STAT is not in reset,1: Peripheral A53_Cluster_STAT is in reset"
rgroup.long 0x14C++0x03
line.long 0x00 "PSTAT1_1,Peripheral Reset Status Register"
bitfld.long 0x00 31. "PERIPH_127_STAT,Reset Status for peripheral PERIPH_127_STAT" "0: Peripheral PERIPH_127_STAT is not in reset,1: Peripheral PERIPH_127_STAT is in reset"
newline
bitfld.long 0x00 30. "PERIPH_126_STAT,Reset Status for peripheral PERIPH_126_STAT" "0: Peripheral PERIPH_126_STAT is not in reset,1: Peripheral PERIPH_126_STAT is in reset"
newline
bitfld.long 0x00 29. "PERIPH_125_STAT,Reset Status for peripheral PERIPH_125_STAT" "0: Peripheral PERIPH_125_STAT is not in reset,1: Peripheral PERIPH_125_STAT is in reset"
newline
bitfld.long 0x00 28. "PERIPH_124_STAT,Reset Status for peripheral PERIPH_124_STAT" "0: Peripheral PERIPH_124_STAT is not in reset,1: Peripheral PERIPH_124_STAT is in reset"
newline
bitfld.long 0x00 27. "PERIPH_123_STAT,Reset Status for peripheral PERIPH_123_STAT" "0: Peripheral PERIPH_123_STAT is not in reset,1: Peripheral PERIPH_123_STAT is in reset"
newline
bitfld.long 0x00 26. "PERIPH_122_STAT,Reset Status for peripheral PERIPH_122_STAT" "0: Peripheral PERIPH_122_STAT is not in reset,1: Peripheral PERIPH_122_STAT is in reset"
newline
bitfld.long 0x00 25. "PERIPH_121_STAT,Reset Status for peripheral PERIPH_121_STAT" "0: Peripheral PERIPH_121_STAT is not in reset,1: Peripheral PERIPH_121_STAT is in reset"
newline
bitfld.long 0x00 24. "PERIPH_120_STAT,Reset Status for peripheral PERIPH_120_STAT" "0: Peripheral PERIPH_120_STAT is not in reset,1: Peripheral PERIPH_120_STAT is in reset"
newline
bitfld.long 0x00 23. "PERIPH_119_STAT,Reset Status for peripheral PERIPH_119_STAT" "0: Peripheral PERIPH_119_STAT is not in reset,1: Peripheral PERIPH_119_STAT is in reset"
newline
bitfld.long 0x00 22. "PERIPH_118_STAT,Reset Status for peripheral PERIPH_118_STAT" "0: Peripheral PERIPH_118_STAT is not in reset,1: Peripheral PERIPH_118_STAT is in reset"
newline
bitfld.long 0x00 21. "PERIPH_117_STAT,Reset Status for peripheral PERIPH_117_STAT" "0: Peripheral PERIPH_117_STAT is not in reset,1: Peripheral PERIPH_117_STAT is in reset"
newline
bitfld.long 0x00 20. "PERIPH_116_STAT,Reset Status for peripheral PERIPH_116_STAT" "0: Peripheral PERIPH_116_STAT is not in reset,1: Peripheral PERIPH_116_STAT is in reset"
newline
bitfld.long 0x00 19. "PERIPH_115_STAT,Reset Status for peripheral PERIPH_115_STAT" "0: Peripheral PERIPH_115_STAT is not in reset,1: Peripheral PERIPH_115_STAT is in reset"
newline
bitfld.long 0x00 18. "PERIPH_114_STAT,Reset Status for peripheral PERIPH_114_STAT" "0: Peripheral PERIPH_114_STAT is not in reset,1: Peripheral PERIPH_114_STAT is in reset"
newline
bitfld.long 0x00 17. "PERIPH_113_STAT,Reset Status for peripheral PERIPH_113_STAT" "0: Peripheral PERIPH_113_STAT is not in reset,1: Peripheral PERIPH_113_STAT is in reset"
newline
bitfld.long 0x00 16. "PERIPH_112_STAT,Reset Status for peripheral PERIPH_112_STAT" "0: Peripheral PERIPH_112_STAT is not in reset,1: Peripheral PERIPH_112_STAT is in reset"
newline
bitfld.long 0x00 15. "PERIPH_111_STAT,Reset Status for peripheral PERIPH_111_STAT" "0: Peripheral PERIPH_111_STAT is not in reset,1: Peripheral PERIPH_111_STAT is in reset"
newline
bitfld.long 0x00 14. "PERIPH_110_STAT,Reset Status for peripheral PERIPH_110_STAT" "0: Peripheral PERIPH_110_STAT is not in reset,1: Peripheral PERIPH_110_STAT is in reset"
newline
bitfld.long 0x00 13. "PERIPH_109_STAT,Reset Status for peripheral PERIPH_109_STAT" "0: Peripheral PERIPH_109_STAT is not in reset,1: Peripheral PERIPH_109_STAT is in reset"
newline
bitfld.long 0x00 12. "PERIPH_108_STAT,Reset Status for peripheral PERIPH_108_STAT" "0: Peripheral PERIPH_108_STAT is not in reset,1: Peripheral PERIPH_108_STAT is in reset"
newline
bitfld.long 0x00 11. "PERIPH_107_STAT,Reset Status for peripheral PERIPH_107_STAT" "0: Peripheral PERIPH_107_STAT is not in reset,1: Peripheral PERIPH_107_STAT is in reset"
newline
bitfld.long 0x00 10. "PERIPH_106_STAT,Reset Status for peripheral PERIPH_106_STAT" "0: Peripheral PERIPH_106_STAT is not in reset,1: Peripheral PERIPH_106_STAT is in reset"
newline
bitfld.long 0x00 9. "PERIPH_105_STAT,Reset Status for peripheral PERIPH_105_STAT" "0: Peripheral PERIPH_105_STAT is not in reset,1: Peripheral PERIPH_105_STAT is in reset"
newline
bitfld.long 0x00 8. "PERIPH_104_STAT,Reset Status for peripheral PERIPH_104_STAT" "0: Peripheral PERIPH_104_STAT is not in reset,1: Peripheral PERIPH_104_STAT is in reset"
newline
bitfld.long 0x00 7. "PERIPH_103_STAT,Reset Status for peripheral PERIPH_103_STAT" "0: Peripheral PERIPH_103_STAT is not in reset,1: Peripheral PERIPH_103_STAT is in reset"
newline
bitfld.long 0x00 6. "PERIPH_102_STAT,Reset Status for peripheral PERIPH_102_STAT" "0: Peripheral PERIPH_102_STAT is not in reset,1: Peripheral PERIPH_102_STAT is in reset"
newline
bitfld.long 0x00 5. "PERIPH_101_STAT,Reset Status for peripheral PERIPH_101_STAT" "0: Peripheral PERIPH_101_STAT is not in reset,1: Peripheral PERIPH_101_STAT is in reset"
newline
bitfld.long 0x00 4. "PERIPH_100_STAT,Reset Status for peripheral PERIPH_100_STAT" "0: Peripheral PERIPH_100_STAT is not in reset,1: Peripheral PERIPH_100_STAT is in reset"
newline
bitfld.long 0x00 3. "PERIPH_99_STAT,Reset Status for peripheral PERIPH_99_STAT" "0: Peripheral PERIPH_99_STAT is not in reset,1: Peripheral PERIPH_99_STAT is in reset"
newline
bitfld.long 0x00 2. "PERIPH_98_STAT,Reset Status for peripheral PERIPH_98_STAT" "0: Peripheral PERIPH_98_STAT is not in reset,1: Peripheral PERIPH_98_STAT is in reset"
newline
bitfld.long 0x00 1. "PERIPH_97_STAT,Reset Status for peripheral PERIPH_97_STAT" "0: Peripheral PERIPH_97_STAT is not in reset,1: Peripheral PERIPH_97_STAT is in reset"
newline
bitfld.long 0x00 0. "PERIPH_96_STAT,Reset Status for peripheral PERIPH_96_STAT" "0: Peripheral PERIPH_96_STAT is not in reset,1: Peripheral PERIPH_96_STAT is in reset"
rgroup.long 0x150++0x03
line.long 0x00 "PSTAT2_0,Peripheral Reset Status Register"
bitfld.long 0x00 31. "PERIPH_159_STAT,Reset Status for peripheral PERIPH_159_STAT" "0: Peripheral PERIPH_159_STAT is not in reset,1: Peripheral PERIPH_159_STAT is in reset"
newline
bitfld.long 0x00 30. "PERIPH_158_STAT,Reset Status for peripheral PERIPH_158_STAT" "0: Peripheral PERIPH_158_STAT is not in reset,1: Peripheral PERIPH_158_STAT is in reset"
newline
bitfld.long 0x00 29. "PERIPH_157_STAT,Reset Status for peripheral PERIPH_157_STAT" "0: Peripheral PERIPH_157_STAT is not in reset,1: Peripheral PERIPH_157_STAT is in reset"
newline
bitfld.long 0x00 28. "PERIPH_156_STAT,Reset Status for peripheral PERIPH_156_STAT" "0: Peripheral PERIPH_156_STAT is not in reset,1: Peripheral PERIPH_156_STAT is in reset"
newline
bitfld.long 0x00 27. "PERIPH_155_STAT,Reset Status for peripheral PERIPH_155_STAT" "0: Peripheral PERIPH_155_STAT is not in reset,1: Peripheral PERIPH_155_STAT is in reset"
newline
bitfld.long 0x00 26. "PERIPH_154_STAT,Reset Status for peripheral PERIPH_154_STAT" "0: Peripheral PERIPH_154_STAT is not in reset,1: Peripheral PERIPH_154_STAT is in reset"
newline
bitfld.long 0x00 25. "PERIPH_153_STAT,Reset Status for peripheral PERIPH_153_STAT" "0: Peripheral PERIPH_153_STAT is not in reset,1: Peripheral PERIPH_153_STAT is in reset"
newline
bitfld.long 0x00 24. "PERIPH_152_STAT,Reset Status for peripheral PERIPH_152_STAT" "0: Peripheral PERIPH_152_STAT is not in reset,1: Peripheral PERIPH_152_STAT is in reset"
newline
bitfld.long 0x00 23. "PERIPH_151_STAT,Reset Status for peripheral PERIPH_151_STAT" "0: Peripheral PERIPH_151_STAT is not in reset,1: Peripheral PERIPH_151_STAT is in reset"
newline
bitfld.long 0x00 22. "PERIPH_150_STAT,Reset Status for peripheral PERIPH_150_STAT" "0: Peripheral PERIPH_150_STAT is not in reset,1: Peripheral PERIPH_150_STAT is in reset"
newline
bitfld.long 0x00 21. "PERIPH_149_STAT,Reset Status for peripheral PERIPH_149_STAT" "0: Peripheral PERIPH_149_STAT is not in reset,1: Peripheral PERIPH_149_STAT is in reset"
newline
bitfld.long 0x00 20. "PERIPH_148_STAT,Reset Status for peripheral PERIPH_148_STAT" "0: Peripheral PERIPH_148_STAT is not in reset,1: Peripheral PERIPH_148_STAT is in reset"
newline
bitfld.long 0x00 19. "PERIPH_147_STAT,Reset Status for peripheral PERIPH_147_STAT" "0: Peripheral PERIPH_147_STAT is not in reset,1: Peripheral PERIPH_147_STAT is in reset"
newline
bitfld.long 0x00 18. "PERIPH_146_STAT,Reset Status for peripheral PERIPH_146_STAT" "0: Peripheral PERIPH_146_STAT is not in reset,1: Peripheral PERIPH_146_STAT is in reset"
newline
bitfld.long 0x00 17. "PERIPH_145_STAT,Reset Status for peripheral PERIPH_145_STAT" "0: Peripheral PERIPH_145_STAT is not in reset,1: Peripheral PERIPH_145_STAT is in reset"
newline
bitfld.long 0x00 16. "PERIPH_144_STAT,Reset Status for peripheral PERIPH_144_STAT" "0: Peripheral PERIPH_144_STAT is not in reset,1: Peripheral PERIPH_144_STAT is in reset"
newline
bitfld.long 0x00 15. "PERIPH_143_STAT,Reset Status for peripheral PERIPH_143_STAT" "0: Peripheral PERIPH_143_STAT is not in reset,1: Peripheral PERIPH_143_STAT is in reset"
newline
bitfld.long 0x00 14. "PERIPH_142_STAT,Reset Status for peripheral PERIPH_142_STAT" "0: Peripheral PERIPH_142_STAT is not in reset,1: Peripheral PERIPH_142_STAT is in reset"
newline
bitfld.long 0x00 13. "PERIPH_141_STAT,Reset Status for peripheral PERIPH_141_STAT" "0: Peripheral PERIPH_141_STAT is not in reset,1: Peripheral PERIPH_141_STAT is in reset"
newline
bitfld.long 0x00 12. "PERIPH_140_STAT,Reset Status for peripheral PERIPH_140_STAT" "0: Peripheral PERIPH_140_STAT is not in reset,1: Peripheral PERIPH_140_STAT is in reset"
newline
bitfld.long 0x00 11. "PERIPH_139_STAT,Reset Status for peripheral PERIPH_139_STAT" "0: Peripheral PERIPH_139_STAT is not in reset,1: Peripheral PERIPH_139_STAT is in reset"
newline
bitfld.long 0x00 10. "PERIPH_138_STAT,Reset Status for peripheral PERIPH_138_STAT" "0: Peripheral PERIPH_138_STAT is not in reset,1: Peripheral PERIPH_138_STAT is in reset"
newline
bitfld.long 0x00 9. "PERIPH_137_STAT,Reset Status for peripheral PERIPH_137_STAT" "0: Peripheral PERIPH_137_STAT is not in reset,1: Peripheral PERIPH_137_STAT is in reset"
newline
bitfld.long 0x00 8. "PERIPH_136_STAT,Reset Status for peripheral PERIPH_136_STAT" "0: Peripheral PERIPH_136_STAT is not in reset,1: Peripheral PERIPH_136_STAT is in reset"
newline
bitfld.long 0x00 7. "PERIPH_135_STAT,Reset Status for peripheral PERIPH_135_STAT" "0: Peripheral PERIPH_135_STAT is not in reset,1: Peripheral PERIPH_135_STAT is in reset"
newline
bitfld.long 0x00 6. "PERIPH_134_STAT,Reset Status for peripheral PERIPH_134_STAT" "0: Peripheral PERIPH_134_STAT is not in reset,1: Peripheral PERIPH_134_STAT is in reset"
newline
bitfld.long 0x00 5. "PERIPH_133_STAT,Reset Status for peripheral PERIPH_133_STAT" "0: Peripheral PERIPH_133_STAT is not in reset,1: Peripheral PERIPH_133_STAT is in reset"
newline
bitfld.long 0x00 4. "PERIPH_132_STAT,Reset Status for peripheral PERIPH_132_STAT" "0: Peripheral PERIPH_132_STAT is not in reset,1: Peripheral PERIPH_132_STAT is in reset"
newline
bitfld.long 0x00 3. "PERIPH_131_STAT,Reset Status for peripheral PERIPH_131_STAT" "0: Peripheral PERIPH_131_STAT is not in reset,1: Peripheral PERIPH_131_STAT is in reset"
newline
bitfld.long 0x00 2. "PERIPH_130_STAT,Reset Status for peripheral PERIPH_130_STAT" "0: Peripheral PERIPH_130_STAT is not in reset,1: Peripheral PERIPH_130_STAT is in reset"
newline
bitfld.long 0x00 1. "PERIPH_129_STAT,Reset Status for peripheral PERIPH_129_STAT" "0: Peripheral PERIPH_129_STAT is not in reset,1: Peripheral PERIPH_129_STAT is in reset"
newline
bitfld.long 0x00 0. "PERIPH_128_STAT,Reset Status for peripheral PERIPH_128_STAT" "0: Peripheral PERIPH_128_STAT is not in reset,1: Peripheral PERIPH_128_STAT is in reset"
rgroup.long 0x154++0x03
line.long 0x00 "PSTAT2_1,Peripheral Reset Status Register"
bitfld.long 0x00 31. "PERIPH_191_STAT,Reset Status for peripheral PERIPH_191_STAT" "0: Peripheral PERIPH_191_STAT is not in reset,1: Peripheral PERIPH_191_STAT is in reset"
newline
bitfld.long 0x00 30. "PERIPH_190_STAT,Reset Status for peripheral PERIPH_190_STAT" "0: Peripheral PERIPH_190_STAT is not in reset,1: Peripheral PERIPH_190_STAT is in reset"
newline
bitfld.long 0x00 29. "PERIPH_189_STAT,Reset Status for peripheral PERIPH_189_STAT" "0: Peripheral PERIPH_189_STAT is not in reset,1: Peripheral PERIPH_189_STAT is in reset"
newline
bitfld.long 0x00 28. "PERIPH_188_STAT,Reset Status for peripheral PERIPH_188_STAT" "0: Peripheral PERIPH_188_STAT is not in reset,1: Peripheral PERIPH_188_STAT is in reset"
newline
bitfld.long 0x00 27. "PERIPH_187_STAT,Reset Status for peripheral PERIPH_187_STAT" "0: Peripheral PERIPH_187_STAT is not in reset,1: Peripheral PERIPH_187_STAT is in reset"
newline
bitfld.long 0x00 26. "PERIPH_186_STAT,Reset Status for peripheral PERIPH_186_STAT" "0: Peripheral PERIPH_186_STAT is not in reset,1: Peripheral PERIPH_186_STAT is in reset"
newline
bitfld.long 0x00 25. "PERIPH_185_STAT,Reset Status for peripheral PERIPH_185_STAT" "0: Peripheral PERIPH_185_STAT is not in reset,1: Peripheral PERIPH_185_STAT is in reset"
newline
bitfld.long 0x00 24. "PERIPH_184_STAT,Reset Status for peripheral PERIPH_184_STAT" "0: Peripheral PERIPH_184_STAT is not in reset,1: Peripheral PERIPH_184_STAT is in reset"
newline
bitfld.long 0x00 23. "PERIPH_183_STAT,Reset Status for peripheral PERIPH_183_STAT" "0: Peripheral PERIPH_183_STAT is not in reset,1: Peripheral PERIPH_183_STAT is in reset"
newline
bitfld.long 0x00 22. "PERIPH_182_STAT,Reset Status for peripheral PERIPH_182_STAT" "0: Peripheral PERIPH_182_STAT is not in reset,1: Peripheral PERIPH_182_STAT is in reset"
newline
bitfld.long 0x00 21. "PERIPH_181_STAT,Reset Status for peripheral PERIPH_181_STAT" "0: Peripheral PERIPH_181_STAT is not in reset,1: Peripheral PERIPH_181_STAT is in reset"
newline
bitfld.long 0x00 20. "PERIPH_180_STAT,Reset Status for peripheral PERIPH_180_STAT" "0: Peripheral PERIPH_180_STAT is not in reset,1: Peripheral PERIPH_180_STAT is in reset"
newline
bitfld.long 0x00 19. "PERIPH_179_STAT,Reset Status for peripheral PERIPH_179_STAT" "0: Peripheral PERIPH_179_STAT is not in reset,1: Peripheral PERIPH_179_STAT is in reset"
newline
bitfld.long 0x00 18. "PERIPH_178_STAT,Reset Status for peripheral PERIPH_178_STAT" "0: Peripheral PERIPH_178_STAT is not in reset,1: Peripheral PERIPH_178_STAT is in reset"
newline
bitfld.long 0x00 17. "PERIPH_177_STAT,Reset Status for peripheral PERIPH_177_STAT" "0: Peripheral PERIPH_177_STAT is not in reset,1: Peripheral PERIPH_177_STAT is in reset"
newline
bitfld.long 0x00 16. "PERIPH_176_STAT,Reset Status for peripheral PERIPH_176_STAT" "0: Peripheral PERIPH_176_STAT is not in reset,1: Peripheral PERIPH_176_STAT is in reset"
newline
bitfld.long 0x00 15. "PERIPH_175_STAT,Reset Status for peripheral PERIPH_175_STAT" "0: Peripheral PERIPH_175_STAT is not in reset,1: Peripheral PERIPH_175_STAT is in reset"
newline
bitfld.long 0x00 14. "PERIPH_174_STAT,Reset Status for peripheral PERIPH_174_STAT" "0: Peripheral PERIPH_174_STAT is not in reset,1: Peripheral PERIPH_174_STAT is in reset"
newline
bitfld.long 0x00 13. "PERIPH_173_STAT,Reset Status for peripheral PERIPH_173_STAT" "0: Peripheral PERIPH_173_STAT is not in reset,1: Peripheral PERIPH_173_STAT is in reset"
newline
bitfld.long 0x00 12. "PERIPH_172_STAT,Reset Status for peripheral PERIPH_172_STAT" "0: Peripheral PERIPH_172_STAT is not in reset,1: Peripheral PERIPH_172_STAT is in reset"
newline
bitfld.long 0x00 11. "PERIPH_171_STAT,Reset Status for peripheral PERIPH_171_STAT" "0: Peripheral PERIPH_171_STAT is not in reset,1: Peripheral PERIPH_171_STAT is in reset"
newline
bitfld.long 0x00 10. "PERIPH_170_STAT,Reset Status for peripheral PERIPH_170_STAT" "0: Peripheral PERIPH_170_STAT is not in reset,1: Peripheral PERIPH_170_STAT is in reset"
newline
bitfld.long 0x00 9. "PERIPH_169_STAT,Reset Status for peripheral PERIPH_169_STAT" "0: Peripheral PERIPH_169_STAT is not in reset,1: Peripheral PERIPH_169_STAT is in reset"
newline
bitfld.long 0x00 8. "PERIPH_168_STAT,Reset Status for peripheral PERIPH_168_STAT" "0: Peripheral PERIPH_168_STAT is not in reset,1: Peripheral PERIPH_168_STAT is in reset"
newline
bitfld.long 0x00 7. "PERIPH_167_STAT,Reset Status for peripheral PERIPH_167_STAT" "0: Peripheral PERIPH_167_STAT is not in reset,1: Peripheral PERIPH_167_STAT is in reset"
newline
bitfld.long 0x00 6. "PERIPH_166_STAT,Reset Status for peripheral PERIPH_166_STAT" "0: Peripheral PERIPH_166_STAT is not in reset,1: Peripheral PERIPH_166_STAT is in reset"
newline
bitfld.long 0x00 5. "PERIPH_165_STAT,Reset Status for peripheral PERIPH_165_STAT" "0: Peripheral PERIPH_165_STAT is not in reset,1: Peripheral PERIPH_165_STAT is in reset"
newline
bitfld.long 0x00 4. "PERIPH_164_STAT,Reset Status for peripheral PERIPH_164_STAT" "0: Peripheral PERIPH_164_STAT is not in reset,1: Peripheral PERIPH_164_STAT is in reset"
newline
bitfld.long 0x00 3. "PERIPH_163_STAT,Reset Status for peripheral PERIPH_163_STAT" "0: Peripheral PERIPH_163_STAT is not in reset,1: Peripheral PERIPH_163_STAT is in reset"
newline
bitfld.long 0x00 2. "PERIPH_162_STAT,Reset Status for peripheral PERIPH_162_STAT" "0: Peripheral PERIPH_162_STAT is not in reset,1: Peripheral PERIPH_162_STAT is in reset"
newline
bitfld.long 0x00 1. "PERIPH_161_STAT,Reset Status for peripheral PERIPH_161_STAT" "0: Peripheral PERIPH_161_STAT is not in reset,1: Peripheral PERIPH_161_STAT is in reset"
newline
bitfld.long 0x00 0. "PERIPH_160_STAT,Reset Status for peripheral PERIPH_160_STAT" "0: Peripheral PERIPH_160_STAT is not in reset,1: Peripheral PERIPH_160_STAT is in reset"
rgroup.long 0x158++0x03
line.long 0x00 "PSTAT3_0,Peripheral Reset Status Register"
bitfld.long 0x00 31. "PERIPH_223_STAT,Reset Status for peripheral PERIPH_223_STAT" "0: Peripheral PERIPH_223_STAT is not in reset,1: Peripheral PERIPH_223_STAT is in reset"
newline
bitfld.long 0x00 30. "PERIPH_222_STAT,Reset Status for peripheral PERIPH_222_STAT" "0: Peripheral PERIPH_222_STAT is not in reset,1: Peripheral PERIPH_222_STAT is in reset"
newline
bitfld.long 0x00 29. "PERIPH_221_STAT,Reset Status for peripheral PERIPH_221_STAT" "0: Peripheral PERIPH_221_STAT is not in reset,1: Peripheral PERIPH_221_STAT is in reset"
newline
bitfld.long 0x00 28. "PERIPH_220_STAT,Reset Status for peripheral PERIPH_220_STAT" "0: Peripheral PERIPH_220_STAT is not in reset,1: Peripheral PERIPH_220_STAT is in reset"
newline
bitfld.long 0x00 27. "PERIPH_219_STAT,Reset Status for peripheral PERIPH_219_STAT" "0: Peripheral PERIPH_219_STAT is not in reset,1: Peripheral PERIPH_219_STAT is in reset"
newline
bitfld.long 0x00 26. "PERIPH_218_STAT,Reset Status for peripheral PERIPH_218_STAT" "0: Peripheral PERIPH_218_STAT is not in reset,1: Peripheral PERIPH_218_STAT is in reset"
newline
bitfld.long 0x00 25. "PERIPH_217_STAT,Reset Status for peripheral PERIPH_217_STAT" "0: Peripheral PERIPH_217_STAT is not in reset,1: Peripheral PERIPH_217_STAT is in reset"
newline
bitfld.long 0x00 24. "PERIPH_216_STAT,Reset Status for peripheral PERIPH_216_STAT" "0: Peripheral PERIPH_216_STAT is not in reset,1: Peripheral PERIPH_216_STAT is in reset"
newline
bitfld.long 0x00 23. "PERIPH_215_STAT,Reset Status for peripheral PERIPH_215_STAT" "0: Peripheral PERIPH_215_STAT is not in reset,1: Peripheral PERIPH_215_STAT is in reset"
newline
bitfld.long 0x00 22. "PERIPH_214_STAT,Reset Status for peripheral PERIPH_214_STAT" "0: Peripheral PERIPH_214_STAT is not in reset,1: Peripheral PERIPH_214_STAT is in reset"
newline
bitfld.long 0x00 21. "PERIPH_213_STAT,Reset Status for peripheral PERIPH_213_STAT" "0: Peripheral PERIPH_213_STAT is not in reset,1: Peripheral PERIPH_213_STAT is in reset"
newline
bitfld.long 0x00 20. "PERIPH_212_STAT,Reset Status for peripheral PERIPH_212_STAT" "0: Peripheral PERIPH_212_STAT is not in reset,1: Peripheral PERIPH_212_STAT is in reset"
newline
bitfld.long 0x00 19. "PERIPH_211_STAT,Reset Status for peripheral PERIPH_211_STAT" "0: Peripheral PERIPH_211_STAT is not in reset,1: Peripheral PERIPH_211_STAT is in reset"
newline
bitfld.long 0x00 18. "PERIPH_210_STAT,Reset Status for peripheral PERIPH_210_STAT" "0: Peripheral PERIPH_210_STAT is not in reset,1: Peripheral PERIPH_210_STAT is in reset"
newline
bitfld.long 0x00 17. "PERIPH_209_STAT,Reset Status for peripheral PERIPH_209_STAT" "0: Peripheral PERIPH_209_STAT is not in reset,1: Peripheral PERIPH_209_STAT is in reset"
newline
bitfld.long 0x00 16. "PERIPH_208_STAT,Reset Status for peripheral PERIPH_208_STAT" "0: Peripheral PERIPH_208_STAT is not in reset,1: Peripheral PERIPH_208_STAT is in reset"
newline
bitfld.long 0x00 15. "PERIPH_207_STAT,Reset Status for peripheral PERIPH_207_STAT" "0: Peripheral PERIPH_207_STAT is not in reset,1: Peripheral PERIPH_207_STAT is in reset"
newline
bitfld.long 0x00 14. "PERIPH_206_STAT,Reset Status for peripheral PERIPH_206_STAT" "0: Peripheral PERIPH_206_STAT is not in reset,1: Peripheral PERIPH_206_STAT is in reset"
newline
bitfld.long 0x00 13. "PERIPH_205_STAT,Reset Status for peripheral PERIPH_205_STAT" "0: Peripheral PERIPH_205_STAT is not in reset,1: Peripheral PERIPH_205_STAT is in reset"
newline
bitfld.long 0x00 12. "PERIPH_204_STAT,Reset Status for peripheral PERIPH_204_STAT" "0: Peripheral PERIPH_204_STAT is not in reset,1: Peripheral PERIPH_204_STAT is in reset"
newline
bitfld.long 0x00 11. "PERIPH_203_STAT,Reset Status for peripheral PERIPH_203_STAT" "0: Peripheral PERIPH_203_STAT is not in reset,1: Peripheral PERIPH_203_STAT is in reset"
newline
bitfld.long 0x00 10. "PERIPH_202_STAT,Reset Status for peripheral PERIPH_202_STAT" "0: Peripheral PERIPH_202_STAT is not in reset,1: Peripheral PERIPH_202_STAT is in reset"
newline
bitfld.long 0x00 9. "PERIPH_201_STAT,Reset Status for peripheral PERIPH_201_STAT" "0: Peripheral PERIPH_201_STAT is not in reset,1: Peripheral PERIPH_201_STAT is in reset"
newline
bitfld.long 0x00 8. "PERIPH_200_STAT,Reset Status for peripheral PERIPH_200_STAT" "0: Peripheral PERIPH_200_STAT is not in reset,1: Peripheral PERIPH_200_STAT is in reset"
newline
bitfld.long 0x00 7. "PERIPH_199_STAT,Reset Status for peripheral PERIPH_199_STAT" "0: Peripheral PERIPH_199_STAT is not in reset,1: Peripheral PERIPH_199_STAT is in reset"
newline
bitfld.long 0x00 6. "PERIPH_198_STAT,Reset Status for peripheral PERIPH_198_STAT" "0: Peripheral PERIPH_198_STAT is not in reset,1: Peripheral PERIPH_198_STAT is in reset"
newline
bitfld.long 0x00 5. "PERIPH_197_STAT,Reset Status for peripheral PERIPH_197_STAT" "0: Peripheral PERIPH_197_STAT is not in reset,1: Peripheral PERIPH_197_STAT is in reset"
newline
bitfld.long 0x00 4. "PERIPH_196_STAT,Reset Status for peripheral PERIPH_196_STAT" "0: Peripheral PERIPH_196_STAT is not in reset,1: Peripheral PERIPH_196_STAT is in reset"
newline
bitfld.long 0x00 3. "PERIPH_195_STAT,Reset Status for peripheral PERIPH_195_STAT" "0: Peripheral PERIPH_195_STAT is not in reset,1: Peripheral PERIPH_195_STAT is in reset"
newline
bitfld.long 0x00 2. "PERIPH_194_STAT,Reset Status for peripheral PERIPH_194_STAT" "0: Peripheral PERIPH_194_STAT is not in reset,1: Peripheral PERIPH_194_STAT is in reset"
newline
bitfld.long 0x00 1. "PERIPH_193_STAT,Reset Status for peripheral PERIPH_193_STAT" "0: Peripheral PERIPH_193_STAT is not in reset,1: Peripheral PERIPH_193_STAT is in reset"
newline
bitfld.long 0x00 0. "PERIPH_192_STAT,Reset Status for peripheral RADAR_SS_STAT" "0: Peripheral RADAR_SS_STAT is not in reset,1: Peripheral RADAR_SS_STAT is in reset"
rgroup.long 0x15C++0x03
line.long 0x00 "PSTAT3_1,Peripheral Reset Status Register"
bitfld.long 0x00 31. "PERIPH_255_STAT,Reset Status for peripheral PERIPH_255_STAT" "0: Peripheral PERIPH_255_STAT is not in reset,1: Peripheral PERIPH_255_STAT is in reset"
newline
bitfld.long 0x00 30. "PERIPH_254_STAT,Reset Status for peripheral PERIPH_254_STAT" "0: Peripheral PERIPH_254_STAT is not in reset,1: Peripheral PERIPH_254_STAT is in reset"
newline
bitfld.long 0x00 29. "PERIPH_253_STAT,Reset Status for peripheral PERIPH_253_STAT" "0: Peripheral PERIPH_253_STAT is not in reset,1: Peripheral PERIPH_253_STAT is in reset"
newline
bitfld.long 0x00 28. "PERIPH_252_STAT,Reset Status for peripheral PERIPH_252_STAT" "0: Peripheral PERIPH_252_STAT is not in reset,1: Peripheral PERIPH_252_STAT is in reset"
newline
bitfld.long 0x00 27. "PERIPH_251_STAT,Reset Status for peripheral PERIPH_251_STAT" "0: Peripheral PERIPH_251_STAT is not in reset,1: Peripheral PERIPH_251_STAT is in reset"
newline
bitfld.long 0x00 26. "PERIPH_250_STAT,Reset Status for peripheral PERIPH_250_STAT" "0: Peripheral PERIPH_250_STAT is not in reset,1: Peripheral PERIPH_250_STAT is in reset"
newline
bitfld.long 0x00 25. "PERIPH_249_STAT,Reset Status for peripheral PERIPH_249_STAT" "0: Peripheral PERIPH_249_STAT is not in reset,1: Peripheral PERIPH_249_STAT is in reset"
newline
bitfld.long 0x00 24. "PERIPH_248_STAT,Reset Status for peripheral PERIPH_248_STAT" "0: Peripheral PERIPH_248_STAT is not in reset,1: Peripheral PERIPH_248_STAT is in reset"
newline
bitfld.long 0x00 23. "PERIPH_247_STAT,Reset Status for peripheral PERIPH_247_STAT" "0: Peripheral PERIPH_247_STAT is not in reset,1: Peripheral PERIPH_247_STAT is in reset"
newline
bitfld.long 0x00 22. "PERIPH_246_STAT,Reset Status for peripheral PERIPH_246_STAT" "0: Peripheral PERIPH_246_STAT is not in reset,1: Peripheral PERIPH_246_STAT is in reset"
newline
bitfld.long 0x00 21. "PERIPH_245_STAT,Reset Status for peripheral PERIPH_245_STAT" "0: Peripheral PERIPH_245_STAT is not in reset,1: Peripheral PERIPH_245_STAT is in reset"
newline
bitfld.long 0x00 20. "PERIPH_244_STAT,Reset Status for peripheral PERIPH_244_STAT" "0: Peripheral PERIPH_244_STAT is not in reset,1: Peripheral PERIPH_244_STAT is in reset"
newline
bitfld.long 0x00 19. "PERIPH_243_STAT,Reset Status for peripheral PERIPH_243_STAT" "0: Peripheral PERIPH_243_STAT is not in reset,1: Peripheral PERIPH_243_STAT is in reset"
newline
bitfld.long 0x00 18. "PERIPH_242_STAT,Reset Status for peripheral PERIPH_242_STAT" "0: Peripheral PERIPH_242_STAT is not in reset,1: Peripheral PERIPH_242_STAT is in reset"
newline
bitfld.long 0x00 17. "PERIPH_241_STAT,Reset Status for peripheral PERIPH_241_STAT" "0: Peripheral PERIPH_241_STAT is not in reset,1: Peripheral PERIPH_241_STAT is in reset"
newline
bitfld.long 0x00 16. "PERIPH_240_STAT,Reset Status for peripheral PERIPH_240_STAT" "0: Peripheral PERIPH_240_STAT is not in reset,1: Peripheral PERIPH_240_STAT is in reset"
newline
bitfld.long 0x00 15. "PERIPH_239_STAT,Reset Status for peripheral PERIPH_239_STAT" "0: Peripheral PERIPH_239_STAT is not in reset,1: Peripheral PERIPH_239_STAT is in reset"
newline
bitfld.long 0x00 14. "PERIPH_238_STAT,Reset Status for peripheral PERIPH_238_STAT" "0: Peripheral PERIPH_238_STAT is not in reset,1: Peripheral PERIPH_238_STAT is in reset"
newline
bitfld.long 0x00 13. "PERIPH_237_STAT,Reset Status for peripheral PERIPH_237_STAT" "0: Peripheral PERIPH_237_STAT is not in reset,1: Peripheral PERIPH_237_STAT is in reset"
newline
bitfld.long 0x00 12. "PERIPH_236_STAT,Reset Status for peripheral PERIPH_236_STAT" "0: Peripheral PERIPH_236_STAT is not in reset,1: Peripheral PERIPH_236_STAT is in reset"
newline
bitfld.long 0x00 11. "PERIPH_235_STAT,Reset Status for peripheral PERIPH_235_STAT" "0: Peripheral PERIPH_235_STAT is not in reset,1: Peripheral PERIPH_235_STAT is in reset"
newline
bitfld.long 0x00 10. "PERIPH_234_STAT,Reset Status for peripheral PERIPH_234_STAT" "0: Peripheral PERIPH_234_STAT is not in reset,1: Peripheral PERIPH_234_STAT is in reset"
newline
bitfld.long 0x00 9. "PERIPH_233_STAT,Reset Status for peripheral PERIPH_233_STAT" "0: Peripheral PERIPH_233_STAT is not in reset,1: Peripheral PERIPH_233_STAT is in reset"
newline
bitfld.long 0x00 8. "PERIPH_232_STAT,Reset Status for peripheral PERIPH_232_STAT" "0: Peripheral PERIPH_232_STAT is not in reset,1: Peripheral PERIPH_232_STAT is in reset"
newline
bitfld.long 0x00 7. "PERIPH_231_STAT,Reset Status for peripheral PERIPH_231_STAT" "0: Peripheral PERIPH_231_STAT is not in reset,1: Peripheral PERIPH_231_STAT is in reset"
newline
bitfld.long 0x00 6. "PERIPH_230_STAT,Reset Status for peripheral PERIPH_230_STAT" "0: Peripheral PERIPH_230_STAT is not in reset,1: Peripheral PERIPH_230_STAT is in reset"
newline
bitfld.long 0x00 5. "PERIPH_229_STAT,Reset Status for peripheral PERIPH_229_STAT" "0: Peripheral PERIPH_229_STAT is not in reset,1: Peripheral PERIPH_229_STAT is in reset"
newline
bitfld.long 0x00 4. "PERIPH_228_STAT,Reset Status for peripheral PERIPH_228_STAT" "0: Peripheral PERIPH_228_STAT is not in reset,1: Peripheral PERIPH_228_STAT is in reset"
newline
bitfld.long 0x00 3. "PERIPH_227_STAT,Reset Status for peripheral PERIPH_227_STAT" "0: Peripheral PERIPH_227_STAT is not in reset,1: Peripheral PERIPH_227_STAT is in reset"
newline
bitfld.long 0x00 2. "PERIPH_226_STAT,Reset Status for peripheral PERIPH_226_STAT" "0: Peripheral PERIPH_226_STAT is not in reset,1: Peripheral PERIPH_226_STAT is in reset"
newline
bitfld.long 0x00 1. "PERIPH_225_STAT,Reset Status for peripheral PERIPH_225_STAT" "0: Peripheral PERIPH_225_STAT is not in reset,1: Peripheral PERIPH_225_STAT is in reset"
newline
bitfld.long 0x00 0. "PERIPH_224_STAT,Reset Status for peripheral PERIPH_224_STAT" "0: Peripheral PERIPH_224_STAT is not in reset,1: Peripheral PERIPH_224_STAT is in reset"
rgroup.long 0x160++0x03
line.long 0x00 "PSTAT4_0,Peripheral Reset Status Register"
bitfld.long 0x00 31. "PERIPH_287_STAT,Reset Status for peripheral PERIPH_287_STAT" "0: Peripheral PERIPH_287_STAT is not in reset,1: Peripheral PERIPH_287_STAT is in reset"
newline
bitfld.long 0x00 30. "PERIPH_286_STAT,Reset Status for peripheral PERIPH_286_STAT" "0: Peripheral PERIPH_286_STAT is not in reset,1: Peripheral PERIPH_286_STAT is in reset"
newline
bitfld.long 0x00 29. "PERIPH_285_STAT,Reset Status for peripheral PERIPH_285_STAT" "0: Peripheral PERIPH_285_STAT is not in reset,1: Peripheral PERIPH_285_STAT is in reset"
newline
bitfld.long 0x00 28. "PERIPH_284_STAT,Reset Status for peripheral PERIPH_284_STAT" "0: Peripheral PERIPH_284_STAT is not in reset,1: Peripheral PERIPH_284_STAT is in reset"
newline
bitfld.long 0x00 27. "PERIPH_283_STAT,Reset Status for peripheral PERIPH_283_STAT" "0: Peripheral PERIPH_283_STAT is not in reset,1: Peripheral PERIPH_283_STAT is in reset"
newline
bitfld.long 0x00 26. "PERIPH_282_STAT,Reset Status for peripheral PERIPH_282_STAT" "0: Peripheral PERIPH_282_STAT is not in reset,1: Peripheral PERIPH_282_STAT is in reset"
newline
bitfld.long 0x00 25. "PERIPH_281_STAT,Reset Status for peripheral PERIPH_281_STAT" "0: Peripheral PERIPH_281_STAT is not in reset,1: Peripheral PERIPH_281_STAT is in reset"
newline
bitfld.long 0x00 24. "PERIPH_280_STAT,Reset Status for peripheral PERIPH_280_STAT" "0: Peripheral PERIPH_280_STAT is not in reset,1: Peripheral PERIPH_280_STAT is in reset"
newline
bitfld.long 0x00 23. "PERIPH_279_STAT,Reset Status for peripheral PERIPH_279_STAT" "0: Peripheral PERIPH_279_STAT is not in reset,1: Peripheral PERIPH_279_STAT is in reset"
newline
bitfld.long 0x00 22. "PERIPH_278_STAT,Reset Status for peripheral PERIPH_278_STAT" "0: Peripheral PERIPH_278_STAT is not in reset,1: Peripheral PERIPH_278_STAT is in reset"
newline
bitfld.long 0x00 21. "PERIPH_277_STAT,Reset Status for peripheral PERIPH_277_STAT" "0: Peripheral PERIPH_277_STAT is not in reset,1: Peripheral PERIPH_277_STAT is in reset"
newline
bitfld.long 0x00 20. "PERIPH_276_STAT,Reset Status for peripheral PERIPH_276_STAT" "0: Peripheral PERIPH_276_STAT is not in reset,1: Peripheral PERIPH_276_STAT is in reset"
newline
bitfld.long 0x00 19. "PERIPH_275_STAT,Reset Status for peripheral PERIPH_275_STAT" "0: Peripheral PERIPH_275_STAT is not in reset,1: Peripheral PERIPH_275_STAT is in reset"
newline
bitfld.long 0x00 18. "PERIPH_274_STAT,Reset Status for peripheral PERIPH_274_STAT" "0: Peripheral PERIPH_274_STAT is not in reset,1: Peripheral PERIPH_274_STAT is in reset"
newline
bitfld.long 0x00 17. "PERIPH_273_STAT,Reset Status for peripheral PERIPH_273_STAT" "0: Peripheral PERIPH_273_STAT is not in reset,1: Peripheral PERIPH_273_STAT is in reset"
newline
bitfld.long 0x00 16. "PERIPH_272_STAT,Reset Status for peripheral PERIPH_272_STAT" "0: Peripheral PERIPH_272_STAT is not in reset,1: Peripheral PERIPH_272_STAT is in reset"
newline
bitfld.long 0x00 15. "PERIPH_271_STAT,Reset Status for peripheral PERIPH_271_STAT" "0: Peripheral PERIPH_271_STAT is not in reset,1: Peripheral PERIPH_271_STAT is in reset"
newline
bitfld.long 0x00 14. "PERIPH_270_STAT,Reset Status for peripheral PERIPH_270_STAT" "0: Peripheral PERIPH_270_STAT is not in reset,1: Peripheral PERIPH_270_STAT is in reset"
newline
bitfld.long 0x00 13. "PERIPH_269_STAT,Reset Status for peripheral PERIPH_269_STAT" "0: Peripheral PERIPH_269_STAT is not in reset,1: Peripheral PERIPH_269_STAT is in reset"
newline
bitfld.long 0x00 12. "PERIPH_268_STAT,Reset Status for peripheral PERIPH_268_STAT" "0: Peripheral PERIPH_268_STAT is not in reset,1: Peripheral PERIPH_268_STAT is in reset"
newline
bitfld.long 0x00 11. "PERIPH_267_STAT,Reset Status for peripheral PERIPH_267_STAT" "0: Peripheral PERIPH_267_STAT is not in reset,1: Peripheral PERIPH_267_STAT is in reset"
newline
bitfld.long 0x00 10. "PERIPH_266_STAT,Reset Status for peripheral PERIPH_266_STAT" "0: Peripheral PERIPH_266_STAT is not in reset,1: Peripheral PERIPH_266_STAT is in reset"
newline
bitfld.long 0x00 9. "PERIPH_265_STAT,Reset Status for peripheral PERIPH_265_STAT" "0: Peripheral PERIPH_265_STAT is not in reset,1: Peripheral PERIPH_265_STAT is in reset"
newline
bitfld.long 0x00 8. "PERIPH_264_STAT,Reset Status for peripheral PERIPH_264_STAT" "0: Peripheral PERIPH_264_STAT is not in reset,1: Peripheral PERIPH_264_STAT is in reset"
newline
bitfld.long 0x00 7. "PERIPH_263_STAT,Reset Status for peripheral PERIPH_263_STAT" "0: Peripheral PERIPH_263_STAT is not in reset,1: Peripheral PERIPH_263_STAT is in reset"
newline
bitfld.long 0x00 6. "PERIPH_262_STAT,Reset Status for peripheral PERIPH_262_STAT" "0: Peripheral PERIPH_262_STAT is not in reset,1: Peripheral PERIPH_262_STAT is in reset"
newline
bitfld.long 0x00 5. "PERIPH_261_STAT,Reset Status for peripheral PERIPH_261_STAT" "0: Peripheral PERIPH_261_STAT is not in reset,1: Peripheral PERIPH_261_STAT is in reset"
newline
bitfld.long 0x00 4. "PERIPH_260_STAT,Reset Status for peripheral PERIPH_260_STAT" "0: Peripheral PERIPH_260_STAT is not in reset,1: Peripheral PERIPH_260_STAT is in reset"
newline
bitfld.long 0x00 3. "PERIPH_259_STAT,Reset Status for peripheral PERIPH_259_STAT" "0: Peripheral PERIPH_259_STAT is not in reset,1: Peripheral PERIPH_259_STAT is in reset"
newline
bitfld.long 0x00 2. "PERIPH_258_STAT,Reset Status for peripheral PERIPH_258_STAT" "0: Peripheral PERIPH_258_STAT is not in reset,1: Peripheral PERIPH_258_STAT is in reset"
newline
bitfld.long 0x00 1. "PERIPH_257_STAT,Reset Status for peripheral PERIPH_257_STAT" "0: Peripheral PERIPH_257_STAT is not in reset,1: Peripheral PERIPH_257_STAT is in reset"
newline
bitfld.long 0x00 0. "PERIPH_256_STAT,Reset Status for peripheral PERIPH_256_STAT" "0: Peripheral PERIPH_256_STAT is not in reset,1: Peripheral PERIPH_256_STAT is in reset"
rgroup.long 0x164++0x03
line.long 0x00 "PSTAT4_1,Peripheral Reset Status Register"
bitfld.long 0x00 31. "PERIPH_319_STAT,Reset Status for peripheral PERIPH_319_STAT" "0: Peripheral PERIPH_319_STAT is not in reset,1: Peripheral PERIPH_319_STAT is in reset"
newline
bitfld.long 0x00 30. "PERIPH_318_STAT,Reset Status for peripheral PERIPH_318_STAT" "0: Peripheral PERIPH_318_STAT is not in reset,1: Peripheral PERIPH_318_STAT is in reset"
newline
bitfld.long 0x00 29. "PERIPH_317_STAT,Reset Status for peripheral PERIPH_317_STAT" "0: Peripheral PERIPH_317_STAT is not in reset,1: Peripheral PERIPH_317_STAT is in reset"
newline
bitfld.long 0x00 28. "PERIPH_316_STAT,Reset Status for peripheral PERIPH_316_STAT" "0: Peripheral PERIPH_316_STAT is not in reset,1: Peripheral PERIPH_316_STAT is in reset"
newline
bitfld.long 0x00 27. "PERIPH_315_STAT,Reset Status for peripheral PERIPH_315_STAT" "0: Peripheral PERIPH_315_STAT is not in reset,1: Peripheral PERIPH_315_STAT is in reset"
newline
bitfld.long 0x00 26. "PERIPH_314_STAT,Reset Status for peripheral PERIPH_314_STAT" "0: Peripheral PERIPH_314_STAT is not in reset,1: Peripheral PERIPH_314_STAT is in reset"
newline
bitfld.long 0x00 25. "PERIPH_313_STAT,Reset Status for peripheral PERIPH_313_STAT" "0: Peripheral PERIPH_313_STAT is not in reset,1: Peripheral PERIPH_313_STAT is in reset"
newline
bitfld.long 0x00 24. "PERIPH_312_STAT,Reset Status for peripheral PERIPH_312_STAT" "0: Peripheral PERIPH_312_STAT is not in reset,1: Peripheral PERIPH_312_STAT is in reset"
newline
bitfld.long 0x00 23. "PERIPH_311_STAT,Reset Status for peripheral PERIPH_311_STAT" "0: Peripheral PERIPH_311_STAT is not in reset,1: Peripheral PERIPH_311_STAT is in reset"
newline
bitfld.long 0x00 22. "PERIPH_310_STAT,Reset Status for peripheral PERIPH_310_STAT" "0: Peripheral PERIPH_310_STAT is not in reset,1: Peripheral PERIPH_310_STAT is in reset"
newline
bitfld.long 0x00 21. "PERIPH_309_STAT,Reset Status for peripheral PERIPH_309_STAT" "0: Peripheral PERIPH_309_STAT is not in reset,1: Peripheral PERIPH_309_STAT is in reset"
newline
bitfld.long 0x00 20. "PERIPH_308_STAT,Reset Status for peripheral PERIPH_308_STAT" "0: Peripheral PERIPH_308_STAT is not in reset,1: Peripheral PERIPH_308_STAT is in reset"
newline
bitfld.long 0x00 19. "PERIPH_307_STAT,Reset Status for peripheral PERIPH_307_STAT" "0: Peripheral PERIPH_307_STAT is not in reset,1: Peripheral PERIPH_307_STAT is in reset"
newline
bitfld.long 0x00 18. "PERIPH_306_STAT,Reset Status for peripheral PERIPH_306_STAT" "0: Peripheral PERIPH_306_STAT is not in reset,1: Peripheral PERIPH_306_STAT is in reset"
newline
bitfld.long 0x00 17. "PERIPH_305_STAT,Reset Status for peripheral PERIPH_305_STAT" "0: Peripheral PERIPH_305_STAT is not in reset,1: Peripheral PERIPH_305_STAT is in reset"
newline
bitfld.long 0x00 16. "PERIPH_304_STAT,Reset Status for peripheral PERIPH_304_STAT" "0: Peripheral PERIPH_304_STAT is not in reset,1: Peripheral PERIPH_304_STAT is in reset"
newline
bitfld.long 0x00 15. "PERIPH_303_STAT,Reset Status for peripheral PERIPH_303_STAT" "0: Peripheral PERIPH_303_STAT is not in reset,1: Peripheral PERIPH_303_STAT is in reset"
newline
bitfld.long 0x00 14. "PERIPH_302_STAT,Reset Status for peripheral PERIPH_302_STAT" "0: Peripheral PERIPH_302_STAT is not in reset,1: Peripheral PERIPH_302_STAT is in reset"
newline
bitfld.long 0x00 13. "PERIPH_301_STAT,Reset Status for peripheral PERIPH_301_STAT" "0: Peripheral PERIPH_301_STAT is not in reset,1: Peripheral PERIPH_301_STAT is in reset"
newline
bitfld.long 0x00 12. "PERIPH_300_STAT,Reset Status for peripheral PERIPH_300_STAT" "0: Peripheral PERIPH_300_STAT is not in reset,1: Peripheral PERIPH_300_STAT is in reset"
newline
bitfld.long 0x00 11. "PERIPH_299_STAT,Reset Status for peripheral PERIPH_299_STAT" "0: Peripheral PERIPH_299_STAT is not in reset,1: Peripheral PERIPH_299_STAT is in reset"
newline
bitfld.long 0x00 10. "PERIPH_298_STAT,Reset Status for peripheral PERIPH_298_STAT" "0: Peripheral PERIPH_298_STAT is not in reset,1: Peripheral PERIPH_298_STAT is in reset"
newline
bitfld.long 0x00 9. "PERIPH_297_STAT,Reset Status for peripheral PERIPH_297_STAT" "0: Peripheral PERIPH_297_STAT is not in reset,1: Peripheral PERIPH_297_STAT is in reset"
newline
bitfld.long 0x00 8. "PERIPH_296_STAT,Reset Status for peripheral PERIPH_296_STAT" "0: Peripheral PERIPH_296_STAT is not in reset,1: Peripheral PERIPH_296_STAT is in reset"
newline
bitfld.long 0x00 7. "PERIPH_295_STAT,Reset Status for peripheral PERIPH_295_STAT" "0: Peripheral PERIPH_295_STAT is not in reset,1: Peripheral PERIPH_295_STAT is in reset"
newline
bitfld.long 0x00 6. "PERIPH_294_STAT,Reset Status for peripheral PERIPH_294_STAT" "0: Peripheral PERIPH_294_STAT is not in reset,1: Peripheral PERIPH_294_STAT is in reset"
newline
bitfld.long 0x00 5. "PERIPH_293_STAT,Reset Status for peripheral PERIPH_293_STAT" "0: Peripheral PERIPH_293_STAT is not in reset,1: Peripheral PERIPH_293_STAT is in reset"
newline
bitfld.long 0x00 4. "PERIPH_292_STAT,Reset Status for peripheral PERIPH_292_STAT" "0: Peripheral PERIPH_292_STAT is not in reset,1: Peripheral PERIPH_292_STAT is in reset"
newline
bitfld.long 0x00 3. "PERIPH_291_STAT,Reset Status for peripheral PERIPH_291_STAT" "0: Peripheral PERIPH_291_STAT is not in reset,1: Peripheral PERIPH_291_STAT is in reset"
newline
bitfld.long 0x00 2. "PERIPH_290_STAT,Reset Status for peripheral PERIPH_290_STAT" "0: Peripheral PERIPH_290_STAT is not in reset,1: Peripheral PERIPH_290_STAT is in reset"
newline
bitfld.long 0x00 1. "PERIPH_289_STAT,Reset Status for peripheral PERIPH_289_STAT" "0: Peripheral PERIPH_289_STAT is not in reset,1: Peripheral PERIPH_289_STAT is in reset"
newline
bitfld.long 0x00 0. "PERIPH_288_STAT,Reset Status for peripheral PERIPH_288_STAT" "0: Peripheral PERIPH_288_STAT is not in reset,1: Peripheral PERIPH_288_STAT is in reset"
tree.end
tree "MCM"
base ad:0xE0080000
rgroup.word 0x00++0x01
line.word 0x00 "PLREV,SoC-defined Platform Revision"
hexmask.word 0x00 0.--15. 1. "PLREV,The PLREV[15:0] field is specified by a platform input signal to define a software-visible revision number"
rgroup.word 0x02++0x01
line.word 0x00 "PCT,Processor Core Type"
hexmask.word 0x00 0.--15. 1. "PCT,This MCM design supports the Arm Cortex M7 core"
group.long 0x0C++0x03
line.long 0x00 "CPCR,Core Platform Control"
bitfld.long 0x00 27. "CM7_AHBSPRI,AHB Slave Priority" "0: Uses a round-robin arbitration scheme,1: AHB-slave access has priority over a core.."
group.long 0x10++0x03
line.long 0x00 "ISCR,Interrupt Status and Control"
bitfld.long 0x00 31. "FIDCE,FPU Input Denormal Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x00 28. "FIXCE,FPU Inexact Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
newline
bitfld.long 0x00 27. "FUFCE,FPU Underflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x00 26. "FOFCE,FPU Overflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
newline
bitfld.long 0x00 25. "FDZCE,FPU Divide-by-Zero Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
bitfld.long 0x00 24. "FIOCE,FPU Invalid Operation Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
newline
bitfld.long 0x00 21. "WABE,TCM Write Abort Interrupt Enable" "0: Disable interrupt,1: Enable Interrupt"
rbitfld.long 0x00 15. "FIDC,FPU Input Denormal Interrupt Status" "0: No interrupt,1: Interrupt occurred"
newline
rbitfld.long 0x00 12. "FIXC,FPU Inexact Interrupt Status" "0: No interrupt,1: Interrupt occurred"
rbitfld.long 0x00 11. "FUFC,FPU Underflow Interrupt Status" "0: No interrupt,1: Interrupt occurred"
newline
rbitfld.long 0x00 10. "FOFC,FPU Overflow Interrupt Status" "0: No interrupt,1: Interrupt occurred"
rbitfld.long 0x00 9. "FDZC,FPU Divide-by-Zero Interrupt Status" "0: No interrupt,1: Interrupt occurred"
newline
rbitfld.long 0x00 8. "FIOC,FPU Invalid Operation Interrupt Status" "0: No interrupt,1: Interrupt occurred"
rbitfld.long 0x00 6. "WABSO,Write Abort on Slave Overrun" "0: No write abort overrun,1: Write abort overrun occurred"
newline
eventfld.long 0x00 5. "WABS,Write Abort on Slave" "0: No write abort occurred on AHBS interface,1: Write abort occurred on AHBS interface"
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x400)++0x03
line.long 0x00 "LMEM_DESC_$1,Local Memory Descriptor $1"
rbitfld.long 0x00 31. "LMV,Local Memory Valid" "0: LMEMn not present,1: LMEMn present"
rbitfld.long 0x00 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with capacity of.."
newline
rbitfld.long 0x00 24.--27. "LMSZ,Local Memory Size" "0: LMSZ_0,1: LMSZ_1,2: LMSZ_2,3: LMSZ_3,4: LMSZ_4,5: LMSZ_5,6: LMSZ_6,7: LMSZ_7,8: LMSZ_8,9: LMSZ_9,10: LMSZ_10,11: LMSZ_11,12: LMSZ_12,13: LMSZ_13,14: LMSZ_14,15: 16384 KB"
rbitfld.long 0x00 20.--23. "WY,Level 1 Cache Ways" "0: No cache,?,2: 2-way set associative,?,4: 4-way set associative,?..."
newline
rbitfld.long 0x00 17.--19. "DPW,Data Path Width" "?,?,2: LMEMn is 32-bits wide,3: LMEMn is 64-bits wide,?..."
rbitfld.long 0x00 13.--15. "MT,Memory Type" "0: ITCM,1: DTCM,2: ICACHE,3: DCACHE,?..."
repeat.end
tree.end
tree "MDM_AP"
base edp:0x0600
rgroup.long 0x00++0x03
line.long 0x00 "STATUS_0,Status 0"
bitfld.long 0x00 31. "HSE_CM7_DBGRSTRTD,Handshake Signal For HSE_M Cortex-M7 Core DBGRSTRT" "0: Debug,1: NORMAL"
newline
bitfld.long 0x00 29. "M7_1_DBGRSTRTD,Handshake Signal For Cortex-M7_1_DBGRSTRT" "0: Debug,1: NORMAL"
newline
bitfld.long 0x00 28. "M7_0_DBGRSTRTD,Handshake Signal For Cortex-M7_0_DBGRSTRT" "0: Debug,1: NORMAL"
newline
bitfld.long 0x00 23. "HSE_CM7_SLEEPING,HSE_M Cortex-M7 Core Sleep Mode" "0: Running or wants to leave Sleep mode,1: Ready to enter a low-power state"
newline
bitfld.long 0x00 21. "CM7_1_SLEEPING,Cortex-M7_1 Core Sleep Mode" "0: Running or wants to leave Sleep mode,1: Ready to enter a low-power state"
newline
bitfld.long 0x00 20. "CM7_0_SLEEPING,Cortex-M7_0 Core Sleep Mode" "0: Running or wants to leave Sleep mode,1: Ready to enter a low-power state"
newline
bitfld.long 0x00 19. "HSE_CM7_SLEEPDEEP,HSE_M Cortex-M7 Core Deep Sleep" "0: Not in Deep Sleep mode,1: Ready to enter a low-power state"
newline
bitfld.long 0x00 17. "CM7_1_SLEEPDEEP,Cortex-M7_1 Core Deep Sleep" "0: Not in Deep Sleep mode,1: Ready to enter a low-power state"
newline
bitfld.long 0x00 16. "CM7_0_SLEEPDEEP,Cortex-M7_0 Deep Sleep" "0: Not in Deep Sleep mode,1: Ready to enter a low-power state"
newline
bitfld.long 0x00 15. "HSE_CM7_HALTED,HSE_M Cortex-M7 Core Halted" "0: Not halted,1: Halted"
newline
bitfld.long 0x00 13. "CM7_1_HALTED,Cortex-M7_1 Core Halted" "0: Not halted,1: Halted"
newline
bitfld.long 0x00 12. "CM7_0_HALTED,Cortex-M7 Core Halted" "0: Not halted,1: Halted"
newline
bitfld.long 0x00 8. "JTAG_ACTIVE,Status Of Reset To AUX TAPs" "0: TRST of AUX TAPs asserted,1: TRST of AUX TAPs deasserted"
newline
bitfld.long 0x00 7. "CDBGPWRUPREQ,CDBGPWRUPREQ Status" "0: Deasserted,1: Asserted"
newline
bitfld.long 0x00 6. "CSYSPWRUPREQ,CSYSPWRUPREQ Status" "0: Deasserted,1: Asserted"
newline
bitfld.long 0x00 5. "READY_FOR_DBG,Ready For Debug" "0: Debugger to wait until the fields are asserted,1: Debugger can proceed to run its routine"
newline
bitfld.long 0x00 2. "SYSTEM_RESET,Indicates the system reset state" "0: Not in reset,1: In reset"
group.long 0x04++0x03
line.long 0x00 "CTRL_0,Control 0"
bitfld.long 0x00 31. "M7_HSE_DBGRSTRT,Debug Restart Input To Cortex-M7 HSE_M Core" "0: Inactive value,1: Request asserted"
newline
bitfld.long 0x00 29. "M7_1_DBGRSTRT,Debug Restart Input To Cortex-M7_1 Core" "0: Inactive value,1: Request asserted"
newline
bitfld.long 0x00 28. "M7_0_DBGRSTRT,Debug Restart Input To Cortex-M7_0 Core" "0: Inactive value,1: Request asserted"
newline
bitfld.long 0x00 24. "MSK_FCCU_RST_TRIGGER,Mask FCCU Reset Trigger" "0: Not masked,1: MASKED"
newline
bitfld.long 0x00 23. "MSK_DBG_FAULT,Mask Debug Fault" "0: Not masked,1: MASKED"
newline
bitfld.long 0x00 21. "ETR_OVERRIDE,ETR Override" "0: Not overridden and ETR generates the trace..,1: Overridden"
newline
bitfld.long 0x00 20. "TPIU_OVERRIDE,TPIU Override" "0: Not overridden and the TPIU generates the..,1: Overridden and forced asserted"
newline
bitfld.long 0x00 17. "DSP0_OCDHALTONRESET,OCD Halt On Reset" "0,1"
newline
bitfld.long 0x00 16. "CA53_A_EDBGREQ,Cortex-A53 Core EDBGREQ" "0: Inactive value,1: Request asserted to place the core in Debug.."
newline
bitfld.long 0x00 15. "DIS_POR_WDOG_MSK,Disable POR Watchdog Masking" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 13. "MSK_LOCKSTEP_ALARM_CM7_1,Mask Lockstep Alarm For Cortex-M7_1 Core" "0: Disables masking,1: Enables masking"
newline
bitfld.long 0x00 12. "MSK_LOCKSTEP_ALARM_CM7_0,Mask Lockstep Alarm For Cortex-M7_0 Core" "0: Disables masking,1: Enables masking"
newline
bitfld.long 0x00 11. "CM7_HSE_EDBGREQ,HSE_M Cortex-M7_1 Core EDBGREQ" "0: Inactive value,1: Request asserted to place the core in Debug.."
newline
bitfld.long 0x00 9. "CM7_1_EDBGREQ,Cortex-M7_1 Core EDBGREQ" "0: Inactive value,1: Request asserted to place the core in Debug.."
newline
bitfld.long 0x00 8. "CM7_0_EDBGREQ,Cortex-M7_0 Core EDBGREQ" "0: Inactive value,1: Request asserted to place the core in Debug.."
newline
bitfld.long 0x00 7. "ETR_HANDSHAKE_1,ETR Handshake 1" "0: Inactive value,1: Enables ETR"
newline
bitfld.long 0x00 6. "ETR_HANDSHAKE_0,ETR Handshake 0" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 5. "SYSFUNCRST,System Functional Reset" "0: D_ASSERT,1: ASSERT"
newline
bitfld.long 0x00 4. "SYSDESTRST,System Destructive Reset" "0: D_ASSERT,1: ASSERT"
newline
bitfld.long 0x00 3. "DBG_SETUP_DONE,Boot ROM Debugger Handshake" "0: Inactive value,1: Debug setup complete"
rgroup.long 0x40++0x03
line.long 0x00 "STATUS_1,Status 1"
bitfld.long 0x00 25. "DSP_DEBUGMODE,DSP DEBUGMODE" "0,1"
newline
bitfld.long 0x00 24. "DSP_XOCDMODE,DSP XOCDMODE" "0,1"
newline
bitfld.long 0x00 8. "CA53_A_WFE,Cortex-A53 Core A WFE" "0: Core not in WFE low-power state,1: Core in WFE low-power state"
newline
bitfld.long 0x00 4. "CA53_A_WFI,Cortex-A53 Core A WFI" "0: Core not in WFI low-power state,1: Core in WFI low-power state"
newline
bitfld.long 0x00 0. "CA53_A_DBGMODE,Cortex-A53 Core A Debug Mode" "0: External debug request not acknowledged,1: External debug request acknowledged"
group.long 0x70++0x03
line.long 0x00 "CORTEX_A53_IP_DBG,Cortex-A53 Core Debug"
bitfld.long 0x00 0. "CA53_IP_DBGDIS,Cortex-A53 Core IP Debug" "0: Modules also enter Debug mode,1: Modules do not enter Debug mode"
group.long 0x78++0x03
line.long 0x00 "HSE_CORTEX_M7_IP_DBG,HSE_M Cortex-M7 Core Debug"
bitfld.long 0x00 0. "CM7_HSE_IP_DBGDIS,Cortex-M7_HSE_M Core IP Debug" "0: Modules also enter Debug mode,1: Modules do not enter Debug mode"
group.long 0x80++0x03
line.long 0x00 "CORTEX_M7_0_IP_DBG,Cortex-M7_0 Core IP Debug"
bitfld.long 0x00 0. "CM7_0_IP_DBGDIS,Cortex-M7_0 Core IP Debug" "0: Modules also enter Debug mode,1: Modules do not enter Debug mode"
group.long 0x88++0x03
line.long 0x00 "CORTEX_M7_1_IP_DBG,Cortex-M7_1 Core IP Debug"
bitfld.long 0x00 0. "CM7_1_IP_DBGDIS,Cortex-M7_1 Core IP Debug" "0: Modules also enter Debug mode,1: Modules do not enter Debug mode"
group.long 0x90++0x03
line.long 0x00 "BBE32DSP_IP_DBG,BBE32DSP Debug"
bitfld.long 0x00 0. "BBE32DSP_IP_DBGDIS,BBE32DSP IP Debug" "0: Modules also enter Debug mode,1: Modules do not enter Debug mode"
rgroup.long 0xFC++0x03
line.long 0x00 "MDM_AP_ID,MDM_AP Identification"
hexmask.long 0x00 0.--31. 1. "ID,MDM_AP Identity"
tree.end
tree "MIPICSI2"
tree "MIPICSI2_0"
base ad:0x44094000
group.long 0x00++0x03
line.long 0x00 "DPHY_RSTCFG,DPHY Reset Configuration"
bitfld.long 0x00 1. "RSTZ,This field puts the digital portion of DPHY under reset" "0: Digital portion of DPHY in reset,1: Digital portion of DPHY out of reset"
newline
bitfld.long 0x00 0. "SHUTDWNZ,This field puts the entire DPHY under reset" "0: DPHY in reset (including digital portion),1: DPHY out of reset (including digital portion)"
group.long 0x08++0x03
line.long 0x00 "DPHY_CLEAR,DPHY Clear"
bitfld.long 0x00 0. "CLRREG,This field is used for clearing the DPHY register space before any configuration is performed" "0: DPHY registers are out of reset,1: DPHY registers in reset"
group.long 0x0C++0x03
line.long 0x00 "DPHY_FREQCFG,DPHY Frequency Configuration"
hexmask.long.byte 0x00 7.--14. 1. "CLKFREQRNG,This field allows configuring the system clock frequency configuration preset"
newline
hexmask.long.byte 0x00 0.--6. 1. "HSFREQRNG,This field allows selection of operating frequency range for the DPHY"
group.long 0x18++0x03
line.long 0x00 "RX_RXNULANE,Receive Number of Lanes Configuration"
bitfld.long 0x00 0.--3. "RXNULANE,Number of data lanes enabled for high-speed MIPICSI2 data reception" "0: Controller off,1: High-speed data reception on lane 0 only,2: High-speed data reception on lanes 0 and 1,3: High-speed data reception on lanes 0 1 and 2,4: High-speed data reception on all data lanes,?..."
group.long 0x1C++0x03
line.long 0x00 "RX_RXENABLE,Receive Enable Configuration"
bitfld.long 0x00 5.--8. "CFG_FLUSH_CNT,This field is used to program the FIFO flush count in different speeds of operation in the receive controller" "?,?,?,3: For data rates greater than 200 MHz,?,?,?,7: For data rates up to 200 MHz,?..."
newline
bitfld.long 0x00 1.--4. "CFG_DATA_LANE_EN,Enables the PHY Data Lanes" "?,1: Enable lane 0 of the DPHY,2: Enable lane 1 of the DPHY,?,4: Enable lane 2 of the DPHY,?,?,?,8: Enable lane 3 of the DPHY,?..."
newline
bitfld.long 0x00 0. "CFG_CLK_LANE_EN,Enables the PHY Clock Lane" "0: Clock lane is not enabled,1: Clock lane is enabled"
group.long 0x20++0x03
line.long 0x00 "RX_RXLANESWAP,Receive Lane Swap Configuration"
bitfld.long 0x00 6.--7. "O_CFG_LANE3_SEL,Selects the PPI interface lane that is used as lane 3 by the RX core" "0: O_CFG_LANE3_SEL_0,1: O_CFG_LANE3_SEL_1,2: O_CFG_LANE3_SEL_2,3: O_CFG_LANE3_SEL_3"
newline
bitfld.long 0x00 4.--5. "O_CFG_LANE2_SEL,Selects the PPI interface lane that is used as lane 2 by the RX core" "0: O_CFG_LANE2_SEL_0,1: O_CFG_LANE2_SEL_1,2: O_CFG_LANE2_SEL_2,3: O_CFG_LANE2_SEL_3"
newline
bitfld.long 0x00 2.--3. "O_CFG_LANE1_SEL,Selects the PPI interface lane that is used as lane 1 by the RX core" "0: O_CFG_LANE1_SEL_0,1: O_CFG_LANE1_SEL_1,2: O_CFG_LANE1_SEL_2,3: O_CFG_LANE1_SEL_3"
newline
bitfld.long 0x00 0.--1. "O_CFG_LANE0_SEL,Selects the PPI interface lane that is used as lane 0 by the RX core" "0: O_CFG_LANE0_SEL_0,1: O_CFG_LANE0_SEL_1,2: O_CFG_LANE0_SEL_2,3: O_CFG_LANE0_SEL_3"
rgroup.long 0x24++0x03
line.long 0x00 "RX_CLKCS,Clock Configuration Status"
bitfld.long 0x00 4. "CULPMA,Clock Lane ULPS Mark Active State" "0: Clock lane not in Mark-1 active state,1: Clock lane is in Mark-1 active state"
newline
bitfld.long 0x00 3. "CULPSA,Clock Lane ULPS Active" "0: Clock lane not in ULPS mode,1: Clock lane in ULPS mode"
newline
bitfld.long 0x00 2. "CSTOP,Clock Lane Stop State" "0: Clock lane not in stop state,1: Clock lane in stop state"
newline
bitfld.long 0x00 1. "ULPSC,Clock Lane ULPS" "0: Clock lane not in the ULP state,1: Clock lane in ultra in the ULP state"
newline
bitfld.long 0x00 0. "HSRA,High-Speed Clock Receive Active" "0: DDR clock not being received on the clock lane,1: Clock lane is receiving DDR clock"
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x28)++0x03
line.long 0x00 "RX_LANCS[$1],D-PHY Lane i Configuration Status $1"
bitfld.long 0x00 5. "DULMA,Data Lane ULPS Mark Active" "0: Data lane 0 is not in Mark-1 state,1: Data lane 0 is in Mark-1 state"
newline
bitfld.long 0x00 4. "DULPA,Data Lane ULPS Active" "0: Data lane 0 ULPS not active,1: Data lane 0 ULPS is active"
newline
bitfld.long 0x00 3. "DSTOP,Data Lane Stop State" "0: Data lane 0 not in the Stop state,1: Data lane 0 in the Stop state"
newline
bitfld.long 0x00 1. "RXACTH,D-PHY Data Lane 0 RX Active High-Speed Data" "0: No high-speed data reception ongoing from the..,1: High-speed data reception ongoing from lane.."
newline
bitfld.long 0x00 0. "RXVALH,Data Lane 0 RX Valid High Speed" "0: No valid high-speed data is being driven from..,1: Valid high-speed data is being driven from.."
repeat.end
group.long 0x38++0x03
line.long 0x00 "RX_SR,Soft Reset Config"
bitfld.long 0x00 31. "SOFRST,Software Reset" "0: Soft reset not requested,1: Soft reset requested"
group.long 0x3C++0x03
line.long 0x00 "RX_VCENABLE,Receive Virtual Channel and circular Buffer Enable Configuration"
bitfld.long 0x00 19. "CBUF11EN,Enable Reception of Data Corresponding to Circular buffer 11" "0: Circular buffer 11 data reception disabled,1: Circular buffer 11 data reception enabled"
newline
bitfld.long 0x00 18. "CBUF10EN,Enable Reception of Data Corresponding to Circular buffer 10" "0: Circular buffer 10 data reception disabled,1: Circular buffer 10 data reception enabled"
newline
bitfld.long 0x00 17. "CBUF9EN,Enable Reception of Data Corresponding to Circular buffer 9" "0: Circular buffer 9 data reception disabled,1: Circular buffer 9 data reception enabled"
newline
bitfld.long 0x00 16. "CBUF8EN,Enable Reception of Data Corresponding to Circular buffer 8" "0: Circular buffer 8 data reception disabled,1: Circular buffer 8 data reception enabled"
newline
bitfld.long 0x00 15. "CBUF7EN,Enable Reception of Data Corresponding to Circular buffer 7" "0: Circular buffer 7 data reception disabled,1: Circular buffer 7 data reception enabled"
newline
bitfld.long 0x00 14. "CBUF6EN,Enable Reception of Data Corresponding to Circular buffer 6" "0: Circular buffer 6 data reception disabled,1: Circular buffer 6 data reception enabled"
newline
bitfld.long 0x00 13. "CBUF5EN,Enable Reception of Data Corresponding to Circular buffer 5" "0: Circular buffer 5 data reception disabled,1: Circular buffer 5 data reception enabled"
newline
bitfld.long 0x00 12. "CBUF4EN,Enable Reception of Data Corresponding to Circular buffer 4" "0: Circular buffer 4 data reception disabled,1: Circular buffer 4 data reception enabled"
newline
bitfld.long 0x00 11. "CBUF3EN,Enable Reception of Data Corresponding to Circular buffer 3" "0: Circular buffer 3 data reception disabled,1: Circular buffer 3 data reception enabled"
newline
bitfld.long 0x00 10. "CBUF2EN,Enable Reception of Data Corresponding to Circular buffer 2" "0: Circular buffer 2 data reception disabled,1: Circular buffer 2 data reception enabled"
newline
bitfld.long 0x00 9. "CBUF1EN,Enable Reception of Data Corresponding to Circular buffer 1" "0: Circular buffer 1 data reception disabled,1: Circular buffer 1 data reception enabled"
newline
bitfld.long 0x00 8. "CBUF0EN,Enable Reception of Data Corresponding to Circular buffer 0" "0: Circular buffer 0 data reception disabled,1: Circular buffer 0 data reception enabled"
newline
bitfld.long 0x00 3. "VC3EN,Enable Reception of Data Corresponding to Virtual Channel 3" "0: Virtual channel 3 data reception disabled,1: Virtual channel 3 data reception enabled"
newline
bitfld.long 0x00 2. "VC2EN,Enable Reception of Data Corresponding to Virtual Channel 2" "0: Virtual channel 2 data reception disabled,1: Virtual channel 2 data reception enabled"
newline
bitfld.long 0x00 1. "VC1EN,Enable Reception of Data Corresponding to Virtual Channel 1" "0: Virtual channel 1 data reception disabled,1: Virtual channel 1 data reception enabled"
newline
bitfld.long 0x00 0. "VC0EN,Enable Reception of Data Corresponding to Virtual Channel 0" "0: Virtual channel 0 data reception disabled,1: Virtual channel 0 data reception enabled"
rgroup.long 0x40++0x03
line.long 0x00 "RX_DATAIDR,Receive Data ID Report"
bitfld.long 0x00 6.--7. "VCID,Virtual channel ID being received currently over MIPICSI2 data lanes" "0: MIPICSI2 packet data being received currently..,1: MIPICSI2 packet data being received currently..,2: MIPICSI2 packet data being received currently..,3: MIPICSI2 packet data being received currently.."
newline
bitfld.long 0x00 0.--5. "DATAID,Data ID of MIPICSI2 Data" "0: Frame start packet being received,1: Frame end packet being received,2: Line start packet being received,3: Line end packet being received,?,?,?,?,8: Generic short packet being received,9: Generic short packet being received,10: Generic short packet being received,11: Generic short packet being received,12: Generic short packet being received,13: Generic short packet being received,?,?,16: Null packet being received,17: Blanking packet being received,18: Embedded packet being received,?,?,?,?,?,?,?,?,?,?,?,30: YUV 422,31: YUV 422,?,?,34: RGB 565 packet being received,?,36: RGB 888 packet being received,?,?,?,?,?,42: RAW 8 packet being received,43: RAW 10 packet being received,44: RAW 12 packet being received,45: RAW 14 packet being received,46: RAW 16 packet being received,?..."
rgroup.long 0x4C++0x03
line.long 0x00 "RX_INVIDR,Receive Invalid Data ID Report"
bitfld.long 0x00 6.--7. "VCID,Virtual channel ID being received currently over MIPICSI2 data lanes" "0: MIPICSI2 packet data being received currently..,1: MIPICSI2 packet data being received currently..,2: MIPICSI2 packet data being received currently..,3: MIPICSI2 packet data being received currently.."
newline
bitfld.long 0x00 0.--5. "DATAID,Unsupported Data ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x50)++0x03
line.long 0x00 "RX_GNSPR_VC[$1],Receive Generic Short Packet Report $1"
hexmask.long.word 0x00 6.--21. 1. "DATA,Data content of the generic short packet being received for processing by the application"
newline
bitfld.long 0x00 0.--5. "DATAID,Data ID of the generic short packet being received currently" "?,?,?,?,?,?,?,?,8: Data ID of the generic packet being received,9: Data ID of the generic packet being received,10: Data ID of the generic packet being received,11: Data ID of the generic packet being received,12: Data ID of the generic packet being received,13: Data ID of the generic packet being received,14: Data ID of the generic packet being received,15: Data ID of the generic packet being received,?..."
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x60)++0x03
line.long 0x00 "RX_NUMPKTS_VC[$1],Receive Number of Packets for VC $1"
hexmask.long.word 0x00 16.--31. 1. "LONGPKTS,Number of Long Packets Received"
newline
hexmask.long.word 0x00 0.--15. 1. "SHORTPKTS,Number of Short Packets Received"
repeat.end
group.long 0x70++0x03
line.long 0x00 "RX_VCINTRS,Receive VC Data Interrupt Status"
eventfld.long 0x00 15. "CRC_CAPTURED3,MIPI protocol received CRC for the configured data type line is available in the register" "0,1"
newline
eventfld.long 0x00 14. "CRC_CAPTURED2,MIPI protocol received CRC for the configured data type line is available in the register" "0,1"
newline
eventfld.long 0x00 13. "CRC_CAPTURED1,MIPI protocol received CRC for the configured data type line is available in the register" "0,1"
newline
eventfld.long 0x00 12. "CRC_CAPTURED0,MIPI protocol received CRC for the configured data type line is available in the register" "0,1"
newline
eventfld.long 0x00 11. "GNSP3,Generic Short Packet Received on Virtual Channel 3" "0,1"
newline
eventfld.long 0x00 10. "FE3,Frame End on Virtual Channel 3" "0,1"
newline
eventfld.long 0x00 9. "FS3,Frame Start on Virtual Channel 3" "0,1"
newline
eventfld.long 0x00 8. "GNSP2,Generic Short Packet Received on Virtual Channel 2" "0,1"
newline
eventfld.long 0x00 7. "FE2,Frame End on Virtual Channel 2" "0,1"
newline
eventfld.long 0x00 6. "FS2,Frame Start on Virtual Channel 2" "0,1"
newline
eventfld.long 0x00 5. "GNSP1,Generic Short Packet Received on Virtual Channel 1" "0,1"
newline
eventfld.long 0x00 4. "FE1,Frame End on Virtual Channel 1" "0,1"
newline
eventfld.long 0x00 3. "FS1,Frame Start on Virtual Channel 1" "0,1"
newline
eventfld.long 0x00 2. "GNSP0,Generic Short Packet Received on Virtual Channel 0" "0,1"
newline
eventfld.long 0x00 1. "FE0,Frame End on Virtual Channel 0" "0,1"
newline
eventfld.long 0x00 0. "FS0,Frame Start on Virtual Channel 0" "0,1"
group.long 0x74++0x03
line.long 0x00 "RX_VCINTRE,Receive Data VC Event Interrupt Enable"
bitfld.long 0x00 15. "CRC_CAPTUREDIE3,Interrupt enable for receiving interrupt on receiving CRC for the configured data type" "0,1"
newline
bitfld.long 0x00 14. "CRC_CAPTUREDIE2,Interrupt enable for receiving interrupt on receiving CRC for the configured data type" "0,1"
newline
bitfld.long 0x00 13. "CRC_CAPTUREDIE1,Interrupt enable for receiving interrupt on receiving CRC for the configured data type" "0,1"
newline
bitfld.long 0x00 12. "CRC_CAPTUREDIE0,Interrupt enable for receiving interrupt on receiving CRC for the configured data type" "0,1"
newline
bitfld.long 0x00 11. "GNSPIE3,Generic Short Packet Received on Virtual Channel 3 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 10. "FEIE3,Frame End on Virtual Channel 3 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 9. "FSIE3,Frame Start on Virtual Channel 3 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 8. "GNSPIE2,Generic Short Packet Received on Virtual Channel 2 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 7. "FEIE2,Frame End on Virtual Channel 2 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 6. "FSIE2,Frame Start on Virtual Channel 2 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 5. "GNSPIE1,Generic Short Packet Received on Virtual Channel 1 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 4. "FEIE1,Frame End on Virtual Channel 1 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 3. "FSIE1,Frame Start on Virtual Channel 1 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 2. "GNSPIE0,Generic Short Packet Received on Virtual Channel 0 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 1. "FEIE0,Frame End on Virtual Channel 0 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 0. "FSIE0,Frame Start on Virtual Channel 0 Interrupt Enable" "0,1"
rgroup.long 0x90++0x03
line.long 0x00 "CONTROLLER_STATUS_REGISTER,Controller Status"
bitfld.long 0x00 0.--5. "ECC_RECEIVED,This field reports the ECC value received at the controller end" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x98++0x03
line.long 0x00 "CONTROLLER_ERR_STATUS_REGISTER,Controller Error Status"
eventfld.long 0x00 1. "FIFO_OVERFLOW_ERROR,This field indicates overflow of the internal FIFO in the controller" "0,1"
newline
eventfld.long 0x00 0. "EXIT_HS_ERROR,Asserted at the end of the packet by the controller to indicate that the PHY has stopped high speed transmission before the number of required bytes have been received" "0,1"
group.long 0x9C++0x03
line.long 0x00 "CONTROLLER_ERR_IE,Controller Interrupt Enable"
bitfld.long 0x00 1. "HS_EXIT_ERRIE,Enables the interrupt for the High speed exit error reporting to the system" "0,1"
newline
bitfld.long 0x00 0. "FIFO_OVERFLOW_ERRIE,Enables the interrupt for the FIFO overflow error reporting to the system" "0,1"
group.long 0xE4++0x03
line.long 0x00 "RX_PHYERRIS,Receive Data PHY Level Error Interrupt Status"
eventfld.long 0x00 19. "ERCTRL3,Control Command Error on Lane 3" "0,1"
newline
eventfld.long 0x00 18. "ERSYES3,Synchronization Error in Escape Mode on Lane 3" "0,1"
newline
eventfld.long 0x00 17. "ERRESC3,Escape Mode Entry Error on Lane 3" "0,1"
newline
eventfld.long 0x00 16. "NOSYN3,Multi-Bit Error in Synchronization Pattern Detected on Lane 3" "0,1"
newline
eventfld.long 0x00 15. "ERRSY3,Error in Synchronization Pattern Detected on Lane 3" "0,1"
newline
eventfld.long 0x00 14. "ERCTRL2,Control Command Error on Lane 2" "0,1"
newline
eventfld.long 0x00 13. "ERSYES2,Synchronization Error in Escape Mode on Lane 2" "0,1"
newline
eventfld.long 0x00 12. "ERRESC2,Escape Mode Entry Error on Lane 2" "0,1"
newline
eventfld.long 0x00 11. "NOSYN2,Multi-Bit Error in Synchronization Pattern Detected on Lane 2" "0,1"
newline
eventfld.long 0x00 10. "ERRSY2,Error in Synchronization Pattern Detected on Lane 2" "0,1"
newline
eventfld.long 0x00 9. "ERCTRL1,Control Command Error on Lane 1" "0,1"
newline
eventfld.long 0x00 8. "ERSYES1,Synchronization Error in Escape Mode on Lane 1" "0,1"
newline
eventfld.long 0x00 7. "ERRESC1,Escape Mode Entry Error on Lane 1" "0,1"
newline
eventfld.long 0x00 6. "NOSYN1,Multi-Bit Error in Synchronization Pattern Detected on Lane 1" "0,1"
newline
eventfld.long 0x00 5. "ERRSY1,Error in Synchronization Pattern Detected on Lane 1" "0,1"
newline
eventfld.long 0x00 4. "ERCTRL0,Control Command Error on Lane 0" "0,1"
newline
eventfld.long 0x00 3. "ERSYES0,Synchronization Error in Escape Mode on Lane 0" "0,1"
newline
eventfld.long 0x00 2. "ERRESC0,Escape Mode Entry Error on Lane 0" "0,1"
newline
eventfld.long 0x00 1. "NOSYN0,Multi-Bit Error in Synchronization Pattern Detected on Lane 0" "0,1"
newline
eventfld.long 0x00 0. "ERRSY0,Error in Synchronization Pattern Detected on Lane 0" "0,1"
group.long 0xE8++0x03
line.long 0x00 "RX_PHYERRIE,Receive Data PHY Level Error Interrupt Enable"
bitfld.long 0x00 19. "ERCTRLIE3,Control Command Error on Lane 3 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 18. "ERSYESIE3,Synchronization Error in Escape Mode on Lane 3 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 17. "ERRESCIE3,Escape Mode Entry Error on Lane 3 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 16. "NOSYNIE3,Multi-Bit Error in Synchronization Pattern on Lane 3 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 15. "ERRSYIE3,Error in Synchronization Pattern on Lane 3 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 14. "ERCTRLIE2,Control Command Error on Lane 2 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 13. "ERSYESIE2,Synchronization Error in Escape Mode on Lane 2 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 12. "ERRESCIE2,Escape Mode Entry Error on Lane 2 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 11. "NOSYNIE2,Multi-Bit Error in Synchronization Pattern on Lane 2 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 10. "ERRSYIE2,Error in Synchronization Pattern on Lane 2 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 9. "ERCTRLIE1,Control Command Error on Lane 1 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 8. "ERSYESIE1,Synchronization Error in Escape Mode on Lane 1 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 7. "ERRESCIE1,Escape Mode Entry Error on Lane 1 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 6. "NOSYNIE1,Multi-Bit Error in Synchronization Pattern on Lane 1 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 5. "ERRSYIE1,Error in Synchronization Pattern on Lane 1 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 4. "ERCTRLIE0,Control Command Error on Lane 0 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 3. "ERSYESIE0,Synchronization Error in Escape Mode on Lane 0 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 2. "ERRESCIE0,Escape Mode Entry Error on Lane 0 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 1. "NOSYNIE0,Multi-Bit Error in Synchronization Pattern on Lane 0 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 0. "ERRSYIE0,Error in Synchronization Pattern on Lane 0 Interrupt Enabled" "0,1"
group.long 0xF0++0x03
line.long 0x00 "RX_VC_CBUF_DIS_IE,Receive Virtual channel and Circular Buffer Disabled interrupt Enable"
bitfld.long 0x00 19. "CBUF11_DIS_IE,Circular Buffer 11 Disabled Interrupt Enable" "0: Circular Buffer 11 Disabled Interrupt Disable,1: Circular Buffer 11 Disabled Interrupt Enable"
newline
bitfld.long 0x00 18. "CBUF10_DIS_IE,Circular Buffer 10 Disabled Interrupt Enable" "0: Circular Buffer 10 Disabled Interrupt Disable,1: Circular Buffer 10 Disabled Interrupt Enable"
newline
bitfld.long 0x00 17. "CBUF9_DIS_IE,Circular Buffer 9 Disabled Interrupt Enable" "0: Circular Buffer 9 Disabled Interrupt Disable,1: Circular Buffer 9 Disabled Interrupt Enable"
newline
bitfld.long 0x00 16. "CBUF8_DIS_IE,Circular Buffer 8 Disabled Interrupt Enable" "0: Circular Buffer 8 Disabled Interrupt Disable,1: Circular Buffer 8 Disabled Interrupt Enable"
newline
bitfld.long 0x00 15. "CBUF7_DIS_IE,Circular Buffer 7 Disabled Interrupt Enable" "0: Circular Buffer 7 Disabled Interrupt Disable,1: Circular Buffer 7 Disabled Interrupt Enable"
newline
bitfld.long 0x00 14. "CBUF6_DIS_IE,Circular Buffer 6 Disabled Interrupt Enable" "0: Circular Buffer 6 Disabled Interrupt Disable,1: Circular Buffer 6 Disabled Interrupt Enable"
newline
bitfld.long 0x00 13. "CBUF5_DIS_IE,Circular Buffer 5 Disabled Interrupt Enable" "0: Circular Buffer 5 Disabled Interrupt Disable,1: Circular Buffer 5 Disabled Interrupt Enable"
newline
bitfld.long 0x00 12. "CBUF4_DIS_IE,Circular Buffer 4 Disabled Interrupt Enable" "0: Circular Buffer 4 Disabled Interrupt Disable,1: Circular Buffer 4 Disabled Interrupt Enable"
newline
bitfld.long 0x00 11. "CBUF3_DIS_IE,Circular Buffer 3 Disabled Interrupt Enable" "0: Circular Buffer 3 Disabled Interrupt Disable,1: Circular Buffer 3 Disabled Interrupt Enable"
newline
bitfld.long 0x00 10. "CBUF2_DIS_IE,Circular Buffer 2 Disabled Interrupt Enable" "0: Circular Buffer 2 Disabled Interrupt Disable,1: Circular Buffer 2 Disabled Interrupt Enable"
newline
bitfld.long 0x00 9. "CBUF1_DIS_IE,Circular Buffer 1 Disabled Interrupt Enable" "0: Circular Buffer 1 Disabled Interrupt Disable,1: Circular Buffer 1 Disabled Interrupt Enable"
newline
bitfld.long 0x00 8. "CBUF0_DIS_IE,Circular Buffer 0 Disabled Interrupt Enable" "0: Circular Buffer 0 Disabled Interrupt Disable,1: Circular Buffer 0 Disabled Interrupt Enable"
newline
bitfld.long 0x00 3. "VC3_DIS_IE,Virtual Channel 3 Disabled Interrupt Enable" "0: Virtual Channel 3 Disabled Interrupt Disable,1: Virtual Channel 3 Disabled Interrupt Enable"
newline
bitfld.long 0x00 2. "VC2_DIS_IE,Virtual Channel 2 Disabled Interrupt Enable" "0: Virtual Channel 2 Disabled Interrupt Disable,1: Virtual Channel 2 Disabled Interrupt Enable"
newline
bitfld.long 0x00 1. "VC1_DIS_IE,Virtual Channel 1 Disabled Interrupt Enable" "0: Virtual Channel 1 Disabled Interrupt Disable,1: Virtual Channel 1 Disabled Interrupt Enable"
newline
bitfld.long 0x00 0. "VC0_DIS_IE,Virtual Channel 0 Disabled Interrupt Enable" "0: Virtual Channel 0 Disabled Interrupt Disable,1: Virtual Channel 0 Disabled Interrupt Enable"
group.long 0xF4++0x03
line.long 0x00 "RX_VC_CBUF_DIS_STAT,Receive Virtual Channel and Circular Buffer Disabled Status"
eventfld.long 0x00 19. "CBUF11_DIS,Buffer Disabled Status for Circular Buffer 11" "0,1"
newline
eventfld.long 0x00 18. "CBUF10_DIS,Buffer Disabled Status for Circular Buffer 10" "0,1"
newline
eventfld.long 0x00 17. "CBUF9_DIS,Buffer Disabled Status for Circular Buffer 9" "0,1"
newline
eventfld.long 0x00 16. "CBUF8_DIS,Buffer Disabled Status for Circular Buffer 8" "0,1"
newline
eventfld.long 0x00 15. "CBUF7_DIS,Buffer Disabled Status for Circular Buffer 7" "0,1"
newline
eventfld.long 0x00 14. "CBUF6_DIS,Buffer Disabled Status for Circular Buffer 6" "0,1"
newline
eventfld.long 0x00 13. "CBUF5_DIS,Buffer Disabled Status for Circular Buffer 5" "0,1"
newline
eventfld.long 0x00 12. "CBUF4_DIS,Buffer Disabled Status for Circular Buffer 4" "0,1"
newline
eventfld.long 0x00 11. "CBUF3_DIS,Buffer Disabled Status for Circular Buffer 3" "0,1"
newline
eventfld.long 0x00 10. "CBUF2_DIS,Buffer Disabled Status for Circular Buffer 2" "0,1"
newline
eventfld.long 0x00 9. "CBUF1_DIS,Buffer Disabled Status for Circular Buffer 1" "0,1"
newline
eventfld.long 0x00 8. "CBUF0_DIS,Buffer Disabled Status for Circular Buffer 0" "0,1"
newline
eventfld.long 0x00 3. "VC3_DIS,Channel Disabled Status for Virtual Channel 3" "0,1"
newline
eventfld.long 0x00 2. "VC2_DIS,Channel Disabled Status for Virtual Channel 2" "0,1"
newline
eventfld.long 0x00 1. "VC1_DIS,Channel Disabled Status for Virtual Channel 1" "0,1"
newline
eventfld.long 0x00 0. "VC0_DIS,Channel Disabled Status for Virtual Channel 0" "0,1"
group.long 0xFC++0x03
line.long 0x00 "RX_STAT_CONFIG,Receive Data Statistical Computation Configuration"
bitfld.long 0x00 0. "STATEN,This field enables statistical computation on incoming raw data" "0: Statistical computation of raw data disabled,1: Statistical computation of raw data enabled"
group.long 0x400++0x03
line.long 0x00 "CBUF_INTRS,Receive Data Circular Buffer Error Interrupt Status"
eventfld.long 0x00 23. "LINCNTERR11,Line Count Error Indication for Circular Buffer 11" "0,1"
newline
eventfld.long 0x00 22. "LINLENERR11,Line Length Error Indication for Circular Buffer 11" "0,1"
newline
eventfld.long 0x00 21. "LINCNTERR10,Line Count Error Indication for Circular Buffer 10" "0,1"
newline
eventfld.long 0x00 20. "LINLENERR10,Line Length Error Indication for Circular Buffer 10" "0,1"
newline
eventfld.long 0x00 19. "LINCNTERR9,Line Count Error Indication for Circular Buffer 9" "0,1"
newline
eventfld.long 0x00 18. "LINLENERR9,Line Length Error Indication for Circular Buffer 9" "0,1"
newline
eventfld.long 0x00 17. "LINCNTERR8,Line Count Error Indication for Circular Buffer 8" "0,1"
newline
eventfld.long 0x00 16. "LINLENERR8,Line Length Error Indication for Circular Buffer 8" "0,1"
newline
eventfld.long 0x00 15. "LINCNTERR7,Line Count Error Indication for Circular Buffer 7" "0,1"
newline
eventfld.long 0x00 14. "LINLENERR7,Line Length Error Indication for Circular Buffer 7" "0,1"
newline
eventfld.long 0x00 13. "LINCNTERR6,Line Count Error Indication for Circular Buffer 6" "0,1"
newline
eventfld.long 0x00 12. "LINLENERR6,Line Length Error Indication for Circular Buffer 6" "0,1"
newline
eventfld.long 0x00 11. "LINCNTERR5,Line Count Error Indication for Circular Buffer 5" "0,1"
newline
eventfld.long 0x00 10. "LINLENERR5,Line Length Error Indication for Circular Buffer 5" "0,1"
newline
eventfld.long 0x00 9. "LINCNTERR4,Line Count Error Indication for Circular Buffer 4" "0,1"
newline
eventfld.long 0x00 8. "LINLENERR4,Line Length Error Indication for Circular Buffer 4" "0,1"
newline
eventfld.long 0x00 7. "LINCNTERR3,Line Count Error Indication for Circular Buffer 3" "0,1"
newline
eventfld.long 0x00 6. "LINLENERR3,Line Length Error Indication for Circular Buffer 3" "0,1"
newline
eventfld.long 0x00 5. "LINCNTERR2,Line Count Error Indication for Circular Buffer 2" "0,1"
newline
eventfld.long 0x00 4. "LINLENERR2,Line Length Error Indication for Circular Buffer 2" "0,1"
newline
eventfld.long 0x00 3. "LINCNTERR1,Line Count Error Indication for Circular Buffer 1" "0,1"
newline
eventfld.long 0x00 2. "LINLENERR1,Line Length Error Indication for Circular Buffer 1" "0,1"
newline
eventfld.long 0x00 1. "LINCNTERR0,Line Count Error Indication for Circular Buffer 0" "0,1"
newline
eventfld.long 0x00 0. "LINLENERR0,Line Length Error Indication for Circular Buffer 0" "0,1"
group.long 0x404++0x03
line.long 0x00 "CBUF_INTRE,Receive Circular Buffer Error Interrupt Enable"
bitfld.long 0x00 23. "LINCNTIE11,Line Count Error on Circular Buffer 11 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 22. "LINLENIE11,Line Length Error on Circular Buffer 11 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 21. "LINCNTIE10,Line Count Error on Circular Buffer 10 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 20. "LINLENIE10,Line Length Error on Circular Buffer 10 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 19. "LINCNTIE9,Line Count Error on Circular Buffer 9 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 18. "LINLENIE9,Line Length Error on Circular Buffer 9 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 17. "LINCNTIE8,Line Count Error on Circular Buffer 8 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 16. "LINLENIE8,Line Length Error on Circular Buffer 8 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 15. "LINCNTIE7,Line Count Error on Circular Buffer 7 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 14. "LINLENIE7,Line Length Error on Circular Buffer 7 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 13. "LINCNTIE6,Line Count Error on Circular Buffer 6 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 12. "LINLENIE6,Line Length Error on Circular Buffer 6 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 11. "LINCNTIE5,Line Count Error on Circular Buffer 5 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 10. "LINLENIE5,Line Length Error on Circular Buffer 5 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 9. "LINCNTIE4,Line Count Error on Circular Buffer 4 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 8. "LINLENIE4,Line Length Error on Circular Buffer 4 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 7. "LINCNTIE3,Line Count Error on Circular Buffer 3 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 6. "LINLENIE3,Line Length Error on Circular Buffer 3 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 5. "LINCNTIE2,Line Count Error on Circular Buffer 2 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 4. "LINLENIE2,Line Length Error on Circular Buffer 2 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 3. "LINCNTIE1,Line Count Error on Circular Buffer 1 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 2. "LINLENIE1,Line Length Error on Circular Buffer 1 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 1. "LINCNTIE0,Line Count Error on Circular Buffer 0 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 0. "LINLENIE0,Line Length Error on Circular Buffer 0 Interrupt Enable" "0,1"
repeat 4. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x410)++0x03
line.long 0x00 "RX_DROPDATAR[$1],Received Drop Data Type and VC Report $1"
bitfld.long 0x00 30.--31. "DROPVCID3,VCID Dropped" "0: VC0 data dropped,1: VC1 data dropped,2: VC2 data dropped,3: VC3 data dropped"
newline
bitfld.long 0x00 24.--29. "DROPDATAID3,Data ID Dropped" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,18: Embedded packet dropped,?,?,?,?,?,?,?,?,?,?,?,30: YUV 422,31: YUV 422,?,?,34: RGB 565 packet dropped,?,36: RGB 888 packet dropped,?,?,?,?,?,42: RAW 8 packet dropped,43: RAW 10 packet dropped,44: RAW 12 packet dropped,45: RAW 14 packet dropped,46: RAW 16 packet dropped,?,48: User-defined packet dropped,49: User-defined packet dropped,50: User-defined packet dropped,51: User-defined packet dropped,52: User-defined packet dropped,53: User-defined packet dropped,54: User-defined packet dropped,55: User-defined packet dropped,?..."
newline
bitfld.long 0x00 22.--23. "DROPVCID2,VCID Dropped" "0: VC0 data dropped,1: VC1 data dropped,2: VC2 data dropped,3: VC3 data dropped"
newline
bitfld.long 0x00 16.--21. "DROPDATAID2,Data ID Dropped" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,18: Embedded packet dropped,?,?,?,?,?,?,?,?,?,?,?,30: YUV 422,31: YUV 422,?,?,34: RGB 565 packet dropped,?,36: RGB 888 packet dropped,?,?,?,?,?,42: RAW 8 packet dropped,43: RAW 10 packet dropped,44: RAW 12 packet dropped,45: RAW 14 packet dropped,46: RAW 16 packet dropped,?,48: User-defined packet dropped,49: User-defined packet dropped,50: User-defined packet dropped,51: User-defined packet dropped,52: User-defined packet dropped,53: User-defined packet dropped,54: User-defined packet dropped,55: User-defined packet dropped,?..."
newline
bitfld.long 0x00 14.--15. "DROPVCID1,VCID Dropped" "0: VC0 data dropped,1: VC1 data dropped,2: VC2 data dropped,3: VC3 data dropped"
newline
bitfld.long 0x00 8.--13. "DROPDATAID1,Data ID Dropped" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,18: Embedded packet dropped,?,?,?,?,?,?,?,?,?,?,?,30: YUV 422,31: YUV 422,?,?,34: RGB 565 packet dropped,?,36: RGB 888 packet dropped,?,?,?,?,?,42: RAW 8 packet dropped,43: RAW 10 packet dropped,44: RAW 12 packet dropped,45: RAW 14 packet dropped,46: RAW 16 packet dropped,?,48: User-defined packet dropped,49: User-defined packet dropped,50: User-defined packet dropped,51: User-defined packet dropped,52: User-defined packet dropped,53: User-defined packet dropped,54: User-defined packet dropped,55: User-defined packet dropped,?..."
newline
bitfld.long 0x00 6.--7. "DROPVCID0,VCID Dropped" "0: VC0 data dropped,1: VC1 data dropped,2: VC2 data dropped,3: VC3 data dropped"
newline
bitfld.long 0x00 0.--5. "DROPDATAID0,Data ID Dropped" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,18: Embedded packet dropped,?,?,?,?,?,?,?,?,?,?,?,30: YUV 422,31: YUV 422,?,?,34: RGB 565 packet dropped,?,36: RGB 888 packet dropped,?,?,?,?,?,42: RAW 8 packet dropped,43: RAW 10 packet dropped,44: RAW 12 packet dropped,45: RAW 14 packet dropped,46: RAW 16 packet dropped,?,48: User-defined packet dropped,49: User-defined packet dropped,50: User-defined packet dropped,51: User-defined packet dropped,52: User-defined packet dropped,53: User-defined packet dropped,54: User-defined packet dropped,55: User-defined packet dropped,?..."
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x420)++0x03
line.long 0x00 "RX_CBUF_OUTCFG[$1],Receive Data Channel Output Configuration $1"
bitfld.long 0x00 9. "FLIP_BIT_AUX,Defines the signed or unsigned nature of auxiliary channel data" "0: Auxiliary channel data should not be flipped,1: Auxiliary channel data is to be flipped while.."
newline
bitfld.long 0x00 8. "BYTE_ORDER_LSB_FIRST,Byte order of incoming RAW16 data" "0: First RAW8 pixel at LSB,1: Second RAW8 pixel at LSB"
newline
bitfld.long 0x00 7. "SWAPRAWDATA,Swap the data for RAW8 incoming data to align as RAW 16 data in memory" "0: Incoming data is RAW 8 data,1: Incoming data is RAW 16"
newline
bitfld.long 0x00 6. "FLIP_BIT,Defines the signed or unsigned nature of data that is received for the ADC channel data" "0: Non-auxiliary raw data should not be flipped,1: Non-auxiliary raw data is to be flipped"
newline
bitfld.long 0x00 4.--5. "OUTPUT_MODE,This field is used to configure the output data format in SRAM for the received channel data" "0: Channel data written in interleaved format in..,1: Channel data written in tile 8 format in the..,2: Channel data written in tile 16 format in the..,?..."
newline
bitfld.long 0x00 2.--3. "DROP_RATE,Configures the number of samples of fifth channel that needs to be dropped" "0: No auxiliary data sample dropped case in..,1: Alternate auxiliary data sample dropped,2: Three samples out of four auxiliary samples..,3: No auxiliary data sample dropped case in.."
newline
bitfld.long 0x00 1. "CALIB_ON,Enables the fifth channel" "0: Auxiliary channel is disabled for current..,1: Auxiliary channel reception is enabled in.."
newline
bitfld.long 0x00 0. "DATA_MODE,Defines the type of data" "0: Real data only mode,1: Complex data mode"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x430)++0x03
line.long 0x00 "RX_CBUF_CHNLENBL[$1],Receive Data Channel Enable/Disable Configuration $1"
bitfld.long 0x00 7. "CHH_ENBL,Enable Reception of Channel H Content" "0,1"
newline
bitfld.long 0x00 6. "CHG_ENBL,Enable Reception of Channel G Content" "0,1"
newline
bitfld.long 0x00 5. "CHF_ENBL,Enable Reception of Channel F Content" "0,1"
newline
bitfld.long 0x00 4. "CHE_ENBL,Enable Reception of Channel E Content" "0,1"
newline
bitfld.long 0x00 3. "CHD_ENBL,Enable Reception of Channel D Content" "0,1"
newline
bitfld.long 0x00 2. "CHC_ENBL,Enable Reception of Channel C Content" "0,1"
newline
bitfld.long 0x00 1. "CHB_ENBL,Enable Reception of Channel B Content" "0,1"
newline
bitfld.long 0x00 0. "CHA_ENBL,Enable Reception of Channel A Content" "0,1"
repeat.end
group.long 0x440++0x03
line.long 0x00 "RX_CBUF0_CHNLOFFSET0_0,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHB_DC,Channel B Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHA_DC,Channel A Offset Compensation Value"
group.long 0x444++0x03
line.long 0x00 "RX_CBUF0_CHNLOFFSET1_0,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHD_DC,Channel D Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHC_DC,Channel C Offset Compensation Value"
group.long 0x448++0x03
line.long 0x00 "RX_CBUF0_CHNLOFFSET2_0,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHF_DC,Channel F Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHE_DC,Channel E Offset Compensation Value"
group.long 0x44C++0x03
line.long 0x00 "RX_CBUF0_CHNLOFFSET3_0,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHH_DC,Channel H Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHG_DC,Channel G Offset Compensation Value"
group.long 0x450++0x03
line.long 0x00 "RX_CBUF1_CHNLOFFSET0_1,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHB_DC,Channel B Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHA_DC,Channel A Offset Compensation Value"
group.long 0x454++0x03
line.long 0x00 "RX_CBUF1_CHNLOFFSET1_1,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHD_DC,Channel D Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHC_DC,Channel C Offset Compensation Value"
group.long 0x458++0x03
line.long 0x00 "RX_CBUF1_CHNLOFFSET2_1,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHF_DC,Channel F Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHE_DC,Channel E Offset Compensation Value"
group.long 0x45C++0x03
line.long 0x00 "RX_CBUF1_CHNLOFFSET3_1,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHH_DC,Channel H Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHG_DC,Channel G Offset Compensation Value"
group.long 0x460++0x03
line.long 0x00 "RX_CBUF2_CHNLOFFSET0_2,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHB_DC,Channel B Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHA_DC,Channel A Offset Compensation Value"
group.long 0x464++0x03
line.long 0x00 "RX_CBUF2_CHNLOFFSET1_2,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHD_DC,Channel D Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHC_DC,Channel C Offset Compensation Value"
group.long 0x468++0x03
line.long 0x00 "RX_CBUF2_CHNLOFFSET2_2,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHF_DC,Channel F Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHE_DC,Channel E Offset Compensation Value"
group.long 0x46C++0x03
line.long 0x00 "RX_CBUF2_CHNLOFFSET3_2,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHH_DC,Channel H Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHG_DC,Channel G Offset Compensation Value"
group.long 0x470++0x03
line.long 0x00 "RX_CBUF3_CHNLOFFSET0_3,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHB_DC,Channel B Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHA_DC,Channel A Offset Compensation Value"
group.long 0x474++0x03
line.long 0x00 "RX_CBUF3_CHNLOFFSET1_3,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHD_DC,Channel D Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHC_DC,Channel C Offset Compensation Value"
group.long 0x478++0x03
line.long 0x00 "RX_CBUF3_CHNLOFFSET2_3,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHF_DC,Channel F Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHE_DC,Channel E Offset Compensation Value"
group.long 0x47C++0x03
line.long 0x00 "RX_CBUF3_CHNLOFFSET3_3,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHH_DC,Channel H Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHG_DC,Channel G Offset Compensation Value"
group.long 0x490++0x03
line.long 0x00 "RX_CHNL_INTRS,Receive Data Channel Status"
eventfld.long 0x00 1. "BUFFOVF,Internal Buffer Overflow Indication" "0,1"
newline
eventfld.long 0x00 0. "LINEDONE,Long Packet Complete Indication" "0,1"
group.long 0x494++0x03
line.long 0x00 "RX_CHNL_INTRE,Receive Channel Interrupt Enable"
bitfld.long 0x00 1. "BUFFOVFIE,Internal Buffer Overflow Indication Interrupt Enable" "0,1"
newline
bitfld.long 0x00 0. "LINEDONEIE,Long Packet Complete Indication Interrupt Enable" "0,1"
group.long 0x498++0x03
line.long 0x00 "WR_CHNL_INTRS,AXI Write Channel Interrupt Status"
eventfld.long 0x00 1. "BUFFOVFAXI,When the number of outstanding transactions has reached eight for AXI master write side and a new burst request is needed then this is set" "0,1"
newline
eventfld.long 0x00 0. "ERRRESP,Error Response on the AXI Write Channel" "0,1"
group.long 0x49C++0x03
line.long 0x00 "WR_CHNL_INTRE,AXI Write Channel Interrupt Enable"
bitfld.long 0x00 1. "BUFFOVFAXIIE,Internal Buffer Overflow Indication Interrupt Enable" "0,1"
newline
bitfld.long 0x00 0. "ERRRESPIE,Error Response on the AXI Write Response Channel Interrupt Enable" "0,1"
group.long 0x584++0x03
line.long 0x00 "TURNCFG,Turnaround Request Configuration"
bitfld.long 0x00 4. "FORCERXMODE4,Force Receive Mode on Data Lane" "0: Receive mode is not forced on lane 4,1: Lane module 4 is forced to transition into.."
newline
bitfld.long 0x00 3. "FORCERXMODE3,Force Receive Mode on Data Lane" "0: Receive mode is not forced on lane 3,1: Lane module 3 is forced to transition into.."
newline
bitfld.long 0x00 2. "FORCERXMODE2,Force Receive Mode on Data Lane" "0: Receive mode is not forced on lane 2,1: Lane module 2 is forced to transition into.."
newline
bitfld.long 0x00 1. "FORCERXMODE1,Force Receive Mode on Data Lane" "0: Receive mode is not forced on lane 1,1: Lane module 1 is forced to transition into.."
group.long 0x598++0x03
line.long 0x00 "TRIGGER_GPIO1,GPIO1 Pad Event Trigger Control"
bitfld.long 0x00 30.--31. "RSVD_3,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "TRIGGERONPKTID_VC3,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 26.--27. "TRIGGERONPKT_VC3,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 24.--25. "TRIGGERONERR_VC3,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC or ECC 2-bit error trigger enable,3: No synchronization on DPHY data lane trigger.."
newline
bitfld.long 0x00 22.--23. "RSVD_2,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 20.--21. "TRIGGERONPKTID_VC2,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 18.--19. "TRIGGERONPKT_VC2,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 16.--17. "TRIGGERONERR_VC2,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC or ECC 2-bit error trigger enable,3: No synchronization on DPHY data lane trigger.."
newline
bitfld.long 0x00 14.--15. "RSVD_1,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "TRIGGERONPKTID_VC1,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 10.--11. "TRIGGERONPKT_VC1,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 8.--9. "TRIGGERONERR_VC1,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC or ECC 2-bit error trigger enable,3: No synchronization on DPHY data lane trigger.."
newline
bitfld.long 0x00 6.--7. "RSVD_0,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "TRIGGERONPKTID_VC0,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 2.--3. "TRIGGERONPKT_VC0,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 0.--1. "TRIGGERONERR_VC0,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC or ECC 2-bit error trigger enable,3: No synchronization on DPHY data lane trigger.."
group.long 0x5A0++0x03
line.long 0x00 "TRIGGER_SDMA1,SDMA1 Pad Event Trigger Control"
bitfld.long 0x00 30.--31. "RSVD_3,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "TRIGGERONPKTID_VC3,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 26.--27. "TRIGGERONPKT_VC3,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 24.--25. "TRIGGERONERR_VC3,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC error or ECC 2-bit trigger enable,3: No synchronization on DPHY data lane trigger.."
newline
bitfld.long 0x00 22.--23. "RSVD_2,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 20.--21. "TRIGGERONPKTID_VC2,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 18.--19. "TRIGGERONPKT_VC2,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 16.--17. "TRIGGERONERR_VC2,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC error or ECC 2-bit trigger enable,3: No synchronization on DPHY data lane trigger.."
newline
bitfld.long 0x00 14.--15. "RSVD_1,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "TRIGGERONPKTID_VC1,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 10.--11. "TRIGGERONPKT_VC1,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 8.--9. "TRIGGERONERR_VC1,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC error or ECC 2-bit trigger enable,3: No synchronization on DPHY data lane trigger.."
newline
bitfld.long 0x00 6.--7. "RSVD_0,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "TRIGGERONPKTID_VC0,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 2.--3. "TRIGGERONPKT_VC0,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 0.--1. "TRIGGERONERR_VC0,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC error or ECC 2-bit trigger enable,3: No synchronization on DPHY data lane trigger.."
group.long 0x5A8++0x03
line.long 0x00 "TRIGGEREN_GPIO,GPIO Pad Event Trigger Enable Control"
bitfld.long 0x00 23. "GPIO2_TRIGGERONPKTIDEN_VC3,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 22. "GPIO2_TRIGGERONPKTEN_VC3,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 21. "GPIO2_TRIGGERONERR_VC3,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 20. "GPIO2_TRIGGERONPKTIDEN_VC2,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 19. "GPIO2_TRIGGERONPKTEN_VC2,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 18. "GPIO2_TRIGGERONERR_VC2,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 17. "GPIO2_TRIGGERONPKTIDEN_VC1,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 16. "GPIO2_TRIGGERONPKTEN_VC1,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 15. "GPIO2_TRIGGERONERR_VC1,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 14. "GPIO2_TRIGGERONPKTIDEN_VC0,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 13. "GPIO2_TRIGGERONPKTEN_VC0,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 12. "GPIO2_TRIGGERONERR_VC0,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 11. "GPIO1_TRIGGERONPKTIDEN_VC3,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 10. "GPIO1_TRIGGERONPKTEN_VC3,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 9. "GPIO1_TRIGGERONERR_VC3,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 8. "GPIO1_TRIGGERONPKTIDEN_VC2,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 7. "GPIO1_TRIGGERONPKTEN_VC2,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 6. "GPIO1_TRIGGERONERR_VC2,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 5. "GPIO1_TRIGGERONPKTIDEN_VC1,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 4. "GPIO1_TRIGGERONPKTEN_VC1,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 3. "GPIO1_TRIGGERONERR_VC1,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 2. "GPIO1_TRIGGERONPKTIDEN_VC0,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 1. "GPIO1_TRIGGERONPKTEN_VC0,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 0. "GPIO1_TRIGGERONERR_VC0,Enable Trigger Generation on Errors for each VC" "0,1"
group.long 0x5AC++0x03
line.long 0x00 "TRIGGEREN_SDMA,SDMA Pad Event Trigger Enable Control"
bitfld.long 0x00 23. "SDMA2_TRIGGERONPKTIDEN_VC3,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 22. "SDMA2_TRIGGERONPKTEN_VC3,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 21. "SDMA2_TRIGGERONERR_VC3,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 20. "SDMA2_TRIGGERONPKTIDEN_VC2,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 19. "SDMA2_TRIGGERONPKTEN_VC2,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 18. "SDMA2_TRIGGERONERR_VC2,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 17. "SDMA2_TRIGGERONPKTIDEN_VC1,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 16. "SDMA2_TRIGGERONPKTEN_VC1,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 15. "SDMA2_TRIGGERONERR_VC1,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 14. "SDMA2_TRIGGERONPKTIDEN_VC0,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 13. "SDMA2_TRIGGERONPKTEN_VC0,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 12. "SDMA2_TRIGGERONERR_VC0,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 11. "SDMA1_TRIGGERONPKTIDEN_VC3,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 10. "SDMA1_TRIGGERONPKTEN_VC3,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 9. "SDMA1_TRIGGERONERR_VC3,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 8. "SDMA1_TRIGGERONPKTIDEN_VC2,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 7. "SDMA1_TRIGGERONPKTEN_VC2,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 6. "SDMA1_TRIGGERONERR_VC2,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 5. "SDMA1_TRIGGERONPKTIDEN_VC1,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 4. "SDMA1_TRIGGERONPKTEN_VC1,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 3. "SDMA1_TRIGGERONERR_VC1,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 2. "SDMA1_TRIGGERONPKTIDEN_VC0,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 1. "SDMA1_TRIGGERONPKTEN_VC0,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 0. "SDMA1_TRIGGERONERR_VC0,Enable Trigger Generation on Errors for each VC" "0,1"
group.byte 0x608++0x00
line.byte 0x00 "DPHY_CALTYPE_CNTRL,System Configuration"
bitfld.byte 0x00 5. "CMP_POLARITY_RW,Comparator polarity" "0,1"
newline
bitfld.byte 0x00 4. "NOEXT_BURNIN_RES_CAL_RW,Selection between type of calibration (if 1 no REXT will be done)" "0,1"
group.byte 0x60C++0x00
line.byte 0x00 "DPHY_SKEWCAL_CNTRL,System Configuration"
bitfld.byte 0x00 7. "TCLK_MISS_DIV2_OVR_EN_RW,Use divider by 2 on Tclk-miss detection circuit override" "0,1"
newline
bitfld.byte 0x00 6. "TCLK_MISS_DIV2_OVR_RW,Use divider by 2 on Tclk-miss detection circuit override" "0,1"
newline
bitfld.byte 0x00 5. "DESKEW_POLARITY_RW,De-skew Calibration pattern control (only used in backwards compatibility)" "0: datain = datain_afe,1: datain = ~datain_afe"
newline
bitfld.byte 0x00 3.--4. "DESKEW_LATENCY_RW__1__0__,Controls the latency between applying one setting and starting the integration" "0: DESKEW_LATENCY_RW__1__0___0,1: DESKEW_LATENCY_RW__1__0___1,2: DESKEW_LATENCY_RW__1__0___2,3: DESKEW_LATENCY_RW__1__0___3"
newline
bitfld.byte 0x00 1. "SKEW_MUX_SEL_RW,Selects between auto mode and manual selection of de-skew calibration mechanism" "0,1"
newline
bitfld.byte 0x00 0. "SKEW_MUX_RUN_RW,Selects the type of deskew calibration mode to run (internal or burst based)" "0,1"
group.byte 0x60D++0x00
line.byte 0x00 "DPHY_RX_SYNALIGN_CFG,System Configuration"
bitfld.byte 0x00 5.--6. "ALIGNER_DK_CNF_RW__1__0__,Used in the lane aligner to set the number of ones to identify in the deskew sync pattern" "0: ALIGNER_DK_CNF_RW__1__0___0,1: ALIGNER_DK_CNF_RW__1__0___1,2: ALIGNER_DK_CNF_RW__1__0___2,3: ALIGNER_DK_CNF_RW__1__0___3"
newline
bitfld.byte 0x00 4. "NOALIGN_ERROR_RW,No alignment error bit" "0,1"
newline
bitfld.byte 0x00 2.--3. "DESKEW_JUMP2STEPS_RW__1__0__,De-skew Calibration steps control" "0: DESKEW_JUMP2STEPS_RW__1__0___0,1: DESKEW_JUMP2STEPS_RW__1__0___1,2: DESKEW_JUMP2STEPS_RW__1__0___2,3: DESKEW_JUMP2STEPS_RW__1__0___3"
newline
bitfld.byte 0x00 1. "DESKEW_OVERFLOW_RW,Feature that forces de-skew algorithm convergence by setting 2nd edge pointer to step 31 (for situations where eventual DDL variation over PVT could cause potential failures)" "0,1"
newline
bitfld.byte 0x00 0. "DESKEW_NUMEDGES_UPDATE_RW,Procedure Set deskew_nemedge_update to 1'b0 Change deskew_numedges to desired value Set deskew_nemedge_update to 1'b1 Circuitry ensures synchronous update of internal counters" "0,1"
group.byte 0x60E++0x00
line.byte 0x00 "DPHY_DESKEW_CFG,This register is used to program the Deskew accumulator size(FJUMP)"
hexmask.byte 0x00 0.--7. 1. "DESKEW_NUMEDGES_RW,De-skew accumulator size (sinusoidal jitter tolerance)"
group.byte 0x6E4++0x00
line.byte 0x00 "DPHY_RX_STARTUP_OVERRIDE,System Startup Observability"
bitfld.byte 0x00 7. "RX_RXHS_COMPATIBILITY_MODE_OVR_EN_RW,When set to 1'b1 the value of rx_rxhs_compatibility_mode will be the same as rx_rxhs_compatibility_mode_ovr" "0,1"
newline
bitfld.byte 0x00 6. "BYPASS_SKEW_MACHINE_RW,Bypass of de-skew machine" "0,1"
newline
bitfld.byte 0x00 5. "SKEW_BACK_COMP_EN_OVR_RW,Deskew Backwards Compatibility Override Enable Value" "0,1"
newline
bitfld.byte 0x00 4. "SKEW_BACK_COMP_EN_OVR_EN_RW,Deskew Back Comparator Override Enable Control" "0,1"
newline
bitfld.byte 0x00 3. "BYPASS_DDLTUNNING_MACHINE_RW,Bypass DDL Tunning Machine" "0,1"
newline
bitfld.byte 0x00 2. "BYPASS_OFFSET_MACHINE_RW,Bypass Offset Machine Bit" "0,1"
newline
bitfld.byte 0x00 0. "CLK_EN_LANES_BYPASS_RW,Clock Enable Lanes Bypass" "0,1"
group.byte 0x6E6++0x00
line.byte 0x00 "DPHY_DDLOSCFREQ_CFG1,System Startup Override"
hexmask.byte 0x00 0.--7. 1. "DDL_OSC_FREQ_TARGET_OVR_RW__7__0__,DDL oscillation frequency override value (main)"
group.byte 0x6E7++0x00
line.byte 0x00 "DPHY_DDLOSCFREQ_CFG2,System Startup Override"
bitfld.byte 0x00 0.--3. "DDL_OSC_FREQ_TARGET_OVR_RW__11__8__,DDL oscillation frequency override value (main)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x6E8++0x00
line.byte 0x00 "DPHY_DDLOSCFREQ_OVREN,System Startup Override"
bitfld.byte 0x00 4.--7. "COUNTER_FOR_DES_EN_CONFIG_IF_RW__3__0__,Override the counter_for_des_en_if in the hardmacro when counter_for_des_en_bypass_rw is set to 1'b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 2.--3. "RX_RXHS_GMODE_IF_OVR_RW__1__0__,Overrides the rx_rxhs_gmode_int which is set according to hsfreqrange from the softmacro to the hardmacro when RX_RXHS_GMODE_IF_OVR_EN_RW is set to 1'b1" "0,1,2,3"
newline
bitfld.byte 0x00 1. "RX_RXHS_GMODE_IF_OVR_EN_RW,overrides the rx_rxhs_gmode_int which is set according to hsfreqrange from the softmacro to the hardmacro when RX_RXHS_GMODE_IF_OVR_EN_RW is set to 1'b1" "0,1"
newline
bitfld.byte 0x00 0. "DDL_OSC_FREQ_TARGET_OVR_EN_RW,Overrides the ddl_osc_freq_target which is set according to hsfreqrange from the softmacro to the hardmacro when DDL_OSC_FREQ_TARGET_OVR_EN_RW is set to 1'b1" "0,1"
rgroup.byte 0x824++0x00
line.byte 0x00 "DPHY_RX_TERM_CAL_0,Termination Calibration Observability"
bitfld.byte 0x00 2.--5. "CB_CAL_REPL__3__0__,register is used to observe (read_only) the value of rx_cb_cal_repl_if signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x825++0x00
line.byte 0x00 "DPHY_RX_TERM_CAL_1,Termination Calibration Observability"
bitfld.byte 0x00 7. "RESCAL_DONE,Lower section termination calibration algorithm done (volatile)" "0,1"
newline
bitfld.byte 0x00 5. "RESCAL_EN,Lower section termination calibration algorithm enable (volatile)" "0,1"
group.byte 0x90B++0x00
line.byte 0x00 "DPHY_CLOCK_LANE_CNTRL,Clock Lane Control"
bitfld.byte 0x00 7. "RXCLK_RXHS_PULL_LONG_CHANNEL_IF_RW,RX high-speed pull long channel" "0,1"
newline
bitfld.byte 0x00 6. "RXCLK_RXHS_INT_CLK_SEL_RW,RX high-speed internal clock selection" "0,1"
newline
bitfld.byte 0x00 5. "RXCLK_RXHS_FEED_INT_CLK_OVR_EN_RW,RX high-speed source data override enable control" "0,1"
newline
bitfld.byte 0x00 4. "RXCLK_RXHS_FEED_INT_CLK_OVR_RW,Overrides rxclk_rxhs_feed_int_clk_if signal when RXCLK_RXHS_FEED_INT_CLK_OVR_EN_RW is set to 1'b1" "0: RXCLK_RXHS_FEED_INT_CLK_OVR_RW_0,1: RXCLK_RXHS_FEED_INT_CLK_OVR_RW_1"
newline
bitfld.byte 0x00 3. "RXCLK_RXHS_DDR_CLK_EN_IF_RW,Enable DDR clock divider" "0,1"
newline
bitfld.byte 0x00 2. "RXCLK_RXHS_CLK_TO_LONG_CHANNEL_IF_RW,RX HS clock to long channel bits" "0: use single macro (short),1: use double macro (long)"
group.byte 0x97F++0x00
line.byte 0x00 "DPHY_CLKOFFSETCAL_OVRRIDE,Clock Lane Offset Cancellation Control"
bitfld.byte 0x00 4. "RXCLK_START_CALIBRATION_OVR_RW,Clock lane digital offset start calibration override enable control" "0,1"
newline
bitfld.byte 0x00 3. "RXCLK_START_CALIBRATION_OVR_EN_RW,Clock lane digital offset start calibration override enable control" "0,1"
newline
bitfld.byte 0x00 2. "RXCLK_RXHS_START_CALIBRATION_OVR_RW,Enables override of clock lane analog offset start calibration" "0,1"
newline
bitfld.byte 0x00 1. "RXCLK_RXHS_START_CALIBRATION_OVR_EN_RW,Controls override of clock lane analog offset start calibration" "0,1"
newline
bitfld.byte 0x00 0. "RXCLK_RXHS_CLK_OFFSET_CAL_OVR_EN_RW,RX HS clock offset calibration override enable control" "0,1"
group.byte 0x980++0x00
line.byte 0x00 "DPHY_CLKOFFSETCAL_OVRRIDEVAL,Clock Lane Offset Cancellation Control 2"
hexmask.byte 0x00 0.--6. 1. "RXCLK_RXHS_CLK_OFFSET_CAL_OVR_RW__6__0__,RX HS clock offset calibration override control"
rgroup.byte 0x9A0++0x00
line.byte 0x00 "DPHY_CLKCALVAL_COMPS,Clock Lane Offset Cancellation Observability 3"
hexmask.byte 0x00 0.--6. 1. "RXCLK_RXHS_CLK_OFFSET_CAL__6__0__,Register is used to observe (read_only) the value of rxclk_rxhs_clk_offset_cal_if"
rgroup.byte 0x9A1++0x00
line.byte 0x00 "DPHY_CLKOFFSETCAL_COMPS,Clock Lane Offset Cancellation Observability"
bitfld.byte 0x00 5. "RXCLK_RXHS_CLK_M_CAL,Register is used to observe (read_only) the value of rxclk_rxhs_clk_m_cal_if" "0,1"
newline
bitfld.byte 0x00 1.--4. "RXCLK_ERRCAL__3__0__,Clock lane offset calibration error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0. "RXCLK_CALDONE,register is used to observe (read_only) the value of rxclk_caldone which is a flag to indicate when calibration ends in the clock lane offset calibration machine" "0,1"
group.byte 0xB09++0x00
line.byte 0x00 "DPHY_RX_LPRXPON_LANE0,Lane 0 Low Power Receive Control"
bitfld.byte 0x00 4. "LPRXPONULP_LANE0_RW,LP RX ULP power-on" "0,1"
newline
bitfld.byte 0x00 3. "LPRXPONULP_BYPASS_LANE0_RW,LP RX ULP power-on bypass override" "0,1"
newline
bitfld.byte 0x00 2. "LPRXPONLP_LANE0_RW,LP RX LP power-on" "0,1"
newline
bitfld.byte 0x00 1. "LPRXPONLP_BYPASS_LANE0_RW,LP RX LP power-on bypass override" "0,1"
newline
bitfld.byte 0x00 0. "LPRXPONCD_LANE0_RW,LP RX contention detector power-on" "0,1"
rgroup.byte 0xB33++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_COMPS0,Lane 0 Observability"
bitfld.byte 0x00 4. "RX0_DESKEWCALFAILED_IF,Register is used to observe (read_only) the value of rx0_deskewcalfailed_if which is the deskew calibration error flag" "0,1"
newline
bitfld.byte 0x00 3. "RX0_DESKEWCALDONE_IF,Register is used to observe (read_only) the value of rx0_deskewcaldone_if which is the deskew calibration process completion flag" "0,1"
newline
bitfld.byte 0x00 2. "LSRXCLK_LANE0,Low-Speed Clock(Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--1. "LPRXDOUTULP_LANE0__1__0__,Register is used to observe (read_only) the value of lprxdoutulp_lane0_if which is the output of the ulp comparator" "0,1,2,3"
group.byte 0xB7F++0x00
line.byte 0x00 "DPHY_DATAL0OFFSETCAL_OVRCNTRL,Lane 0 Offset Compensation Control"
bitfld.byte 0x00 7. "RX0_RXHS_DATA_OFFSET_CAL_EN_OVR_EN_RW,Data Offset Calibration Override Enable Control" "0,1"
newline
bitfld.byte 0x00 6. "RX0_CAL_DONE_OVR_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 5. "RX0_CAL_DONE_OVR_EN_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 4. "RX0_START_CALIBRATION_OVR_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 3. "RX0_START_CALIBRATION_OVR_EN_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 2. "RX0_RXHS_DATA_OFFSET_CAL_OVR_EN_RW,Offset Calibration Setting Override" "0,1"
group.byte 0xB80++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_OVRVALUE0,Lane 0 Offset Compensation Control"
hexmask.byte 0x00 1.--7. 1. "RX0_RXHS_DATA_OFFSET_CAL_OVR_RW__6__0__,Offset Calibration Setting Override Enable"
newline
bitfld.byte 0x00 0. "RX0_RXHS_DATA_OFFSET_CAL_EN_OVR_RW,Data Offset Calibration Override Enable Control" "0,1"
rgroup.byte 0xBA3++0x00
line.byte 0x00 "DPHY_DATALANE_OFFSETCAL_COMPS0,Lane Offset Compensation Observability"
bitfld.byte 0x00 2. "RX0_CAL_ERROR,Offset Calibration Algorithm Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_CAL_DONE,Offset Calibration Algorithm Done (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX0_START_CALIBRATION,Offset Calibration Algorithm Start (Volatile)" "0,1"
rgroup.byte 0xBA5++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_VALUE0,Lane Offset Compensation Observability"
bitfld.byte 0x00 7. "RX0_RXHS_DATA_OFFSET_CAL_EN,Offset calibration algorithm enable (volatile)" "0,1"
newline
hexmask.byte 0x00 0.--6. 1. "RX0_RXHS_DATA_OFFSET_CAL__6__0__,Offset calibration algorithm setting chosen (volatile)"
rgroup.byte 0xBE4++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_COMP0,Lane DDL Tune Observability"
bitfld.byte 0x00 3. "RX0_DDL_START_CALIBRATION_IF,DDL Tune Digital Algorithm Start (Volatile)" "0,1"
newline
bitfld.byte 0x00 2. "RX0_DDL_FINISHED_IF,DDL Tune Done Indication (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_DDL_ERROR_FLAG_IF,DDL Tune Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "DDL_TUNE_EN_LANE0_IF,DDL Tune Analog Circuitry Enable Indication (Volatile)" "0,1"
rgroup.byte 0xBE9++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_VALUE0,Lane 0 DDL Tune Observability"
bitfld.byte 0x00 5. "RX0_RXHS_DDL_PHASE_CHANGE_P_IF,RX HS DDL Phase Change (Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_IF__4__0__,RX HS DDL Tunning Setting (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.byte 0xBEA++0x00
line.byte 0x00 "DPHY_DATALANE0_DESKEW_VALUE1,Lane 0 DDL Tune Observability"
bitfld.byte 0x00 5.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_PHASE_CLK_IF__4__0__,Clock DDL Setting Chosen (volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.byte 0xBEB++0x00
line.byte 0x00 "DPHY_DATALANE0_DESKEW_VALUE2,Lane 0 DDL Tune Observability"
bitfld.byte 0x00 4.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0.--3. "RX0_RXHS_DDL_PHASE_DATA_IF__3__0__,Data DDL Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xC0B++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_OVRVALUE0,Lane 0 DDL Tune Control"
bitfld.byte 0x00 7. "RX0_RXHS_DDL_PHASE_CHANGE_P_OVR_RW,RX HS DDL Phase Changed Override Control" "0,1"
newline
bitfld.byte 0x00 6. "RX0_RXHS_DDL_PHASE_CHANGE_P_OVR_EN_RW,RX HS DDL Phase Changed Override Control" "0,1"
newline
bitfld.byte 0x00 5. "RX0_RXHS_DDL_TUNE_OVR_EN_RW,RX HS DDL Tune Override Enable Control" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_OVR_RW__4__0__,RX HS DDL Tune Override for Lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0xC0C++0x00
line.byte 0x00 "DPHY_DATALANE0_DESKEW_OVRVALUE1,Lane 0 DDL Tune Control"
rbitfld.byte 0x00 6.--7. "RESERVED_0,Reserved field" "0,1,2,3"
newline
bitfld.byte 0x00 5. "RX0_RXHS_DDL_PHASE_CLK_OVR_EN_RW,RX HS DDL Phase Clock Override Control" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_PHASE_CLK_OVR_RW__4__0__,RX HS DDL Phase Clock Override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0xC0D++0x00
line.byte 0x00 "DPHY_DATALANE0_DESKEW_OVRVALUE2,Lane 0 DDL Tune Control"
rbitfld.byte 0x00 5.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 4. "RX0_RXHS_DDL_PHASE_DATA_OVR_EN_RW,Override Enable for DDL Phase Data" "0,1"
newline
bitfld.byte 0x00 0.--3. "RX0_RXHS_DDL_PHASE_DATA_OVR_RW__3__0__,RX HS DDL Phase Data Override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xD0F++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_OVRVALUE11,Lane 1 Control"
bitfld.byte 0x00 7. "RX1_RXHS_DDL_PHASE_CLK_OVR_EN_RW,RX HS DDL Phase Data Override Control" "0,1"
newline
bitfld.byte 0x00 2.--6. "RX1_RXHS_DDL_PHASE_CLK_OVR_RW__4__0__,RX HS DDL Phase Clock Override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.byte 0x00 1. "RX1_RXHS_DDL_PHASE_CHANGE_P_OVR_EN_RW,RX HS DDL Phase Changed Override Control" "0,1"
newline
bitfld.byte 0x00 0. "RX1_RXHS_DDL_PHASE_CHANGE_P_OVR_RW,RX HS DDL Phase Changed Override Control" "0,1"
group.byte 0xD10++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_OVRVALUE21,Lane 1 Control"
rbitfld.byte 0x00 5.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 4. "RX1_RXHS_DDL_PHASE_DATA_OVR_EN_RW,Override Enable for DDL Phase Data" "0,1"
newline
bitfld.byte 0x00 0.--3. "RX1_RXHS_DDL_PHASE_DATA_OVR_RW__3__0__,RX HS DDL phase clock override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0xD33++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_COMPS1,Lane 0 Observability"
bitfld.byte 0x00 4. "RX0_DESKEWCALFAILED_IF,Register is used to observe (read_only) the value of rx0_deskewcalfailed_if which is the deskew calibration error flag" "0,1"
newline
bitfld.byte 0x00 3. "RX0_DESKEWCALDONE_IF,Register is used to observe (read_only) the value of rx0_deskewcaldone_if which is the deskew calibration process completion flag" "0,1"
newline
bitfld.byte 0x00 2. "LSRXCLK_LANE0,Low-Speed Clock(Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--1. "LPRXDOUTULP_LANE0__1__0__,Register is used to observe (read_only) the value of lprxdoutulp_lane0_if which is the output of the ulp comparator" "0,1,2,3"
rgroup.byte 0xD38++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_VALUE11,Lane 1 Observability"
bitfld.byte 0x00 7. "RESERVED_0,Reserved field" "0,1"
newline
bitfld.byte 0x00 2.--6. "RX1_RXHS_DDL_PHASE_CLK_IF__4__0__,Clock DDL Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.byte 0x00 1. "RX1_RXHS_DDL_PHASE_CHANGE_P_IF,DDL Setting Change Latch Pulse (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX1_PM_START,Pattern Matcher Start Flag Observation (Volatile)" "0,1"
rgroup.byte 0xD39++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_VALUE21,Lane 1 Observability"
bitfld.byte 0x00 4.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0.--3. "RX1_RXHS_DDL_PHASE_DATA_IF__3__0__,Data DDl Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xD7F++0x00
line.byte 0x00 "DPHY_DATAL1OFFSETCAL_OVRCNTRL,Lane 1 Offset Compensation Control"
bitfld.byte 0x00 7. "RX1_RXHS_DATA_OFFSET_CAL_EN_OVR_EN_RW,Data Offset Calibration Override Enable Control" "0,1"
newline
bitfld.byte 0x00 6. "RX1_CAL_DONE_OVR_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 5. "RX1_CAL_DONE_OVR_EN_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 4. "RX1_START_CALIBRATION_OVR_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 3. "RX1_START_CALIBRATION_OVR_EN_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 2. "RX1_RXHS_DATA_OFFSET_CAL_OVR_EN_RW,Offset Calibration Setting Override" "0,1"
group.byte 0xD80++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_OVRVALUE1,Lane 0 Offset Compensation Control"
hexmask.byte 0x00 1.--7. 1. "RX0_RXHS_DATA_OFFSET_CAL_OVR_RW__6__0__,Offset Calibration Setting Override Enable"
newline
bitfld.byte 0x00 0. "RX0_RXHS_DATA_OFFSET_CAL_EN_OVR_RW,Data Offset Calibration Override Enable Control" "0,1"
rgroup.byte 0xDA3++0x00
line.byte 0x00 "DPHY_DATALANE_OFFSETCAL_COMPS1,Lane Offset Compensation Observability"
bitfld.byte 0x00 2. "RX0_CAL_ERROR,Offset Calibration Algorithm Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_CAL_DONE,Offset Calibration Algorithm Done (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX0_START_CALIBRATION,Offset Calibration Algorithm Start (Volatile)" "0,1"
rgroup.byte 0xDA5++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_VALUE1,Lane Offset Compensation Observability"
bitfld.byte 0x00 7. "RX0_RXHS_DATA_OFFSET_CAL_EN,Offset calibration algorithm enable (volatile)" "0,1"
newline
hexmask.byte 0x00 0.--6. 1. "RX0_RXHS_DATA_OFFSET_CAL__6__0__,Offset calibration algorithm setting chosen (volatile)"
rgroup.byte 0xDE4++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_COMP1,Lane DDL Tune Observability"
bitfld.byte 0x00 3. "RX0_DDL_START_CALIBRATION_IF,DDL Tune Digital Algorithm Start (Volatile)" "0,1"
newline
bitfld.byte 0x00 2. "RX0_DDL_FINISHED_IF,DDL Tune Done Indication (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_DDL_ERROR_FLAG_IF,DDL Tune Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "DDL_TUNE_EN_LANE0_IF,DDL Tune Analog Circuitry Enable Indication (Volatile)" "0,1"
rgroup.byte 0xDE9++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_VALUE1,Lane 0 DDL Tune Observability"
bitfld.byte 0x00 5. "RX0_RXHS_DDL_PHASE_CHANGE_P_IF,RX HS DDL Phase Change (Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_IF__4__0__,RX HS DDL Tunning Setting (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0xE0B++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_OVRVALUE1,Lane 0 DDL Tune Control"
rbitfld.byte 0x00 6.--7. "reserved_0,Reserved field" "0,1,2,3"
newline
bitfld.byte 0x00 5. "RX0_RXHS_DDL_TUNE_OVR_EN_RW,RX HS DDL Tune Override Enable Control" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_OVR_RW__4__0__,RX HS DDL Tune Override for Lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0xF0F++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_OVRVALUE12,Lane 1 Control"
bitfld.byte 0x00 7. "RX1_RXHS_DDL_PHASE_CLK_OVR_EN_RW,RX HS DDL Phase Data Override Control" "0,1"
newline
bitfld.byte 0x00 2.--6. "RX1_RXHS_DDL_PHASE_CLK_OVR_RW__4__0__,RX HS DDL Phase Clock Override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.byte 0x00 1. "RX1_RXHS_DDL_PHASE_CHANGE_P_OVR_EN_RW,RX HS DDL Phase Changed Override Control" "0,1"
newline
bitfld.byte 0x00 0. "RX1_RXHS_DDL_PHASE_CHANGE_P_OVR_RW,RX HS DDL Phase Changed Override Control" "0,1"
group.byte 0xF10++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_OVRVALUE22,Lane 1 Control"
rbitfld.byte 0x00 5.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 4. "RX1_RXHS_DDL_PHASE_DATA_OVR_EN_RW,Override Enable for DDL Phase Data" "0,1"
newline
bitfld.byte 0x00 0.--3. "RX1_RXHS_DDL_PHASE_DATA_OVR_RW__3__0__,RX HS DDL phase clock override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0xF33++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_COMPS2,Lane 0 Observability"
bitfld.byte 0x00 4. "RX0_DESKEWCALFAILED_IF,Register is used to observe (read_only) the value of rx0_deskewcalfailed_if which is the deskew calibration error flag" "0,1"
newline
bitfld.byte 0x00 3. "RX0_DESKEWCALDONE_IF,Register is used to observe (read_only) the value of rx0_deskewcaldone_if which is the deskew calibration process completion flag" "0,1"
newline
bitfld.byte 0x00 2. "LSRXCLK_LANE0,Low-Speed Clock(Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--1. "LPRXDOUTULP_LANE0__1__0__,Register is used to observe (read_only) the value of lprxdoutulp_lane0_if which is the output of the ulp comparator" "0,1,2,3"
rgroup.byte 0xF38++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_VALUE12,Lane 1 Observability"
bitfld.byte 0x00 7. "RESERVED_0,Reserved field" "0,1"
newline
bitfld.byte 0x00 2.--6. "RX1_RXHS_DDL_PHASE_CLK_IF__4__0__,Clock DDL Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.byte 0x00 1. "RX1_RXHS_DDL_PHASE_CHANGE_P_IF,DDL Setting Change Latch Pulse (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX1_PM_START,Pattern Matcher Start Flag Observation (Volatile)" "0,1"
rgroup.byte 0xF39++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_VALUE22,Lane 1 Observability"
bitfld.byte 0x00 4.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0.--3. "RX1_RXHS_DDL_PHASE_DATA_IF__3__0__,Data DDl Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xF7F++0x00
line.byte 0x00 "DPHY_DATAL2OFFSETCAL_OVRCNTRL,Lane 1 Offset Compensation Control"
bitfld.byte 0x00 7. "RX2_RXHS_DATA_OFFSET_CAL_EN_OVR_EN_RW,Data Offset Calibration Override Enable Control" "0,1"
newline
bitfld.byte 0x00 6. "RX2_CAL_DONE_OVR_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 5. "RX2_CAL_DONE_OVR_EN_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 4. "RX2_START_CALIBRATION_OVR_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 3. "RX2_START_CALIBRATION_OVR_EN_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 2. "RX2_RXHS_DATA_OFFSET_CAL_OVR_EN_RW,Offset Calibration Setting Override" "0,1"
group.byte 0xF80++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_OVRVALUE2,Lane 0 Offset Compensation Control"
hexmask.byte 0x00 1.--7. 1. "RX0_RXHS_DATA_OFFSET_CAL_OVR_RW__6__0__,Offset Calibration Setting Override Enable"
newline
bitfld.byte 0x00 0. "RX0_RXHS_DATA_OFFSET_CAL_EN_OVR_RW,Data Offset Calibration Override Enable Control" "0,1"
rgroup.byte 0xFA3++0x00
line.byte 0x00 "DPHY_DATALANE_OFFSETCAL_COMPS2,Lane Offset Compensation Observability"
bitfld.byte 0x00 2. "RX0_CAL_ERROR,Offset Calibration Algorithm Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_CAL_DONE,Offset Calibration Algorithm Done (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX0_START_CALIBRATION,Offset Calibration Algorithm Start (Volatile)" "0,1"
rgroup.byte 0xFA5++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_VALUE2,Lane Offset Compensation Observability"
bitfld.byte 0x00 7. "RX0_RXHS_DATA_OFFSET_CAL_EN,Offset calibration algorithm enable (volatile)" "0,1"
newline
hexmask.byte 0x00 0.--6. 1. "RX0_RXHS_DATA_OFFSET_CAL__6__0__,Offset calibration algorithm setting chosen (volatile)"
rgroup.byte 0xFE4++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_COMP2,Lane DDL Tune Observability"
bitfld.byte 0x00 3. "RX0_DDL_START_CALIBRATION_IF,DDL Tune Digital Algorithm Start (Volatile)" "0,1"
newline
bitfld.byte 0x00 2. "RX0_DDL_FINISHED_IF,DDL Tune Done Indication (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_DDL_ERROR_FLAG_IF,DDL Tune Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "DDL_TUNE_EN_LANE0_IF,DDL Tune Analog Circuitry Enable Indication (Volatile)" "0,1"
rgroup.byte 0xFE9++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_VALUE2,Lane 0 DDL Tune Observability"
bitfld.byte 0x00 5. "RX0_RXHS_DDL_PHASE_CHANGE_P_IF,RX HS DDL Phase Change (Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_IF__4__0__,RX HS DDL Tunning Setting (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x100B++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_OVRVALUE2,Lane 0 DDL Tune Control"
rbitfld.byte 0x00 6.--7. "reserved_0,Reserved field" "0,1,2,3"
newline
bitfld.byte 0x00 5. "RX0_RXHS_DDL_TUNE_OVR_EN_RW,RX HS DDL Tune Override Enable Control" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_OVR_RW__4__0__,RX HS DDL Tune Override for Lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x110B++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_OVRVALUE3,Lane 0 DDL Tune Control"
rbitfld.byte 0x00 6.--7. "RESERVED_0,Reserved field" "0,1,2,3"
newline
bitfld.byte 0x00 5. "RX0_RXHS_DDL_TUNE_OVR_EN_RW,RX HS DDL Tune Override Enable Control" "0,1"
newline
bitfld.byte 0x00 4. "RX0_RXHS_DDL_TUNE_OVR_RW__4,RX HS DDL Tune Override for Lane 0" "0,1"
newline
rbitfld.byte 0x00 1.--3. "RESERVED_1,Reserved field" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 0. "RX0_RXHS_DDL_TUNE_OVR_RW__4__0__,RX HS DDL Tune Override for Lane 0" "0,1"
group.byte 0x110F++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_OVRVALUE13,Lane 1 Control"
bitfld.byte 0x00 7. "RX1_RXHS_DDL_PHASE_CLK_OVR_EN_RW,RX HS DDL Phase Data Override Control" "0,1"
newline
bitfld.byte 0x00 2.--6. "RX1_RXHS_DDL_PHASE_CLK_OVR_RW__4__0__,RX HS DDL Phase Clock Override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.byte 0x00 1. "RX1_RXHS_DDL_PHASE_CHANGE_P_OVR_EN_RW,RX HS DDL Phase Changed Override Control" "0,1"
newline
bitfld.byte 0x00 0. "RX1_RXHS_DDL_PHASE_CHANGE_P_OVR_RW,RX HS DDL Phase Changed Override Control" "0,1"
group.byte 0x1110++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_OVRVALUE23,Lane 1 Control"
rbitfld.byte 0x00 5.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 4. "RX1_RXHS_DDL_PHASE_DATA_OVR_EN_RW,Override Enable for DDL Phase Data" "0,1"
newline
bitfld.byte 0x00 0.--3. "RX1_RXHS_DDL_PHASE_DATA_OVR_RW__3__0__,RX HS DDL phase clock override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x1133++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_COMPS3,Lane 0 Observability"
bitfld.byte 0x00 4. "RX0_DESKEWCALFAILED_IF,Register is used to observe (read_only) the value of rx0_deskewcalfailed_if which is the deskew calibration error flag" "0,1"
newline
bitfld.byte 0x00 3. "RX0_DESKEWCALDONE_IF,Register is used to observe (read_only) the value of rx0_deskewcaldone_if which is the deskew calibration process completion flag" "0,1"
newline
bitfld.byte 0x00 2. "LSRXCLK_LANE0,Low-Speed Clock(Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--1. "LPRXDOUTULP_LANE0__1__0__,Register is used to observe (read_only) the value of lprxdoutulp_lane0_if which is the output of the ulp comparator" "0,1,2,3"
rgroup.byte 0x1138++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_VALUE13,Lane 1 Observability"
bitfld.byte 0x00 7. "RESERVED_0,Reserved field" "0,1"
newline
bitfld.byte 0x00 2.--6. "RX1_RXHS_DDL_PHASE_CLK_IF__4__0__,Clock DDL Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.byte 0x00 1. "RX1_RXHS_DDL_PHASE_CHANGE_P_IF,DDL Setting Change Latch Pulse (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX1_PM_START,Pattern Matcher Start Flag Observation (Volatile)" "0,1"
rgroup.byte 0x1139++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_VALUE23,Lane 1 Observability"
bitfld.byte 0x00 4.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0.--3. "RX1_RXHS_DDL_PHASE_DATA_IF__3__0__,Data DDl Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x117F++0x00
line.byte 0x00 "DPHY_DATAL3OFFSETCAL_OVRCNTRL,Lane 1 Offset Compensation Control"
bitfld.byte 0x00 7. "RX3_RXHS_DATA_OFFSET_CAL_EN_OVR_EN_RW,Data Offset Calibration Override Enable Control" "0,1"
newline
bitfld.byte 0x00 6. "RX3_CAL_DONE_OVR_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 5. "RX3_CAL_DONE_OVR_EN_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 4. "RX3_START_CALIBRATION_OVR_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 3. "RX3_START_CALIBRATION_OVR_EN_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 2. "RX3_RXHS_DATA_OFFSET_CAL_OVR_EN_RW,Offset Calibration Setting Override" "0,1"
group.byte 0x1180++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_OVRVALUE3,Lane 0 Offset Compensation Control"
hexmask.byte 0x00 1.--7. 1. "RX0_RXHS_DATA_OFFSET_CAL_OVR_RW__6__0__,Offset Calibration Setting Override Enable"
newline
bitfld.byte 0x00 0. "RX0_RXHS_DATA_OFFSET_CAL_EN_OVR_RW,Data Offset Calibration Override Enable Control" "0,1"
rgroup.byte 0x11A3++0x00
line.byte 0x00 "DPHY_DATALANE_OFFSETCAL_COMPS3,Lane Offset Compensation Observability"
bitfld.byte 0x00 2. "RX0_CAL_ERROR,Offset Calibration Algorithm Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_CAL_DONE,Offset Calibration Algorithm Done (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX0_START_CALIBRATION,Offset Calibration Algorithm Start (Volatile)" "0,1"
rgroup.byte 0x11A5++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_VALUE3,Lane Offset Compensation Observability"
bitfld.byte 0x00 7. "RX0_RXHS_DATA_OFFSET_CAL_EN,Offset calibration algorithm enable (volatile)" "0,1"
newline
hexmask.byte 0x00 0.--6. 1. "RX0_RXHS_DATA_OFFSET_CAL__6__0__,Offset calibration algorithm setting chosen (volatile)"
rgroup.byte 0x11E4++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_COMP3,Lane DDL Tune Observability"
bitfld.byte 0x00 3. "RX0_DDL_START_CALIBRATION_IF,DDL Tune Digital Algorithm Start (Volatile)" "0,1"
newline
bitfld.byte 0x00 2. "RX0_DDL_FINISHED_IF,DDL Tune Done Indication (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_DDL_ERROR_FLAG_IF,DDL Tune Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "DDL_TUNE_EN_LANE0_IF,DDL Tune Analog Circuitry Enable Indication (Volatile)" "0,1"
rgroup.byte 0x11E9++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_VALUE3,Lane 0 DDL Tune Observability"
bitfld.byte 0x00 5. "RX0_RXHS_DDL_PHASE_CHANGE_P_IF,RX HS DDL Phase Change (Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_IF__4__0__,RX HS DDL Tunning Setting (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x146A++0x00
line.byte 0x00 "DPHY_PLL_VREF_CONFIG,PLL control"
hexmask.byte 0x00 0.--7. 1. "PLL_MPLL_PROG_RW__7__0__,PLL analog programmability control If you select the bits Result is 7 Nothing is visible on the analog test bus"
group.byte 0x14AA++0x00
line.byte 0x00 "DPHY_CB_VBE_SEL,Common Block Control"
bitfld.byte 0x00 5.--6. "CB_SEL_VREFCD_LPRX_RW__1__0__,LPRX Contention Detector Voltage Reference Selection" "0: CB_SEL_VREFCD_LPRX_RW__1__0___0,1: CB_SEL_VREFCD_LPRX_RW__1__0___1,2: CB_SEL_VREFCD_LPRX_RW__1__0___2,3: CB_SEL_VREFCD_LPRX_RW__1__0___3"
newline
bitfld.byte 0x00 2.--4. "CB_SEL_V400_PROG_RW__2__0__,Select Value Of cb_v400" "0: CB_SEL_V400_PROG_RW__2__0___0,1: CB_SEL_V400_PROG_RW__2__0___1,2: CB_SEL_V400_PROG_RW__2__0___2,3: CB_SEL_V400_PROG_RW__2__0___3,?..."
newline
bitfld.byte 0x00 1. "CB_SEL_CHOP_CLK_RW,Select Bandgap Clock Source" "0: Internal oscillator (internal clock source),1: External clock signal"
newline
bitfld.byte 0x00 0. "CB_CHOP_CLK_EN_RW,Bandgap Chop Clock Enable" "0: CB_CHOP_CLK_EN_RW_0,1: Chop clock switching"
group.byte 0x14AB++0x00
line.byte 0x00 "DPHY_ATB_CB_ATB_VBE_SEL,Common Block Control"
bitfld.byte 0x00 6. "CB_ATB_VBE_SEL_RW,VBE Selection To Analog Test Bus (ATB)" "0,1"
newline
bitfld.byte 0x00 3.--5. "TXLP_PROG_RW_2_0,LP-TX programmability" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 2. "CB_SEL_VREFLPTX_PROG_RW,LP-TX Voltage Reference Selection" "0: CB_SEL_VREFLPTX_PROG_RW_0,1: CB_SEL_VREFLPTX_PROG_RW_1"
newline
bitfld.byte 0x00 0.--1. "CB_SEL_VREF_LPRX_RW_1_0,LP-RX Contention Detector Voltage Reference Selection" "0: CB_SEL_VREF_LPRX_RW_1_0_0,1: CB_SEL_VREF_LPRX_RW_1_0_1,2: CB_SEL_VREF_LPRX_RW_1_0_2,3: CB_SEL_VREF_LPRX_RW_1_0_3"
group.byte 0x1509++0x00
line.byte 0x00 "DPHY_TX_RDWR_TERM_CAL_0,Termination Calibration Control"
bitfld.byte 0x00 4.--7. "CB_CAL_REPL_OVR_RW__3__0__,Calibration word for termination lower section override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 3. "CB_CAL_EN_UP_OVR_RW,Upper section termination calibration algorithm enable override" "0,1"
newline
bitfld.byte 0x00 2. "CB_CAL_EN_UP_OVR_EN_RW,Upper section termination calibration algorithm enable override enable" "0,1"
newline
bitfld.byte 0x00 1. "CB_CAL_EN_OVR_RW,Allow to override the lower part termination control" "0,1"
newline
bitfld.byte 0x00 0. "CB_CAL_EN_OVR_EN_RW,Allow to override the lower part termination control" "0,1"
group.byte 0x150A++0x00
line.byte 0x00 "DPHY_TX_TERM_CAL_OVR,Termination Calibration Control"
bitfld.byte 0x00 7. "CB_EN_45_OHM_RW,Selection For 45 ohm Termination Impedance" "0,1"
newline
bitfld.byte 0x00 6. "CB_CAL_REPL_UP_OVR_EN_RW,Upper Section Termination Replica Setting" "0,1"
newline
bitfld.byte 0x00 2.--5. "CB_CAL_REPL_UP_OVR_RW__3__0__,Upper Section Termination Replica Setting Override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 1. "CB_CAL_REPL_UP_BYPASS_RW,Upper Section Of Termination Replica Calibration Bypass" "0,1"
newline
bitfld.byte 0x00 0. "CB_CAL_REPL_OVR_EN_RW,Calibration Word For Termination Lower Section replica Override Enable" "0,1"
rgroup.byte 0x1520++0x00
line.byte 0x00 "DPHY_TX_TERM_CAL_0,Termination Calibration Observability"
bitfld.byte 0x00 6. "CB_SEL_UP_1ST,Register is used to observe (read_only) Boosting voltage selection for upper section of TX replica to be probed on ATB bus" "0,1"
newline
bitfld.byte 0x00 2.--5. "CB_CAL_REPL__3__0__,Register is used to observe (read_only) Termination lower section replica setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 1. "CB_CAL_EN_UP,Register is used to observe (read_only) Termination upper section analog circuitry enable" "0,1"
newline
bitfld.byte 0x00 0. "CB_CAL_EN,Register is used to observe (read_only) Termination lower section analog circuitry enable" "0,1"
rgroup.byte 0x1521++0x00
line.byte 0x00 "DPHY_TX_TERM_CAL_1,Termination Calibration Observability"
bitfld.byte 0x00 7. "RESCAL_DONE,Lower Section Termination Calibration Algorithm Done (Volatile)" "0,1"
newline
bitfld.byte 0x00 6. "RESCAL_UP_EN,Upper Section Termination Calibration Algorithm Enable (Volatile)" "0,1"
newline
bitfld.byte 0x00 5. "RESCAL_EN,Lower Section Termination Calibration Algorithm Enable (Volatile)" "0,1"
newline
bitfld.byte 0x00 4. "CB_COMP_OUT,Register is used to observe (read_only) the value of rx_cb_comp_out_if which is the output of the ATB comparator" "0,1"
newline
bitfld.byte 0x00 0.--3. "CB_CAL_REPL_UP__3__0__,Termination Upper Section Replica Setting (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x1522++0x00
line.byte 0x00 "DPHY_TERMCAL_STAT2,Termination Calibration Observability"
bitfld.byte 0x00 2. "RESCAL_UP_ERROR,Register is used to observe (read_only) Termination upper section calibration algorithm error" "0,1"
newline
bitfld.byte 0x00 1. "RESCAL_UP_DONE,Register is used to observe (read_only) Termination upper section calibration algorithm done" "0,1"
newline
bitfld.byte 0x00 0. "RESCAL_ERROR,Register is used to observe (read_only) Termination upper section calibration algorithm error" "0,1"
group.byte 0x1607++0x00
line.byte 0x00 "DPHY_CLKLANE_POLCFG,Clock Lane Control"
bitfld.byte 0x00 0. "POLARITY_CLKLANE_RW,Clock Lane DP/DN Swap - Active High" "0,1"
group.byte 0x1A01++0x00
line.byte 0x00 "DPHY_ATB_DATA_LANE1,Lane 1 Control"
bitfld.byte 0x00 7. "HSTXBITREV_LANE1_RW,Allows inverting serialization order in lane 1 (MSB -> LSB)" "0,1"
newline
bitfld.byte 0x00 6. "BINTPON_LANE1_RW,Bias Block Power-On" "0,1"
newline
bitfld.byte 0x00 5. "BINTPON_BYPASS_LANE1_RW,Bias Block Power-On Bypass Override" "0,1"
newline
bitfld.byte 0x00 1.--4. "ATB_SEL_LANE1_RW_3_0,Analog Test Bus Signals Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0. "ATB_LPTX1200_ON_LANE1_RW,Select to probe in analog test bus LP transmitter voltage reference" "0,1"
group.byte 0x1C01++0x00
line.byte 0x00 "DPHY_ATB_DATA_LANE2,Lane 2 Control"
bitfld.byte 0x00 7. "HSTXBITREV_LANE2_RW,Allows inverting serialization order in lane 2 (MSB -> LSB)" "0,1"
newline
bitfld.byte 0x00 6. "BINTPON_LANE2_RW,Bias Block Power-On" "0,1"
newline
bitfld.byte 0x00 5. "BINTPON_BYPASS_LANE2_RW,Bias Block Power-On Bypass Override" "0,1"
newline
bitfld.byte 0x00 1.--4. "ATB_SEL_LANE2_RW_3_0,Analog Test Bus Signals Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0. "ATB_LPTX1200_ON_LANE2_RW,Selection to probe in analog test bus LP transmitter voltage reference" "0,1"
group.byte 0x1E01++0x00
line.byte 0x00 "DPHY_ATB_DATA_LANE3,Lane 3 Control"
bitfld.byte 0x00 7. "HSTXBITREV_LANE3_RW,Allows inverting serialization order in lane 3 (MSB -> LSB)" "0,1"
newline
bitfld.byte 0x00 6. "BINTPON_LANE3_RW,Bias Block Power-On" "0,1"
newline
bitfld.byte 0x00 5. "BINTPON_BYPASS_LANE3_RW,Bias Block Power-On Bypass Override" "0,1"
newline
bitfld.byte 0x00 1.--4. "ATB_SEL_LANE3_RW_3_0,Analog Test Bus Signals Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0. "ATB_LPTX1200_ON_LANE3_RW,Selection to probe in analog test bus LP transmitter voltage reference" "0,1"
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2000)++0x03
line.long 0x00 "CRC_LINE_NUM_CFG_REGISTER_VC[$1],This register allows configuration for line number in a frame for which the calculated and expected CRC value need to be captured for VC@{i $1"
bitfld.long 0x00 31. "CRC_LINE_NUM_EN,This field allows configuring if CRC for each received packet needs to be captured/updated in register or should be done for only the configured line number" "0: CRC value is captured for each line received..,1: CRC value is captured for configured line.."
newline
bitfld.long 0x00 16.--21. "CRC_CFG_DATA_TYPE,Data-type for which CRC received and calculated need to be captured" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "CRC_LINE_NUM,Line number for which CRC received and calculated need to be captured"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x2010)++0x03
line.long 0x00 "CRC_REGISTER[$1],This register records the CRC value calculated by the controller and the CRC value that is received by the controller for every packet of the VC@{i $1"
hexmask.long.word 0x00 16.--31. 1. "PAYLOAD_CRC_CALCULATED,CRC calculated by the controller on the incoming packet"
newline
hexmask.long.word 0x00 0.--15. 1. "PAYLOAD_CRC_RECEIVED,CRC received by the controller along with the packet"
repeat.end
group.long 0x2100++0x03
line.long 0x00 "AXI_WRITE_CFG,AXI write channel configuration"
bitfld.long 0x00 5.--6. "AXI_DOMAIN,This field is programmed to program the shareability domain of the write transaction on AXI channel" "0,1,2,3"
newline
bitfld.long 0x00 1.--4. "AXI_AWCACHE,This field is used to program the cacheability of the AXI write transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "AXI_WRITE_CFG_EN,AXI write channel configuration Enable" "0: AXI write channel configuration through..,1: AXI write channel configuration through.."
group.long 0x2108++0x03
line.long 0x00 "MIPICSI2_SCRAMBLING_CFG,Scrambling configuration"
bitfld.long 0x00 1. "Reserved,Reserved" "0,1"
newline
bitfld.long 0x00 0. "CFG_DESCRAMBLE_EN,This field is used to enable the descrambling in CSI2" "0: Descrambling is Disabled,1: Descrambling on incoming MIPICSI2 stream is.."
repeat 12. (increment 0 1)(increment  0 0x30)
tree "RX[$1]"
group.long ($2+0x100)++0x03
line.long 0x00 "RX_CBUF_CONFIG,Receive Data Circular Buffer Configuration"
bitfld.long 0x00 10. "FIFTHCH_ENABLE,Fifth channel data capture enabled for the buffer" "0: Fifth channel data capture disabled for..,1: Fifth channel data capture enabled for.."
bitfld.long 0x00 8.--9. "VCID,This field indicates the virtual channel the content of which is to be received in the circular buffer" "0: VC to be received is VC0,1: VC to be received is VC1,2: VC to be received is VC2,3: VC to be received is VC3"
newline
bitfld.long 0x00 2.--7. "DATAID,This field indicates the data type to be received in the circular buffer" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,18: Embedded packet,?,?,?,?,?,?,?,?,?,?,?,30: YUV 422,31: YUV 422,?,?,34: RGB 565 packet,?,36: RGB 888 packet,?,?,?,?,?,42: RAW 8 packet,43: RAW 10 packet,44: RAW 12 packet,45: RAW 14 packet,46: RAW 16 packet,?,48: User-defined packet,49: User-defined packet,50: User-defined packet,51: User-defined packet,52: User-defined packet,53: User-defined packet,54: User-defined packet,55: User-defined packet,?..."
bitfld.long 0x00 0. "TRACE,This field indicates whether the data being written over the current buffer is a traceable AXI transaction" "0: Non-traceable transaction,1: Traceable transaction"
group.long ($2+0x104)++0x03
line.long 0x00 "RX_INPLINELEN_CONFIG,Receive Data Input Line Length Configuration"
hexmask.long.word 0x00 0.--15. 1. "INPLINELEN,Expected length of the incoming MIPI packet in bytes Minimum no"
group.long ($2+0x108)++0x03
line.long 0x00 "RX_LINELEN_CONFIG,Receive Data Line Length Configuration"
hexmask.long.word 0x00 0.--15. 1. "LINELEN,Expected length of the packet in bytes to be received"
group.long ($2+0x10C)++0x03
line.long 0x00 "RX_NUMLINES_CONFIG,Receive Data Expected Number of Lines Configuration"
hexmask.long.word 0x00 0.--15. 1. "NUMLINES,Number of Lines"
group.long ($2+0x110)++0x03
line.long 0x00 "RX_CBUF_SRTPTR,Receive Data Circular Buffer Start Pointer"
hexmask.long 0x00 4.--31. 1. "STRPTR,Start address offset of the circular buffer for MIPICSI2 receive data"
group.long ($2+0x114)++0x03
line.long 0x00 "RX_CBUF_BUFLEN,Receive Data Circular Buffer Length"
hexmask.long.word 0x00 0.--15. 1. "BUFLEN,16-byte aligned length for each line written in the circular buffer for MIPICSI2 data"
group.long ($2+0x118)++0x03
line.long 0x00 "RX_CBUF_NUMLINE,Receive Data Circular Buffer Number of Lines"
bitfld.long 0x00 31. "CBUF_START_PTR_RESET,If this field is set circular buffer pointer for next frame will be set to the start pointer of circular buffer" "0: Circular buffer pointer for next frame will..,1: Circular buffer pointer for next frame will.."
hexmask.long.word 0x00 0.--15. 1. "NUMLINES,Number of lines in the circular buffer for MIPICSI2 received data"
group.long ($2+0x11C)++0x03
line.long 0x00 "RX_CBUF_LPDI,Receive Data Circular Buffer Lines Done Generation"
hexmask.long.byte 0x00 0.--7. 1. "NUMLINES,Number of lines captured in the circular buffer after which done trigger is generated"
rgroup.long ($2+0x120)++0x03
line.long 0x00 "RX_CBUF_NXTLINE,Receive Data Circular Buffer Next Row Indication"
hexmask.long.word 0x00 0.--15. 1. "NXTLINE,Row number in the circular buffer where next line of MIPICSI2 received data is to be written"
rgroup.long ($2+0x124)++0x03
line.long 0x00 "RX_CBUF_RXLINE,Receive Data Circular Buffer Total Lines Received Status"
hexmask.long.word 0x00 0.--15. 1. "TOTLINES,Total Number of Lines"
rgroup.long ($2+0x128)++0x03
line.long 0x00 "RX_CBUF_ERRLEN,Receive Data Circular Buffer Error Line Length Status"
hexmask.long.word 0x00 0.--15. 1. "ERRLEN,Length of first line in bytes the length of which is different from the one configured for the circular buffer for MIPICSI2 received data"
rgroup.long ($2+0x12C)++0x03
line.long 0x00 "RX_CBUF_ERRLINE,Receive Data Circular Buffer Line Number for Incorrect Length Status"
hexmask.long.word 0x00 0.--15. 1. "ERRLINE,Line number of first line the length of which is different from the one configured for the circular buffer for MIPICSI2 received data"
tree.end
repeat.end
repeat 4. (increment 0 1)(increment  0 0xFFFFFFB0)
tree "RX_VC[$1]"
group.long ($2+0xA0)++0x03
line.long 0x00 "PPERRIS,Receive Data Protocol and Packet Error Interrupt Status for VCi"
eventfld.long 0x00 6. "Reserved,Reserved" "0,1"
eventfld.long 0x00 5. "INVIDERR,Invalid ID Detected in Received Data Stream" "0,1"
eventfld.long 0x00 4. "CRCERR,CRC Error in Received Data Stream" "0,1"
eventfld.long 0x00 3. "ERFDAT,Error in Data in Received Data Stream" "0,1"
eventfld.long 0x00 2. "ERFSYN,Frame Synchronization Error in Received Data Stream" "0,1"
eventfld.long 0x00 1. "ECCTWO,2-Bit ECC Error in Received Packet Header" "0,1"
eventfld.long 0x00 0. "ECCONE,1-Bit ECC Error in Received Packet Header" "0,1"
group.long ($2+0xA4)++0x03
line.long 0x00 "PPERRIE,Receive Data Protocol and Packet Error Interrupt Enable for VCi"
bitfld.long 0x00 6. "Reserved,Reserved" "0,1"
bitfld.long 0x00 5. "INVIDERRIE,Invalid ID Interrupt Enable" "0,1"
bitfld.long 0x00 4. "CRCERRIE,CRC Error Interrupt Enable" "0,1"
bitfld.long 0x00 3. "ERFDATIE,Frame Data Error Interrupt Enable" "0,1"
bitfld.long 0x00 2. "ERFSYNIE,Frame Synchronization Error Interrupt Enable" "0,1"
bitfld.long 0x00 1. "ECCTWOIE,ECC 2-Bit Error Interrupt Enable" "0,1"
bitfld.long 0x00 0. "ECCONEIE,ECC 1-Bit Error Interrupt Enable" "0,1"
rgroup.long ($2+0xA8)++0x03
line.long 0x00 "ERRPOS,Receive ECC 1-Bit Error Position for VCi"
bitfld.long 0x00 0.--4. "ERRPOS,Error Position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long ($2+0xAC)++0x03
line.long 0x00 "NUMPPERR,Receive Packets Number of Protocol Errors for VCi"
hexmask.long.word 0x00 16.--31. 1. "NUMECCERR,Number of ECC 2-Bit Errors"
hexmask.long.word 0x00 0.--15. 1. "NUMCRCERR,Number of CRC Errors"
tree.end
repeat.end
tree.end
tree "MIPICSI2_1"
base ad:0x44090000
group.long 0x00++0x03
line.long 0x00 "DPHY_RSTCFG,DPHY Reset Configuration"
bitfld.long 0x00 1. "RSTZ,This field puts the digital portion of DPHY under reset" "0: Digital portion of DPHY in reset,1: Digital portion of DPHY out of reset"
newline
bitfld.long 0x00 0. "SHUTDWNZ,This field puts the entire DPHY under reset" "0: DPHY in reset (including digital portion),1: DPHY out of reset (including digital portion)"
group.long 0x08++0x03
line.long 0x00 "DPHY_CLEAR,DPHY Clear"
bitfld.long 0x00 0. "CLRREG,This field is used for clearing the DPHY register space before any configuration is performed" "0: DPHY registers are out of reset,1: DPHY registers in reset"
group.long 0x0C++0x03
line.long 0x00 "DPHY_FREQCFG,DPHY Frequency Configuration"
hexmask.long.byte 0x00 7.--14. 1. "CLKFREQRNG,This field allows configuring the system clock frequency configuration preset"
newline
hexmask.long.byte 0x00 0.--6. 1. "HSFREQRNG,This field allows selection of operating frequency range for the DPHY"
group.long 0x18++0x03
line.long 0x00 "RX_RXNULANE,Receive Number of Lanes Configuration"
bitfld.long 0x00 0.--3. "RXNULANE,Number of data lanes enabled for high-speed MIPICSI2 data reception" "0: Controller off,1: High-speed data reception on lane 0 only,2: High-speed data reception on lanes 0 and 1,3: High-speed data reception on lanes 0 1 and 2,4: High-speed data reception on all data lanes,?..."
group.long 0x1C++0x03
line.long 0x00 "RX_RXENABLE,Receive Enable Configuration"
bitfld.long 0x00 5.--8. "CFG_FLUSH_CNT,This field is used to program the FIFO flush count in different speeds of operation in the receive controller" "?,?,?,3: For data rates greater than 200 MHz,?,?,?,7: For data rates up to 200 MHz,?..."
newline
bitfld.long 0x00 1.--4. "CFG_DATA_LANE_EN,Enables the PHY Data Lanes" "?,1: Enable lane 0 of the DPHY,2: Enable lane 1 of the DPHY,?,4: Enable lane 2 of the DPHY,?,?,?,8: Enable lane 3 of the DPHY,?..."
newline
bitfld.long 0x00 0. "CFG_CLK_LANE_EN,Enables the PHY Clock Lane" "0: Clock lane is not enabled,1: Clock lane is enabled"
group.long 0x20++0x03
line.long 0x00 "RX_RXLANESWAP,Receive Lane Swap Configuration"
bitfld.long 0x00 6.--7. "O_CFG_LANE3_SEL,Selects the PPI interface lane that is used as lane 3 by the RX core" "0: O_CFG_LANE3_SEL_0,1: O_CFG_LANE3_SEL_1,2: O_CFG_LANE3_SEL_2,3: O_CFG_LANE3_SEL_3"
newline
bitfld.long 0x00 4.--5. "O_CFG_LANE2_SEL,Selects the PPI interface lane that is used as lane 2 by the RX core" "0: O_CFG_LANE2_SEL_0,1: O_CFG_LANE2_SEL_1,2: O_CFG_LANE2_SEL_2,3: O_CFG_LANE2_SEL_3"
newline
bitfld.long 0x00 2.--3. "O_CFG_LANE1_SEL,Selects the PPI interface lane that is used as lane 1 by the RX core" "0: O_CFG_LANE1_SEL_0,1: O_CFG_LANE1_SEL_1,2: O_CFG_LANE1_SEL_2,3: O_CFG_LANE1_SEL_3"
newline
bitfld.long 0x00 0.--1. "O_CFG_LANE0_SEL,Selects the PPI interface lane that is used as lane 0 by the RX core" "0: O_CFG_LANE0_SEL_0,1: O_CFG_LANE0_SEL_1,2: O_CFG_LANE0_SEL_2,3: O_CFG_LANE0_SEL_3"
rgroup.long 0x24++0x03
line.long 0x00 "RX_CLKCS,Clock Configuration Status"
bitfld.long 0x00 4. "CULPMA,Clock Lane ULPS Mark Active State" "0: Clock lane not in Mark-1 active state,1: Clock lane is in Mark-1 active state"
newline
bitfld.long 0x00 3. "CULPSA,Clock Lane ULPS Active" "0: Clock lane not in ULPS mode,1: Clock lane in ULPS mode"
newline
bitfld.long 0x00 2. "CSTOP,Clock Lane Stop State" "0: Clock lane not in stop state,1: Clock lane in stop state"
newline
bitfld.long 0x00 1. "ULPSC,Clock Lane ULPS" "0: Clock lane not in the ULP state,1: Clock lane in ultra in the ULP state"
newline
bitfld.long 0x00 0. "HSRA,High-Speed Clock Receive Active" "0: DDR clock not being received on the clock lane,1: Clock lane is receiving DDR clock"
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x28)++0x03
line.long 0x00 "RX_LANCS[$1],D-PHY Lane i Configuration Status $1"
bitfld.long 0x00 5. "DULMA,Data Lane ULPS Mark Active" "0: Data lane 0 is not in Mark-1 state,1: Data lane 0 is in Mark-1 state"
newline
bitfld.long 0x00 4. "DULPA,Data Lane ULPS Active" "0: Data lane 0 ULPS not active,1: Data lane 0 ULPS is active"
newline
bitfld.long 0x00 3. "DSTOP,Data Lane Stop State" "0: Data lane 0 not in the Stop state,1: Data lane 0 in the Stop state"
newline
bitfld.long 0x00 1. "RXACTH,D-PHY Data Lane 0 RX Active High-Speed Data" "0: No high-speed data reception ongoing from the..,1: High-speed data reception ongoing from lane.."
newline
bitfld.long 0x00 0. "RXVALH,Data Lane 0 RX Valid High Speed" "0: No valid high-speed data is being driven from..,1: Valid high-speed data is being driven from.."
repeat.end
group.long 0x38++0x03
line.long 0x00 "RX_SR,Soft Reset Config"
bitfld.long 0x00 31. "SOFRST,Software Reset" "0: Soft reset not requested,1: Soft reset requested"
group.long 0x3C++0x03
line.long 0x00 "RX_VCENABLE,Receive Virtual Channel and circular Buffer Enable Configuration"
bitfld.long 0x00 19. "CBUF11EN,Enable Reception of Data Corresponding to Circular buffer 11" "0: Circular buffer 11 data reception disabled,1: Circular buffer 11 data reception enabled"
newline
bitfld.long 0x00 18. "CBUF10EN,Enable Reception of Data Corresponding to Circular buffer 10" "0: Circular buffer 10 data reception disabled,1: Circular buffer 10 data reception enabled"
newline
bitfld.long 0x00 17. "CBUF9EN,Enable Reception of Data Corresponding to Circular buffer 9" "0: Circular buffer 9 data reception disabled,1: Circular buffer 9 data reception enabled"
newline
bitfld.long 0x00 16. "CBUF8EN,Enable Reception of Data Corresponding to Circular buffer 8" "0: Circular buffer 8 data reception disabled,1: Circular buffer 8 data reception enabled"
newline
bitfld.long 0x00 15. "CBUF7EN,Enable Reception of Data Corresponding to Circular buffer 7" "0: Circular buffer 7 data reception disabled,1: Circular buffer 7 data reception enabled"
newline
bitfld.long 0x00 14. "CBUF6EN,Enable Reception of Data Corresponding to Circular buffer 6" "0: Circular buffer 6 data reception disabled,1: Circular buffer 6 data reception enabled"
newline
bitfld.long 0x00 13. "CBUF5EN,Enable Reception of Data Corresponding to Circular buffer 5" "0: Circular buffer 5 data reception disabled,1: Circular buffer 5 data reception enabled"
newline
bitfld.long 0x00 12. "CBUF4EN,Enable Reception of Data Corresponding to Circular buffer 4" "0: Circular buffer 4 data reception disabled,1: Circular buffer 4 data reception enabled"
newline
bitfld.long 0x00 11. "CBUF3EN,Enable Reception of Data Corresponding to Circular buffer 3" "0: Circular buffer 3 data reception disabled,1: Circular buffer 3 data reception enabled"
newline
bitfld.long 0x00 10. "CBUF2EN,Enable Reception of Data Corresponding to Circular buffer 2" "0: Circular buffer 2 data reception disabled,1: Circular buffer 2 data reception enabled"
newline
bitfld.long 0x00 9. "CBUF1EN,Enable Reception of Data Corresponding to Circular buffer 1" "0: Circular buffer 1 data reception disabled,1: Circular buffer 1 data reception enabled"
newline
bitfld.long 0x00 8. "CBUF0EN,Enable Reception of Data Corresponding to Circular buffer 0" "0: Circular buffer 0 data reception disabled,1: Circular buffer 0 data reception enabled"
newline
bitfld.long 0x00 3. "VC3EN,Enable Reception of Data Corresponding to Virtual Channel 3" "0: Virtual channel 3 data reception disabled,1: Virtual channel 3 data reception enabled"
newline
bitfld.long 0x00 2. "VC2EN,Enable Reception of Data Corresponding to Virtual Channel 2" "0: Virtual channel 2 data reception disabled,1: Virtual channel 2 data reception enabled"
newline
bitfld.long 0x00 1. "VC1EN,Enable Reception of Data Corresponding to Virtual Channel 1" "0: Virtual channel 1 data reception disabled,1: Virtual channel 1 data reception enabled"
newline
bitfld.long 0x00 0. "VC0EN,Enable Reception of Data Corresponding to Virtual Channel 0" "0: Virtual channel 0 data reception disabled,1: Virtual channel 0 data reception enabled"
rgroup.long 0x40++0x03
line.long 0x00 "RX_DATAIDR,Receive Data ID Report"
bitfld.long 0x00 6.--7. "VCID,Virtual channel ID being received currently over MIPICSI2 data lanes" "0: MIPICSI2 packet data being received currently..,1: MIPICSI2 packet data being received currently..,2: MIPICSI2 packet data being received currently..,3: MIPICSI2 packet data being received currently.."
newline
bitfld.long 0x00 0.--5. "DATAID,Data ID of MIPICSI2 Data" "0: Frame start packet being received,1: Frame end packet being received,2: Line start packet being received,3: Line end packet being received,?,?,?,?,8: Generic short packet being received,9: Generic short packet being received,10: Generic short packet being received,11: Generic short packet being received,12: Generic short packet being received,13: Generic short packet being received,?,?,16: Null packet being received,17: Blanking packet being received,18: Embedded packet being received,?,?,?,?,?,?,?,?,?,?,?,30: YUV 422,31: YUV 422,?,?,34: RGB 565 packet being received,?,36: RGB 888 packet being received,?,?,?,?,?,42: RAW 8 packet being received,43: RAW 10 packet being received,44: RAW 12 packet being received,45: RAW 14 packet being received,46: RAW 16 packet being received,?..."
rgroup.long 0x4C++0x03
line.long 0x00 "RX_INVIDR,Receive Invalid Data ID Report"
bitfld.long 0x00 6.--7. "VCID,Virtual channel ID being received currently over MIPICSI2 data lanes" "0: MIPICSI2 packet data being received currently..,1: MIPICSI2 packet data being received currently..,2: MIPICSI2 packet data being received currently..,3: MIPICSI2 packet data being received currently.."
newline
bitfld.long 0x00 0.--5. "DATAID,Unsupported Data ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x50)++0x03
line.long 0x00 "RX_GNSPR_VC[$1],Receive Generic Short Packet Report $1"
hexmask.long.word 0x00 6.--21. 1. "DATA,Data content of the generic short packet being received for processing by the application"
newline
bitfld.long 0x00 0.--5. "DATAID,Data ID of the generic short packet being received currently" "?,?,?,?,?,?,?,?,8: Data ID of the generic packet being received,9: Data ID of the generic packet being received,10: Data ID of the generic packet being received,11: Data ID of the generic packet being received,12: Data ID of the generic packet being received,13: Data ID of the generic packet being received,14: Data ID of the generic packet being received,15: Data ID of the generic packet being received,?..."
repeat.end
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x60)++0x03
line.long 0x00 "RX_NUMPKTS_VC[$1],Receive Number of Packets for VC $1"
hexmask.long.word 0x00 16.--31. 1. "LONGPKTS,Number of Long Packets Received"
newline
hexmask.long.word 0x00 0.--15. 1. "SHORTPKTS,Number of Short Packets Received"
repeat.end
group.long 0x70++0x03
line.long 0x00 "RX_VCINTRS,Receive VC Data Interrupt Status"
eventfld.long 0x00 15. "CRC_CAPTURED3,MIPI protocol received CRC for the configured data type line is available in the register" "0,1"
newline
eventfld.long 0x00 14. "CRC_CAPTURED2,MIPI protocol received CRC for the configured data type line is available in the register" "0,1"
newline
eventfld.long 0x00 13. "CRC_CAPTURED1,MIPI protocol received CRC for the configured data type line is available in the register" "0,1"
newline
eventfld.long 0x00 12. "CRC_CAPTURED0,MIPI protocol received CRC for the configured data type line is available in the register" "0,1"
newline
eventfld.long 0x00 11. "GNSP3,Generic Short Packet Received on Virtual Channel 3" "0,1"
newline
eventfld.long 0x00 10. "FE3,Frame End on Virtual Channel 3" "0,1"
newline
eventfld.long 0x00 9. "FS3,Frame Start on Virtual Channel 3" "0,1"
newline
eventfld.long 0x00 8. "GNSP2,Generic Short Packet Received on Virtual Channel 2" "0,1"
newline
eventfld.long 0x00 7. "FE2,Frame End on Virtual Channel 2" "0,1"
newline
eventfld.long 0x00 6. "FS2,Frame Start on Virtual Channel 2" "0,1"
newline
eventfld.long 0x00 5. "GNSP1,Generic Short Packet Received on Virtual Channel 1" "0,1"
newline
eventfld.long 0x00 4. "FE1,Frame End on Virtual Channel 1" "0,1"
newline
eventfld.long 0x00 3. "FS1,Frame Start on Virtual Channel 1" "0,1"
newline
eventfld.long 0x00 2. "GNSP0,Generic Short Packet Received on Virtual Channel 0" "0,1"
newline
eventfld.long 0x00 1. "FE0,Frame End on Virtual Channel 0" "0,1"
newline
eventfld.long 0x00 0. "FS0,Frame Start on Virtual Channel 0" "0,1"
group.long 0x74++0x03
line.long 0x00 "RX_VCINTRE,Receive Data VC Event Interrupt Enable"
bitfld.long 0x00 15. "CRC_CAPTUREDIE3,Interrupt enable for receiving interrupt on receiving CRC for the configured data type" "0,1"
newline
bitfld.long 0x00 14. "CRC_CAPTUREDIE2,Interrupt enable for receiving interrupt on receiving CRC for the configured data type" "0,1"
newline
bitfld.long 0x00 13. "CRC_CAPTUREDIE1,Interrupt enable for receiving interrupt on receiving CRC for the configured data type" "0,1"
newline
bitfld.long 0x00 12. "CRC_CAPTUREDIE0,Interrupt enable for receiving interrupt on receiving CRC for the configured data type" "0,1"
newline
bitfld.long 0x00 11. "GNSPIE3,Generic Short Packet Received on Virtual Channel 3 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 10. "FEIE3,Frame End on Virtual Channel 3 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 9. "FSIE3,Frame Start on Virtual Channel 3 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 8. "GNSPIE2,Generic Short Packet Received on Virtual Channel 2 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 7. "FEIE2,Frame End on Virtual Channel 2 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 6. "FSIE2,Frame Start on Virtual Channel 2 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 5. "GNSPIE1,Generic Short Packet Received on Virtual Channel 1 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 4. "FEIE1,Frame End on Virtual Channel 1 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 3. "FSIE1,Frame Start on Virtual Channel 1 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 2. "GNSPIE0,Generic Short Packet Received on Virtual Channel 0 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 1. "FEIE0,Frame End on Virtual Channel 0 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 0. "FSIE0,Frame Start on Virtual Channel 0 Interrupt Enable" "0,1"
rgroup.long 0x90++0x03
line.long 0x00 "CONTROLLER_STATUS_REGISTER,Controller Status"
bitfld.long 0x00 0.--5. "ECC_RECEIVED,This field reports the ECC value received at the controller end" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x98++0x03
line.long 0x00 "CONTROLLER_ERR_STATUS_REGISTER,Controller Error Status"
eventfld.long 0x00 1. "FIFO_OVERFLOW_ERROR,This field indicates overflow of the internal FIFO in the controller" "0,1"
newline
eventfld.long 0x00 0. "EXIT_HS_ERROR,Asserted at the end of the packet by the controller to indicate that the PHY has stopped high speed transmission before the number of required bytes have been received" "0,1"
group.long 0x9C++0x03
line.long 0x00 "CONTROLLER_ERR_IE,Controller Interrupt Enable"
bitfld.long 0x00 1. "HS_EXIT_ERRIE,Enables the interrupt for the High speed exit error reporting to the system" "0,1"
newline
bitfld.long 0x00 0. "FIFO_OVERFLOW_ERRIE,Enables the interrupt for the FIFO overflow error reporting to the system" "0,1"
group.long 0xE4++0x03
line.long 0x00 "RX_PHYERRIS,Receive Data PHY Level Error Interrupt Status"
eventfld.long 0x00 19. "ERCTRL3,Control Command Error on Lane 3" "0,1"
newline
eventfld.long 0x00 18. "ERSYES3,Synchronization Error in Escape Mode on Lane 3" "0,1"
newline
eventfld.long 0x00 17. "ERRESC3,Escape Mode Entry Error on Lane 3" "0,1"
newline
eventfld.long 0x00 16. "NOSYN3,Multi-Bit Error in Synchronization Pattern Detected on Lane 3" "0,1"
newline
eventfld.long 0x00 15. "ERRSY3,Error in Synchronization Pattern Detected on Lane 3" "0,1"
newline
eventfld.long 0x00 14. "ERCTRL2,Control Command Error on Lane 2" "0,1"
newline
eventfld.long 0x00 13. "ERSYES2,Synchronization Error in Escape Mode on Lane 2" "0,1"
newline
eventfld.long 0x00 12. "ERRESC2,Escape Mode Entry Error on Lane 2" "0,1"
newline
eventfld.long 0x00 11. "NOSYN2,Multi-Bit Error in Synchronization Pattern Detected on Lane 2" "0,1"
newline
eventfld.long 0x00 10. "ERRSY2,Error in Synchronization Pattern Detected on Lane 2" "0,1"
newline
eventfld.long 0x00 9. "ERCTRL1,Control Command Error on Lane 1" "0,1"
newline
eventfld.long 0x00 8. "ERSYES1,Synchronization Error in Escape Mode on Lane 1" "0,1"
newline
eventfld.long 0x00 7. "ERRESC1,Escape Mode Entry Error on Lane 1" "0,1"
newline
eventfld.long 0x00 6. "NOSYN1,Multi-Bit Error in Synchronization Pattern Detected on Lane 1" "0,1"
newline
eventfld.long 0x00 5. "ERRSY1,Error in Synchronization Pattern Detected on Lane 1" "0,1"
newline
eventfld.long 0x00 4. "ERCTRL0,Control Command Error on Lane 0" "0,1"
newline
eventfld.long 0x00 3. "ERSYES0,Synchronization Error in Escape Mode on Lane 0" "0,1"
newline
eventfld.long 0x00 2. "ERRESC0,Escape Mode Entry Error on Lane 0" "0,1"
newline
eventfld.long 0x00 1. "NOSYN0,Multi-Bit Error in Synchronization Pattern Detected on Lane 0" "0,1"
newline
eventfld.long 0x00 0. "ERRSY0,Error in Synchronization Pattern Detected on Lane 0" "0,1"
group.long 0xE8++0x03
line.long 0x00 "RX_PHYERRIE,Receive Data PHY Level Error Interrupt Enable"
bitfld.long 0x00 19. "ERCTRLIE3,Control Command Error on Lane 3 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 18. "ERSYESIE3,Synchronization Error in Escape Mode on Lane 3 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 17. "ERRESCIE3,Escape Mode Entry Error on Lane 3 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 16. "NOSYNIE3,Multi-Bit Error in Synchronization Pattern on Lane 3 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 15. "ERRSYIE3,Error in Synchronization Pattern on Lane 3 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 14. "ERCTRLIE2,Control Command Error on Lane 2 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 13. "ERSYESIE2,Synchronization Error in Escape Mode on Lane 2 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 12. "ERRESCIE2,Escape Mode Entry Error on Lane 2 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 11. "NOSYNIE2,Multi-Bit Error in Synchronization Pattern on Lane 2 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 10. "ERRSYIE2,Error in Synchronization Pattern on Lane 2 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 9. "ERCTRLIE1,Control Command Error on Lane 1 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 8. "ERSYESIE1,Synchronization Error in Escape Mode on Lane 1 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 7. "ERRESCIE1,Escape Mode Entry Error on Lane 1 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 6. "NOSYNIE1,Multi-Bit Error in Synchronization Pattern on Lane 1 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 5. "ERRSYIE1,Error in Synchronization Pattern on Lane 1 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 4. "ERCTRLIE0,Control Command Error on Lane 0 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 3. "ERSYESIE0,Synchronization Error in Escape Mode on Lane 0 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 2. "ERRESCIE0,Escape Mode Entry Error on Lane 0 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 1. "NOSYNIE0,Multi-Bit Error in Synchronization Pattern on Lane 0 Interrupt Enabled" "0,1"
newline
bitfld.long 0x00 0. "ERRSYIE0,Error in Synchronization Pattern on Lane 0 Interrupt Enabled" "0,1"
group.long 0xF0++0x03
line.long 0x00 "RX_VC_CBUF_DIS_IE,Receive Virtual channel and Circular Buffer Disabled interrupt Enable"
bitfld.long 0x00 19. "CBUF11_DIS_IE,Circular Buffer 11 Disabled Interrupt Enable" "0: Circular Buffer 11 Disabled Interrupt Disable,1: Circular Buffer 11 Disabled Interrupt Enable"
newline
bitfld.long 0x00 18. "CBUF10_DIS_IE,Circular Buffer 10 Disabled Interrupt Enable" "0: Circular Buffer 10 Disabled Interrupt Disable,1: Circular Buffer 10 Disabled Interrupt Enable"
newline
bitfld.long 0x00 17. "CBUF9_DIS_IE,Circular Buffer 9 Disabled Interrupt Enable" "0: Circular Buffer 9 Disabled Interrupt Disable,1: Circular Buffer 9 Disabled Interrupt Enable"
newline
bitfld.long 0x00 16. "CBUF8_DIS_IE,Circular Buffer 8 Disabled Interrupt Enable" "0: Circular Buffer 8 Disabled Interrupt Disable,1: Circular Buffer 8 Disabled Interrupt Enable"
newline
bitfld.long 0x00 15. "CBUF7_DIS_IE,Circular Buffer 7 Disabled Interrupt Enable" "0: Circular Buffer 7 Disabled Interrupt Disable,1: Circular Buffer 7 Disabled Interrupt Enable"
newline
bitfld.long 0x00 14. "CBUF6_DIS_IE,Circular Buffer 6 Disabled Interrupt Enable" "0: Circular Buffer 6 Disabled Interrupt Disable,1: Circular Buffer 6 Disabled Interrupt Enable"
newline
bitfld.long 0x00 13. "CBUF5_DIS_IE,Circular Buffer 5 Disabled Interrupt Enable" "0: Circular Buffer 5 Disabled Interrupt Disable,1: Circular Buffer 5 Disabled Interrupt Enable"
newline
bitfld.long 0x00 12. "CBUF4_DIS_IE,Circular Buffer 4 Disabled Interrupt Enable" "0: Circular Buffer 4 Disabled Interrupt Disable,1: Circular Buffer 4 Disabled Interrupt Enable"
newline
bitfld.long 0x00 11. "CBUF3_DIS_IE,Circular Buffer 3 Disabled Interrupt Enable" "0: Circular Buffer 3 Disabled Interrupt Disable,1: Circular Buffer 3 Disabled Interrupt Enable"
newline
bitfld.long 0x00 10. "CBUF2_DIS_IE,Circular Buffer 2 Disabled Interrupt Enable" "0: Circular Buffer 2 Disabled Interrupt Disable,1: Circular Buffer 2 Disabled Interrupt Enable"
newline
bitfld.long 0x00 9. "CBUF1_DIS_IE,Circular Buffer 1 Disabled Interrupt Enable" "0: Circular Buffer 1 Disabled Interrupt Disable,1: Circular Buffer 1 Disabled Interrupt Enable"
newline
bitfld.long 0x00 8. "CBUF0_DIS_IE,Circular Buffer 0 Disabled Interrupt Enable" "0: Circular Buffer 0 Disabled Interrupt Disable,1: Circular Buffer 0 Disabled Interrupt Enable"
newline
bitfld.long 0x00 3. "VC3_DIS_IE,Virtual Channel 3 Disabled Interrupt Enable" "0: Virtual Channel 3 Disabled Interrupt Disable,1: Virtual Channel 3 Disabled Interrupt Enable"
newline
bitfld.long 0x00 2. "VC2_DIS_IE,Virtual Channel 2 Disabled Interrupt Enable" "0: Virtual Channel 2 Disabled Interrupt Disable,1: Virtual Channel 2 Disabled Interrupt Enable"
newline
bitfld.long 0x00 1. "VC1_DIS_IE,Virtual Channel 1 Disabled Interrupt Enable" "0: Virtual Channel 1 Disabled Interrupt Disable,1: Virtual Channel 1 Disabled Interrupt Enable"
newline
bitfld.long 0x00 0. "VC0_DIS_IE,Virtual Channel 0 Disabled Interrupt Enable" "0: Virtual Channel 0 Disabled Interrupt Disable,1: Virtual Channel 0 Disabled Interrupt Enable"
group.long 0xF4++0x03
line.long 0x00 "RX_VC_CBUF_DIS_STAT,Receive Virtual Channel and Circular Buffer Disabled Status"
eventfld.long 0x00 19. "CBUF11_DIS,Buffer Disabled Status for Circular Buffer 11" "0,1"
newline
eventfld.long 0x00 18. "CBUF10_DIS,Buffer Disabled Status for Circular Buffer 10" "0,1"
newline
eventfld.long 0x00 17. "CBUF9_DIS,Buffer Disabled Status for Circular Buffer 9" "0,1"
newline
eventfld.long 0x00 16. "CBUF8_DIS,Buffer Disabled Status for Circular Buffer 8" "0,1"
newline
eventfld.long 0x00 15. "CBUF7_DIS,Buffer Disabled Status for Circular Buffer 7" "0,1"
newline
eventfld.long 0x00 14. "CBUF6_DIS,Buffer Disabled Status for Circular Buffer 6" "0,1"
newline
eventfld.long 0x00 13. "CBUF5_DIS,Buffer Disabled Status for Circular Buffer 5" "0,1"
newline
eventfld.long 0x00 12. "CBUF4_DIS,Buffer Disabled Status for Circular Buffer 4" "0,1"
newline
eventfld.long 0x00 11. "CBUF3_DIS,Buffer Disabled Status for Circular Buffer 3" "0,1"
newline
eventfld.long 0x00 10. "CBUF2_DIS,Buffer Disabled Status for Circular Buffer 2" "0,1"
newline
eventfld.long 0x00 9. "CBUF1_DIS,Buffer Disabled Status for Circular Buffer 1" "0,1"
newline
eventfld.long 0x00 8. "CBUF0_DIS,Buffer Disabled Status for Circular Buffer 0" "0,1"
newline
eventfld.long 0x00 3. "VC3_DIS,Channel Disabled Status for Virtual Channel 3" "0,1"
newline
eventfld.long 0x00 2. "VC2_DIS,Channel Disabled Status for Virtual Channel 2" "0,1"
newline
eventfld.long 0x00 1. "VC1_DIS,Channel Disabled Status for Virtual Channel 1" "0,1"
newline
eventfld.long 0x00 0. "VC0_DIS,Channel Disabled Status for Virtual Channel 0" "0,1"
group.long 0xFC++0x03
line.long 0x00 "RX_STAT_CONFIG,Receive Data Statistical Computation Configuration"
bitfld.long 0x00 0. "STATEN,This field enables statistical computation on incoming raw data" "0: Statistical computation of raw data disabled,1: Statistical computation of raw data enabled"
group.long 0x400++0x03
line.long 0x00 "CBUF_INTRS,Receive Data Circular Buffer Error Interrupt Status"
eventfld.long 0x00 23. "LINCNTERR11,Line Count Error Indication for Circular Buffer 11" "0,1"
newline
eventfld.long 0x00 22. "LINLENERR11,Line Length Error Indication for Circular Buffer 11" "0,1"
newline
eventfld.long 0x00 21. "LINCNTERR10,Line Count Error Indication for Circular Buffer 10" "0,1"
newline
eventfld.long 0x00 20. "LINLENERR10,Line Length Error Indication for Circular Buffer 10" "0,1"
newline
eventfld.long 0x00 19. "LINCNTERR9,Line Count Error Indication for Circular Buffer 9" "0,1"
newline
eventfld.long 0x00 18. "LINLENERR9,Line Length Error Indication for Circular Buffer 9" "0,1"
newline
eventfld.long 0x00 17. "LINCNTERR8,Line Count Error Indication for Circular Buffer 8" "0,1"
newline
eventfld.long 0x00 16. "LINLENERR8,Line Length Error Indication for Circular Buffer 8" "0,1"
newline
eventfld.long 0x00 15. "LINCNTERR7,Line Count Error Indication for Circular Buffer 7" "0,1"
newline
eventfld.long 0x00 14. "LINLENERR7,Line Length Error Indication for Circular Buffer 7" "0,1"
newline
eventfld.long 0x00 13. "LINCNTERR6,Line Count Error Indication for Circular Buffer 6" "0,1"
newline
eventfld.long 0x00 12. "LINLENERR6,Line Length Error Indication for Circular Buffer 6" "0,1"
newline
eventfld.long 0x00 11. "LINCNTERR5,Line Count Error Indication for Circular Buffer 5" "0,1"
newline
eventfld.long 0x00 10. "LINLENERR5,Line Length Error Indication for Circular Buffer 5" "0,1"
newline
eventfld.long 0x00 9. "LINCNTERR4,Line Count Error Indication for Circular Buffer 4" "0,1"
newline
eventfld.long 0x00 8. "LINLENERR4,Line Length Error Indication for Circular Buffer 4" "0,1"
newline
eventfld.long 0x00 7. "LINCNTERR3,Line Count Error Indication for Circular Buffer 3" "0,1"
newline
eventfld.long 0x00 6. "LINLENERR3,Line Length Error Indication for Circular Buffer 3" "0,1"
newline
eventfld.long 0x00 5. "LINCNTERR2,Line Count Error Indication for Circular Buffer 2" "0,1"
newline
eventfld.long 0x00 4. "LINLENERR2,Line Length Error Indication for Circular Buffer 2" "0,1"
newline
eventfld.long 0x00 3. "LINCNTERR1,Line Count Error Indication for Circular Buffer 1" "0,1"
newline
eventfld.long 0x00 2. "LINLENERR1,Line Length Error Indication for Circular Buffer 1" "0,1"
newline
eventfld.long 0x00 1. "LINCNTERR0,Line Count Error Indication for Circular Buffer 0" "0,1"
newline
eventfld.long 0x00 0. "LINLENERR0,Line Length Error Indication for Circular Buffer 0" "0,1"
group.long 0x404++0x03
line.long 0x00 "CBUF_INTRE,Receive Circular Buffer Error Interrupt Enable"
bitfld.long 0x00 23. "LINCNTIE11,Line Count Error on Circular Buffer 11 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 22. "LINLENIE11,Line Length Error on Circular Buffer 11 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 21. "LINCNTIE10,Line Count Error on Circular Buffer 10 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 20. "LINLENIE10,Line Length Error on Circular Buffer 10 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 19. "LINCNTIE9,Line Count Error on Circular Buffer 9 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 18. "LINLENIE9,Line Length Error on Circular Buffer 9 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 17. "LINCNTIE8,Line Count Error on Circular Buffer 8 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 16. "LINLENIE8,Line Length Error on Circular Buffer 8 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 15. "LINCNTIE7,Line Count Error on Circular Buffer 7 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 14. "LINLENIE7,Line Length Error on Circular Buffer 7 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 13. "LINCNTIE6,Line Count Error on Circular Buffer 6 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 12. "LINLENIE6,Line Length Error on Circular Buffer 6 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 11. "LINCNTIE5,Line Count Error on Circular Buffer 5 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 10. "LINLENIE5,Line Length Error on Circular Buffer 5 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 9. "LINCNTIE4,Line Count Error on Circular Buffer 4 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 8. "LINLENIE4,Line Length Error on Circular Buffer 4 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 7. "LINCNTIE3,Line Count Error on Circular Buffer 3 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 6. "LINLENIE3,Line Length Error on Circular Buffer 3 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 5. "LINCNTIE2,Line Count Error on Circular Buffer 2 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 4. "LINLENIE2,Line Length Error on Circular Buffer 2 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 3. "LINCNTIE1,Line Count Error on Circular Buffer 1 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 2. "LINLENIE1,Line Length Error on Circular Buffer 1 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 1. "LINCNTIE0,Line Count Error on Circular Buffer 0 Interrupt Enable" "0,1"
newline
bitfld.long 0x00 0. "LINLENIE0,Line Length Error on Circular Buffer 0 Interrupt Enable" "0,1"
repeat 4. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x410)++0x03
line.long 0x00 "RX_DROPDATAR[$1],Received Drop Data Type and VC Report $1"
bitfld.long 0x00 30.--31. "DROPVCID3,VCID Dropped" "0: VC0 data dropped,1: VC1 data dropped,2: VC2 data dropped,3: VC3 data dropped"
newline
bitfld.long 0x00 24.--29. "DROPDATAID3,Data ID Dropped" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,18: Embedded packet dropped,?,?,?,?,?,?,?,?,?,?,?,30: YUV 422,31: YUV 422,?,?,34: RGB 565 packet dropped,?,36: RGB 888 packet dropped,?,?,?,?,?,42: RAW 8 packet dropped,43: RAW 10 packet dropped,44: RAW 12 packet dropped,45: RAW 14 packet dropped,46: RAW 16 packet dropped,?,48: User-defined packet dropped,49: User-defined packet dropped,50: User-defined packet dropped,51: User-defined packet dropped,52: User-defined packet dropped,53: User-defined packet dropped,54: User-defined packet dropped,55: User-defined packet dropped,?..."
newline
bitfld.long 0x00 22.--23. "DROPVCID2,VCID Dropped" "0: VC0 data dropped,1: VC1 data dropped,2: VC2 data dropped,3: VC3 data dropped"
newline
bitfld.long 0x00 16.--21. "DROPDATAID2,Data ID Dropped" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,18: Embedded packet dropped,?,?,?,?,?,?,?,?,?,?,?,30: YUV 422,31: YUV 422,?,?,34: RGB 565 packet dropped,?,36: RGB 888 packet dropped,?,?,?,?,?,42: RAW 8 packet dropped,43: RAW 10 packet dropped,44: RAW 12 packet dropped,45: RAW 14 packet dropped,46: RAW 16 packet dropped,?,48: User-defined packet dropped,49: User-defined packet dropped,50: User-defined packet dropped,51: User-defined packet dropped,52: User-defined packet dropped,53: User-defined packet dropped,54: User-defined packet dropped,55: User-defined packet dropped,?..."
newline
bitfld.long 0x00 14.--15. "DROPVCID1,VCID Dropped" "0: VC0 data dropped,1: VC1 data dropped,2: VC2 data dropped,3: VC3 data dropped"
newline
bitfld.long 0x00 8.--13. "DROPDATAID1,Data ID Dropped" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,18: Embedded packet dropped,?,?,?,?,?,?,?,?,?,?,?,30: YUV 422,31: YUV 422,?,?,34: RGB 565 packet dropped,?,36: RGB 888 packet dropped,?,?,?,?,?,42: RAW 8 packet dropped,43: RAW 10 packet dropped,44: RAW 12 packet dropped,45: RAW 14 packet dropped,46: RAW 16 packet dropped,?,48: User-defined packet dropped,49: User-defined packet dropped,50: User-defined packet dropped,51: User-defined packet dropped,52: User-defined packet dropped,53: User-defined packet dropped,54: User-defined packet dropped,55: User-defined packet dropped,?..."
newline
bitfld.long 0x00 6.--7. "DROPVCID0,VCID Dropped" "0: VC0 data dropped,1: VC1 data dropped,2: VC2 data dropped,3: VC3 data dropped"
newline
bitfld.long 0x00 0.--5. "DROPDATAID0,Data ID Dropped" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,18: Embedded packet dropped,?,?,?,?,?,?,?,?,?,?,?,30: YUV 422,31: YUV 422,?,?,34: RGB 565 packet dropped,?,36: RGB 888 packet dropped,?,?,?,?,?,42: RAW 8 packet dropped,43: RAW 10 packet dropped,44: RAW 12 packet dropped,45: RAW 14 packet dropped,46: RAW 16 packet dropped,?,48: User-defined packet dropped,49: User-defined packet dropped,50: User-defined packet dropped,51: User-defined packet dropped,52: User-defined packet dropped,53: User-defined packet dropped,54: User-defined packet dropped,55: User-defined packet dropped,?..."
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x420)++0x03
line.long 0x00 "RX_CBUF_OUTCFG[$1],Receive Data Channel Output Configuration $1"
bitfld.long 0x00 9. "FLIP_BIT_AUX,Defines the signed or unsigned nature of auxiliary channel data" "0: Auxiliary channel data should not be flipped,1: Auxiliary channel data is to be flipped while.."
newline
bitfld.long 0x00 8. "BYTE_ORDER_LSB_FIRST,Byte order of incoming RAW16 data" "0: First RAW8 pixel at LSB,1: Second RAW8 pixel at LSB"
newline
bitfld.long 0x00 7. "SWAPRAWDATA,Swap the data for RAW8 incoming data to align as RAW 16 data in memory" "0: Incoming data is RAW 8 data,1: Incoming data is RAW 16"
newline
bitfld.long 0x00 6. "FLIP_BIT,Defines the signed or unsigned nature of data that is received for the ADC channel data" "0: Non-auxiliary raw data should not be flipped,1: Non-auxiliary raw data is to be flipped"
newline
bitfld.long 0x00 4.--5. "OUTPUT_MODE,This field is used to configure the output data format in SRAM for the received channel data" "0: Channel data written in interleaved format in..,1: Channel data written in tile 8 format in the..,2: Channel data written in tile 16 format in the..,?..."
newline
bitfld.long 0x00 2.--3. "DROP_RATE,Configures the number of samples of fifth channel that needs to be dropped" "0: No auxiliary data sample dropped case in..,1: Alternate auxiliary data sample dropped,2: Three samples out of four auxiliary samples..,3: No auxiliary data sample dropped case in.."
newline
bitfld.long 0x00 1. "CALIB_ON,Enables the fifth channel" "0: Auxiliary channel is disabled for current..,1: Auxiliary channel reception is enabled in.."
newline
bitfld.long 0x00 0. "DATA_MODE,Defines the type of data" "0: Real data only mode,1: Complex data mode"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x430)++0x03
line.long 0x00 "RX_CBUF_CHNLENBL[$1],Receive Data Channel Enable/Disable Configuration $1"
bitfld.long 0x00 7. "CHH_ENBL,Enable Reception of Channel H Content" "0,1"
newline
bitfld.long 0x00 6. "CHG_ENBL,Enable Reception of Channel G Content" "0,1"
newline
bitfld.long 0x00 5. "CHF_ENBL,Enable Reception of Channel F Content" "0,1"
newline
bitfld.long 0x00 4. "CHE_ENBL,Enable Reception of Channel E Content" "0,1"
newline
bitfld.long 0x00 3. "CHD_ENBL,Enable Reception of Channel D Content" "0,1"
newline
bitfld.long 0x00 2. "CHC_ENBL,Enable Reception of Channel C Content" "0,1"
newline
bitfld.long 0x00 1. "CHB_ENBL,Enable Reception of Channel B Content" "0,1"
newline
bitfld.long 0x00 0. "CHA_ENBL,Enable Reception of Channel A Content" "0,1"
repeat.end
group.long 0x440++0x03
line.long 0x00 "RX_CBUF0_CHNLOFFSET0_0,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHB_DC,Channel B Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHA_DC,Channel A Offset Compensation Value"
group.long 0x444++0x03
line.long 0x00 "RX_CBUF0_CHNLOFFSET1_0,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHD_DC,Channel D Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHC_DC,Channel C Offset Compensation Value"
group.long 0x448++0x03
line.long 0x00 "RX_CBUF0_CHNLOFFSET2_0,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHF_DC,Channel F Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHE_DC,Channel E Offset Compensation Value"
group.long 0x44C++0x03
line.long 0x00 "RX_CBUF0_CHNLOFFSET3_0,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHH_DC,Channel H Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHG_DC,Channel G Offset Compensation Value"
group.long 0x450++0x03
line.long 0x00 "RX_CBUF1_CHNLOFFSET0_1,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHB_DC,Channel B Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHA_DC,Channel A Offset Compensation Value"
group.long 0x454++0x03
line.long 0x00 "RX_CBUF1_CHNLOFFSET1_1,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHD_DC,Channel D Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHC_DC,Channel C Offset Compensation Value"
group.long 0x458++0x03
line.long 0x00 "RX_CBUF1_CHNLOFFSET2_1,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHF_DC,Channel F Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHE_DC,Channel E Offset Compensation Value"
group.long 0x45C++0x03
line.long 0x00 "RX_CBUF1_CHNLOFFSET3_1,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHH_DC,Channel H Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHG_DC,Channel G Offset Compensation Value"
group.long 0x460++0x03
line.long 0x00 "RX_CBUF2_CHNLOFFSET0_2,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHB_DC,Channel B Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHA_DC,Channel A Offset Compensation Value"
group.long 0x464++0x03
line.long 0x00 "RX_CBUF2_CHNLOFFSET1_2,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHD_DC,Channel D Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHC_DC,Channel C Offset Compensation Value"
group.long 0x468++0x03
line.long 0x00 "RX_CBUF2_CHNLOFFSET2_2,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHF_DC,Channel F Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHE_DC,Channel E Offset Compensation Value"
group.long 0x46C++0x03
line.long 0x00 "RX_CBUF2_CHNLOFFSET3_2,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHH_DC,Channel H Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHG_DC,Channel G Offset Compensation Value"
group.long 0x470++0x03
line.long 0x00 "RX_CBUF3_CHNLOFFSET0_3,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHB_DC,Channel B Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHA_DC,Channel A Offset Compensation Value"
group.long 0x474++0x03
line.long 0x00 "RX_CBUF3_CHNLOFFSET1_3,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHD_DC,Channel D Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHC_DC,Channel C Offset Compensation Value"
group.long 0x478++0x03
line.long 0x00 "RX_CBUF3_CHNLOFFSET2_3,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHF_DC,Channel F Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHE_DC,Channel E Offset Compensation Value"
group.long 0x47C++0x03
line.long 0x00 "RX_CBUF3_CHNLOFFSET3_3,Receive Data Channel Offset Compensation Configuration"
hexmask.long.word 0x00 17.--31. 1. "CHH_DC,Channel H Offset Compensation Value"
newline
hexmask.long.word 0x00 1.--15. 1. "CHG_DC,Channel G Offset Compensation Value"
group.long 0x490++0x03
line.long 0x00 "RX_CHNL_INTRS,Receive Data Channel Status"
eventfld.long 0x00 1. "BUFFOVF,Internal Buffer Overflow Indication" "0,1"
newline
eventfld.long 0x00 0. "LINEDONE,Long Packet Complete Indication" "0,1"
group.long 0x494++0x03
line.long 0x00 "RX_CHNL_INTRE,Receive Channel Interrupt Enable"
bitfld.long 0x00 1. "BUFFOVFIE,Internal Buffer Overflow Indication Interrupt Enable" "0,1"
newline
bitfld.long 0x00 0. "LINEDONEIE,Long Packet Complete Indication Interrupt Enable" "0,1"
group.long 0x498++0x03
line.long 0x00 "WR_CHNL_INTRS,AXI Write Channel Interrupt Status"
eventfld.long 0x00 1. "BUFFOVFAXI,When the number of outstanding transactions has reached eight for AXI master write side and a new burst request is needed then this is set" "0,1"
newline
eventfld.long 0x00 0. "ERRRESP,Error Response on the AXI Write Channel" "0,1"
group.long 0x49C++0x03
line.long 0x00 "WR_CHNL_INTRE,AXI Write Channel Interrupt Enable"
bitfld.long 0x00 1. "BUFFOVFAXIIE,Internal Buffer Overflow Indication Interrupt Enable" "0,1"
newline
bitfld.long 0x00 0. "ERRRESPIE,Error Response on the AXI Write Response Channel Interrupt Enable" "0,1"
group.long 0x584++0x03
line.long 0x00 "TURNCFG,Turnaround Request Configuration"
bitfld.long 0x00 4. "FORCERXMODE4,Force Receive Mode on Data Lane" "0: Receive mode is not forced on lane 4,1: Lane module 4 is forced to transition into.."
newline
bitfld.long 0x00 3. "FORCERXMODE3,Force Receive Mode on Data Lane" "0: Receive mode is not forced on lane 3,1: Lane module 3 is forced to transition into.."
newline
bitfld.long 0x00 2. "FORCERXMODE2,Force Receive Mode on Data Lane" "0: Receive mode is not forced on lane 2,1: Lane module 2 is forced to transition into.."
newline
bitfld.long 0x00 1. "FORCERXMODE1,Force Receive Mode on Data Lane" "0: Receive mode is not forced on lane 1,1: Lane module 1 is forced to transition into.."
group.long 0x598++0x03
line.long 0x00 "TRIGGER_GPIO1,GPIO1 Pad Event Trigger Control"
bitfld.long 0x00 30.--31. "RSVD_3,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "TRIGGERONPKTID_VC3,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 26.--27. "TRIGGERONPKT_VC3,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 24.--25. "TRIGGERONERR_VC3,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC or ECC 2-bit error trigger enable,3: No synchronization on DPHY data lane trigger.."
newline
bitfld.long 0x00 22.--23. "RSVD_2,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 20.--21. "TRIGGERONPKTID_VC2,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 18.--19. "TRIGGERONPKT_VC2,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 16.--17. "TRIGGERONERR_VC2,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC or ECC 2-bit error trigger enable,3: No synchronization on DPHY data lane trigger.."
newline
bitfld.long 0x00 14.--15. "RSVD_1,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "TRIGGERONPKTID_VC1,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 10.--11. "TRIGGERONPKT_VC1,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 8.--9. "TRIGGERONERR_VC1,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC or ECC 2-bit error trigger enable,3: No synchronization on DPHY data lane trigger.."
newline
bitfld.long 0x00 6.--7. "RSVD_0,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "TRIGGERONPKTID_VC0,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 2.--3. "TRIGGERONPKT_VC0,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 0.--1. "TRIGGERONERR_VC0,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC or ECC 2-bit error trigger enable,3: No synchronization on DPHY data lane trigger.."
group.long 0x5A0++0x03
line.long 0x00 "TRIGGER_SDMA1,SDMA1 Pad Event Trigger Control"
bitfld.long 0x00 30.--31. "RSVD_3,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "TRIGGERONPKTID_VC3,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 26.--27. "TRIGGERONPKT_VC3,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 24.--25. "TRIGGERONERR_VC3,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC error or ECC 2-bit trigger enable,3: No synchronization on DPHY data lane trigger.."
newline
bitfld.long 0x00 22.--23. "RSVD_2,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 20.--21. "TRIGGERONPKTID_VC2,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 18.--19. "TRIGGERONPKT_VC2,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 16.--17. "TRIGGERONERR_VC2,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC error or ECC 2-bit trigger enable,3: No synchronization on DPHY data lane trigger.."
newline
bitfld.long 0x00 14.--15. "RSVD_1,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "TRIGGERONPKTID_VC1,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 10.--11. "TRIGGERONPKT_VC1,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 8.--9. "TRIGGERONERR_VC1,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC error or ECC 2-bit trigger enable,3: No synchronization on DPHY data lane trigger.."
newline
bitfld.long 0x00 6.--7. "RSVD_0,Reserved" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "TRIGGERONPKTID_VC0,Trigger to be generated on specific packet and frame identifiers" "0: Frame start reception trigger enable,1: Frame end reception trigger enable,2: Packet start reception trigger enable,3: Packet complete reception trigger enable"
newline
bitfld.long 0x00 2.--3. "TRIGGERONPKT_VC0,Trigger to be generated on which packet type for each VC" "0: Embedded data reception trigger enable,1: User-defined data reception trigger enable,2: RAW data reception trigger enable,3: RGB data type trigger enable"
newline
bitfld.long 0x00 0.--1. "TRIGGERONERR_VC0,Trigger to be generated on which error for each VC" "0: Line count error trigger enable,1: Line length error trigger enable,2: CRC error or ECC 2-bit trigger enable,3: No synchronization on DPHY data lane trigger.."
group.long 0x5A8++0x03
line.long 0x00 "TRIGGEREN_GPIO,GPIO Pad Event Trigger Enable Control"
bitfld.long 0x00 23. "GPIO2_TRIGGERONPKTIDEN_VC3,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 22. "GPIO2_TRIGGERONPKTEN_VC3,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 21. "GPIO2_TRIGGERONERR_VC3,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 20. "GPIO2_TRIGGERONPKTIDEN_VC2,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 19. "GPIO2_TRIGGERONPKTEN_VC2,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 18. "GPIO2_TRIGGERONERR_VC2,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 17. "GPIO2_TRIGGERONPKTIDEN_VC1,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 16. "GPIO2_TRIGGERONPKTEN_VC1,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 15. "GPIO2_TRIGGERONERR_VC1,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 14. "GPIO2_TRIGGERONPKTIDEN_VC0,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 13. "GPIO2_TRIGGERONPKTEN_VC0,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 12. "GPIO2_TRIGGERONERR_VC0,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 11. "GPIO1_TRIGGERONPKTIDEN_VC3,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 10. "GPIO1_TRIGGERONPKTEN_VC3,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 9. "GPIO1_TRIGGERONERR_VC3,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 8. "GPIO1_TRIGGERONPKTIDEN_VC2,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 7. "GPIO1_TRIGGERONPKTEN_VC2,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 6. "GPIO1_TRIGGERONERR_VC2,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 5. "GPIO1_TRIGGERONPKTIDEN_VC1,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 4. "GPIO1_TRIGGERONPKTEN_VC1,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 3. "GPIO1_TRIGGERONERR_VC1,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 2. "GPIO1_TRIGGERONPKTIDEN_VC0,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 1. "GPIO1_TRIGGERONPKTEN_VC0,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 0. "GPIO1_TRIGGERONERR_VC0,Enable Trigger Generation on Errors for each VC" "0,1"
group.long 0x5AC++0x03
line.long 0x00 "TRIGGEREN_SDMA,SDMA Pad Event Trigger Enable Control"
bitfld.long 0x00 23. "SDMA2_TRIGGERONPKTIDEN_VC3,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 22. "SDMA2_TRIGGERONPKTEN_VC3,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 21. "SDMA2_TRIGGERONERR_VC3,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 20. "SDMA2_TRIGGERONPKTIDEN_VC2,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 19. "SDMA2_TRIGGERONPKTEN_VC2,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 18. "SDMA2_TRIGGERONERR_VC2,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 17. "SDMA2_TRIGGERONPKTIDEN_VC1,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 16. "SDMA2_TRIGGERONPKTEN_VC1,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 15. "SDMA2_TRIGGERONERR_VC1,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 14. "SDMA2_TRIGGERONPKTIDEN_VC0,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 13. "SDMA2_TRIGGERONPKTEN_VC0,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 12. "SDMA2_TRIGGERONERR_VC0,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 11. "SDMA1_TRIGGERONPKTIDEN_VC3,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 10. "SDMA1_TRIGGERONPKTEN_VC3,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 9. "SDMA1_TRIGGERONERR_VC3,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 8. "SDMA1_TRIGGERONPKTIDEN_VC2,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 7. "SDMA1_TRIGGERONPKTEN_VC2,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 6. "SDMA1_TRIGGERONERR_VC2,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 5. "SDMA1_TRIGGERONPKTIDEN_VC1,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 4. "SDMA1_TRIGGERONPKTEN_VC1,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 3. "SDMA1_TRIGGERONERR_VC1,Enable Trigger Generation on Errors for each VC" "0,1"
newline
bitfld.long 0x00 2. "SDMA1_TRIGGERONPKTIDEN_VC0,Enable Trigger Generation on Specific Packet and Frame Identifiers" "0,1"
newline
bitfld.long 0x00 1. "SDMA1_TRIGGERONPKTEN_VC0,Enable Trigger Generation on Specific Packet Type for each VC" "0,1"
newline
bitfld.long 0x00 0. "SDMA1_TRIGGERONERR_VC0,Enable Trigger Generation on Errors for each VC" "0,1"
group.byte 0x608++0x00
line.byte 0x00 "DPHY_CALTYPE_CNTRL,System Configuration"
bitfld.byte 0x00 5. "CMP_POLARITY_RW,Comparator polarity" "0,1"
newline
bitfld.byte 0x00 4. "NOEXT_BURNIN_RES_CAL_RW,Selection between type of calibration (if 1 no REXT will be done)" "0,1"
group.byte 0x60C++0x00
line.byte 0x00 "DPHY_SKEWCAL_CNTRL,System Configuration"
bitfld.byte 0x00 7. "TCLK_MISS_DIV2_OVR_EN_RW,Use divider by 2 on Tclk-miss detection circuit override" "0,1"
newline
bitfld.byte 0x00 6. "TCLK_MISS_DIV2_OVR_RW,Use divider by 2 on Tclk-miss detection circuit override" "0,1"
newline
bitfld.byte 0x00 5. "DESKEW_POLARITY_RW,De-skew Calibration pattern control (only used in backwards compatibility)" "0: datain = datain_afe,1: datain = ~datain_afe"
newline
bitfld.byte 0x00 3.--4. "DESKEW_LATENCY_RW__1__0__,Controls the latency between applying one setting and starting the integration" "0: DESKEW_LATENCY_RW__1__0___0,1: DESKEW_LATENCY_RW__1__0___1,2: DESKEW_LATENCY_RW__1__0___2,3: DESKEW_LATENCY_RW__1__0___3"
newline
bitfld.byte 0x00 1. "SKEW_MUX_SEL_RW,Selects between auto mode and manual selection of de-skew calibration mechanism" "0,1"
newline
bitfld.byte 0x00 0. "SKEW_MUX_RUN_RW,Selects the type of deskew calibration mode to run (internal or burst based)" "0,1"
group.byte 0x60D++0x00
line.byte 0x00 "DPHY_RX_SYNALIGN_CFG,System Configuration"
bitfld.byte 0x00 5.--6. "ALIGNER_DK_CNF_RW__1__0__,Used in the lane aligner to set the number of ones to identify in the deskew sync pattern" "0: ALIGNER_DK_CNF_RW__1__0___0,1: ALIGNER_DK_CNF_RW__1__0___1,2: ALIGNER_DK_CNF_RW__1__0___2,3: ALIGNER_DK_CNF_RW__1__0___3"
newline
bitfld.byte 0x00 4. "NOALIGN_ERROR_RW,No alignment error bit" "0,1"
newline
bitfld.byte 0x00 2.--3. "DESKEW_JUMP2STEPS_RW__1__0__,De-skew Calibration steps control" "0: DESKEW_JUMP2STEPS_RW__1__0___0,1: DESKEW_JUMP2STEPS_RW__1__0___1,2: DESKEW_JUMP2STEPS_RW__1__0___2,3: DESKEW_JUMP2STEPS_RW__1__0___3"
newline
bitfld.byte 0x00 1. "DESKEW_OVERFLOW_RW,Feature that forces de-skew algorithm convergence by setting 2nd edge pointer to step 31 (for situations where eventual DDL variation over PVT could cause potential failures)" "0,1"
newline
bitfld.byte 0x00 0. "DESKEW_NUMEDGES_UPDATE_RW,Procedure Set deskew_nemedge_update to 1'b0 Change deskew_numedges to desired value Set deskew_nemedge_update to 1'b1 Circuitry ensures synchronous update of internal counters" "0,1"
group.byte 0x60E++0x00
line.byte 0x00 "DPHY_DESKEW_CFG,This register is used to program the Deskew accumulator size(FJUMP)"
hexmask.byte 0x00 0.--7. 1. "DESKEW_NUMEDGES_RW,De-skew accumulator size (sinusoidal jitter tolerance)"
group.byte 0x6E4++0x00
line.byte 0x00 "DPHY_RX_STARTUP_OVERRIDE,System Startup Observability"
bitfld.byte 0x00 7. "RX_RXHS_COMPATIBILITY_MODE_OVR_EN_RW,When set to 1'b1 the value of rx_rxhs_compatibility_mode will be the same as rx_rxhs_compatibility_mode_ovr" "0,1"
newline
bitfld.byte 0x00 6. "BYPASS_SKEW_MACHINE_RW,Bypass of de-skew machine" "0,1"
newline
bitfld.byte 0x00 5. "SKEW_BACK_COMP_EN_OVR_RW,Deskew Backwards Compatibility Override Enable Value" "0,1"
newline
bitfld.byte 0x00 4. "SKEW_BACK_COMP_EN_OVR_EN_RW,Deskew Back Comparator Override Enable Control" "0,1"
newline
bitfld.byte 0x00 3. "BYPASS_DDLTUNNING_MACHINE_RW,Bypass DDL Tunning Machine" "0,1"
newline
bitfld.byte 0x00 2. "BYPASS_OFFSET_MACHINE_RW,Bypass Offset Machine Bit" "0,1"
newline
bitfld.byte 0x00 0. "CLK_EN_LANES_BYPASS_RW,Clock Enable Lanes Bypass" "0,1"
group.byte 0x6E6++0x00
line.byte 0x00 "DPHY_DDLOSCFREQ_CFG1,System Startup Override"
hexmask.byte 0x00 0.--7. 1. "DDL_OSC_FREQ_TARGET_OVR_RW__7__0__,DDL oscillation frequency override value (main)"
group.byte 0x6E7++0x00
line.byte 0x00 "DPHY_DDLOSCFREQ_CFG2,System Startup Override"
bitfld.byte 0x00 0.--3. "DDL_OSC_FREQ_TARGET_OVR_RW__11__8__,DDL oscillation frequency override value (main)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x6E8++0x00
line.byte 0x00 "DPHY_DDLOSCFREQ_OVREN,System Startup Override"
bitfld.byte 0x00 4.--7. "COUNTER_FOR_DES_EN_CONFIG_IF_RW__3__0__,Override the counter_for_des_en_if in the hardmacro when counter_for_des_en_bypass_rw is set to 1'b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 2.--3. "RX_RXHS_GMODE_IF_OVR_RW__1__0__,Overrides the rx_rxhs_gmode_int which is set according to hsfreqrange from the softmacro to the hardmacro when RX_RXHS_GMODE_IF_OVR_EN_RW is set to 1'b1" "0,1,2,3"
newline
bitfld.byte 0x00 1. "RX_RXHS_GMODE_IF_OVR_EN_RW,overrides the rx_rxhs_gmode_int which is set according to hsfreqrange from the softmacro to the hardmacro when RX_RXHS_GMODE_IF_OVR_EN_RW is set to 1'b1" "0,1"
newline
bitfld.byte 0x00 0. "DDL_OSC_FREQ_TARGET_OVR_EN_RW,Overrides the ddl_osc_freq_target which is set according to hsfreqrange from the softmacro to the hardmacro when DDL_OSC_FREQ_TARGET_OVR_EN_RW is set to 1'b1" "0,1"
rgroup.byte 0x824++0x00
line.byte 0x00 "DPHY_RX_TERM_CAL_0,Termination Calibration Observability"
bitfld.byte 0x00 2.--5. "CB_CAL_REPL__3__0__,register is used to observe (read_only) the value of rx_cb_cal_repl_if signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x825++0x00
line.byte 0x00 "DPHY_RX_TERM_CAL_1,Termination Calibration Observability"
bitfld.byte 0x00 7. "RESCAL_DONE,Lower section termination calibration algorithm done (volatile)" "0,1"
newline
bitfld.byte 0x00 5. "RESCAL_EN,Lower section termination calibration algorithm enable (volatile)" "0,1"
group.byte 0x90B++0x00
line.byte 0x00 "DPHY_CLOCK_LANE_CNTRL,Clock Lane Control"
bitfld.byte 0x00 7. "RXCLK_RXHS_PULL_LONG_CHANNEL_IF_RW,RX high-speed pull long channel" "0,1"
newline
bitfld.byte 0x00 6. "RXCLK_RXHS_INT_CLK_SEL_RW,RX high-speed internal clock selection" "0,1"
newline
bitfld.byte 0x00 5. "RXCLK_RXHS_FEED_INT_CLK_OVR_EN_RW,RX high-speed source data override enable control" "0,1"
newline
bitfld.byte 0x00 4. "RXCLK_RXHS_FEED_INT_CLK_OVR_RW,Overrides rxclk_rxhs_feed_int_clk_if signal when RXCLK_RXHS_FEED_INT_CLK_OVR_EN_RW is set to 1'b1" "0: RXCLK_RXHS_FEED_INT_CLK_OVR_RW_0,1: RXCLK_RXHS_FEED_INT_CLK_OVR_RW_1"
newline
bitfld.byte 0x00 3. "RXCLK_RXHS_DDR_CLK_EN_IF_RW,Enable DDR clock divider" "0,1"
newline
bitfld.byte 0x00 2. "RXCLK_RXHS_CLK_TO_LONG_CHANNEL_IF_RW,RX HS clock to long channel bits" "0: use single macro (short),1: use double macro (long)"
group.byte 0x97F++0x00
line.byte 0x00 "DPHY_CLKOFFSETCAL_OVRRIDE,Clock Lane Offset Cancellation Control"
bitfld.byte 0x00 4. "RXCLK_START_CALIBRATION_OVR_RW,Clock lane digital offset start calibration override enable control" "0,1"
newline
bitfld.byte 0x00 3. "RXCLK_START_CALIBRATION_OVR_EN_RW,Clock lane digital offset start calibration override enable control" "0,1"
newline
bitfld.byte 0x00 2. "RXCLK_RXHS_START_CALIBRATION_OVR_RW,Enables override of clock lane analog offset start calibration" "0,1"
newline
bitfld.byte 0x00 1. "RXCLK_RXHS_START_CALIBRATION_OVR_EN_RW,Controls override of clock lane analog offset start calibration" "0,1"
newline
bitfld.byte 0x00 0. "RXCLK_RXHS_CLK_OFFSET_CAL_OVR_EN_RW,RX HS clock offset calibration override enable control" "0,1"
group.byte 0x980++0x00
line.byte 0x00 "DPHY_CLKOFFSETCAL_OVRRIDEVAL,Clock Lane Offset Cancellation Control 2"
hexmask.byte 0x00 0.--6. 1. "RXCLK_RXHS_CLK_OFFSET_CAL_OVR_RW__6__0__,RX HS clock offset calibration override control"
rgroup.byte 0x9A0++0x00
line.byte 0x00 "DPHY_CLKCALVAL_COMPS,Clock Lane Offset Cancellation Observability 3"
hexmask.byte 0x00 0.--6. 1. "RXCLK_RXHS_CLK_OFFSET_CAL__6__0__,Register is used to observe (read_only) the value of rxclk_rxhs_clk_offset_cal_if"
rgroup.byte 0x9A1++0x00
line.byte 0x00 "DPHY_CLKOFFSETCAL_COMPS,Clock Lane Offset Cancellation Observability"
bitfld.byte 0x00 5. "RXCLK_RXHS_CLK_M_CAL,Register is used to observe (read_only) the value of rxclk_rxhs_clk_m_cal_if" "0,1"
newline
bitfld.byte 0x00 1.--4. "RXCLK_ERRCAL__3__0__,Clock lane offset calibration error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0. "RXCLK_CALDONE,register is used to observe (read_only) the value of rxclk_caldone which is a flag to indicate when calibration ends in the clock lane offset calibration machine" "0,1"
group.byte 0xB09++0x00
line.byte 0x00 "DPHY_RX_LPRXPON_LANE0,Lane 0 Low Power Receive Control"
bitfld.byte 0x00 4. "LPRXPONULP_LANE0_RW,LP RX ULP power-on" "0,1"
newline
bitfld.byte 0x00 3. "LPRXPONULP_BYPASS_LANE0_RW,LP RX ULP power-on bypass override" "0,1"
newline
bitfld.byte 0x00 2. "LPRXPONLP_LANE0_RW,LP RX LP power-on" "0,1"
newline
bitfld.byte 0x00 1. "LPRXPONLP_BYPASS_LANE0_RW,LP RX LP power-on bypass override" "0,1"
newline
bitfld.byte 0x00 0. "LPRXPONCD_LANE0_RW,LP RX contention detector power-on" "0,1"
rgroup.byte 0xB33++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_COMPS0,Lane 0 Observability"
bitfld.byte 0x00 4. "RX0_DESKEWCALFAILED_IF,Register is used to observe (read_only) the value of rx0_deskewcalfailed_if which is the deskew calibration error flag" "0,1"
newline
bitfld.byte 0x00 3. "RX0_DESKEWCALDONE_IF,Register is used to observe (read_only) the value of rx0_deskewcaldone_if which is the deskew calibration process completion flag" "0,1"
newline
bitfld.byte 0x00 2. "LSRXCLK_LANE0,Low-Speed Clock(Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--1. "LPRXDOUTULP_LANE0__1__0__,Register is used to observe (read_only) the value of lprxdoutulp_lane0_if which is the output of the ulp comparator" "0,1,2,3"
group.byte 0xB7F++0x00
line.byte 0x00 "DPHY_DATAL0OFFSETCAL_OVRCNTRL,Lane 0 Offset Compensation Control"
bitfld.byte 0x00 7. "RX0_RXHS_DATA_OFFSET_CAL_EN_OVR_EN_RW,Data Offset Calibration Override Enable Control" "0,1"
newline
bitfld.byte 0x00 6. "RX0_CAL_DONE_OVR_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 5. "RX0_CAL_DONE_OVR_EN_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 4. "RX0_START_CALIBRATION_OVR_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 3. "RX0_START_CALIBRATION_OVR_EN_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 2. "RX0_RXHS_DATA_OFFSET_CAL_OVR_EN_RW,Offset Calibration Setting Override" "0,1"
group.byte 0xB80++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_OVRVALUE0,Lane 0 Offset Compensation Control"
hexmask.byte 0x00 1.--7. 1. "RX0_RXHS_DATA_OFFSET_CAL_OVR_RW__6__0__,Offset Calibration Setting Override Enable"
newline
bitfld.byte 0x00 0. "RX0_RXHS_DATA_OFFSET_CAL_EN_OVR_RW,Data Offset Calibration Override Enable Control" "0,1"
rgroup.byte 0xBA3++0x00
line.byte 0x00 "DPHY_DATALANE_OFFSETCAL_COMPS0,Lane Offset Compensation Observability"
bitfld.byte 0x00 2. "RX0_CAL_ERROR,Offset Calibration Algorithm Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_CAL_DONE,Offset Calibration Algorithm Done (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX0_START_CALIBRATION,Offset Calibration Algorithm Start (Volatile)" "0,1"
rgroup.byte 0xBA5++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_VALUE0,Lane Offset Compensation Observability"
bitfld.byte 0x00 7. "RX0_RXHS_DATA_OFFSET_CAL_EN,Offset calibration algorithm enable (volatile)" "0,1"
newline
hexmask.byte 0x00 0.--6. 1. "RX0_RXHS_DATA_OFFSET_CAL__6__0__,Offset calibration algorithm setting chosen (volatile)"
rgroup.byte 0xBE4++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_COMP0,Lane DDL Tune Observability"
bitfld.byte 0x00 3. "RX0_DDL_START_CALIBRATION_IF,DDL Tune Digital Algorithm Start (Volatile)" "0,1"
newline
bitfld.byte 0x00 2. "RX0_DDL_FINISHED_IF,DDL Tune Done Indication (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_DDL_ERROR_FLAG_IF,DDL Tune Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "DDL_TUNE_EN_LANE0_IF,DDL Tune Analog Circuitry Enable Indication (Volatile)" "0,1"
rgroup.byte 0xBE9++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_VALUE0,Lane 0 DDL Tune Observability"
bitfld.byte 0x00 5. "RX0_RXHS_DDL_PHASE_CHANGE_P_IF,RX HS DDL Phase Change (Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_IF__4__0__,RX HS DDL Tunning Setting (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.byte 0xBEA++0x00
line.byte 0x00 "DPHY_DATALANE0_DESKEW_VALUE1,Lane 0 DDL Tune Observability"
bitfld.byte 0x00 5.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_PHASE_CLK_IF__4__0__,Clock DDL Setting Chosen (volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.byte 0xBEB++0x00
line.byte 0x00 "DPHY_DATALANE0_DESKEW_VALUE2,Lane 0 DDL Tune Observability"
bitfld.byte 0x00 4.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0.--3. "RX0_RXHS_DDL_PHASE_DATA_IF__3__0__,Data DDL Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xC0B++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_OVRVALUE0,Lane 0 DDL Tune Control"
bitfld.byte 0x00 7. "RX0_RXHS_DDL_PHASE_CHANGE_P_OVR_RW,RX HS DDL Phase Changed Override Control" "0,1"
newline
bitfld.byte 0x00 6. "RX0_RXHS_DDL_PHASE_CHANGE_P_OVR_EN_RW,RX HS DDL Phase Changed Override Control" "0,1"
newline
bitfld.byte 0x00 5. "RX0_RXHS_DDL_TUNE_OVR_EN_RW,RX HS DDL Tune Override Enable Control" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_OVR_RW__4__0__,RX HS DDL Tune Override for Lane 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0xC0C++0x00
line.byte 0x00 "DPHY_DATALANE0_DESKEW_OVRVALUE1,Lane 0 DDL Tune Control"
rbitfld.byte 0x00 6.--7. "RESERVED_0,Reserved field" "0,1,2,3"
newline
bitfld.byte 0x00 5. "RX0_RXHS_DDL_PHASE_CLK_OVR_EN_RW,RX HS DDL Phase Clock Override Control" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_PHASE_CLK_OVR_RW__4__0__,RX HS DDL Phase Clock Override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0xC0D++0x00
line.byte 0x00 "DPHY_DATALANE0_DESKEW_OVRVALUE2,Lane 0 DDL Tune Control"
rbitfld.byte 0x00 5.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 4. "RX0_RXHS_DDL_PHASE_DATA_OVR_EN_RW,Override Enable for DDL Phase Data" "0,1"
newline
bitfld.byte 0x00 0.--3. "RX0_RXHS_DDL_PHASE_DATA_OVR_RW__3__0__,RX HS DDL Phase Data Override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xD0F++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_OVRVALUE11,Lane 1 Control"
bitfld.byte 0x00 7. "RX1_RXHS_DDL_PHASE_CLK_OVR_EN_RW,RX HS DDL Phase Data Override Control" "0,1"
newline
bitfld.byte 0x00 2.--6. "RX1_RXHS_DDL_PHASE_CLK_OVR_RW__4__0__,RX HS DDL Phase Clock Override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.byte 0x00 1. "RX1_RXHS_DDL_PHASE_CHANGE_P_OVR_EN_RW,RX HS DDL Phase Changed Override Control" "0,1"
newline
bitfld.byte 0x00 0. "RX1_RXHS_DDL_PHASE_CHANGE_P_OVR_RW,RX HS DDL Phase Changed Override Control" "0,1"
group.byte 0xD10++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_OVRVALUE21,Lane 1 Control"
rbitfld.byte 0x00 5.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 4. "RX1_RXHS_DDL_PHASE_DATA_OVR_EN_RW,Override Enable for DDL Phase Data" "0,1"
newline
bitfld.byte 0x00 0.--3. "RX1_RXHS_DDL_PHASE_DATA_OVR_RW__3__0__,RX HS DDL phase clock override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0xD33++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_COMPS1,Lane 0 Observability"
bitfld.byte 0x00 4. "RX0_DESKEWCALFAILED_IF,Register is used to observe (read_only) the value of rx0_deskewcalfailed_if which is the deskew calibration error flag" "0,1"
newline
bitfld.byte 0x00 3. "RX0_DESKEWCALDONE_IF,Register is used to observe (read_only) the value of rx0_deskewcaldone_if which is the deskew calibration process completion flag" "0,1"
newline
bitfld.byte 0x00 2. "LSRXCLK_LANE0,Low-Speed Clock(Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--1. "LPRXDOUTULP_LANE0__1__0__,Register is used to observe (read_only) the value of lprxdoutulp_lane0_if which is the output of the ulp comparator" "0,1,2,3"
rgroup.byte 0xD38++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_VALUE11,Lane 1 Observability"
bitfld.byte 0x00 7. "RESERVED_0,Reserved field" "0,1"
newline
bitfld.byte 0x00 2.--6. "RX1_RXHS_DDL_PHASE_CLK_IF__4__0__,Clock DDL Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.byte 0x00 1. "RX1_RXHS_DDL_PHASE_CHANGE_P_IF,DDL Setting Change Latch Pulse (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX1_PM_START,Pattern Matcher Start Flag Observation (Volatile)" "0,1"
rgroup.byte 0xD39++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_VALUE21,Lane 1 Observability"
bitfld.byte 0x00 4.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0.--3. "RX1_RXHS_DDL_PHASE_DATA_IF__3__0__,Data DDl Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xD7F++0x00
line.byte 0x00 "DPHY_DATAL1OFFSETCAL_OVRCNTRL,Lane 1 Offset Compensation Control"
bitfld.byte 0x00 7. "RX1_RXHS_DATA_OFFSET_CAL_EN_OVR_EN_RW,Data Offset Calibration Override Enable Control" "0,1"
newline
bitfld.byte 0x00 6. "RX1_CAL_DONE_OVR_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 5. "RX1_CAL_DONE_OVR_EN_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 4. "RX1_START_CALIBRATION_OVR_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 3. "RX1_START_CALIBRATION_OVR_EN_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 2. "RX1_RXHS_DATA_OFFSET_CAL_OVR_EN_RW,Offset Calibration Setting Override" "0,1"
group.byte 0xD80++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_OVRVALUE1,Lane 0 Offset Compensation Control"
hexmask.byte 0x00 1.--7. 1. "RX0_RXHS_DATA_OFFSET_CAL_OVR_RW__6__0__,Offset Calibration Setting Override Enable"
newline
bitfld.byte 0x00 0. "RX0_RXHS_DATA_OFFSET_CAL_EN_OVR_RW,Data Offset Calibration Override Enable Control" "0,1"
rgroup.byte 0xDA3++0x00
line.byte 0x00 "DPHY_DATALANE_OFFSETCAL_COMPS1,Lane Offset Compensation Observability"
bitfld.byte 0x00 2. "RX0_CAL_ERROR,Offset Calibration Algorithm Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_CAL_DONE,Offset Calibration Algorithm Done (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX0_START_CALIBRATION,Offset Calibration Algorithm Start (Volatile)" "0,1"
rgroup.byte 0xDA5++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_VALUE1,Lane Offset Compensation Observability"
bitfld.byte 0x00 7. "RX0_RXHS_DATA_OFFSET_CAL_EN,Offset calibration algorithm enable (volatile)" "0,1"
newline
hexmask.byte 0x00 0.--6. 1. "RX0_RXHS_DATA_OFFSET_CAL__6__0__,Offset calibration algorithm setting chosen (volatile)"
rgroup.byte 0xDE4++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_COMP1,Lane DDL Tune Observability"
bitfld.byte 0x00 3. "RX0_DDL_START_CALIBRATION_IF,DDL Tune Digital Algorithm Start (Volatile)" "0,1"
newline
bitfld.byte 0x00 2. "RX0_DDL_FINISHED_IF,DDL Tune Done Indication (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_DDL_ERROR_FLAG_IF,DDL Tune Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "DDL_TUNE_EN_LANE0_IF,DDL Tune Analog Circuitry Enable Indication (Volatile)" "0,1"
rgroup.byte 0xDE9++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_VALUE1,Lane 0 DDL Tune Observability"
bitfld.byte 0x00 5. "RX0_RXHS_DDL_PHASE_CHANGE_P_IF,RX HS DDL Phase Change (Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_IF__4__0__,RX HS DDL Tunning Setting (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0xE0B++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_OVRVALUE1,Lane 0 DDL Tune Control"
rbitfld.byte 0x00 6.--7. "reserved_0,Reserved field" "0,1,2,3"
newline
bitfld.byte 0x00 5. "RX0_RXHS_DDL_TUNE_OVR_EN_RW,RX HS DDL Tune Override Enable Control" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_OVR_RW__4__0__,RX HS DDL Tune Override for Lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0xF0F++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_OVRVALUE12,Lane 1 Control"
bitfld.byte 0x00 7. "RX1_RXHS_DDL_PHASE_CLK_OVR_EN_RW,RX HS DDL Phase Data Override Control" "0,1"
newline
bitfld.byte 0x00 2.--6. "RX1_RXHS_DDL_PHASE_CLK_OVR_RW__4__0__,RX HS DDL Phase Clock Override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.byte 0x00 1. "RX1_RXHS_DDL_PHASE_CHANGE_P_OVR_EN_RW,RX HS DDL Phase Changed Override Control" "0,1"
newline
bitfld.byte 0x00 0. "RX1_RXHS_DDL_PHASE_CHANGE_P_OVR_RW,RX HS DDL Phase Changed Override Control" "0,1"
group.byte 0xF10++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_OVRVALUE22,Lane 1 Control"
rbitfld.byte 0x00 5.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 4. "RX1_RXHS_DDL_PHASE_DATA_OVR_EN_RW,Override Enable for DDL Phase Data" "0,1"
newline
bitfld.byte 0x00 0.--3. "RX1_RXHS_DDL_PHASE_DATA_OVR_RW__3__0__,RX HS DDL phase clock override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0xF33++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_COMPS2,Lane 0 Observability"
bitfld.byte 0x00 4. "RX0_DESKEWCALFAILED_IF,Register is used to observe (read_only) the value of rx0_deskewcalfailed_if which is the deskew calibration error flag" "0,1"
newline
bitfld.byte 0x00 3. "RX0_DESKEWCALDONE_IF,Register is used to observe (read_only) the value of rx0_deskewcaldone_if which is the deskew calibration process completion flag" "0,1"
newline
bitfld.byte 0x00 2. "LSRXCLK_LANE0,Low-Speed Clock(Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--1. "LPRXDOUTULP_LANE0__1__0__,Register is used to observe (read_only) the value of lprxdoutulp_lane0_if which is the output of the ulp comparator" "0,1,2,3"
rgroup.byte 0xF38++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_VALUE12,Lane 1 Observability"
bitfld.byte 0x00 7. "RESERVED_0,Reserved field" "0,1"
newline
bitfld.byte 0x00 2.--6. "RX1_RXHS_DDL_PHASE_CLK_IF__4__0__,Clock DDL Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.byte 0x00 1. "RX1_RXHS_DDL_PHASE_CHANGE_P_IF,DDL Setting Change Latch Pulse (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX1_PM_START,Pattern Matcher Start Flag Observation (Volatile)" "0,1"
rgroup.byte 0xF39++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_VALUE22,Lane 1 Observability"
bitfld.byte 0x00 4.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0.--3. "RX1_RXHS_DDL_PHASE_DATA_IF__3__0__,Data DDl Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xF7F++0x00
line.byte 0x00 "DPHY_DATAL2OFFSETCAL_OVRCNTRL,Lane 1 Offset Compensation Control"
bitfld.byte 0x00 7. "RX2_RXHS_DATA_OFFSET_CAL_EN_OVR_EN_RW,Data Offset Calibration Override Enable Control" "0,1"
newline
bitfld.byte 0x00 6. "RX2_CAL_DONE_OVR_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 5. "RX2_CAL_DONE_OVR_EN_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 4. "RX2_START_CALIBRATION_OVR_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 3. "RX2_START_CALIBRATION_OVR_EN_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 2. "RX2_RXHS_DATA_OFFSET_CAL_OVR_EN_RW,Offset Calibration Setting Override" "0,1"
group.byte 0xF80++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_OVRVALUE2,Lane 0 Offset Compensation Control"
hexmask.byte 0x00 1.--7. 1. "RX0_RXHS_DATA_OFFSET_CAL_OVR_RW__6__0__,Offset Calibration Setting Override Enable"
newline
bitfld.byte 0x00 0. "RX0_RXHS_DATA_OFFSET_CAL_EN_OVR_RW,Data Offset Calibration Override Enable Control" "0,1"
rgroup.byte 0xFA3++0x00
line.byte 0x00 "DPHY_DATALANE_OFFSETCAL_COMPS2,Lane Offset Compensation Observability"
bitfld.byte 0x00 2. "RX0_CAL_ERROR,Offset Calibration Algorithm Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_CAL_DONE,Offset Calibration Algorithm Done (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX0_START_CALIBRATION,Offset Calibration Algorithm Start (Volatile)" "0,1"
rgroup.byte 0xFA5++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_VALUE2,Lane Offset Compensation Observability"
bitfld.byte 0x00 7. "RX0_RXHS_DATA_OFFSET_CAL_EN,Offset calibration algorithm enable (volatile)" "0,1"
newline
hexmask.byte 0x00 0.--6. 1. "RX0_RXHS_DATA_OFFSET_CAL__6__0__,Offset calibration algorithm setting chosen (volatile)"
rgroup.byte 0xFE4++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_COMP2,Lane DDL Tune Observability"
bitfld.byte 0x00 3. "RX0_DDL_START_CALIBRATION_IF,DDL Tune Digital Algorithm Start (Volatile)" "0,1"
newline
bitfld.byte 0x00 2. "RX0_DDL_FINISHED_IF,DDL Tune Done Indication (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_DDL_ERROR_FLAG_IF,DDL Tune Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "DDL_TUNE_EN_LANE0_IF,DDL Tune Analog Circuitry Enable Indication (Volatile)" "0,1"
rgroup.byte 0xFE9++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_VALUE2,Lane 0 DDL Tune Observability"
bitfld.byte 0x00 5. "RX0_RXHS_DDL_PHASE_CHANGE_P_IF,RX HS DDL Phase Change (Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_IF__4__0__,RX HS DDL Tunning Setting (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x100B++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_OVRVALUE2,Lane 0 DDL Tune Control"
rbitfld.byte 0x00 6.--7. "reserved_0,Reserved field" "0,1,2,3"
newline
bitfld.byte 0x00 5. "RX0_RXHS_DDL_TUNE_OVR_EN_RW,RX HS DDL Tune Override Enable Control" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_OVR_RW__4__0__,RX HS DDL Tune Override for Lane 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x110B++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_OVRVALUE3,Lane 0 DDL Tune Control"
rbitfld.byte 0x00 6.--7. "RESERVED_0,Reserved field" "0,1,2,3"
newline
bitfld.byte 0x00 5. "RX0_RXHS_DDL_TUNE_OVR_EN_RW,RX HS DDL Tune Override Enable Control" "0,1"
newline
bitfld.byte 0x00 4. "RX0_RXHS_DDL_TUNE_OVR_RW__4,RX HS DDL Tune Override for Lane 0" "0,1"
newline
rbitfld.byte 0x00 1.--3. "RESERVED_1,Reserved field" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 0. "RX0_RXHS_DDL_TUNE_OVR_RW__4__0__,RX HS DDL Tune Override for Lane 0" "0,1"
group.byte 0x110F++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_OVRVALUE13,Lane 1 Control"
bitfld.byte 0x00 7. "RX1_RXHS_DDL_PHASE_CLK_OVR_EN_RW,RX HS DDL Phase Data Override Control" "0,1"
newline
bitfld.byte 0x00 2.--6. "RX1_RXHS_DDL_PHASE_CLK_OVR_RW__4__0__,RX HS DDL Phase Clock Override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.byte 0x00 1. "RX1_RXHS_DDL_PHASE_CHANGE_P_OVR_EN_RW,RX HS DDL Phase Changed Override Control" "0,1"
newline
bitfld.byte 0x00 0. "RX1_RXHS_DDL_PHASE_CHANGE_P_OVR_RW,RX HS DDL Phase Changed Override Control" "0,1"
group.byte 0x1110++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_OVRVALUE23,Lane 1 Control"
rbitfld.byte 0x00 5.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 4. "RX1_RXHS_DDL_PHASE_DATA_OVR_EN_RW,Override Enable for DDL Phase Data" "0,1"
newline
bitfld.byte 0x00 0.--3. "RX1_RXHS_DDL_PHASE_DATA_OVR_RW__3__0__,RX HS DDL phase clock override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x1133++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_COMPS3,Lane 0 Observability"
bitfld.byte 0x00 4. "RX0_DESKEWCALFAILED_IF,Register is used to observe (read_only) the value of rx0_deskewcalfailed_if which is the deskew calibration error flag" "0,1"
newline
bitfld.byte 0x00 3. "RX0_DESKEWCALDONE_IF,Register is used to observe (read_only) the value of rx0_deskewcaldone_if which is the deskew calibration process completion flag" "0,1"
newline
bitfld.byte 0x00 2. "LSRXCLK_LANE0,Low-Speed Clock(Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--1. "LPRXDOUTULP_LANE0__1__0__,Register is used to observe (read_only) the value of lprxdoutulp_lane0_if which is the output of the ulp comparator" "0,1,2,3"
rgroup.byte 0x1138++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_VALUE13,Lane 1 Observability"
bitfld.byte 0x00 7. "RESERVED_0,Reserved field" "0,1"
newline
bitfld.byte 0x00 2.--6. "RX1_RXHS_DDL_PHASE_CLK_IF__4__0__,Clock DDL Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.byte 0x00 1. "RX1_RXHS_DDL_PHASE_CHANGE_P_IF,DDL Setting Change Latch Pulse (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX1_PM_START,Pattern Matcher Start Flag Observation (Volatile)" "0,1"
rgroup.byte 0x1139++0x00
line.byte 0x00 "DPHY_DATALANE_DESKEW_VALUE23,Lane 1 Observability"
bitfld.byte 0x00 4.--7. "RESERVED_0,Reserved field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0.--3. "RX1_RXHS_DDL_PHASE_DATA_IF__3__0__,Data DDl Setting Chosen (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x117F++0x00
line.byte 0x00 "DPHY_DATAL3OFFSETCAL_OVRCNTRL,Lane 1 Offset Compensation Control"
bitfld.byte 0x00 7. "RX3_RXHS_DATA_OFFSET_CAL_EN_OVR_EN_RW,Data Offset Calibration Override Enable Control" "0,1"
newline
bitfld.byte 0x00 6. "RX3_CAL_DONE_OVR_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 5. "RX3_CAL_DONE_OVR_EN_RW,Calibration Done Override Enable Control" "0,1"
newline
bitfld.byte 0x00 4. "RX3_START_CALIBRATION_OVR_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 3. "RX3_START_CALIBRATION_OVR_EN_RW,RX Start Calibration" "0,1"
newline
bitfld.byte 0x00 2. "RX3_RXHS_DATA_OFFSET_CAL_OVR_EN_RW,Offset Calibration Setting Override" "0,1"
group.byte 0x1180++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_OVRVALUE3,Lane 0 Offset Compensation Control"
hexmask.byte 0x00 1.--7. 1. "RX0_RXHS_DATA_OFFSET_CAL_OVR_RW__6__0__,Offset Calibration Setting Override Enable"
newline
bitfld.byte 0x00 0. "RX0_RXHS_DATA_OFFSET_CAL_EN_OVR_RW,Data Offset Calibration Override Enable Control" "0,1"
rgroup.byte 0x11A3++0x00
line.byte 0x00 "DPHY_DATALANE_OFFSETCAL_COMPS3,Lane Offset Compensation Observability"
bitfld.byte 0x00 2. "RX0_CAL_ERROR,Offset Calibration Algorithm Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_CAL_DONE,Offset Calibration Algorithm Done (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "RX0_START_CALIBRATION,Offset Calibration Algorithm Start (Volatile)" "0,1"
rgroup.byte 0x11A5++0x00
line.byte 0x00 "DPHY_DATALOFFSETCAL_VALUE3,Lane Offset Compensation Observability"
bitfld.byte 0x00 7. "RX0_RXHS_DATA_OFFSET_CAL_EN,Offset calibration algorithm enable (volatile)" "0,1"
newline
hexmask.byte 0x00 0.--6. 1. "RX0_RXHS_DATA_OFFSET_CAL__6__0__,Offset calibration algorithm setting chosen (volatile)"
rgroup.byte 0x11E4++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_COMP3,Lane DDL Tune Observability"
bitfld.byte 0x00 3. "RX0_DDL_START_CALIBRATION_IF,DDL Tune Digital Algorithm Start (Volatile)" "0,1"
newline
bitfld.byte 0x00 2. "RX0_DDL_FINISHED_IF,DDL Tune Done Indication (Volatile)" "0,1"
newline
bitfld.byte 0x00 1. "RX0_DDL_ERROR_FLAG_IF,DDL Tune Error (Volatile)" "0,1"
newline
bitfld.byte 0x00 0. "DDL_TUNE_EN_LANE0_IF,DDL Tune Analog Circuitry Enable Indication (Volatile)" "0,1"
rgroup.byte 0x11E9++0x00
line.byte 0x00 "DPHY_DATALANE_DDLTUNE_VALUE3,Lane 0 DDL Tune Observability"
bitfld.byte 0x00 5. "RX0_RXHS_DDL_PHASE_CHANGE_P_IF,RX HS DDL Phase Change (Volatile)" "0,1"
newline
bitfld.byte 0x00 0.--4. "RX0_RXHS_DDL_TUNE_IF__4__0__,RX HS DDL Tunning Setting (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.byte 0x14AA++0x00
line.byte 0x00 "DPHY_CB_VBE_SEL,Common Block Control"
bitfld.byte 0x00 5.--6. "CB_SEL_VREFCD_LPRX_RW__1__0__,LPRX Contention Detector Voltage Reference Selection" "0: CB_SEL_VREFCD_LPRX_RW__1__0___0,1: CB_SEL_VREFCD_LPRX_RW__1__0___1,2: CB_SEL_VREFCD_LPRX_RW__1__0___2,3: CB_SEL_VREFCD_LPRX_RW__1__0___3"
newline
bitfld.byte 0x00 2.--4. "CB_SEL_V400_PROG_RW__2__0__,Select Value Of cb_v400" "0: CB_SEL_V400_PROG_RW__2__0___0,1: CB_SEL_V400_PROG_RW__2__0___1,2: CB_SEL_V400_PROG_RW__2__0___2,3: CB_SEL_V400_PROG_RW__2__0___3,?..."
newline
bitfld.byte 0x00 1. "CB_SEL_CHOP_CLK_RW,Select Bandgap Clock Source" "0: Internal oscillator (internal clock source),1: External clock signal"
newline
bitfld.byte 0x00 0. "CB_CHOP_CLK_EN_RW,Bandgap Chop Clock Enable" "0: CB_CHOP_CLK_EN_RW_0,1: Chop clock switching"
group.byte 0x14AB++0x00
line.byte 0x00 "DPHY_ATB_CB_ATB_VBE_SEL,Common Block Control"
bitfld.byte 0x00 6. "CB_ATB_VBE_SEL_RW,VBE Selection To Analog Test Bus (ATB)" "0,1"
newline
bitfld.byte 0x00 3.--5. "TXLP_PROG_RW_2_0,LP-TX programmability" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x00 2. "CB_SEL_VREFLPTX_PROG_RW,LP-TX Voltage Reference Selection" "0: CB_SEL_VREFLPTX_PROG_RW_0,1: CB_SEL_VREFLPTX_PROG_RW_1"
newline
bitfld.byte 0x00 0.--1. "CB_SEL_VREF_LPRX_RW_1_0,LP-RX Contention Detector Voltage Reference Selection" "0: CB_SEL_VREF_LPRX_RW_1_0_0,1: CB_SEL_VREF_LPRX_RW_1_0_1,2: CB_SEL_VREF_LPRX_RW_1_0_2,3: CB_SEL_VREF_LPRX_RW_1_0_3"
group.byte 0x1509++0x00
line.byte 0x00 "DPHY_TX_RDWR_TERM_CAL_0,Termination Calibration Control"
bitfld.byte 0x00 4.--7. "CB_CAL_REPL_OVR_RW__3__0__,Calibration word for termination lower section override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 3. "CB_CAL_EN_UP_OVR_RW,Upper section termination calibration algorithm enable override" "0,1"
newline
bitfld.byte 0x00 2. "CB_CAL_EN_UP_OVR_EN_RW,Upper section termination calibration algorithm enable override enable" "0,1"
newline
bitfld.byte 0x00 1. "CB_CAL_EN_OVR_RW,Allow to override the lower part termination control" "0,1"
newline
bitfld.byte 0x00 0. "CB_CAL_EN_OVR_EN_RW,Allow to override the lower part termination control" "0,1"
group.byte 0x150A++0x00
line.byte 0x00 "DPHY_TX_TERM_CAL_OVR,Termination Calibration Control"
bitfld.byte 0x00 7. "CB_EN_45_OHM_RW,Selection For 45 ohm Termination Impedance" "0,1"
newline
bitfld.byte 0x00 6. "CB_CAL_REPL_UP_OVR_EN_RW,Upper Section Termination Replica Setting" "0,1"
newline
bitfld.byte 0x00 2.--5. "CB_CAL_REPL_UP_OVR_RW__3__0__,Upper Section Termination Replica Setting Override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 1. "CB_CAL_REPL_UP_BYPASS_RW,Upper Section Of Termination Replica Calibration Bypass" "0,1"
newline
bitfld.byte 0x00 0. "CB_CAL_REPL_OVR_EN_RW,Calibration Word For Termination Lower Section replica Override Enable" "0,1"
rgroup.byte 0x1520++0x00
line.byte 0x00 "DPHY_TX_TERM_CAL_0,Termination Calibration Observability"
bitfld.byte 0x00 6. "CB_SEL_UP_1ST,Register is used to observe (read_only) Boosting voltage selection for upper section of TX replica to be probed on ATB bus" "0,1"
newline
bitfld.byte 0x00 2.--5. "CB_CAL_REPL__3__0__,Register is used to observe (read_only) Termination lower section replica setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 1. "CB_CAL_EN_UP,Register is used to observe (read_only) Termination upper section analog circuitry enable" "0,1"
newline
bitfld.byte 0x00 0. "CB_CAL_EN,Register is used to observe (read_only) Termination lower section analog circuitry enable" "0,1"
rgroup.byte 0x1521++0x00
line.byte 0x00 "DPHY_TX_TERM_CAL_1,Termination Calibration Observability"
bitfld.byte 0x00 7. "RESCAL_DONE,Lower Section Termination Calibration Algorithm Done (Volatile)" "0,1"
newline
bitfld.byte 0x00 6. "RESCAL_UP_EN,Upper Section Termination Calibration Algorithm Enable (Volatile)" "0,1"
newline
bitfld.byte 0x00 5. "RESCAL_EN,Lower Section Termination Calibration Algorithm Enable (Volatile)" "0,1"
newline
bitfld.byte 0x00 4. "CB_COMP_OUT,Register is used to observe (read_only) the value of rx_cb_comp_out_if which is the output of the ATB comparator" "0,1"
newline
bitfld.byte 0x00 0.--3. "CB_CAL_REPL_UP__3__0__,Termination Upper Section Replica Setting (Volatile)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x1522++0x00
line.byte 0x00 "DPHY_TERMCAL_STAT2,Termination Calibration Observability"
bitfld.byte 0x00 2. "RESCAL_UP_ERROR,Register is used to observe (read_only) Termination upper section calibration algorithm error" "0,1"
newline
bitfld.byte 0x00 1. "RESCAL_UP_DONE,Register is used to observe (read_only) Termination upper section calibration algorithm done" "0,1"
newline
bitfld.byte 0x00 0. "RESCAL_ERROR,Register is used to observe (read_only) Termination upper section calibration algorithm error" "0,1"
group.byte 0x1607++0x00
line.byte 0x00 "DPHY_CLKLANE_POLCFG,Clock Lane Control"
bitfld.byte 0x00 0. "POLARITY_CLKLANE_RW,Clock Lane DP/DN Swap - Active High" "0,1"
group.byte 0x1A01++0x00
line.byte 0x00 "DPHY_ATB_DATA_LANE1,Lane 1 Control"
bitfld.byte 0x00 7. "HSTXBITREV_LANE1_RW,Allows inverting serialization order in lane 1 (MSB -> LSB)" "0,1"
newline
bitfld.byte 0x00 6. "BINTPON_LANE1_RW,Bias Block Power-On" "0,1"
newline
bitfld.byte 0x00 5. "BINTPON_BYPASS_LANE1_RW,Bias Block Power-On Bypass Override" "0,1"
newline
bitfld.byte 0x00 1.--4. "ATB_SEL_LANE1_RW_3_0,Analog Test Bus Signals Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0. "ATB_LPTX1200_ON_LANE1_RW,Select to probe in analog test bus LP transmitter voltage reference" "0,1"
group.byte 0x1C01++0x00
line.byte 0x00 "DPHY_ATB_DATA_LANE2,Lane 2 Control"
bitfld.byte 0x00 7. "HSTXBITREV_LANE2_RW,Allows inverting serialization order in lane 2 (MSB -> LSB)" "0,1"
newline
bitfld.byte 0x00 6. "BINTPON_LANE2_RW,Bias Block Power-On" "0,1"
newline
bitfld.byte 0x00 5. "BINTPON_BYPASS_LANE2_RW,Bias Block Power-On Bypass Override" "0,1"
newline
bitfld.byte 0x00 1.--4. "ATB_SEL_LANE2_RW_3_0,Analog Test Bus Signals Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0. "ATB_LPTX1200_ON_LANE2_RW,Selection to probe in analog test bus LP transmitter voltage reference" "0,1"
group.byte 0x1E01++0x00
line.byte 0x00 "DPHY_ATB_DATA_LANE3,Lane 3 Control"
bitfld.byte 0x00 7. "HSTXBITREV_LANE3_RW,Allows inverting serialization order in lane 3 (MSB -> LSB)" "0,1"
newline
bitfld.byte 0x00 6. "BINTPON_LANE3_RW,Bias Block Power-On" "0,1"
newline
bitfld.byte 0x00 5. "BINTPON_BYPASS_LANE3_RW,Bias Block Power-On Bypass Override" "0,1"
newline
bitfld.byte 0x00 1.--4. "ATB_SEL_LANE3_RW_3_0,Analog Test Bus Signals Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.byte 0x00 0. "ATB_LPTX1200_ON_LANE3_RW,Selection to probe in analog test bus LP transmitter voltage reference" "0,1"
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2000)++0x03
line.long 0x00 "CRC_LINE_NUM_CFG_REGISTER_VC[$1],This register allows configuration for line number in a frame for which the calculated and expected CRC value need to be captured for VC@{i $1"
bitfld.long 0x00 31. "CRC_LINE_NUM_EN,This field allows configuring if CRC for each received packet needs to be captured/updated in register or should be done for only the configured line number" "0: CRC value is captured for each line received..,1: CRC value is captured for configured line.."
newline
bitfld.long 0x00 16.--21. "CRC_CFG_DATA_TYPE,Data-type for which CRC received and calculated need to be captured" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "CRC_LINE_NUM,Line number for which CRC received and calculated need to be captured"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x2010)++0x03
line.long 0x00 "CRC_REGISTER[$1],This register records the CRC value calculated by the controller and the CRC value that is received by the controller for every packet of the VC@{i $1"
hexmask.long.word 0x00 16.--31. 1. "PAYLOAD_CRC_CALCULATED,CRC calculated by the controller on the incoming packet"
newline
hexmask.long.word 0x00 0.--15. 1. "PAYLOAD_CRC_RECEIVED,CRC received by the controller along with the packet"
repeat.end
group.long 0x2100++0x03
line.long 0x00 "AXI_WRITE_CFG,AXI write channel configuration"
bitfld.long 0x00 5.--6. "AXI_DOMAIN,This field is programmed to program the shareability domain of the write transaction on AXI channel" "0,1,2,3"
newline
bitfld.long 0x00 1.--4. "AXI_AWCACHE,This field is used to program the cacheability of the AXI write transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "AXI_WRITE_CFG_EN,AXI write channel configuration Enable" "0: AXI write channel configuration through..,1: AXI write channel configuration through.."
group.long 0x2108++0x03
line.long 0x00 "MIPICSI2_SCRAMBLING_CFG,Scrambling configuration"
bitfld.long 0x00 1. "Reserved,Reserved" "0,1"
newline
bitfld.long 0x00 0. "CFG_DESCRAMBLE_EN,This field is used to enable the descrambling in CSI2" "0: Descrambling is Disabled,1: Descrambling on incoming MIPICSI2 stream is.."
repeat 12. (increment 0 1)(increment  0 0x30)
tree "RX[$1]"
group.long ($2+0x100)++0x03
line.long 0x00 "RX_CBUF_CONFIG,Receive Data Circular Buffer Configuration"
bitfld.long 0x00 10. "FIFTHCH_ENABLE,Fifth channel data capture enabled for the buffer" "0: Fifth channel data capture disabled for..,1: Fifth channel data capture enabled for.."
bitfld.long 0x00 8.--9. "VCID,This field indicates the virtual channel the content of which is to be received in the circular buffer" "0: VC to be received is VC0,1: VC to be received is VC1,2: VC to be received is VC2,3: VC to be received is VC3"
newline
bitfld.long 0x00 2.--7. "DATAID,This field indicates the data type to be received in the circular buffer" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,18: Embedded packet,?,?,?,?,?,?,?,?,?,?,?,30: YUV 422,31: YUV 422,?,?,34: RGB 565 packet,?,36: RGB 888 packet,?,?,?,?,?,42: RAW 8 packet,43: RAW 10 packet,44: RAW 12 packet,45: RAW 14 packet,46: RAW 16 packet,?,48: User-defined packet,49: User-defined packet,50: User-defined packet,51: User-defined packet,52: User-defined packet,53: User-defined packet,54: User-defined packet,55: User-defined packet,?..."
bitfld.long 0x00 0. "TRACE,This field indicates whether the data being written over the current buffer is a traceable AXI transaction" "0: Non-traceable transaction,1: Traceable transaction"
group.long ($2+0x104)++0x03
line.long 0x00 "RX_INPLINELEN_CONFIG,Receive Data Input Line Length Configuration"
hexmask.long.word 0x00 0.--15. 1. "INPLINELEN,Expected length of the incoming MIPI packet in bytes Minimum no"
group.long ($2+0x108)++0x03
line.long 0x00 "RX_LINELEN_CONFIG,Receive Data Line Length Configuration"
hexmask.long.word 0x00 0.--15. 1. "LINELEN,Expected length of the packet in bytes to be received"
group.long ($2+0x10C)++0x03
line.long 0x00 "RX_NUMLINES_CONFIG,Receive Data Expected Number of Lines Configuration"
hexmask.long.word 0x00 0.--15. 1. "NUMLINES,Number of Lines"
group.long ($2+0x110)++0x03
line.long 0x00 "RX_CBUF_SRTPTR,Receive Data Circular Buffer Start Pointer"
hexmask.long 0x00 4.--31. 1. "STRPTR,Start address offset of the circular buffer for MIPICSI2 receive data"
group.long ($2+0x114)++0x03
line.long 0x00 "RX_CBUF_BUFLEN,Receive Data Circular Buffer Length"
hexmask.long.word 0x00 0.--15. 1. "BUFLEN,16-byte aligned length for each line written in the circular buffer for MIPICSI2 data"
group.long ($2+0x118)++0x03
line.long 0x00 "RX_CBUF_NUMLINE,Receive Data Circular Buffer Number of Lines"
bitfld.long 0x00 31. "CBUF_START_PTR_RESET,If this field is set circular buffer pointer for next frame will be set to the start pointer of circular buffer" "0: Circular buffer pointer for next frame will..,1: Circular buffer pointer for next frame will.."
hexmask.long.word 0x00 0.--15. 1. "NUMLINES,Number of lines in the circular buffer for MIPICSI2 received data"
group.long ($2+0x11C)++0x03
line.long 0x00 "RX_CBUF_LPDI,Receive Data Circular Buffer Lines Done Generation"
hexmask.long.byte 0x00 0.--7. 1. "NUMLINES,Number of lines captured in the circular buffer after which done trigger is generated"
rgroup.long ($2+0x120)++0x03
line.long 0x00 "RX_CBUF_NXTLINE,Receive Data Circular Buffer Next Row Indication"
hexmask.long.word 0x00 0.--15. 1. "NXTLINE,Row number in the circular buffer where next line of MIPICSI2 received data is to be written"
rgroup.long ($2+0x124)++0x03
line.long 0x00 "RX_CBUF_RXLINE,Receive Data Circular Buffer Total Lines Received Status"
hexmask.long.word 0x00 0.--15. 1. "TOTLINES,Total Number of Lines"
rgroup.long ($2+0x128)++0x03
line.long 0x00 "RX_CBUF_ERRLEN,Receive Data Circular Buffer Error Line Length Status"
hexmask.long.word 0x00 0.--15. 1. "ERRLEN,Length of first line in bytes the length of which is different from the one configured for the circular buffer for MIPICSI2 received data"
rgroup.long ($2+0x12C)++0x03
line.long 0x00 "RX_CBUF_ERRLINE,Receive Data Circular Buffer Line Number for Incorrect Length Status"
hexmask.long.word 0x00 0.--15. 1. "ERRLINE,Line number of first line the length of which is different from the one configured for the circular buffer for MIPICSI2 received data"
tree.end
repeat.end
repeat 4. (increment 0 1)(increment  0 0xFFFFFFB0)
tree "RX_VC[$1]"
group.long ($2+0xA0)++0x03
line.long 0x00 "PPERRIS,Receive Data Protocol and Packet Error Interrupt Status for VCi"
eventfld.long 0x00 6. "Reserved,Reserved" "0,1"
eventfld.long 0x00 5. "INVIDERR,Invalid ID Detected in Received Data Stream" "0,1"
eventfld.long 0x00 4. "CRCERR,CRC Error in Received Data Stream" "0,1"
eventfld.long 0x00 3. "ERFDAT,Error in Data in Received Data Stream" "0,1"
eventfld.long 0x00 2. "ERFSYN,Frame Synchronization Error in Received Data Stream" "0,1"
eventfld.long 0x00 1. "ECCTWO,2-Bit ECC Error in Received Packet Header" "0,1"
eventfld.long 0x00 0. "ECCONE,1-Bit ECC Error in Received Packet Header" "0,1"
group.long ($2+0xA4)++0x03
line.long 0x00 "PPERRIE,Receive Data Protocol and Packet Error Interrupt Enable for VCi"
bitfld.long 0x00 6. "Reserved,Reserved" "0,1"
bitfld.long 0x00 5. "INVIDERRIE,Invalid ID Interrupt Enable" "0,1"
bitfld.long 0x00 4. "CRCERRIE,CRC Error Interrupt Enable" "0,1"
bitfld.long 0x00 3. "ERFDATIE,Frame Data Error Interrupt Enable" "0,1"
bitfld.long 0x00 2. "ERFSYNIE,Frame Synchronization Error Interrupt Enable" "0,1"
bitfld.long 0x00 1. "ECCTWOIE,ECC 2-Bit Error Interrupt Enable" "0,1"
bitfld.long 0x00 0. "ECCONEIE,ECC 1-Bit Error Interrupt Enable" "0,1"
rgroup.long ($2+0xA8)++0x03
line.long 0x00 "ERRPOS,Receive ECC 1-Bit Error Position for VCi"
bitfld.long 0x00 0.--4. "ERRPOS,Error Position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long ($2+0xAC)++0x03
line.long 0x00 "NUMPPERR,Receive Packets Number of Protocol Errors for VCi"
hexmask.long.word 0x00 16.--31. 1. "NUMECCERR,Number of ECC 2-Bit Errors"
hexmask.long.word 0x00 0.--15. 1. "NUMCRCERR,Number of CRC Errors"
tree.end
repeat.end
tree.end
tree.end
tree "MSCM"
base ad:0x40010000
rgroup.long 0x00++0x03
line.long 0x00 "CPXTYPE,Processor x Type"
hexmask.long 0x00 0.--31. 1. "PERSONALITY,Personality Of CPx"
rgroup.long 0x04++0x03
line.long 0x00 "CPXNUM,Processor x Number"
bitfld.long 0x00 0.--1. "CPN,Processor Number" "0: Core 0,1: Core 1,2: Core 2,?..."
rgroup.long 0x08++0x03
line.long 0x00 "CPXREV,Processor x Revision"
hexmask.long.byte 0x00 0.--7. 1. "RYPZ,Processor Revision"
rgroup.long 0x0C++0x03
line.long 0x00 "CPXCFG0,Processor x Configuration 0"
hexmask.long.byte 0x00 24.--31. 1. "ICSZ,L1 Instruction Cache Size"
hexmask.long.byte 0x00 16.--23. 1. "ICWY,L1 Instruction Cache Ways"
newline
hexmask.long.byte 0x00 8.--15. 1. "DCSZ,L1 Data Cache Size"
hexmask.long.byte 0x00 0.--7. 1. "DCWY,L1 Data Cache Ways"
rgroup.long 0x10++0x03
line.long 0x00 "CPXCFG1,Processor x Configuration 1"
hexmask.long.byte 0x00 24.--31. 1. "L2SZ,L2 Cache Size"
hexmask.long.byte 0x00 16.--23. 1. "L2WY,L2 Cache Ways"
rgroup.long 0x14++0x03
line.long 0x00 "CPXCFG2,Processor x Configuration 2"
hexmask.long.byte 0x00 24.--31. 1. "DTCMSZ,Data Tightly Coupled Memory Size"
hexmask.long.byte 0x00 16.--23. 1. "ITCMSZ,Instruction Tightly Coupled Memory Size"
rgroup.long 0x18++0x03
line.long 0x00 "CPXCFG3,Processor x Configuration 3"
bitfld.long 0x00 4. "CPY,Cryptography" "0: Does not support,1: Supports"
bitfld.long 0x00 3. "CMP,Core Memory Protection Unit" "0: Does not include,1: Includes"
newline
bitfld.long 0x00 2. "MMU,Memory Management Unit" "0: Does not support,1: Supports"
bitfld.long 0x00 1. "SIMD,SIMD And NEON Instruction Support" "0: Does not include,1: Includes"
newline
bitfld.long 0x00 0. "HW_FPU,Floating Point Unit" "0: Does not support,1: HW_FPU_1"
rgroup.long 0x20++0x03
line.long 0x00 "CP0TYPE,Processor 0 Type"
hexmask.long 0x00 0.--31. 1. "PERSONALITY,Processor Personality"
rgroup.long 0x24++0x03
line.long 0x00 "CP0NUM,Processor 0 Number"
bitfld.long 0x00 0.--1. "CPN,Processor Number" "0,1,2,3"
rgroup.long 0x28++0x03
line.long 0x00 "CP0REV,Processor 0 Count"
hexmask.long.byte 0x00 0.--7. 1. "RYPZ,Processor Revision"
rgroup.long 0x2C++0x03
line.long 0x00 "CP0CFG0,Processor 0 Configuration 0"
hexmask.long.byte 0x00 24.--31. 1. "ICSZ,L1 Instruction Cache Size"
hexmask.long.byte 0x00 16.--23. 1. "ICWY,L1 Instruction Cache Ways"
newline
hexmask.long.byte 0x00 8.--15. 1. "DCSZ,L1 Data Cache Size"
hexmask.long.byte 0x00 0.--7. 1. "DCWY,L1 Data Cache Ways"
rgroup.long 0x30++0x03
line.long 0x00 "CP0CFG1,Processor 0 Configuration 1"
hexmask.long.byte 0x00 24.--31. 1. "L2SZ,L2 Cache Size"
hexmask.long.byte 0x00 16.--23. 1. "L2WY,L2 Cache Ways"
rgroup.long 0x34++0x03
line.long 0x00 "CP0CFG2,Processor 0 Configuration 2"
hexmask.long.byte 0x00 24.--31. 1. "DTCMSZ,Data Tightly Coupled Memory Size"
hexmask.long.byte 0x00 16.--23. 1. "ITCMSZ,Instruction Tightly Coupled Memory Size"
rgroup.long 0x38++0x03
line.long 0x00 "CP0CFG3,Processor 0 Configuration 3"
bitfld.long 0x00 4. "CPY,Cryptography" "0: Does not support,1: Supports"
bitfld.long 0x00 3. "CMP,Core Memory Protection Unit" "0: Does not include,1: Includes"
newline
bitfld.long 0x00 2. "MMU,Memory Management Unit" "0: Does not support,1: Supports"
bitfld.long 0x00 1. "SIMD,SIMD And NEON Instruction Support" "0: Does not include,1: Includes"
newline
bitfld.long 0x00 0. "HW_FPU,Floating Point Unit" "0: Does not support,1: HW_FPU_1"
rgroup.long 0x40++0x03
line.long 0x00 "CP1TYPE,Processor 1 Type"
hexmask.long 0x00 0.--31. 1. "PERSONALITY,Personality Processor"
rgroup.long 0x44++0x03
line.long 0x00 "CP1NUM,Processor 1 Number"
bitfld.long 0x00 0.--1. "CPN,Processor Number" "0,1,2,3"
rgroup.long 0x48++0x03
line.long 0x00 "CP1REV,Processor 1 Count"
hexmask.long.byte 0x00 0.--7. 1. "RYPZ,Processor Revision"
rgroup.long 0x4C++0x03
line.long 0x00 "CP1CFG0,Processor 1 Configuration 0"
hexmask.long.byte 0x00 24.--31. 1. "ICSZ,L1 Instruction Cache Size"
hexmask.long.byte 0x00 16.--23. 1. "ICWY,L1 Instruction Cache Ways"
newline
hexmask.long.byte 0x00 8.--15. 1. "DCSZ,L1 Data Cache Size"
hexmask.long.byte 0x00 0.--7. 1. "DCWY,L1 Data Cache Ways"
rgroup.long 0x50++0x03
line.long 0x00 "CP1CFG1,Processor 1 Configuration 1"
hexmask.long.byte 0x00 24.--31. 1. "L2SZ,L2 Cache Size"
hexmask.long.byte 0x00 16.--23. 1. "L2WY,L2 Cache Ways"
rgroup.long 0x54++0x03
line.long 0x00 "CP1CFG2,Processor 1 Configuration 2"
hexmask.long.byte 0x00 24.--31. 1. "DTCMSZ,Data Tightly Coupled Memory Size"
hexmask.long.byte 0x00 16.--23. 1. "ITCMSZ,Instruction Tightly Coupled Memory Size"
rgroup.long 0x58++0x03
line.long 0x00 "CP1CFG3,Processor 1 Configuration 3"
bitfld.long 0x00 4. "CPY,Cryptography" "0: Does not support,1: Supports"
bitfld.long 0x00 3. "CMP,Core Memory Protection Unit" "0: Does not include,1: Includes"
newline
bitfld.long 0x00 2. "MMU,Memory Management Unit" "0: Does not support,1: Supports"
bitfld.long 0x00 1. "SIMD,SIMD And NEON Instruction Support" "0: Does not include,1: Includes"
newline
bitfld.long 0x00 0. "HW_FPU,Floating Point Unit" "0: Does not support,1: HW_FPU_1"
rgroup.long 0x60++0x03
line.long 0x00 "CP2TYPE,Processor 2 Type"
hexmask.long 0x00 0.--31. 1. "PERSONALITY,Personality Processor"
rgroup.long 0x64++0x03
line.long 0x00 "CP2NUM,Processor 2 Number"
bitfld.long 0x00 0.--1. "CPN,Logical Processor Number" "0,1,2,3"
rgroup.long 0x68++0x03
line.long 0x00 "CP2REV,Processor 2 Count"
hexmask.long.byte 0x00 0.--7. 1. "RYPZ,Processor Revision"
rgroup.long 0x6C++0x03
line.long 0x00 "CP2CFG0,Processor 2 Configuration 0"
hexmask.long.byte 0x00 24.--31. 1. "ICSZ,L1 Instruction Cache Size"
hexmask.long.byte 0x00 16.--23. 1. "ICWY,L1 Instruction Cache Ways"
newline
hexmask.long.byte 0x00 8.--15. 1. "DCSZ,L1 Data Cache Size"
hexmask.long.byte 0x00 0.--7. 1. "DCWY,L1 Data Cache Ways"
rgroup.long 0x70++0x03
line.long 0x00 "CP2CFG1,Processor 2 Configuration 1"
hexmask.long.byte 0x00 24.--31. 1. "L2SZ,L2 Cache Size"
hexmask.long.byte 0x00 16.--23. 1. "L2WY,L2 Cache Ways"
rgroup.long 0x74++0x03
line.long 0x00 "CP2CFG2,Processor 2 Configuration 2"
hexmask.long.byte 0x00 24.--31. 1. "DTCMSZ,Data Tightly Coupled Memory Size"
hexmask.long.byte 0x00 16.--23. 1. "ITCMSZ,Instruction Tightly Coupled Memory Size"
rgroup.long 0x78++0x03
line.long 0x00 "CP2CFG3,Processor 2 Configuration 3"
bitfld.long 0x00 4. "CPY,Cryptography" "0: Does not support,1: Supports"
bitfld.long 0x00 3. "CMP,Core Memory Protection Unit" "0: Does not include,1: Includes"
newline
bitfld.long 0x00 2. "MMU,Memory Management Unit" "0: Does not support,1: Supports"
bitfld.long 0x00 1. "SIMD,SIMD And NEON Instruction Support" "0: Does not include,1: Includes"
newline
bitfld.long 0x00 0. "HW_FPU,Floating Point Unit" "0: Does not support,1: HW_FPU_1"
group.long 0x200++0x03
line.long 0x00 "IRCP0ISR0,Interrupt Router CP0 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x204++0x03
line.long 0x00 "IRCP0IGR0,Interrupt Router CP0 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x208++0x03
line.long 0x00 "IRCP0ISR1,Interrupt Router CP0 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x20C++0x03
line.long 0x00 "IRCP0IGR1,Interrupt Router CP0 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x210++0x03
line.long 0x00 "IRCP0ISR2,Interrupt Router CP0 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x214++0x03
line.long 0x00 "IRCP0IGR2,Interrupt Router CP0 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x218++0x03
line.long 0x00 "IRCP0ISR3,Interrupt Router CP0 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x21C++0x03
line.long 0x00 "IRCP0IGR3,Interrupt Router CP0 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x220++0x03
line.long 0x00 "IRCP1ISR0,Interrupt Router CP1 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x224++0x03
line.long 0x00 "IRCP1IGR0,Interrupt Router CP1 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x228++0x03
line.long 0x00 "IRCP1ISR1,Interrupt Router CP1 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x22C++0x03
line.long 0x00 "IRCP1IGR1,Interrupt Router CP1 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x230++0x03
line.long 0x00 "IRCP1ISR2,Interrupt Router CP1 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x234++0x03
line.long 0x00 "IRCP1IGR2,Interrupt Router CP1 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x238++0x03
line.long 0x00 "IRCP1ISR3,Interrupt Router CP1 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x23C++0x03
line.long 0x00 "IRCP1IGR3,Interrupt Router CP1 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x240++0x03
line.long 0x00 "IRCP2ISR0,Interrupt Router CP2 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x244++0x03
line.long 0x00 "IRCP2IGR0,Interrupt Router CP2 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x248++0x03
line.long 0x00 "IRCP2ISR1,Interrupt Router CP2 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x24C++0x03
line.long 0x00 "IRCP2IGR1,Interrupt Router CP2 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x250++0x03
line.long 0x00 "IRCP2ISR2,Interrupt Router CP2 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x254++0x03
line.long 0x00 "IRCP2IGR2,Interrupt Router CP2 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x258++0x03
line.long 0x00 "IRCP2ISR3,Interrupt Router CP2 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x25C++0x03
line.long 0x00 "IRCP2IGR3,Interrupt Router CP2 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x260++0x03
line.long 0x00 "IRCP3ISR0,Interrupt Router CP3 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x264++0x03
line.long 0x00 "IRCP3IGR0,Interrupt Router CP3 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x268++0x03
line.long 0x00 "IRCP3ISR1,Interrupt Router CP3 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x26C++0x03
line.long 0x00 "IRCP3IGR1,Interrupt Router CP3 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x270++0x03
line.long 0x00 "IRCP3ISR2,Interrupt Router CP3 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x274++0x03
line.long 0x00 "IRCP3IGR2,Interrupt Router CP3 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x278++0x03
line.long 0x00 "IRCP3ISR3,Interrupt Router CP3 Interrupt Status"
eventfld.long 0x00 3. "CP3_INT,CP3-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 2. "CP2_INT,CP2-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
newline
eventfld.long 0x00 1. "CP1_INT,CP1-to-CPn Interrupt" "0: No interrupt is asserted to CPn,1: Interrupt to CPn is asserted"
eventfld.long 0x00 0. "CP0_INT,CP0-to-CPn Interrupt" "0: No interrupt asserted to CPn,1: Interrupt to CPn asserted"
group.long 0x27C++0x03
line.long 0x00 "IRCP3IGR3,Interrupt Router CP3 Interrupt Generation"
bitfld.long 0x00 0. "INT_EN,Interrupt Enable" "0,1"
group.long 0x400++0x03
line.long 0x00 "IRCPCFG,Interrupt Router Configuration"
bitfld.long 0x00 31. "LOCK,Lock" "0: Register can be written by any privileged,1: Register is locked (read-only) until the next.."
bitfld.long 0x00 3. "CP3_TR,CP3 As Trusted Core" "0: Not trusted,1: CP3_TR_1"
newline
bitfld.long 0x00 2. "CP2_TR,CP2 As Trusted Core" "0: Not trusted,1: CP2_TR_1"
bitfld.long 0x00 1. "CP1_TR,CP1 As Trusted Core" "0: Not trusted,1: CP1_TR_1"
newline
bitfld.long 0x00 0. "CP0_TR,CP0 As Trusted Core" "0: Not trusted,1: CP0_TR_1"
group.long 0x600++0x03
line.long 0x00 "ENEDC0,Read Data Check Enable"
bitfld.long 0x00 12. "APP2RTPRAM,Application To Realtime PRAM" "0: APP2RTPRAM_0,1: APP2RTPRAM_1"
bitfld.long 0x00 11. "APP2RTPERIPH,Application To Realtime Peripheral" "0: APP2RTPERIPH_0,1: APP2RTPERIPH_1"
newline
bitfld.long 0x00 10. "DEBUG,Debug Master Read Data Check" "0: Disables,1: DEBUG_1"
bitfld.long 0x00 9. "STAM,STAM Read Data Check" "0: Disables,1: Enables"
newline
bitfld.long 0x00 8. "TCM,TCM Read Data Check" "0: Disables,1: Enables"
bitfld.long 0x00 7. "CM7_1_AHBP,AHBP Read Data Check For Cortex-M7_1" "0: CM7_1_AHBP_0,1: CM7_1_AHBP_1"
newline
bitfld.long 0x00 6. "CM7_1_AHBM,AHBM Read Data Check For Cortex-M7_1" "0: CM7_1_AHBM_0,1: CM7_1_AHBM_1"
bitfld.long 0x00 5. "ENET,ENET Read Data Check" "0: Disables,1: Enables"
newline
bitfld.long 0x00 4. "HSE,HSE_M Read Data Check" "0: Disables,1: Enables"
bitfld.long 0x00 3. "APP2RT,APP2RT Read Data Check" "0: APP2RT_0,1: APP2RT_1"
newline
bitfld.long 0x00 2. "eDMA,eDMA Read Data Check" "0: Disables,1: Enables"
bitfld.long 0x00 1. "CM7_0_AHBP,AHBP Read Data Check For Cortex-M7_0" "0: CM7_0_AHBP_0,1: CM7_0_AHBP_1"
newline
bitfld.long 0x00 0. "CM7_0_AHBM,AHBM Read Data Check For Cortex-M7_0" "0: CM7_0_AHBM_0,1: CM7_0_AHBM_1"
group.long 0x604++0x03
line.long 0x00 "ENEDC1,Write Data Check Enable"
bitfld.long 0x00 17. "DEBUG,Debug Slave Write Data Check" "0: Disables,1: DEBUG_1"
bitfld.long 0x00 16. "CM7_1_TCM,Cortex-M7_1_TCM Write Data Check" "0: CM7_1_TCM_0,1: CM7_1_TCM_1"
newline
bitfld.long 0x00 15. "CM7_0_TCM,Cortex-M7_0_TCM Write Data Check" "0: CM7_0_TCM_0,1: CM7_0_TCM_1"
bitfld.long 0x00 14. "AIPS2,AIPS2 Write Data Check" "0: Disables,1: AIPS2_1"
newline
bitfld.long 0x00 13. "AIPS1,AIPS1 Write Data Check" "0: Disables,1: AIPS1_1"
bitfld.long 0x00 12. "AIPS0,AIPS0 Write Data Check" "0: Disables,1: AIPS0_1"
newline
bitfld.long 0x00 11. "RT2APP,RT2APP Write Data Check" "0: RT2APP_0,1: RT2APP_1"
bitfld.long 0x00 10. "QSPI,QuadSPI Write Data Check" "0: Disables,1: Enables"
newline
bitfld.long 0x00 9. "TCM,TCM Write Data Check" "0: Disables,1: Enables"
bitfld.long 0x00 8. "PRAM8,PRAM8 Write Data Check" "0: Disables,1: PRAM8_1"
newline
bitfld.long 0x00 7. "PRAM7,PRAM7 Write Data Check" "0: Disables,1: PRAM7_1"
bitfld.long 0x00 6. "PRAM6,PRAM6 Write Data Check" "0: Disables,1: PRAM6_1"
newline
bitfld.long 0x00 5. "PRAM5,PRAM5 Write Data Check" "0: Disables,1: PRAM5_1"
bitfld.long 0x00 4. "PRAM4,PRAM4 Write Data Check" "0: Disables,1: PRAM4_1"
newline
bitfld.long 0x00 3. "PRAM3,PRAM3 Write Data Check" "0: Disables,1: PRAM3_1"
bitfld.long 0x00 2. "PRAM2,PRAM2 Write Data Check" "0: Disables,1: PRAM2_1"
newline
bitfld.long 0x00 1. "PRAM1,PRAM1 Write Data Check" "0: Disables,1: PRAM1_1"
bitfld.long 0x00 0. "PRAM0,PRAM0 Write Data Check" "0: Disables,1: PRAM0_1"
group.long 0x608++0x03
line.long 0x00 "ENEDC2,Address Check Enable"
bitfld.long 0x00 25. "PERIPH_2_MAIN,Peripheral AXBS To Main AXBS Address Check" "0: PERIPH_2_MAIN_0,1: PERIPH_2_MAIN_1"
bitfld.long 0x00 24. "MAIN_2_PERIPH,Main AXBS To Peripheral AXBS Address Check" "0: MAIN_2_PERIPH_0,1: MAIN_2_PERIPH_1"
newline
bitfld.long 0x00 23. "DMA_S1,DMA AXBS Slave1 Address Check" "0: DMA_S1_0,1: DMA_S1_1"
bitfld.long 0x00 22. "DMA_S0,DMA AXBS Slave0 Address Check" "0: DMA_S0_0,1: DMA_S0_1"
newline
bitfld.long 0x00 21. "PRAM_P3,PRAM AHB Port3 Address Check" "0: PRAM_P3_0,1: PRAM_P3_1"
bitfld.long 0x00 20. "PRAM_P2,PRAM AHB Port2 Address Check" "0: PRAM_P2_0,1: PRAM_P2_1"
newline
bitfld.long 0x00 19. "PRAM_P1,PRAM AHB Port1 Address Check" "0: PRAM_P1_0,1: PRAM_P1_1"
bitfld.long 0x00 18. "PRAM_P0,PRAM AHB Port0 Address Check" "0: PRAM_P0_0,1: PRAM_P0_1"
newline
bitfld.long 0x00 17. "DEBUG,Debug Slave Address Check" "0: Disables,1: DEBUG_1"
bitfld.long 0x00 16. "CM7_1_TCM,Cortex-M7_1_TCM Address Check" "0: CM7_1_TCM_0,1: CM7_1_TCM_1"
newline
bitfld.long 0x00 15. "CM7_0_TCM,Cortex-M7_0_TCM Address Check" "0: CM7_0_TCM_0,1: CM7_0_TCM_1"
bitfld.long 0x00 14. "AIPS2,AIPS2 Address Check" "0: Disables,1: AIPS2_1"
newline
bitfld.long 0x00 13. "AIPS1,AIPS1 Address Check" "0: Disables,1: AIPS1_1"
bitfld.long 0x00 12. "AIPS0,AIPS0 Address Check" "0: Disables,1: AIPS0_1"
newline
bitfld.long 0x00 11. "RT2APP,RT2APP Address Check" "0: RT2APP_0,1: RT2APP_1"
bitfld.long 0x00 10. "QSPI,QuadSPI Address Check" "0: Disables,1: Enables"
newline
bitfld.long 0x00 9. "TCM,TCM Address Check" "0: Disables,1: Enables"
bitfld.long 0x00 8. "PRAM8,PRAM8 Address Check" "0: Disables,1: PRAM8_1"
newline
bitfld.long 0x00 7. "PRAM7,PRAM7 Address Check" "0: Disables,1: PRAM7_1"
bitfld.long 0x00 6. "PRAM6,PRAM6 Address Check" "0: Disables,1: PRAM6_1"
newline
bitfld.long 0x00 5. "PRAM5,PRAM5 Address Check" "0: Disables,1: PRAM5_1"
bitfld.long 0x00 4. "PRAM4,PRAM4 Address Check" "0: Disables,1: PRAM4_1"
newline
bitfld.long 0x00 3. "PRAM3,PRAM3 Address Check" "0: Disables,1: PRAM3_1"
bitfld.long 0x00 2. "PRAM2,PRAM2 Address Check" "0: Disables,1: PRAM2_1"
newline
bitfld.long 0x00 1. "PRAM1,PRAM1 Address Check" "0: Disables,1: PRAM1_1"
bitfld.long 0x00 0. "PRAM0,PRAM0 Address Check" "0: Disables,1: PRAM0_1"
group.long 0x700++0x03
line.long 0x00 "IAHBCFGREG0,AHB Gasket Configuration 0"
bitfld.long 0x00 28. "PRAM0_DIS_WR_OPT,PRAM0 Disable Write Optimization" "0: PRAM0_DIS_WR_OPT_0,1: PRAM0_DIS_WR_OPT_1"
bitfld.long 0x00 24. "TCM_DIS_WR_OPT,TCM Disable Write Optimization" "0: TCM_DIS_WR_OPT_0,1: TCM_DIS_WR_OPT_1"
newline
bitfld.long 0x00 20. "DBG_MSTR_DIS_WR_OPT,Debug Master Disable Write Optimization" "0: DBG_MSTR_DIS_WR_OPT_0,1: DBG_MSTR_DIS_WR_OPT_1"
bitfld.long 0x00 16. "STAM_DIS_WR_OPT,STAM Disable Write Optimization" "0: STAM_DIS_WR_OPT_0,1: STAM_DIS_WR_OPT_1"
newline
bitfld.long 0x00 12. "HSE_DIS_WR_OPT,HSE_M Disable Write Optimization" "0: HSE_DIS_WR_OPT_0,1: HSE_DIS_WR_OPT_1"
bitfld.long 0x00 8. "DMA_AXBS_S1_DIS_WR_OPT,DMA AXBS S1 Disable Write Optimization" "0: DMA_AXBS_S1_DIS_WR_OPT_0,1: DMA_AXBS_S1_DIS_WR_OPT_1"
newline
bitfld.long 0x00 4. "DMA_AXBS_S0_DIS_WR_OPT,DMA AXBS S0 Disable Write Optimization" "0: DMA_AXBS_S0_DIS_WR_OPT_0,1: DMA_AXBS_S0_DIS_WR_OPT_1"
bitfld.long 0x00 0. "ENET_DIS_WR_OPT,ENET Disable Write Optimization" "0: ENET_DIS_WR_OPT_0,1: ENET_DIS_WR_OPT_1"
group.long 0x704++0x03
line.long 0x00 "IAHBCFGREG1,AHB Gasket Configuration 1"
bitfld.long 0x00 28. "AIPS2_DIS_WR_OPT,AIPS2 Disable Write Optimization" "0: AIPS2_DIS_WR_OPT_0,1: AIPS2_DIS_WR_OPT_1"
bitfld.long 0x00 24. "AIPS1_DIS_WR_OPT,AIPS1 Disable Write Optimization" "0: AIPS1_DIS_WR_OPT_0,1: AIPS1_DIS_WR_OPT_1"
newline
bitfld.long 0x00 20. "AIPS0_DIS_WR_OPT,AIPS0 Disable Write Optimization" "0: AIPS0_DIS_WR_OPT_0,1: AIPS0_DIS_WR_OPT_1"
bitfld.long 0x00 16. "QSPI_DIS_WR_OPT,QuadSPI Disable Write Optimization" "0: QSPI_DIS_WR_OPT_0,1: QSPI_DIS_WR_OPT_1"
newline
bitfld.long 0x00 12. "DBG_SLV_DIS_WR_OPT,Debug Slave Disable Write Optimization" "0: DBG_SLV_DIS_WR_OPT_0,1: DBG_SLV_DIS_WR_OPT_1"
bitfld.long 0x00 8. "PRAM3_DIS_WR_OPT,PRAM3 Disable Write Optimization" "0: PRAM3_DIS_WR_OPT_0,1: PRAM3_DIS_WR_OPT_1"
newline
bitfld.long 0x00 4. "PRAM2_DIS_WR_OPT,PRAM2 Disable Write Optimization" "0: PRAM2_DIS_WR_OPT_0,1: PRAM2_DIS_WR_OPT_1"
bitfld.long 0x00 0. "PRAM1_DIS_WR_OPT,PRAM1 Disable Write Optimization" "0: PRAM1_DIS_WR_OPT_0,1: PRAM1_DIS_WR_OPT_1"
group.long 0x708++0x03
line.long 0x00 "IAHBCFGREG2,AHB Gasket Configuration 2"
bitfld.long 0x00 12. "CM7_1_AHBP_WR_DIS_OPT,Cortex-M7_1 AHBP Write Disable Optimization" "0: CM7_1_AHBP_WR_DIS_OPT_0,1: CM7_1_AHBP_WR_DIS_OPT_1"
bitfld.long 0x00 8. "CM7_0_AHBP_WR_DIS_OPT,Cortex-M7_0 AHBP Write Disable Optimization" "0: CM7_0_AHBP_WR_DIS_OPT_0,1: CM7_0_AHBP_WR_DIS_OPT_1"
newline
bitfld.long 0x00 4. "P2M_AXBS_DIS_WR_OPT,P2M AXBS Disable Write Optimization" "0: P2M_AXBS_DIS_WR_OPT_0,1: P2M_AXBS_DIS_WR_OPT_1"
bitfld.long 0x00 0. "M2P_AXBS_DIS_WR_OPT,M2P AXBS Disable Write Optimization" "0: M2P_AXBS_DIS_WR_OPT_0,1: M2P_AXBS_DIS_WR_OPT_1"
group.long 0x800++0x03
line.long 0x00 "IRNMIC,Interrupt Router Non-Maskable Interrupt Control Register"
bitfld.long 0x00 2. "CP2_NMI0_EN,CP2 NMI0 Enable" "0: Enables,1: Disables"
bitfld.long 0x00 1. "CP1_NMI_EN,CP1 NMI Enable" "0: Disables,1: Enables"
newline
bitfld.long 0x00 0. "CP0_NMI_EN,CP0 NMI Enable" "0: Disables,1: Enables"
repeat 240. (increment 0 1) (increment 0 0x02)
group.word ($2+0x880)++0x01
line.word 0x00 "IRSPRC[$1],Interrupt Router Shared Peripheral Routing Control $1"
bitfld.word 0x00 15. "LOCK,Lock" "0: Writes to this register allowed,1: Writes to this register ignored"
bitfld.word 0x00 3. "BBE32_SPT,Enable BBE32 SPT Interrupt Request" "0: BBE32_SPT_0,1: BBE32_SPT_1"
newline
bitfld.word 0x00 2. "CA53,Enable Cortex-A53 Interrupt Steering" "0: Disables,1: Enables"
bitfld.word 0x00 1. "M7_1,Enable Cortex-M7_1 Interrupt Steering" "0: Disables,1: Enables"
newline
bitfld.word 0x00 0. "M7_0,Enable Cortex-M7_0 Interrupt Steering" "0: Disables,1: Enables"
repeat.end
tree.end
tree "MU (MUA)"
tree "MU0__MUA"
base ad:0x23258000
rgroup.long 0x00++0x03
line.long 0x00 "VER,Version ID"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
newline
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Set Number"
rgroup.long 0x04++0x03
line.long 0x00 "PAR,Parameter Register"
hexmask.long.byte 0x00 24.--31. 1. "FLAG_WIDTH,Flag Width"
hexmask.long.byte 0x00 16.--23. 1. "GIR_NUM,General-purpose Interrupt Request Number"
newline
hexmask.long.byte 0x00 8.--15. 1. "RR_NUM,Receive Register Number"
hexmask.long.byte 0x00 0.--7. 1. "TR_NUM,Transmit Register Number"
group.long 0x08++0x03
line.long 0x00 "CR,Control Register"
bitfld.long 0x00 0. "MUR,MU Reset" "0: zero,1: Reset"
rgroup.long 0x0C++0x03
line.long 0x00 "SR,Status Register"
bitfld.long 0x00 6. "RFP,MUA Receive Full Pending Flag" "0: Not pending,1: Pending"
bitfld.long 0x00 5. "TEP,MUA Transmit Empty Pending" "0: Not pending,1: Pending"
newline
bitfld.long 0x00 4. "GIRP,MUA General-purpose Interrupt Pending" "0: No request sent,1: Request sent"
bitfld.long 0x00 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)"
newline
bitfld.long 0x00 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending"
bitfld.long 0x00 0. "MURS,MUA and MUB Reset State" "0: MUA and MUB are out of reset state,1: MUA or MUB is in reset state"
group.long 0x10++0x03
line.long 0x00 "CCR0,Core Control Register 0"
bitfld.long 0x00 0. "NMI,MUB Non-maskable Interrupt Request" "0: Non-maskable interrupt issued,1: Non-maskable interrupt not issued"
group.long 0x18++0x03
line.long 0x00 "CSSR0,Core Sticky Status Register 0"
eventfld.long 0x00 0. "NMIC,Processor A Non-Maskable-Interrupt Clear" "0: Default,1: Clear MUB_CCR0[NMI]"
group.long 0x100++0x03
line.long 0x00 "FCR,Flag Control Register"
bitfld.long 0x00 31. "F31,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 30. "F30,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 29. "F29,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 28. "F28,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 27. "F27,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 26. "F26,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 25. "F25,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 24. "F24,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 23. "F23,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 22. "F22,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 21. "F21,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 20. "F20,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 19. "F19,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 18. "F18,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 17. "F17,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 16. "F16,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 15. "F15,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 14. "F14,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 13. "F13,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 12. "F12,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 11. "F11,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 10. "F10,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 9. "F9,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 8. "F8,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 7. "F7,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 6. "F6,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 5. "F5,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 4. "F4,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 3. "F3,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
rgroup.long 0x104++0x03
line.long 0x00 "FSR,Flag Status Register"
bitfld.long 0x00 31. "F31,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 30. "F30,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 29. "F29,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 28. "F28,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 27. "F27,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 26. "F26,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 25. "F25,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 24. "F24,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 23. "F23,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 22. "F22,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 21. "F21,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 20. "F20,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 19. "F19,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 18. "F18,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 17. "F17,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 16. "F16,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 15. "F15,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 14. "F14,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 13. "F13,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 12. "F12,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 11. "F11,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 10. "F10,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 9. "F9,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 8. "F8,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 7. "F7,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 6. "F6,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 5. "F5,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 4. "F4,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 3. "F3,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
group.long 0x110++0x03
line.long 0x00 "GIER,General-purpose Interrupt Enable Register"
bitfld.long 0x00 31. "GIE31,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 30. "GIE30,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 29. "GIE29,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 28. "GIE28,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 27. "GIE27,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 26. "GIE26,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 25. "GIE25,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 24. "GIE24,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 23. "GIE23,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 22. "GIE22,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 21. "GIE21,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 20. "GIE20,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 19. "GIE19,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 18. "GIE18,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 17. "GIE17,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 16. "GIE16,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 15. "GIE15,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 14. "GIE14,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 13. "GIE13,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 12. "GIE12,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 11. "GIE11,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 10. "GIE10,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 9. "GIE9,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 8. "GIE8,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 7. "GIE7,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 6. "GIE6,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 5. "GIE5,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 4. "GIE4,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 3. "GIE3,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 2. "GIE2,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 1. "GIE1,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
group.long 0x114++0x03
line.long 0x00 "GCR,General-purpose Control Register"
bitfld.long 0x00 31. "GIR31,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 30. "GIR30,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 29. "GIR29,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 28. "GIR28,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 27. "GIR27,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 26. "GIR26,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 25. "GIR25,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 24. "GIR24,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 23. "GIR23,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 22. "GIR22,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 21. "GIR21,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 20. "GIR20,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 19. "GIR19,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 18. "GIR18,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 17. "GIR17,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 16. "GIR16,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 15. "GIR15,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 14. "GIR14,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 13. "GIR13,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 12. "GIR12,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 11. "GIR11,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 10. "GIR10,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 9. "GIR9,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 8. "GIR8,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 7. "GIR7,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 6. "GIR6,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 5. "GIR5,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 4. "GIR4,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 3. "GIR3,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 2. "GIR2,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 1. "GIR1,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 0. "GIR0,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
group.long 0x118++0x03
line.long 0x00 "GSR,General-purpose Status Register"
eventfld.long 0x00 31. "GIP31,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 30. "GIP30,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 29. "GIP29,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 28. "GIP28,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 27. "GIP27,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 26. "GIP26,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 25. "GIP25,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 24. "GIP24,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 23. "GIP23,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 22. "GIP22,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 21. "GIP21,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 20. "GIP20,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 19. "GIP19,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 18. "GIP18,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 17. "GIP17,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 16. "GIP16,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 15. "GIP15,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 14. "GIP14,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 13. "GIP13,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 12. "GIP12,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 11. "GIP11,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 10. "GIP10,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 9. "GIP9,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 8. "GIP8,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 7. "GIP7,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 6. "GIP6,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 5. "GIP5,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 4. "GIP4,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 3. "GIP3,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 2. "GIP2,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 1. "GIP1,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
group.long 0x120++0x03
line.long 0x00 "TCR,Transmit Control Register"
bitfld.long 0x00 15. "TIE15,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 14. "TIE14,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 13. "TIE13,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 12. "TIE12,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 11. "TIE11,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 10. "TIE10,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 9. "TIE9,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 8. "TIE8,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 7. "TIE7,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 6. "TIE6,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 5. "TIE5,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 4. "TIE4,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
rgroup.long 0x124++0x03
line.long 0x00 "TSR,Transmit Status Register"
bitfld.long 0x00 15. "TE15,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 14. "TE14,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 13. "TE13,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 12. "TE12,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 11. "TE11,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 10. "TE10,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 9. "TE9,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 8. "TE8,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 7. "TE7,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 6. "TE6,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 5. "TE5,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 4. "TE4,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 3. "TE3,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 2. "TE2,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 1. "TE1,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 0. "TE0,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
group.long 0x128++0x03
line.long 0x00 "RCR,Receive Control Register"
bitfld.long 0x00 15. "RIE15,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 14. "RIE14,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 13. "RIE13,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 12. "RIE12,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 11. "RIE11,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 10. "RIE10,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 9. "RIE9,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 8. "RIE8,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 7. "RIE7,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 6. "RIE6,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 5. "RIE5,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 4. "RIE4,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
rgroup.long 0x12C++0x03
line.long 0x00 "RSR,Receive Status Register"
bitfld.long 0x00 15. "RF15,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 14. "RF14,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 13. "RF13,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 12. "RF12,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 11. "RF11,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 10. "RF10,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 9. "RF9,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 8. "RF8,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 7. "RF7,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 6. "RF6,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 5. "RF5,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 4. "RF4,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 3. "RF3,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 2. "RF2,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 1. "RF1,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 0. "RF0,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "TR[$1],Transmit Register $1"
hexmask.long 0x00 0.--31. 1. "TR_DATA,MUA Transmit Data"
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x280)++0x03
line.long 0x00 "RR[$1],Receive Register $1"
hexmask.long 0x00 0.--31. 1. "RR_DATA,MUA Receive Data"
repeat.end
tree.end
tree "MU0__MUB"
base ad:0x40134000
rgroup.long 0x00++0x03
line.long 0x00 "VER,Version ID"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
newline
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Set Number"
rgroup.long 0x04++0x03
line.long 0x00 "PAR,Parameter Register"
hexmask.long.byte 0x00 24.--31. 1. "FLAG_WIDTH,Flag Width"
hexmask.long.byte 0x00 16.--23. 1. "GIR_NUM,General-purpose Interrupt Request Number"
newline
hexmask.long.byte 0x00 8.--15. 1. "RR_NUM,Receive Register Number"
hexmask.long.byte 0x00 0.--7. 1. "TR_NUM,Transmit Register Number"
group.long 0x08++0x03
line.long 0x00 "CR,Control Register"
bitfld.long 0x00 0. "MUR,MU Reset" "0: zero,1: Reset"
rgroup.long 0x0C++0x03
line.long 0x00 "SR,Status Register"
bitfld.long 0x00 6. "RFP,MUA Receive Full Pending Flag" "0: Not pending,1: Pending"
bitfld.long 0x00 5. "TEP,MUA Transmit Empty Pending" "0: Not pending,1: Pending"
newline
bitfld.long 0x00 4. "GIRP,MUA General-purpose Interrupt Pending" "0: No request sent,1: Request sent"
bitfld.long 0x00 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)"
newline
bitfld.long 0x00 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending"
bitfld.long 0x00 0. "MURS,MUA and MUB Reset State" "0: MUA and MUB are out of reset state,1: MUA or MUB is in reset state"
group.long 0x10++0x03
line.long 0x00 "CCR0,Core Control Register 0"
bitfld.long 0x00 0. "NMI,MUB Non-maskable Interrupt Request" "0: Non-maskable interrupt issued,1: Non-maskable interrupt not issued"
group.long 0x18++0x03
line.long 0x00 "CSSR0,Core Sticky Status Register 0"
eventfld.long 0x00 0. "NMIC,Processor A Non-Maskable-Interrupt Clear" "0: Default,1: Clear MUB_CCR0[NMI]"
group.long 0x100++0x03
line.long 0x00 "FCR,Flag Control Register"
bitfld.long 0x00 31. "F31,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 30. "F30,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 29. "F29,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 28. "F28,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 27. "F27,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 26. "F26,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 25. "F25,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 24. "F24,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 23. "F23,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 22. "F22,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 21. "F21,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 20. "F20,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 19. "F19,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 18. "F18,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 17. "F17,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 16. "F16,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 15. "F15,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 14. "F14,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 13. "F13,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 12. "F12,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 11. "F11,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 10. "F10,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 9. "F9,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 8. "F8,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 7. "F7,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 6. "F6,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 5. "F5,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 4. "F4,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 3. "F3,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
rgroup.long 0x104++0x03
line.long 0x00 "FSR,Flag Status Register"
bitfld.long 0x00 31. "F31,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 30. "F30,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 29. "F29,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 28. "F28,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 27. "F27,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 26. "F26,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 25. "F25,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 24. "F24,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 23. "F23,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 22. "F22,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 21. "F21,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 20. "F20,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 19. "F19,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 18. "F18,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 17. "F17,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 16. "F16,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 15. "F15,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 14. "F14,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 13. "F13,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 12. "F12,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 11. "F11,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 10. "F10,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 9. "F9,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 8. "F8,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 7. "F7,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 6. "F6,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 5. "F5,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 4. "F4,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 3. "F3,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
group.long 0x110++0x03
line.long 0x00 "GIER,General-purpose Interrupt Enable Register"
bitfld.long 0x00 31. "GIE31,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 30. "GIE30,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 29. "GIE29,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 28. "GIE28,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 27. "GIE27,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 26. "GIE26,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 25. "GIE25,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 24. "GIE24,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 23. "GIE23,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 22. "GIE22,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 21. "GIE21,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 20. "GIE20,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 19. "GIE19,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 18. "GIE18,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 17. "GIE17,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 16. "GIE16,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 15. "GIE15,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 14. "GIE14,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 13. "GIE13,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 12. "GIE12,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 11. "GIE11,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 10. "GIE10,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 9. "GIE9,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 8. "GIE8,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 7. "GIE7,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 6. "GIE6,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 5. "GIE5,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 4. "GIE4,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 3. "GIE3,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 2. "GIE2,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 1. "GIE1,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
group.long 0x114++0x03
line.long 0x00 "GCR,General-purpose Control Register"
bitfld.long 0x00 31. "GIR31,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 30. "GIR30,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 29. "GIR29,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 28. "GIR28,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 27. "GIR27,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 26. "GIR26,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 25. "GIR25,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 24. "GIR24,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 23. "GIR23,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 22. "GIR22,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 21. "GIR21,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 20. "GIR20,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 19. "GIR19,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 18. "GIR18,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 17. "GIR17,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 16. "GIR16,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 15. "GIR15,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 14. "GIR14,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 13. "GIR13,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 12. "GIR12,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 11. "GIR11,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 10. "GIR10,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 9. "GIR9,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 8. "GIR8,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 7. "GIR7,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 6. "GIR6,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 5. "GIR5,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 4. "GIR4,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 3. "GIR3,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 2. "GIR2,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 1. "GIR1,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 0. "GIR0,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
group.long 0x118++0x03
line.long 0x00 "GSR,General-purpose Status Register"
eventfld.long 0x00 31. "GIP31,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 30. "GIP30,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 29. "GIP29,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 28. "GIP28,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 27. "GIP27,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 26. "GIP26,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 25. "GIP25,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 24. "GIP24,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 23. "GIP23,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 22. "GIP22,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 21. "GIP21,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 20. "GIP20,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 19. "GIP19,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 18. "GIP18,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 17. "GIP17,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 16. "GIP16,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 15. "GIP15,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 14. "GIP14,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 13. "GIP13,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 12. "GIP12,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 11. "GIP11,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 10. "GIP10,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 9. "GIP9,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 8. "GIP8,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 7. "GIP7,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 6. "GIP6,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 5. "GIP5,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 4. "GIP4,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 3. "GIP3,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 2. "GIP2,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 1. "GIP1,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
group.long 0x120++0x03
line.long 0x00 "TCR,Transmit Control Register"
bitfld.long 0x00 15. "TIE15,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 14. "TIE14,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 13. "TIE13,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 12. "TIE12,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 11. "TIE11,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 10. "TIE10,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 9. "TIE9,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 8. "TIE8,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 7. "TIE7,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 6. "TIE6,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 5. "TIE5,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 4. "TIE4,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
rgroup.long 0x124++0x03
line.long 0x00 "TSR,Transmit Status Register"
bitfld.long 0x00 15. "TE15,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 14. "TE14,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 13. "TE13,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 12. "TE12,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 11. "TE11,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 10. "TE10,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 9. "TE9,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 8. "TE8,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 7. "TE7,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 6. "TE6,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 5. "TE5,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 4. "TE4,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 3. "TE3,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 2. "TE2,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 1. "TE1,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 0. "TE0,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
group.long 0x128++0x03
line.long 0x00 "RCR,Receive Control Register"
bitfld.long 0x00 15. "RIE15,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 14. "RIE14,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 13. "RIE13,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 12. "RIE12,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 11. "RIE11,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 10. "RIE10,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 9. "RIE9,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 8. "RIE8,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 7. "RIE7,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 6. "RIE6,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 5. "RIE5,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 4. "RIE4,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
rgroup.long 0x12C++0x03
line.long 0x00 "RSR,Receive Status Register"
bitfld.long 0x00 15. "RF15,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 14. "RF14,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 13. "RF13,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 12. "RF12,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 11. "RF11,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 10. "RF10,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 9. "RF9,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 8. "RF8,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 7. "RF7,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 6. "RF6,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 5. "RF5,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 4. "RF4,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 3. "RF3,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 2. "RF2,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 1. "RF1,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 0. "RF0,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "TR[$1],Transmit Register $1"
hexmask.long 0x00 0.--31. 1. "TR_DATA,MUA Transmit Data"
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x280)++0x03
line.long 0x00 "RR[$1],Receive Register $1"
hexmask.long 0x00 0.--31. 1. "RR_DATA,MUA Receive Data"
repeat.end
tree.end
tree "MU1__MUA"
base ad:0x23259000
rgroup.long 0x00++0x03
line.long 0x00 "VER,Version ID"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
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hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Set Number"
rgroup.long 0x04++0x03
line.long 0x00 "PAR,Parameter Register"
hexmask.long.byte 0x00 24.--31. 1. "FLAG_WIDTH,Flag Width"
hexmask.long.byte 0x00 16.--23. 1. "GIR_NUM,General-purpose Interrupt Request Number"
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hexmask.long.byte 0x00 8.--15. 1. "RR_NUM,Receive Register Number"
hexmask.long.byte 0x00 0.--7. 1. "TR_NUM,Transmit Register Number"
group.long 0x08++0x03
line.long 0x00 "CR,Control Register"
bitfld.long 0x00 0. "MUR,MU Reset" "0: zero,1: Reset"
rgroup.long 0x0C++0x03
line.long 0x00 "SR,Status Register"
bitfld.long 0x00 6. "RFP,MUA Receive Full Pending Flag" "0: Not pending,1: Pending"
bitfld.long 0x00 5. "TEP,MUA Transmit Empty Pending" "0: Not pending,1: Pending"
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bitfld.long 0x00 4. "GIRP,MUA General-purpose Interrupt Pending" "0: No request sent,1: Request sent"
bitfld.long 0x00 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)"
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bitfld.long 0x00 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending"
bitfld.long 0x00 0. "MURS,MUA and MUB Reset State" "0: MUA and MUB are out of reset state,1: MUA or MUB is in reset state"
group.long 0x10++0x03
line.long 0x00 "CCR0,Core Control Register 0"
bitfld.long 0x00 0. "NMI,MUB Non-maskable Interrupt Request" "0: Non-maskable interrupt issued,1: Non-maskable interrupt not issued"
group.long 0x18++0x03
line.long 0x00 "CSSR0,Core Sticky Status Register 0"
eventfld.long 0x00 0. "NMIC,Processor A Non-Maskable-Interrupt Clear" "0: Default,1: Clear MUB_CCR0[NMI]"
group.long 0x100++0x03
line.long 0x00 "FCR,Flag Control Register"
bitfld.long 0x00 31. "F31,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 30. "F30,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
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bitfld.long 0x00 29. "F29,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 28. "F28,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 27. "F27,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 26. "F26,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 25. "F25,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 24. "F24,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 23. "F23,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 22. "F22,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 21. "F21,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 20. "F20,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 19. "F19,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 18. "F18,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 17. "F17,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 16. "F16,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 15. "F15,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 14. "F14,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 13. "F13,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 12. "F12,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 11. "F11,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 10. "F10,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 9. "F9,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 8. "F8,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 7. "F7,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 6. "F6,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 5. "F5,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 4. "F4,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 3. "F3,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
rgroup.long 0x104++0x03
line.long 0x00 "FSR,Flag Status Register"
bitfld.long 0x00 31. "F31,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 30. "F30,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 29. "F29,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 28. "F28,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 27. "F27,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 26. "F26,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 25. "F25,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 24. "F24,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 23. "F23,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 22. "F22,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 21. "F21,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 20. "F20,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
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bitfld.long 0x00 19. "F19,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 18. "F18,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
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bitfld.long 0x00 17. "F17,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 16. "F16,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 15. "F15,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 14. "F14,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 13. "F13,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 12. "F12,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 11. "F11,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 10. "F10,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 9. "F9,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 8. "F8,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 7. "F7,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 6. "F6,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 5. "F5,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 4. "F4,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 3. "F3,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
group.long 0x110++0x03
line.long 0x00 "GIER,General-purpose Interrupt Enable Register"
bitfld.long 0x00 31. "GIE31,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 30. "GIE30,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 29. "GIE29,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 28. "GIE28,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 27. "GIE27,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 26. "GIE26,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 25. "GIE25,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 24. "GIE24,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 23. "GIE23,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 22. "GIE22,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 21. "GIE21,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 20. "GIE20,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 19. "GIE19,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 18. "GIE18,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 17. "GIE17,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 16. "GIE16,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 15. "GIE15,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 14. "GIE14,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 13. "GIE13,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 12. "GIE12,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 11. "GIE11,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 10. "GIE10,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 9. "GIE9,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 8. "GIE8,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 7. "GIE7,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 6. "GIE6,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 5. "GIE5,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 4. "GIE4,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 3. "GIE3,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 2. "GIE2,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 1. "GIE1,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
group.long 0x114++0x03
line.long 0x00 "GCR,General-purpose Control Register"
bitfld.long 0x00 31. "GIR31,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 30. "GIR30,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 29. "GIR29,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 28. "GIR28,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 27. "GIR27,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 26. "GIR26,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 25. "GIR25,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 24. "GIR24,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 23. "GIR23,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 22. "GIR22,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 21. "GIR21,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 20. "GIR20,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 19. "GIR19,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 18. "GIR18,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 17. "GIR17,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 16. "GIR16,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 15. "GIR15,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 14. "GIR14,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 13. "GIR13,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 12. "GIR12,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 11. "GIR11,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 10. "GIR10,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 9. "GIR9,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 8. "GIR8,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 7. "GIR7,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 6. "GIR6,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 5. "GIR5,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 4. "GIR4,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 3. "GIR3,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 2. "GIR2,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 1. "GIR1,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 0. "GIR0,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
group.long 0x118++0x03
line.long 0x00 "GSR,General-purpose Status Register"
eventfld.long 0x00 31. "GIP31,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 30. "GIP30,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 29. "GIP29,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 28. "GIP28,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 27. "GIP27,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 26. "GIP26,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 25. "GIP25,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 24. "GIP24,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 23. "GIP23,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 22. "GIP22,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 21. "GIP21,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 20. "GIP20,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 19. "GIP19,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 18. "GIP18,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 17. "GIP17,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 16. "GIP16,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 15. "GIP15,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 14. "GIP14,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 13. "GIP13,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 12. "GIP12,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 11. "GIP11,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 10. "GIP10,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 9. "GIP9,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 8. "GIP8,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 7. "GIP7,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 6. "GIP6,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 5. "GIP5,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 4. "GIP4,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 3. "GIP3,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 2. "GIP2,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 1. "GIP1,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
group.long 0x120++0x03
line.long 0x00 "TCR,Transmit Control Register"
bitfld.long 0x00 15. "TIE15,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 14. "TIE14,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 13. "TIE13,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 12. "TIE12,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 11. "TIE11,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 10. "TIE10,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 9. "TIE9,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 8. "TIE8,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 7. "TIE7,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 6. "TIE6,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 5. "TIE5,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 4. "TIE4,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
rgroup.long 0x124++0x03
line.long 0x00 "TSR,Transmit Status Register"
bitfld.long 0x00 15. "TE15,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 14. "TE14,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 13. "TE13,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 12. "TE12,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 11. "TE11,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 10. "TE10,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 9. "TE9,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 8. "TE8,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 7. "TE7,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 6. "TE6,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 5. "TE5,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 4. "TE4,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 3. "TE3,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 2. "TE2,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 1. "TE1,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 0. "TE0,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
group.long 0x128++0x03
line.long 0x00 "RCR,Receive Control Register"
bitfld.long 0x00 15. "RIE15,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 14. "RIE14,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 13. "RIE13,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 12. "RIE12,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 11. "RIE11,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 10. "RIE10,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 9. "RIE9,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 8. "RIE8,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 7. "RIE7,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 6. "RIE6,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 5. "RIE5,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 4. "RIE4,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
rgroup.long 0x12C++0x03
line.long 0x00 "RSR,Receive Status Register"
bitfld.long 0x00 15. "RF15,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 14. "RF14,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 13. "RF13,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 12. "RF12,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 11. "RF11,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 10. "RF10,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 9. "RF9,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 8. "RF8,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 7. "RF7,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 6. "RF6,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 5. "RF5,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 4. "RF4,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 3. "RF3,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 2. "RF2,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 1. "RF1,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 0. "RF0,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "TR[$1],Transmit Register $1"
hexmask.long 0x00 0.--31. 1. "TR_DATA,MUA Transmit Data"
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x280)++0x03
line.long 0x00 "RR[$1],Receive Register $1"
hexmask.long 0x00 0.--31. 1. "RR_DATA,MUA Receive Data"
repeat.end
tree.end
tree "MU1__MUB"
base ad:0x40138000
rgroup.long 0x00++0x03
line.long 0x00 "VER,Version ID"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
newline
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Set Number"
rgroup.long 0x04++0x03
line.long 0x00 "PAR,Parameter Register"
hexmask.long.byte 0x00 24.--31. 1. "FLAG_WIDTH,Flag Width"
hexmask.long.byte 0x00 16.--23. 1. "GIR_NUM,General-purpose Interrupt Request Number"
newline
hexmask.long.byte 0x00 8.--15. 1. "RR_NUM,Receive Register Number"
hexmask.long.byte 0x00 0.--7. 1. "TR_NUM,Transmit Register Number"
group.long 0x08++0x03
line.long 0x00 "CR,Control Register"
bitfld.long 0x00 0. "MUR,MU Reset" "0: zero,1: Reset"
rgroup.long 0x0C++0x03
line.long 0x00 "SR,Status Register"
bitfld.long 0x00 6. "RFP,MUA Receive Full Pending Flag" "0: Not pending,1: Pending"
bitfld.long 0x00 5. "TEP,MUA Transmit Empty Pending" "0: Not pending,1: Pending"
newline
bitfld.long 0x00 4. "GIRP,MUA General-purpose Interrupt Pending" "0: No request sent,1: Request sent"
bitfld.long 0x00 3. "FUP,MUA Flags Update Pending" "0: No pending update flags (initiated by MUA),1: Pending update flags (initiated by MUA)"
newline
bitfld.long 0x00 2. "EP,MUA Side Event Pending" "0: Not pending,1: Pending"
bitfld.long 0x00 0. "MURS,MUA and MUB Reset State" "0: MUA and MUB are out of reset state,1: MUA or MUB is in reset state"
group.long 0x10++0x03
line.long 0x00 "CCR0,Core Control Register 0"
bitfld.long 0x00 0. "NMI,MUB Non-maskable Interrupt Request" "0: Non-maskable interrupt issued,1: Non-maskable interrupt not issued"
group.long 0x18++0x03
line.long 0x00 "CSSR0,Core Sticky Status Register 0"
eventfld.long 0x00 0. "NMIC,Processor A Non-Maskable-Interrupt Clear" "0: Default,1: Clear MUB_CCR0[NMI]"
group.long 0x100++0x03
line.long 0x00 "FCR,Flag Control Register"
bitfld.long 0x00 31. "F31,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 30. "F30,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 29. "F29,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 28. "F28,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 27. "F27,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 26. "F26,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 25. "F25,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 24. "F24,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 23. "F23,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 22. "F22,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 21. "F21,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 20. "F20,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 19. "F19,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 18. "F18,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 17. "F17,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 16. "F16,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 15. "F15,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 14. "F14,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 13. "F13,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 12. "F12,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 11. "F11,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 10. "F10,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 9. "F9,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 8. "F8,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 7. "F7,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 6. "F6,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 5. "F5,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 4. "F4,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 3. "F3,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 2. "F2,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
newline
bitfld.long 0x00 1. "F1,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
bitfld.long 0x00 0. "F0,MUA to MUB Flag n" "0: Clear MUB_FSR[Fn],1: Set MUB_FSR[Fn]"
rgroup.long 0x104++0x03
line.long 0x00 "FSR,Flag Status Register"
bitfld.long 0x00 31. "F31,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 30. "F30,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 29. "F29,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 28. "F28,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 27. "F27,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 26. "F26,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 25. "F25,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 24. "F24,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 23. "F23,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 22. "F22,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 21. "F21,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 20. "F20,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 19. "F19,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 18. "F18,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 17. "F17,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 16. "F16,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 15. "F15,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 14. "F14,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 13. "F13,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 12. "F12,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 11. "F11,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 10. "F10,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 9. "F9,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 8. "F8,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 7. "F7,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 6. "F6,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 5. "F5,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 4. "F4,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 3. "F3,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 2. "F2,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
newline
bitfld.long 0x00 1. "F1,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
bitfld.long 0x00 0. "F0,MUB to MUA-Side Flag n" "0: MUB_FCR[Fn] = 0,1: MUB_FCR[Fn] = 1"
group.long 0x110++0x03
line.long 0x00 "GIER,General-purpose Interrupt Enable Register"
bitfld.long 0x00 31. "GIE31,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 30. "GIE30,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 29. "GIE29,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 28. "GIE28,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 27. "GIE27,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 26. "GIE26,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 25. "GIE25,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 24. "GIE24,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 23. "GIE23,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 22. "GIE22,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 21. "GIE21,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 20. "GIE20,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 19. "GIE19,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 18. "GIE18,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 17. "GIE17,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 16. "GIE16,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 15. "GIE15,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 14. "GIE14,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 13. "GIE13,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 12. "GIE12,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 11. "GIE11,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 10. "GIE10,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 9. "GIE9,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 8. "GIE8,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 7. "GIE7,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 6. "GIE6,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 5. "GIE5,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 4. "GIE4,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 3. "GIE3,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 2. "GIE2,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 1. "GIE1,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 0. "GIE0,MUA General-purpose Interrupt Enable n" "0: Disable,1: Enable"
group.long 0x114++0x03
line.long 0x00 "GCR,General-purpose Control Register"
bitfld.long 0x00 31. "GIR31,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 30. "GIR30,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 29. "GIR29,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 28. "GIR28,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 27. "GIR27,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 26. "GIR26,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 25. "GIR25,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 24. "GIR24,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 23. "GIR23,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 22. "GIR22,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 21. "GIR21,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 20. "GIR20,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 19. "GIR19,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 18. "GIR18,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 17. "GIR17,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 16. "GIR16,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 15. "GIR15,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 14. "GIR14,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 13. "GIR13,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 12. "GIR12,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 11. "GIR11,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 10. "GIR10,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 9. "GIR9,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 8. "GIR8,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 7. "GIR7,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 6. "GIR6,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 5. "GIR5,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 4. "GIR4,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 3. "GIR3,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 2. "GIR2,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
newline
bitfld.long 0x00 1. "GIR1,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
bitfld.long 0x00 0. "GIR0,MUA General-purpose Interrupt Request n" "0: Not requested,1: Requested"
group.long 0x118++0x03
line.long 0x00 "GSR,General-purpose Status Register"
eventfld.long 0x00 31. "GIP31,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 30. "GIP30,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 29. "GIP29,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 28. "GIP28,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 27. "GIP27,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 26. "GIP26,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 25. "GIP25,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 24. "GIP24,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 23. "GIP23,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 22. "GIP22,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 21. "GIP21,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 20. "GIP20,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 19. "GIP19,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 18. "GIP18,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 17. "GIP17,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 16. "GIP16,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 15. "GIP15,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 14. "GIP14,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 13. "GIP13,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 12. "GIP12,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 11. "GIP11,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 10. "GIP10,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 9. "GIP9,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 8. "GIP8,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 7. "GIP7,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 6. "GIP6,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 5. "GIP5,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 4. "GIP4,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 3. "GIP3,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 2. "GIP2,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
newline
eventfld.long 0x00 1. "GIP1,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
eventfld.long 0x00 0. "GIP0,MUA General-purpose Interrupt Request Pending n" "0: Not pending,1: Pending"
group.long 0x120++0x03
line.long 0x00 "TCR,Transmit Control Register"
bitfld.long 0x00 15. "TIE15,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 14. "TIE14,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 13. "TIE13,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 12. "TIE12,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 11. "TIE11,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 10. "TIE10,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 9. "TIE9,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 8. "TIE8,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 7. "TIE7,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 6. "TIE6,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 5. "TIE5,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 4. "TIE4,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 3. "TIE3,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 2. "TIE2,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 1. "TIE1,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 0. "TIE0,MUA Transmit Interrupt Enable n" "0: Disable,1: Enable"
rgroup.long 0x124++0x03
line.long 0x00 "TSR,Transmit Status Register"
bitfld.long 0x00 15. "TE15,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 14. "TE14,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 13. "TE13,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 12. "TE12,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 11. "TE11,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 10. "TE10,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 9. "TE9,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 8. "TE8,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 7. "TE7,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 6. "TE6,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 5. "TE5,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 4. "TE4,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 3. "TE3,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 2. "TE2,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 1. "TE1,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
bitfld.long 0x00 0. "TE0,MUA Transmit Register n Empty" "0: Not empty,1: Empty"
group.long 0x128++0x03
line.long 0x00 "RCR,Receive Control Register"
bitfld.long 0x00 15. "RIE15,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 14. "RIE14,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 13. "RIE13,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 12. "RIE12,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 11. "RIE11,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 10. "RIE10,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 9. "RIE9,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 8. "RIE8,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 7. "RIE7,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 6. "RIE6,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 5. "RIE5,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 4. "RIE4,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 3. "RIE3,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 2. "RIE2,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 1. "RIE1,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
bitfld.long 0x00 0. "RIE0,MUA Receive Interrupt Enable n" "0: Disable,1: Enable"
rgroup.long 0x12C++0x03
line.long 0x00 "RSR,Receive Status Register"
bitfld.long 0x00 15. "RF15,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 14. "RF14,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 13. "RF13,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 12. "RF12,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 11. "RF11,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 10. "RF10,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 9. "RF9,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 8. "RF8,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 7. "RF7,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 6. "RF6,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 5. "RF5,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 4. "RF4,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 3. "RF3,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 2. "RF2,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
newline
bitfld.long 0x00 1. "RF1,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
bitfld.long 0x00 0. "RF0,MUA Receive Register n Full" "0: Not full,1: MUA_RRn register has received data from MUB.."
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "TR[$1],Transmit Register $1"
hexmask.long 0x00 0.--31. 1. "TR_DATA,MUA Transmit Data"
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x280)++0x03
line.long 0x00 "RR[$1],Receive Register $1"
hexmask.long 0x00 0.--31. 1. "RR_DATA,MUA Receive Data"
repeat.end
tree.end
tree.end
tree "OCOTP"
base ad:0x400E0000
group.long 0x00++0x03
line.long 0x00 "CTRL_SYS,System master's control"
hexmask.long.word 0x00 16.--31. 1. "AUTH_KEY,Key to unlock read and write operation"
bitfld.long 0x00 6. "TGLLTH,Toggle eFuse-latch" "0,1"
newline
bitfld.long 0x00 2.--5. "RD_WR,eFuse read and write control for the system master" "0: Invalid combination no action,1: Read eFuse,2: Write eFuse,3: Invalid combination no action,4: Invalid combination no action,5: Invalid combination no action,?,7: Invalid combination no action,?,9: Read eFuse and toggle eFuse-latch after the,10: Write eFuse and toggle eFuse-latch after the,?,?,?,14: Write eFuse and reload eFuse shadow register,?..."
bitfld.long 0x00 1. "CRC_TEST,CRC (Polynomial CRC-32/MPEG-2) test for system master" "?,1: CRC test enable for eFuses"
group.long 0x04++0x03
line.long 0x00 "ADDR_SYS,System master's eFuse address for read or write operation"
hexmask.long.word 0x00 0.--15. 1. "ADDR,eFuse read or write address"
group.long 0x08++0x03
line.long 0x00 "WRDATA_SYS,System master's eFuse write data"
hexmask.long 0x00 0.--31. 1. "DATA,eFuse data for eFuse write operation"
rgroup.long 0x0C++0x03
line.long 0x00 "RDATA_SYS,System master's eFuse read data"
hexmask.long 0x00 0.--31. 1. "DATA,Read data"
group.long 0x30++0x03
line.long 0x00 "CTRL_FBX,FBXC control"
eventfld.long 0x00 18. "IPG_STOP_ACK,Low-power mode acknowledgment" "0,1"
bitfld.long 0x00 17. "IPG_STOP,Low Power entry" "0,1"
newline
bitfld.long 0x00 16. "FBX_PD,Fusebox Power Down" "?,1: Enable fusebox power-down mode"
bitfld.long 0x00 8. "SEC_MODE,Indicates that the FBXC is in Secure mode" "?,1: FBXC is in secure mode"
newline
bitfld.long 0x00 0. "SEC_RST,Security reset for FBXC" "?,1: Resets flops on eFuse output"
group.long 0x34++0x03
line.long 0x00 "CRC_RGN_SYS,eFuse region for CRC validation"
hexmask.long.word 0x00 16.--31. 1. "END_ADDR,End eFuse address for CRC calculation"
hexmask.long.word 0x00 0.--15. 1. "START_ADDR,Start eFuse address for CRC calculation"
group.long 0x38++0x03
line.long 0x00 "CRC_ADDR_SYS,Pre-calculated CRC eFuse address for comparison"
hexmask.long.word 0x00 0.--15. 1. "ADDR,CRC eFuse address used for comparison in CRC test"
rgroup.long 0x3C++0x03
line.long 0x00 "CRC_VALUE_SYS,CRC calculated from the eFuses"
hexmask.long 0x00 0.--31. 1. "CRC,CRC value"
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0x40)++0x03
line.long 0x00 "GPR[$1],General purpose $1"
hexmask.long 0x00 0.--31. 1. "GPR,General-purpose field that you can use to store information for your application"
repeat.end
group.long 0x50++0x03
line.long 0x00 "STATUS_SYS,System master's access status"
eventfld.long 0x00 2. "ERROR,Error status flag" "0,1"
eventfld.long 0x00 1. "CRC_FAIL,CRC compare status" "0,1"
newline
rbitfld.long 0x00 0. "BUSY,OCOTP busy indication" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "VERSION,OCOTP design version"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,The major part of the design version"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,The minor part of the design version"
newline
hexmask.long.word 0x00 0.--15. 1. "STEP,The step part of the design version"
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0x60)++0x03
line.long 0x00 "STR[$1],Sticky $1"
hexmask.long 0x00 0.--31. 1. "STR,Sticky field for your use"
repeat.end
rgroup.long 0x70++0x03
line.long 0x00 "SEC0,ECC status for single-bit ECC error"
bitfld.long 0x00 31. "SEC32,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 30. "SEC31,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 29. "SEC30,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 28. "SEC29,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 27. "SEC28,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 26. "SEC27,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 25. "SEC26,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 24. "SEC25,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 23. "SEC24,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 22. "SEC23,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 21. "SEC22,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 20. "SEC21,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 19. "SEC20,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 18. "SEC19,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 17. "SEC18,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 16. "SEC17,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 15. "SEC16,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 14. "SEC15,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 13. "SEC14,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 12. "SEC13,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 11. "SEC12,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 10. "SEC11,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 9. "SEC10,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 8. "SEC9,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 7. "SEC8,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 6. "SEC7,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 5. "SEC6,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 4. "SEC5,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 3. "SEC4,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 2. "SEC3,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 1. "SEC2,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 0. "SEC1,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
rgroup.long 0x74++0x03
line.long 0x00 "SEC1,ECC status for single-bit ECC error"
bitfld.long 0x00 31. "SEC64,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 30. "SEC63,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 29. "SEC62,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 28. "SEC61,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 27. "SEC60,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 26. "SEC59,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 25. "SEC58,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 24. "SEC57,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 23. "SEC56,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 22. "SEC55,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 21. "SEC54,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 20. "SEC53,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 19. "SEC52,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 18. "SEC51,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 17. "SEC50,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 16. "SEC49,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 15. "SEC48,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 14. "SEC47,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 13. "SEC46,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 12. "SEC45,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 11. "SEC44,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 10. "SEC43,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 9. "SEC42,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 8. "SEC41,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 7. "SEC40,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 6. "SEC39,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 5. "SEC38,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 4. "SEC37,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 3. "SEC36,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 2. "SEC35,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
newline
bitfld.long 0x00 1. "SEC34,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
bitfld.long 0x00 0. "SEC33,SEC error status" "0: No single-bit ECC error detected,1: Single-bit ECC error detected"
rgroup.long 0x78++0x03
line.long 0x00 "SEC2,ECC status for single-bit ECC error"
bitfld.long 0x00 23. "SEC88,SEC error status" "0,1"
bitfld.long 0x00 22. "SEC87,SEC error status" "0,1"
newline
bitfld.long 0x00 21. "SEC86,SEC error status" "0,1"
bitfld.long 0x00 20. "SEC85,SEC error status" "0,1"
newline
bitfld.long 0x00 19. "SEC84,SEC error status" "0,1"
bitfld.long 0x00 18. "SEC83,SEC error status" "0,1"
newline
bitfld.long 0x00 17. "SEC82,SEC error status" "0,1"
bitfld.long 0x00 16. "SEC81,SEC error status" "0,1"
newline
bitfld.long 0x00 15. "SEC80,SEC error status" "0,1"
bitfld.long 0x00 14. "SEC79,SEC error status" "0,1"
newline
bitfld.long 0x00 13. "SEC78,SEC error status" "0,1"
bitfld.long 0x00 12. "SEC77,SEC error status" "0,1"
newline
bitfld.long 0x00 11. "SEC76,SEC error status" "0,1"
bitfld.long 0x00 10. "SEC75,SEC error status" "0,1"
newline
bitfld.long 0x00 9. "SEC74,SEC error status" "0,1"
bitfld.long 0x00 8. "SEC73,SEC error status" "0,1"
newline
bitfld.long 0x00 7. "SEC72,SEC error status" "0,1"
bitfld.long 0x00 6. "SEC71,SEC error status" "0,1"
newline
bitfld.long 0x00 5. "SEC70,SEC error status" "0,1"
bitfld.long 0x00 4. "SEC69,SEC error status" "0,1"
newline
bitfld.long 0x00 3. "SEC68,SEC error status" "0,1"
bitfld.long 0x00 2. "SEC67,SEC error status" "0,1"
newline
bitfld.long 0x00 1. "SEC66,SEC error status" "0,1"
bitfld.long 0x00 0. "SEC65,SEC error status" "0,1"
rgroup.long 0xB0++0x03
line.long 0x00 "DED0,ECC status for double-bit ECC error"
bitfld.long 0x00 31. "DED32,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 30. "DED31,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 29. "DED30,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 28. "DED29,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 27. "DED28,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 26. "DED27,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 25. "DED26,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 24. "DED25,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 23. "DED24,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 22. "DED23,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 21. "DED22,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 20. "DED21,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 19. "DED20,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 18. "DED19,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 17. "DED18,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 16. "DED17,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 15. "DED16,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 14. "DED15,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 13. "DED14,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 12. "DED13,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 11. "DED12,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 10. "DED11,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 9. "DED10,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 8. "DED9,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 7. "DED8,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 6. "DED7,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 5. "DED6,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 4. "DED5,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 3. "DED4,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 2. "DED3,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 1. "DED2,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 0. "DED1,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
rgroup.long 0xB4++0x03
line.long 0x00 "DED1,ECC status for double-bit ECC error"
bitfld.long 0x00 31. "DED64,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 30. "DED63,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 29. "DED62,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 28. "DED61,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 27. "DED60,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 26. "DED59,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 25. "DED58,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 24. "DED57,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 23. "DED56,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 22. "DED55,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 21. "DED54,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 20. "DED53,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 19. "DED52,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 18. "DED51,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 17. "DED50,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 16. "DED49,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 15. "DED48,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 14. "DED47,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 13. "DED46,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 12. "DED45,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 11. "DED44,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 10. "DED43,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 9. "DED42,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 8. "DED41,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 7. "DED40,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 6. "DED39,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 5. "DED38,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 4. "DED37,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 3. "DED36,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 2. "DED35,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 1. "DED34,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 0. "DED33,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
rgroup.long 0xB8++0x03
line.long 0x00 "DED2,ECC status for double-bit ECC error"
bitfld.long 0x00 23. "DED88,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 22. "DED87,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 21. "DED86,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 20. "DED85,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 19. "DED84,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 18. "DED83,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 17. "DED82,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 16. "DED81,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 15. "DED80,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 14. "DED79,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 13. "DED78,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 12. "DED77,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 11. "DED76,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 10. "DED75,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 9. "DED74,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 8. "DED73,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 7. "DED72,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 6. "DED71,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 5. "DED70,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 4. "DED69,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 3. "DED68,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 2. "DED67,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
newline
bitfld.long 0x00 1. "DED66,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
bitfld.long 0x00 0. "DED65,DED error status" "0: No double-bit ECC error detected,1: Double-bit ECC error detected"
group.long 0xF0++0x03
line.long 0x00 "ERR_INJCTR,ECC error injector"
hexmask.long.word 0x00 0.--11. 1. "ADDR,The address of the bit in the shadow register where you want to inject the single-bit ECC error"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "SHADOWS$1,Shadow"
hexmask.long 0x00 0.--31. 1. "EFUSES,OTP data"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x240)++0x03
line.long 0x00 "SHADOWS$1,Shadow"
hexmask.long 0x00 0.--31. 1. "EFUSES,OTP data"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "SHADOWS$1,Shadow"
hexmask.long 0x00 0.--31. 1. "EFUSES,OTP data"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x2C0)++0x03
line.long 0x00 "SHADOWS$1,Shadow"
hexmask.long 0x00 0.--31. 1. "EFUSES,OTP data"
repeat.end
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x300)++0x03
line.long 0x00 "SHADOWS$1,Shadow"
hexmask.long 0x00 0.--31. 1. "EFUSES,OTP data"
repeat.end
repeat 16. (strings "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" "90" "91" "92" "93" "94" "95" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x340)++0x03
line.long 0x00 "SHADOWS$1,Shadow"
hexmask.long 0x00 0.--31. 1. "EFUSES,OTP data"
repeat.end
repeat 16. (strings "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" "106" "107" "108" "109" "110" "111" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x380)++0x03
line.long 0x00 "SHADOWS$1,Shadow"
hexmask.long 0x00 0.--31. 1. "EFUSES,OTP data"
repeat.end
repeat 16. (strings "112" "113" "114" "115" "116" "117" "118" "119" "120" "121" "122" "123" "124" "125" "126" "127" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x3C0)++0x03
line.long 0x00 "SHADOWS$1,Shadow"
hexmask.long 0x00 0.--31. 1. "EFUSES,OTP data"
repeat.end
tree.end
tree "PIT"
repeat 2. (list 0. 2.) (list ad:0x402A4000 ad:0x440D8000)
tree "PIT_$1"
base $2
group.long 0x00++0x03
line.long 0x00 "MCR,PIT Module Control"
bitfld.long 0x00 1. "MDIS,Module Disable for PIT" "0: Enable,1: t00000111"
bitfld.long 0x00 0. "FRZ,Freeze" "0: Timers run in Debug mode,1: Timers stop in Debug mode"
rgroup.long 0xE0++0x03
line.long 0x00 "LTMR64H,PIT Upper Lifetime Timer"
hexmask.long 0x00 0.--31. 1. "LTH,Lifetime Timer Value"
rgroup.long 0xE4++0x03
line.long 0x00 "LTMR64L,PIT Lower Lifetime Timer"
hexmask.long 0x00 0.--31. 1. "LTL,Lifetime Timer Value"
repeat 7. (increment 0 1)(increment  0 0x10)
tree "TIMER[$1]"
group.long ($2+0x100)++0x03
line.long 0x00 "LDVAL,Timer Load Value"
hexmask.long 0x00 0.--31. 1. "TSV,Timer Start Value"
rgroup.long ($2+0x104)++0x03
line.long 0x00 "CVAL,Current Timer Value"
hexmask.long 0x00 0.--31. 1. "TVL,Timer Value"
group.long ($2+0x108)++0x03
line.long 0x00 "TCTRL,Timer Control"
bitfld.long 0x00 2. "CHN,Chain Mode" "0: timer0001,1: timer0081"
bitfld.long 0x00 1. "TIE,Timer Interrupt Enable" "0: Disables,1: t077711"
bitfld.long 0x00 0. "TEN,Timer Enable" "0: Disables,1: Enables"
group.long ($2+0x10C)++0x03
line.long 0x00 "TFLG,Timer Flag"
eventfld.long 0x00 0. "TIF,Timer Interrupt Flag" "0: Timer has not expired,1: Timer expired"
tree.end
repeat.end
tree.end
repeat.end
tree.end
tree "PLLDIG"
tree "CORE_PLL"
base ad:0x440C0000
group.long 0x00++0x03
line.long 0x00 "PLLCR,PLL Control"
bitfld.long 0x00 31. "PLLPD,PLL Power Down" "0: bfv_pllcr_pllpd_0,1: bfv_pllcr_pllpd_1"
group.long 0x04++0x03
line.long 0x00 "PLLSR,PLL Status"
eventfld.long 0x00 3. "LOL,Loss-Of-Lock Flag" "0: No loss of lock detected,1: Loss of lock detected"
rbitfld.long 0x00 2. "LOCK,Lock Status" "0: bfv_pllsr_lock_0,1: bfv_pllsr_lock_1"
group.long 0x08++0x03
line.long 0x00 "PLLDV,PLL Divider"
bitfld.long 0x00 12.--14. "RDIV,Input Clock Predivider" "0: bfv_plldv_rdiv_000,1: bfv_plldv_rdiv_001,2: bfv_plldv_rdiv_010,3: bfv_plldv_rdiv_011,4: bfv_plldv_rdiv_100,5: bfv_plldv_rdiv_101,6: bfv_plldv_rdiv_110,7: bfv_plldv_rdiv_111"
hexmask.long.byte 0x00 0.--7. 1. "MFI,Integer Portion Of Loop Divider"
group.long 0x0C++0x03
line.long 0x00 "PLLFM,PLL Frequency Modulation"
bitfld.long 0x00 30. "SSCGBYP,Frequency Modulation (Spread Spectrum Clock Generation) Bypass" "0: bfv_pllfm_sscgbyp_0,1: bfv_pllfm_sscgbyp_1"
bitfld.long 0x00 29. "SPREADCTL,Modulation Type Selection" "0: Centered around nominal frequency,?..."
hexmask.long.word 0x00 16.--25. 1. "STEPSIZE,Frequency Modulation Step Size"
hexmask.long.word 0x00 0.--10. 1. "STEPNO,Number Of Steps Of Modulation Period Or Frequency Modulation"
group.long 0x10++0x03
line.long 0x00 "PLLFD,PLL Fractional Divider"
bitfld.long 0x00 30. "SDMEN,Fractional Mode Enable" "0: bfv_pllfd_sdmen_0,1: bfv_pllfd_sdmen_1"
hexmask.long.word 0x00 0.--14. 1. "MFN,Numerator Of Fractional Loop Division Factor"
group.long 0x20++0x03
line.long 0x00 "PLLCLKMUX,PLL Clock Multiplexer"
bitfld.long 0x00 0. "REFCLKSEL,Reference Clock Select" "0: bfv_pllclkmux_refclksel_0,1: bfv_pllclkmux_refclksel_1"
repeat 10. (increment 0 1) (increment 0 0x4)
group.long ($2+0x80)++0x03
line.long 0x00 "PLLODIV_[$1],PLL Output Divider $1"
bitfld.long 0x00 31. "DE,Divider Enable" "0: bfv_pllodiv_de_0,1: bfv_pllodiv_de_1"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division Value"
repeat.end
tree.end
tree "PERIPH_PLL"
base ad:0x400BC000
group.long 0x00++0x03
line.long 0x00 "PLLCR,PLL Control"
bitfld.long 0x00 31. "PLLPD,PLL Power Down" "0: bfv_pllcr_pllpd_0,1: bfv_pllcr_pllpd_1"
group.long 0x04++0x03
line.long 0x00 "PLLSR,PLL Status"
eventfld.long 0x00 3. "LOL,Loss-Of-Lock Flag" "0: No loss of lock detected,1: Loss of lock detected"
rbitfld.long 0x00 2. "LOCK,Lock Status" "0: bfv_pllsr_lock_0,1: bfv_pllsr_lock_1"
group.long 0x08++0x03
line.long 0x00 "PLLDV,PLL Divider"
bitfld.long 0x00 12.--14. "RDIV,Input Clock Predivider" "0: bfv_plldv_rdiv_000,1: bfv_plldv_rdiv_001,2: bfv_plldv_rdiv_010,3: bfv_plldv_rdiv_011,4: bfv_plldv_rdiv_100,5: bfv_plldv_rdiv_101,6: bfv_plldv_rdiv_110,7: bfv_plldv_rdiv_111"
hexmask.long.byte 0x00 0.--7. 1. "MFI,Integer Portion Of Loop Divider"
group.long 0x20++0x03
line.long 0x00 "PLLCLKMUX,PLL Clock Multiplexer"
bitfld.long 0x00 0. "REFCLKSEL,Reference Clock Select" "0: bfv_pllclkmux_refclksel_0,1: bfv_pllclkmux_refclksel_1"
repeat 10. (increment 0 1) (increment 0 0x4)
group.long ($2+0x80)++0x03
line.long 0x00 "PLLODIV_[$1],PLL Output Divider $1"
bitfld.long 0x00 31. "DE,Divider Enable" "0: bfv_pllodiv_de_0,1: bfv_pllodiv_de_1"
hexmask.long.byte 0x00 16.--23. 1. "DIV,Division Value"
repeat.end
tree.end
tree.end
tree "PMC"
base ad:0x40090000
group.long 0x00++0x03
line.long 0x00 "SSR,Source of System Reset"
eventfld.long 0x00 2. "POR_WDOG_EVENT,POR watchdog event flag" "0: No event detected after the last clearing of..,1: An event was detected"
newline
eventfld.long 0x00 1. "CSPD_EVENT,Critical supply presence detector event flag" "0: No event detected after last clearing of the..,1: An event was detected"
newline
eventfld.long 0x00 0. "POR_SUP,POR on core supply CSPD event flag" "0: No event detected after the last time this..,1: An event was detected"
group.long 0x04++0x03
line.long 0x00 "NCSPD_CTL,Non-Critical Supply Presence Detector Control"
bitfld.long 0x00 31. "NCSPD_CTL31,NCSPD31 control" "0: NCSPD31 cannot set..,1: NCSPD31 can set NCSPDEF[NCSPD_EVENT_CAPTURE31]"
newline
bitfld.long 0x00 29. "NCSPD_CTL29,NCSPD29 control" "0: NCSPD29 cannot set..,1: NCSPD29 can set NCSPDEF[NCSPD_EVENT_CAPTURE29]"
newline
bitfld.long 0x00 28. "NCSPD_CTL28,NCSPD28 control" "0: NCSPD28 cannot set..,1: NCSPD28 can set NCSPDEF[NCSPD_EVENT_CAPTURE28]"
newline
bitfld.long 0x00 27. "NCSPD_CTL27,NCSPD27 control" "0: NCSPD27 cannot set..,1: NCSPD27 can set NCSPDEF[NCSPD_EVENT_CAPTURE27]"
newline
bitfld.long 0x00 26. "NCSPD_CTL26,NCSPD26 control" "0: NCSPD26 cannot set..,1: NCSPD26 can set NCSPDEF[NCSPD_EVENT_CAPTURE26]"
newline
bitfld.long 0x00 25. "NCSPD_CTL25,NCSPD25 control" "0: NCSPD25 cannot set..,1: NCSPD25 can set NCSPDEF[NCSPD_EVENT_CAPTURE25]"
newline
bitfld.long 0x00 24. "NCSPD_CTL24,NCSPD24 control" "0: NCSPD24 cannot set..,1: NCSPD24 can set NCSPDEF[NCSPD_EVENT_CAPTURE24]"
newline
bitfld.long 0x00 10. "NCSPD_CTL10,NCSPD10 control" "0: NCSPD10 cannot set..,1: NCSPD10 can set NCSPDEF[NCSPD_EVENT_CAPTURE10]"
newline
bitfld.long 0x00 9. "NCSPD_CTL9,NCSPD9 control" "0: NCSPD9 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE9],1: NCSPD9 can set NCSPDEF[NCSPD_EVENT_CAPTURE9]"
newline
bitfld.long 0x00 6. "NCSPD_CTL6,NCSPD6 control" "0: NCSPD6 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE6],1: NCSPD6 can set NCSPDEF[NCSPD_EVENT_CAPTURE6]"
newline
bitfld.long 0x00 5. "NCSPD_CTL5,NCSPD5 control" "0: NCSPD5 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE5],1: NCSPD5 can set NCSPDEF[NCSPD_EVENT_CAPTURE5]"
newline
bitfld.long 0x00 4. "NCSPD_CTL4,NCSPD4 control" "0: NCSPD4 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE4],1: NCSPD4 can set NCSPDEF[NCSPD_EVENT_CAPTURE4]"
newline
bitfld.long 0x00 3. "NCSPD_CTL3,NCSPD3 control" "0: NCSPD3 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE3],1: NCSPD3 can set NCSPDEF[NCSPD_EVENT_CAPTURE3]"
newline
bitfld.long 0x00 1. "NCSPD_CTL1,NCSPD1 control" "0: NCSPD1 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE1],1: NCSPD1 can set NCSPDEF[NCSPD_EVENT_CAPTURE1]"
newline
bitfld.long 0x00 0. "NCSPD_CTL0,NCSPD0 control" "0: NCSPD0 cannot set NCSPDEF[NCSPD_EVENT_CAPTURE0],1: NCSPD0 can set NCSPDEF[NCSPD_EVENT_CAPTURE0]"
rgroup.long 0x0C++0x03
line.long 0x00 "NCSPD_STAT,NCSPD Status Register"
bitfld.long 0x00 31. "NCSPD_STAT31,NCSPD31 status" "0: NCSPD31 has not detected an error condition,1: NCPSD31 has detected an error condition"
newline
bitfld.long 0x00 29. "NCSPD_STAT29,NCSPD29 status" "0: NCSPD29 has not detected an error condition,1: NCPSD29 has detected an error condition"
newline
bitfld.long 0x00 28. "NCSPD_STAT28,NCSPD28 status" "0: NCSPD28 has not detected an error condition,1: NCPSD28 has detected an error condition"
newline
bitfld.long 0x00 27. "NCSPD_STAT27,NCSPD27 status" "0: NCSPD27 has not detected an error condition,1: NCPSD27 has detected an error condition"
newline
bitfld.long 0x00 26. "NCSPD_STAT26,NCSPD26 status" "0: NCSPD26 has not detected an error condition,1: NCPSD26 has detected an error condition"
newline
bitfld.long 0x00 25. "NCSPD_STAT25,NCSPD25 status" "0: NCSPD25 has not detected an error condition,1: NCPSD25 has detected an error condition"
newline
bitfld.long 0x00 24. "NCSPD_STAT24,NCSPD24 status" "0: NCSPD24 has not detected an error condition,1: NCPSD24 has detected an error condition"
newline
bitfld.long 0x00 10. "NCSPD_STAT10,NCSPD10 status" "0: NCSPD10 has not detected an error condition,1: NCPSD10 has detected an error condition"
newline
bitfld.long 0x00 9. "NCSPD_STAT9,NCSPD9 status" "0: NCSPD9 has not detected an error condition,1: NCPSD9 has detected an error condition"
newline
bitfld.long 0x00 6. "NCSPD_STAT6,NCSPD6 status" "0: NCSPD6 has not detected an error condition,1: NCPSD6 has detected an error condition"
newline
bitfld.long 0x00 5. "NCSPD_STAT5,NCSPD5 status" "0: NCSPD5 has not detected an error condition,1: NCPSD5 has detected an error condition"
newline
bitfld.long 0x00 4. "NCSPD_STAT4,NCSPD4 status" "0: NCSPD4 has not detected an error condition,1: NCPSD4 has detected an error condition"
newline
bitfld.long 0x00 3. "NCSPD_STAT3,NCSPD3 status" "0: NCSPD3 has not detected an error condition,1: NCPSD3 has detected an error condition"
newline
bitfld.long 0x00 1. "NCSPD_STAT1,NCSPD1 status" "0: NCSPD1 has not detected an error condition,1: NCPSD1 has detected an error condition"
newline
bitfld.long 0x00 0. "NCSPD_STAT0,NCSPD0 status" "0: NCSPD0 has not detected an error condition,1: NCPSD0 has detected an error condition"
group.long 0x10++0x03
line.long 0x00 "CSPD_EVENT_CAPTURE,CSPD Event Capture (CSPDEF)"
eventfld.long 0x00 31. "CSPD_EVENT_CAPTURE30,CSPD30 event flag" "0: No CSPD30 error condition detected after last..,1: CSPD30 error condition detected"
newline
eventfld.long 0x00 30. "CSPD_EVENT_CAPTURE29,CSPD29 event flag" "0: No CSPD29 error condition detected after last..,1: CSPD29 error condition detected"
newline
eventfld.long 0x00 2. "CSPD_EVENT_CAPTURE1,CSPD1 event flag" "0: No CSPD1 error condition detected after last..,1: CSPD1 error condition detected"
newline
eventfld.long 0x00 1. "CSPD_EVENT_CAPTURE0,CSPD0 event flag" "0: No CSPD0 error condition detected after last..,1: CSPD0 error condition detected"
newline
eventfld.long 0x00 0. "HVCPOREF,PMC supply CSPD event flag" "0: PMC Supply did not cross the lower voltage..,1: PMC Supply was below the lower voltage limit"
group.long 0x14++0x03
line.long 0x00 "NCSPD_EVENT_CAPTURE,NCSPD Event Flag (NCSPDEF)"
eventfld.long 0x00 31. "NCSPD_EVENT_CAPTURE31,NCSPD31 event flag" "0: No NCSPD31 error condition occurred after..,1: NCSPD31 error condition occurred"
newline
eventfld.long 0x00 29. "NCSPD_EVENT_CAPTURE29,NCSPD29 event flag" "0: No NCSPD29 error condition occurred after..,1: NCSPD29 error condition occurred"
newline
eventfld.long 0x00 28. "NCSPD_EVENT_CAPTURE28,NCSPD28 event flag" "0: No NCSPD28 error condition occurred after..,1: NCSPD28 error condition occurred"
newline
eventfld.long 0x00 27. "NCSPD_EVENT_CAPTURE27,NCSPD27 event flag" "0: No NCSPD27 error condition occurred after..,1: NCSPD27 error condition occurred"
newline
eventfld.long 0x00 26. "NCSPD_EVENT_CAPTURE26,NCSPD26 event flag" "0: No NCSPD26 error condition occurred after..,1: NCSPD26 error condition occurred"
newline
eventfld.long 0x00 25. "NCSPD_EVENT_CAPTURE25,NCSPD25 event flag" "0: No NCSPD25 error condition occurred after..,1: NCSPD25 error condition occurred"
newline
eventfld.long 0x00 24. "NCSPD_EVENT_CAPTURE24,NCSPD24 event flag" "0: No NCSPD24 error condition occurred after..,1: NCSPD24 error condition occurred"
newline
eventfld.long 0x00 10. "NCSPD_EVENT_CAPTURE10,NCSPD10 event flag" "0: No NCSPD10 error condition occurred after..,1: NCSPD10 error condition occurred"
newline
eventfld.long 0x00 9. "NCSPD_EVENT_CAPTURE9,NCSPD9 event flag" "0: No NCSPD9 error condition occurred after last..,1: NCSPD9 error condition occurred"
newline
eventfld.long 0x00 6. "NCSPD_EVENT_CAPTURE6,NCSPD6 event flag" "0: No NCSPD6 error condition occurred after last..,1: NCSPD6 error condition occurred"
newline
eventfld.long 0x00 5. "NCSPD_EVENT_CAPTURE5,NCSPD5 event flag" "0: No NCSPD5 error condition occurred after last..,1: NCSPD5 error condition occurred"
newline
eventfld.long 0x00 4. "NCSPD_EVENT_CAPTURE4,NCSPD4 event flag" "0: No NCSPD4 error condition occurred after last..,1: NCSPD4 error condition occurred"
newline
eventfld.long 0x00 3. "NCSPD_EVENT_CAPTURE3,NCSPD3 event flag" "0: No NCSPD3 error condition occurred after last..,1: NCSPD3 error condition occurred"
newline
eventfld.long 0x00 1. "NCSPD_EVENT_CAPTURE1,NCSPD1 event flag" "0: No NCSPD1 error condition occurred after last..,1: NCSPD1 error condition occurred"
newline
eventfld.long 0x00 0. "NCSPD_EVENT_CAPTURE0,NCSPD0 event flag" "0: No NCSPD0 error condition occurred after last..,1: NCSPD0 error condition occurred"
repeat 3. (increment 0 1) (increment 0 0x4)
group.long ($2+0x1C)++0x03
line.long 0x00 "POR_WDOG_EVENT_CAPTURE[$1],Device Status Flag (DSFindex $1"
hexmask.long 0x00 0.--31. 1. "DSFBIT0,See the Chip-specific PMC information at the beginning of this chapter for the mapping between these fields and the Device status signals of the chip (see )"
repeat.end
tree.end
tree "PMUEVENTOBSERVER (PMUEVENT observer)"
base ad:0x440D0200
repeat 30. (increment 0 1) (increment 0 0x4)
group.long ($2+0x00)++0x03
line.long 0x00 "CTL[$1],PMUEVENT Observer Control $1"
bitfld.long 0x00 9. "CLRCNTR,Clear Count" "0: Do not clear,1: CLRCNTR_1"
bitfld.long 0x00 8. "CPYCOUNT,Copy Count" "0: Do not copy,1: CPYCOUNT_1"
newline
bitfld.long 0x00 6.--7. "CTRSTPSEL,Control Stop Select" "?,1: Falling edge detect signal used as stop trigger,?..."
bitfld.long 0x00 4.--5. "CTRSTRTSEL,Control Start Select" "?,1: Input to select the counter start trigger,?..."
newline
bitfld.long 0x00 0.--1. "REVTINPSEL,Rise Event Input Select" "?,1: Rise level of signal used as input to counter,?..."
repeat.end
repeat 30. (increment 0 1) (increment 0 0x4)
group.long ($2+0x80)++0x03
line.long 0x00 "STAT[$1],PMUEVENT Observer Status $1"
hexmask.long 0x00 0.--31. 1. "COUNT_VAL,Count Value"
repeat.end
tree.end
tree "QUADSPI (QuadSPI)"
base ad:0x402D0000
group.long 0x00++0x03
line.long 0x00 "MCR,Module Configuration Register"
bitfld.long 0x00 27. "CK2_DCARS_FA,CK2 DDR center-aligned read strobe for flash memory A" "0,1"
bitfld.long 0x00 24.--25. "DQS_FA_SEL,DQS clock for sampling read data at flash memory A" "0,1,2,3"
newline
bitfld.long 0x00 17. "ISD3FA,Idle signal drive IOFA[3] flash memory A" "0: IOFA[3] is driven to logic L,1: IOFA[3] is driven to logic H"
bitfld.long 0x00 16. "ISD2FA,Idle signal drive IOFA[2] flash memory A" "0: IOFA[2] is driven to logic L,1: IOFA[2] is driven to logic H"
newline
bitfld.long 0x00 14. "MDIS,Module disable" "0: Enable QuadSPI clocks,1: Allow external logic to disable QuadSPI clocks"
bitfld.long 0x00 12. "DLPEN,Data learning pattern enable" "0,1"
newline
bitfld.long 0x00 11. "CLR_TXF,Clear TX FIFO/buffer" "0: No action,1: Read and write pointers of the TX buffer are.."
bitfld.long 0x00 10. "CLR_RXF,Clear RX FIFO" "0: No action,1: Read and write pointers of the RX buffer are.."
newline
bitfld.long 0x00 7. "DDR_EN,DDR mode enable" "0: 2x clock disabled for SDR instructions only,1: 2x clock enabled for DDR instructions"
bitfld.long 0x00 6. "DQS_EN,DQS enable" "?,1: DQS enabled"
newline
bitfld.long 0x00 1. "SWRSTHD,Software reset for AHB domain" "0,1"
bitfld.long 0x00 0. "SWRSTSD,Software reset for serial flash memory domain" "0,1"
group.long 0x08++0x03
line.long 0x00 "IPCR,IP Configuration Register"
bitfld.long 0x00 24.--27. "SEQID,Points to a sequence in the LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "IDATSZ,IP data transfer size"
group.long 0x0C++0x03
line.long 0x00 "FLSHCR,Flash Memory Configuration Register"
bitfld.long 0x00 16.--17. "TDH,Serial flash memory data in hold time" "0: Data aligned with the posedge of internal..,1: Data aligned with 2x serial flash memory half..,?..."
bitfld.long 0x00 8.--11. "TCSH,Serial flash memory CS hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "TCSS,Serial flash memory CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "BUF0CR,Buffer 0 Configuration Register"
hexmask.long.byte 0x00 8.--15. 1. "ADATSZ,AHB data transfer size"
bitfld.long 0x00 0.--4. "MSTRID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x14++0x03
line.long 0x00 "BUF1CR,Buffer 1 Configuration Register"
hexmask.long.byte 0x00 8.--15. 1. "ADATSZ,AHB data transfer size"
bitfld.long 0x00 0.--4. "MSTRID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x18++0x03
line.long 0x00 "BUF2CR,Buffer 2 Configuration Register"
hexmask.long.byte 0x00 8.--15. 1. "ADATSZ,AHB data transfer size"
bitfld.long 0x00 0.--4. "MSTRID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C++0x03
line.long 0x00 "BUF3CR,Buffer 3 Configuration Register"
bitfld.long 0x00 31. "ALLMST,All master enable" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "ADATSZ,AHB data transfer size"
newline
bitfld.long 0x00 0.--4. "MSTRID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x20++0x03
line.long 0x00 "BFGENCR,Buffer Generic Configuration Register"
bitfld.long 0x00 12.--15. "SEQID,Points to a sequence in the LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "BUF0IND,Buffer 0 Top Index Register"
hexmask.long.byte 0x00 3.--10. 1. "TPINDX0,Top index of buffer 0"
group.long 0x34++0x03
line.long 0x00 "BUF1IND,Buffer 1 Top Index Register"
hexmask.long.byte 0x00 3.--10. 1. "TPINDX1,Top index of buffer 1"
group.long 0x38++0x03
line.long 0x00 "BUF2IND,Buffer 2 Top Index Register"
hexmask.long.byte 0x00 3.--10. 1. "TPINDX2,Top index of buffer 2"
group.long 0x60++0x03
line.long 0x00 "DLLCRA,DLL Flash Memory A Configuration Register"
bitfld.long 0x00 31. "DLLEN,DLL enable" "0: DLL reference logic remains in reset and..,1: Enables DLL logic"
bitfld.long 0x00 30. "FREQEN,Frequency enable" "0: Selects delay chain for low frequency of..,1: Selects delay chain for high frequency of.."
newline
bitfld.long 0x00 24.--27. "DLL_REFCNTR,DLL reference counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "DLLRES,DLL resolution" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "SLV_FINE_OFFSET,Fine offset delay elements in incoming DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--14. "SLV_DLY_OFFSET,T/16 offset delay elements in incoming DQS" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--11. "SLV_DLY_COARSE,Delay elements in each delay tap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "SLAVE_AUTO_UPDT,Slave chain update" "0: Auto-update feature is disabled,1: Auto-update feature is enabled"
newline
bitfld.long 0x00 2. "SLV_EN,Slave enable" "0: DLL slave logic remains in reset and its..,1: Enables DQS slave delay chain and should be 1.."
bitfld.long 0x00 1. "SLV_DLL_BYPASS,Slave DLL bypass" "0: Disables manual selection of coarse delays in..,1: Enables selection of number of delays in each.."
newline
bitfld.long 0x00 0. "SLV_UPD,Slave update" "0: Disables any further update on DQS slave..,1: Updates the DQS slave delay chain with either.."
group.long 0x100++0x03
line.long 0x00 "SFAR,Serial Flash Memory Address Register"
hexmask.long 0x00 0.--31. 1. "SFADR,Serial flash memory address"
group.long 0x104++0x03
line.long 0x00 "SFACR,Serial Flash Memory Address Configuration Register"
bitfld.long 0x00 16. "WA,Word addressable" "0: Byte addressable serial flash memory mode,1: Word (2-byte) addressable serial flash memory.."
bitfld.long 0x00 0.--3. "CAS,Column address space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x108++0x03
line.long 0x00 "SMPR,Sampling Register"
bitfld.long 0x00 24.--26. "DLLFSMPFA,Selects the nth tap provided by slave delay chain for flash memory A" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "FSDLY,Full-speed delay selection for internal/pad loop back DQS sampling" "0,1"
newline
bitfld.long 0x00 5. "FSPHS,Full-speed phase selection for SDR instructions" "0,1"
rgroup.long 0x10C++0x03
line.long 0x00 "RBSR,RX Buffer Status Register"
hexmask.long.word 0x00 16.--31. 1. "RDCTR,Read counter"
hexmask.long.byte 0x00 0.--7. 1. "RDBFL,RX buffer fill level"
group.long 0x110++0x03
line.long 0x00 "RBCT,RX Buffer Control Register"
hexmask.long.byte 0x00 0.--6. 1. "WMRK,RX buffer watermark"
rgroup.long 0x12C++0x03
line.long 0x00 "DLLSR,DLL Status Register"
bitfld.long 0x00 15. "DLLA_LOCK,DLL A lock status" "0,1"
bitfld.long 0x00 14. "SLVA_LOCK,Slave high lock status" "0,1"
newline
bitfld.long 0x00 13. "DLLA_RANGE_ERR,DLL master delay chain" "0,1"
bitfld.long 0x00 12. "DLLA_FINE_UNDERFLOW,Fine delay chain underflow" "0,1"
newline
bitfld.long 0x00 4.--7. "DLLA_SLV_FINE_VAL,Fine delay cells in slave delay chain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DLLA_SLV_COARSE_VAL,Coarse delay cells in slave delay chain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x130++0x03
line.long 0x00 "DLCR,Data Learning Configuration Register"
bitfld.long 0x00 24. "DL_NONDLP_FLSH,Data learning enabled for non-DLP flash memory" "0,1"
bitfld.long 0x00 14.--15. "DLP_SEL_FA,Selects pattern matching IO pads" "0: Pattern matching is ignored,1: IO1 is used for matching,2: IO3 is used for matching,3: Both IO1 and IO3 are used for pattern matching"
rgroup.long 0x134++0x03
line.long 0x00 "DLSR_FA,Data Learning Status Flash Memory A Register"
bitfld.long 0x00 31. "DLPFFA,Data learning pattern fail" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "POS_EDGE,DLP positive edge match signature for flash memory A"
newline
hexmask.long.byte 0x00 0.--7. 1. "NEG_EDGE,DLP negative edge match signature for flash memory A"
rgroup.long 0x150++0x03
line.long 0x00 "TBSR,TX Buffer Status Register"
hexmask.long.word 0x00 16.--31. 1. "TRCTR,Transmit counter"
bitfld.long 0x00 0.--5. "TRBFL,TX buffer fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x154++0x03
line.long 0x00 "TBDR,TX Buffer Data Register"
hexmask.long 0x00 0.--31. 1. "TXDATA,TX data"
group.long 0x158++0x03
line.long 0x00 "TBCT,TX Buffer Control Register"
bitfld.long 0x00 0.--4. "WMRK,Watermark for TX buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x15C++0x03
line.long 0x00 "SR,Status Register"
bitfld.long 0x00 27. "TXFULL,TX buffer full" "0,1"
bitfld.long 0x00 26. "TXDMA,TX DMA" "0,1"
newline
bitfld.long 0x00 25. "TXWA,TX buffer watermark available" "0,1"
bitfld.long 0x00 24. "TXNE,TX buffer not empty" "0,1"
newline
bitfld.long 0x00 23. "RXDMA,RX buffer DMA" "0,1"
bitfld.long 0x00 19. "RXFULL,RX buffer full" "0,1"
newline
bitfld.long 0x00 16. "RXWE,RX buffer watermark exceeded" "0,1"
bitfld.long 0x00 14. "AHB3FUL,AHB 3 buffer full" "0,1"
newline
bitfld.long 0x00 13. "AHB2FUL,AHB 2 buffer full" "0,1"
bitfld.long 0x00 12. "AHB1FUL,AHB 1 buffer full" "0,1"
newline
bitfld.long 0x00 11. "AHB0FUL,AHB 0 buffer full" "0,1"
bitfld.long 0x00 10. "AHB3NE,AHB 3 buffer not empty" "0,1"
newline
bitfld.long 0x00 9. "AHB2NE,AHB 2 buffer not empty" "0,1"
bitfld.long 0x00 8. "AHB1NE,AHB 1 buffer not empty" "0,1"
newline
bitfld.long 0x00 7. "AHB0NE,AHB 0 buffer not empty" "0,1"
bitfld.long 0x00 6. "AHBTRN,AHB access transaction pending" "0,1"
newline
bitfld.long 0x00 2. "AHB_ACC,AHB read access" "0,1"
bitfld.long 0x00 1. "IP_ACC,IP access" "0,1"
newline
bitfld.long 0x00 0. "BUSY,Module busy" "0,1"
group.long 0x160++0x03
line.long 0x00 "FR,Flag Register"
eventfld.long 0x00 31. "DLPFF,Data learning pattern failure flag" "0,1"
eventfld.long 0x00 28. "DLLABRT,DLL abort" "?,1: This field is set whenever DLL is unlocked.."
newline
eventfld.long 0x00 27. "TBFF,TX buffer fill flag" "0,1"
eventfld.long 0x00 26. "TBUF,TX buffer underrun flag" "0,1"
newline
eventfld.long 0x00 24. "DLLUNLCK,DLL unlock" "?,1: This field is set whenever DLL unlock event.."
eventfld.long 0x00 23. "ILLINE,Illegal instruction error flag" "0,1"
newline
eventfld.long 0x00 17. "RBOF,RX buffer overflow flag" "0,1"
eventfld.long 0x00 16. "RBDF,RX buffer drain flag" "0,1"
newline
eventfld.long 0x00 15. "AAEF,AHB abort error flag" "0,1"
eventfld.long 0x00 14. "AITEF,AHB illegal transaction error flag" "0,1"
newline
eventfld.long 0x00 12. "ABOF,AHB buffer overflow flag" "0,1"
eventfld.long 0x00 10. "CRCAEF,Sets when there is CRC or ECC error for flash memory A" "0: CRCEF interrupt is not generated,1: CRCEF interrupt is generated"
newline
eventfld.long 0x00 7. "IPAEF,IP command trigger during AHB access error flag" "0,1"
eventfld.long 0x00 6. "IPIEF,IP command trigger could not be executed error flag" "0,1"
newline
eventfld.long 0x00 0. "TFF,IP command transaction finished flag" "0,1"
group.long 0x164++0x03
line.long 0x00 "RSER,Interrupt and DMA Request Select and Enable Register"
bitfld.long 0x00 31. "DLPFIE,Data learning pattern failure interrupt enable" "0: No DLPFF interrupt is generated,1: DLPFF interrupt is generated"
bitfld.long 0x00 27. "TBFIE,TX buffer fill interrupt enable flag" "0: No TBFF interrupt is generated,1: TBFF interrupt is generated"
newline
bitfld.long 0x00 26. "TBUIE,TX buffer underrun interrupt enable flag" "0: No TBUF interrupt is generated,1: TBUF interrupt is generated"
bitfld.long 0x00 25. "TBFDE,TX buffer fill DMA enable" "0: No DMA request is generated,1: DMA request is generated"
newline
bitfld.long 0x00 24. "DLLULIE,DLL unlock interrupt enable" "?,1: Write 1 to this to enable generation of.."
bitfld.long 0x00 23. "ILLINIE,Illegal instruction error interrupt enable" "0: No ILLINE interrupt is generated,1: ILLINE interrupt is generated"
newline
bitfld.long 0x00 21. "RBDDE,RX buffer drain DMA enable" "0: No DMA request is generated,1: DMA request is generated"
bitfld.long 0x00 17. "RBOIE,RX buffer overflow interrupt enable" "0: No RBOF interrupt is generated,1: RBOF interrupt is generated"
newline
bitfld.long 0x00 16. "RBDIE,RX buffer drain interrupt enable" "0: No RBDF interrupt is generated,1: RBDF Interrupt is generated"
bitfld.long 0x00 15. "AAIE,AHB abort error interrupt enable" "0: No AAEF interrupt is generated,1: AAEF interrupt is generated"
newline
bitfld.long 0x00 14. "AITIE,AHB illegal transaction interrupt enable flag" "0: No AITEF interrupt is generated,1: AITEF interrupt is generated"
bitfld.long 0x00 13. "AIBSIE,AHB illegal burst size interrupt enable flag" "0: No AIBSEF interrupt is generated,1: AIBSEF interrupt is generated"
newline
bitfld.long 0x00 12. "ABOIE,AHB buffer overflow interrupt enable flag" "0: No ABOF interrupt is generated,1: ABOF interrupt is generated"
bitfld.long 0x00 10. "CRCAIE,CRC and ECC interrupt enable for flash memory A" "0: CRCAEF interrupt is not generated,1: CRCAEF interrupt is generated"
newline
bitfld.long 0x00 7. "IPAEIE,IP command trigger during AHB read access error interrupt enable flag" "0: No IPAEF interrupt is generated,1: IPAEF interrupt is generated"
bitfld.long 0x00 6. "IPIEIE,IP command trigger during IP access error interrupt enable flag" "0: No IPIEF interrupt is generated,1: IPIEF interrupt is generated"
newline
bitfld.long 0x00 0. "TFIE,Transaction finished interrupt enable flag" "0: No TFF interrupt is generated,1: TFF interrupt is generated"
group.long 0x16C++0x03
line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register"
bitfld.long 0x00 17. "PREFETCH_DIS,Prefetch disable" "0,1"
bitfld.long 0x00 16. "ABRT_CLR,Flash memory Abort/AHB buffer clear" "0,1"
newline
bitfld.long 0x00 8. "IPPTRC,IP pointer clear" "?,1: Clears the sequence pointer for IP accesses.."
bitfld.long 0x00 0. "BFPTRC,Buffer pointer clear" "?,1: Clears the sequence pointer for AHB read.."
group.long 0x180++0x03
line.long 0x00 "SFA1AD,Serial Flash Memory A1 Top Address Register"
hexmask.long.tbyte 0x00 10.--31. 1. "TPADA1,Top address for serial flash memory A1"
group.long 0x184++0x03
line.long 0x00 "SFA2AD,Serial Flash Memory A2 Top Address Register"
hexmask.long.tbyte 0x00 10.--31. 1. "TPADA2,Top address for serial flash memory A2"
group.long 0x190++0x03
line.long 0x00 "DLPR,Data Learn Pattern Register"
hexmask.long 0x00 0.--31. 1. "DLPV,Data learning pattern value"
rgroup.long 0x194++0x03
line.long 0x00 "FAILA_ADDR,Flash Memory A Failing Address Status Register"
hexmask.long 0x00 0.--31. 1. "ADDR,Failing address for flash memory A"
repeat 64. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x200)++0x03
line.long 0x00 "RBDR[$1],RX Buffer Data Register $1"
hexmask.long 0x00 0.--31. 1. "RXDATA,RX data"
repeat.end
group.long 0x300++0x03
line.long 0x00 "LUTKEY,LUT Key Register"
hexmask.long 0x00 0.--31. 1. "KEY,Key to lock or unlock the LUT"
group.long 0x304++0x03
line.long 0x00 "LCKCR,LUT Lock Configuration Register"
bitfld.long 0x00 1. "UNLOCK,Unlock LUT" "0,1"
bitfld.long 0x00 0. "LOCK,Lock LUT" "0,1"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x310)++0x03
line.long 0x00 "LUT$1,LUT Register"
bitfld.long 0x00 26.--31. "INSTR1,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: id11"
newline
hexmask.long.byte 0x00 16.--23. 1. "OPRND1,Operand for INSTR1"
bitfld.long 0x00 10.--15. "INSTR0,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: id11"
hexmask.long.byte 0x00 0.--7. 1. "OPRND0,Operand for INSTR0"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x350)++0x03
line.long 0x00 "LUT$1,LUT Register"
bitfld.long 0x00 26.--31. "INSTR1,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: id11"
newline
hexmask.long.byte 0x00 16.--23. 1. "OPRND1,Operand for INSTR1"
bitfld.long 0x00 10.--15. "INSTR0,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: id11"
hexmask.long.byte 0x00 0.--7. 1. "OPRND0,Operand for INSTR0"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x390)++0x03
line.long 0x00 "LUT$1,LUT Register"
bitfld.long 0x00 26.--31. "INSTR1,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: id11"
newline
hexmask.long.byte 0x00 16.--23. 1. "OPRND1,Operand for INSTR1"
bitfld.long 0x00 10.--15. "INSTR0,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: id11"
hexmask.long.byte 0x00 0.--7. 1. "OPRND0,Operand for INSTR0"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x3D0)++0x03
line.long 0x00 "LUT$1,LUT Register"
bitfld.long 0x00 26.--31. "INSTR1,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: id11"
newline
hexmask.long.byte 0x00 16.--23. 1. "OPRND1,Operand for INSTR1"
bitfld.long 0x00 10.--15. "INSTR0,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: id11"
hexmask.long.byte 0x00 0.--7. 1. "OPRND0,Operand for INSTR0"
repeat.end
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x410)++0x03
line.long 0x00 "LUT$1,LUT Register"
bitfld.long 0x00 26.--31. "INSTR1,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: id11"
newline
hexmask.long.byte 0x00 16.--23. 1. "OPRND1,Operand for INSTR1"
bitfld.long 0x00 10.--15. "INSTR0,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: id11"
hexmask.long.byte 0x00 0.--7. 1. "OPRND0,Operand for INSTR0"
repeat.end
tree.end
tree "QUADSPI_ARDB (ARDB)"
base ad:0x41000000
repeat 128. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x00)++0x03
line.long 0x00 "ARDB[$1],AHB RX Data Buffer Register $1"
hexmask.long 0x00 0.--31. 1. "ARXD,ARDB provided RX buffer data"
repeat.end
tree.end
tree "RESET (Reset Control)"
base ad:0x440D4000
group.long 0x04++0x03
line.long 0x00 "RD1_CTRL_REG,Software Reset Domain 1 Control"
bitfld.long 0x00 31. "RD1_CTRL_UNLOCK,Reset Domain 1 Control Register Unlock" "0: Locked and cannot be updated except for this..,1: Unlocked and can be updated"
newline
bitfld.long 0x00 3. "RD1_INTERCONNECT_INTERFACE_DISABLE,Interconnect Interface Disable For Software Reset Domain 1" "0: ENABLES,1: DISABLES"
rgroup.long 0x84++0x03
line.long 0x00 "RD1_STAT_REG,Software Reset Domain 1 Status"
bitfld.long 0x00 4. "RD1_INTERCONNECT_INTERFACE_DISABLE_STAT,Interconnect Interface Disable Acknowledgment Status" "0: ENABLES,1: DISABLES"
newline
bitfld.long 0x00 3. "RD1_INTERCONNECT_INTERFACE_DISABLE_REQ_ACK_STAT,Interconnect Interface Disable Request Acknowledgment Status" "0: Not acknowledged,1: Acknowledged"
tree.end
tree "SDA_AP"
base edp:0x0700
rgroup.long 0x00++0x03
line.long 0x00 "AUTH_STATUS,Authentication Status"
bitfld.long 0x00 31. "HSEDBGEN,HSE_M Debug Enabled" "0,1"
bitfld.long 0x00 30. "APPDBGEN,Application Debug Enabled" "0,1"
bitfld.long 0x00 2. "UIDREADY,UID Ready" "0,1"
newline
bitfld.long 0x00 0. "CHALRDY,Challenge Ready" "0,1"
wgroup.long 0x04++0x03
line.long 0x00 "AUTH_CONTROL,Authentication Control"
bitfld.long 0x00 1. "HSENEWDATACTL,HSE_M New Data Control" "0,1"
bitfld.long 0x00 0. "HSEAUTHREQ,HSE_M Authentication Request" "0,1"
repeat 8. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x10)++0x03
line.long 0x00 "KEYCHAL[$1],HSE_M Key Challenge $1"
hexmask.long 0x00 0.--31. 1. "HSEKeychallenge,HSE_M Key Challenge"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x4)
group.long ($2+0x40)++0x03
line.long 0x00 "KEYRESP[$1],HSE_M Key Response $1"
hexmask.long 0x00 0.--31. 1. "HSEKeyresponse,Debugger Key Response"
repeat.end
rgroup.long 0x70++0x03
line.long 0x00 "SDA_UID0,SDA UID0"
hexmask.long 0x00 0.--31. 1. "SDAUID0,JTAG User ID Bits Lower Word"
rgroup.long 0x74++0x03
line.long 0x00 "SDA_UID1,SDA UID1"
hexmask.long 0x00 0.--31. 1. "SDAUID1,JTAG User ID Bits Upper Word"
group.long 0x80++0x03
line.long 0x00 "DEBUG_ENABLE_CTRL,Debug Enable Control"
bitfld.long 0x00 31. "CSPNIDEN,Controls SPNIDEN of debug blocks coupled with core subsystems (ETM ITM and CTIs)" "0: CSPNIDEN_0,1: CSPNIDEN_1"
bitfld.long 0x00 30. "CSPIDEN,Controls SPIDEN of debug blocks coupled with core subsystems (ETM ITM and CTIs)" "0: CSPIDEN_0,1: CSPIDEN_1"
bitfld.long 0x00 29. "CNIDEN,Controls NIDEN of debug blocks coupled with core subsystems (ETM ITM and CTIs)" "0: CNIDEN_0,1: CNIDEN_1"
newline
bitfld.long 0x00 28. "CDBGEN,Controls DBGEN of debug blocks coupled with core subsystems (ETM ITM and CTIs)" "0: CDBGEN_0,1: CDBGEN_1"
bitfld.long 0x00 7. "GSPNIDEN,Controls SPNIDEN of NoC probes and observers and the BBE32EP DSP core" "0: GSPNIDEN_0,1: GSPNIDEN_1"
bitfld.long 0x00 6. "GSPIDEN,Controls SPIDEN of NoC probes and observers and the BBE32EP DSP core" "0: GSPIDEN_0,1: GSPIDEN_1"
newline
bitfld.long 0x00 5. "GNIDEN,Controls NIDEN of NoC probes and observers CTIs and BBE32EP DSP core" "0: GNIDEN_0,1: GNIDEN_1"
bitfld.long 0x00 4. "GDBGEN,Global Debug Enable" "0: GDBGEN_0,1: GDBGEN_1"
group.long 0xA4++0x03
line.long 0x00 "GENERIC_CTRL_0,Generic Control 0"
rbitfld.long 0x00 0. "SDAAP_CR_EN,SDAAP CR Enable" "0: Function performed on the basis of JDC,1: Function performed on the basis of SDA_AP"
rgroup.long 0xFC++0x03
line.long 0x00 "SDA_AP_ID,SDA_AP Identification"
hexmask.long 0x00 0.--31. 1. "ID,SDA_AP Identity"
tree.end
tree "SECURITY (Security subsystem)"
base ad:0x400D8900
rgroup.long 0x08++0x03
line.long 0x00 "MISCDAT0,Miscellaneous Data 0"
bitfld.long 0x00 0. "EDB,External Debugger Connectivity Status" "0: Not connected,1: Connected"
rgroup.long 0x1C++0x03
line.long 0x00 "HSE_GPR0,HSE GPR"
hexmask.long 0x00 7.--31. 1. "DATA1,General Purpose Data 1"
bitfld.long 0x00 6. "EDB,External Debugger Connectivity Status" "0: Not connected,1: Connected"
bitfld.long 0x00 0.--5. "DATA0,General Purpose Data 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 11. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 )
rgroup.long ($2+0x20)++0x03
line.long 0x00 "HSE_GPR$1,HSE GPR"
hexmask.long 0x00 0.--31. 1. "DATA,General Purpose Data"
repeat.end
rgroup.long 0x4C++0x03
line.long 0x00 "HSE_GPR12,HSE GPR"
bitfld.long 0x00 0. "SW_DEBUG_EN,Software Debug Enable" "0: Disable,1: Enable"
tree.end
tree "SELFTEST_GPR"
tree "SELFTEST_GPR_APP_MAIN_LBIST_PARTITION"
base ad:0x400B41A0
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree "SELFTEST_GPR_APP_MEM_LBIST_PARTITION"
base ad:0x400B41C0
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree "SELFTEST_GPR_APP_NOC_REST_LBIST_PARTITION"
base ad:0x400B4220
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree "SELFTEST_GPR_CLUSTER0"
base ad:0x400B40A0
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree "SELFTEST_GPR_CM7_0_LBIST_PARTITION"
base ad:0x400B4020
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree "SELFTEST_GPR_CM7_1_LBIST_PARTITION"
base ad:0x400B4040
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree "SELFTEST_GPR_CORE_NIU_LBIST_PARTITION"
base ad:0x400B4200
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree "SELFTEST_GPR_HSE_RUN_LBIST_PARTITION"
base ad:0x400B4000
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree "SELFTEST_GPR_MIPICSI2_SS_1"
base ad:0x400B40E0
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree "SELFTEST_GPR_RADAR_NIU_LBIST_PARTITION"
base ad:0x400B41E0
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree "SELFTEST_GPR_RADAR_SS"
base ad:0x400B4060
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree "SELFTEST_GPR_RADAR_SS_SPT_PARTITION"
base ad:0x400B4080
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree "SELFTEST_GPR_RT_AXBS0_LBIST_PARTITION"
base ad:0x400B4180
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree "SELFTEST_GPR_RT_AXBS1_LBIST_PARTITION"
base ad:0x400B4160
group.long 0x00++0x03
line.long 0x00 "Generic_Reg0,Generic 0"
bitfld.long 0x00 8. "pcs_enable_end,PCS Enable End" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 7. "pcs_enable_start,PCS Enable Start" "0: DISABLES,1: ENABLES"
bitfld.long 0x00 4.--6. "pcs_step_size,PCS Step Size" "0: Number of patterns - 1,1: Number of patterns - 1,2: Number of patterns - 1,3: Number of patterns - 1,4: Number of patterns - 1,5: Number of patterns - 1,6: Number of patterns - 1,7: Number of patterns - 1"
group.long 0x14++0x03
line.long 0x00 "LBIST_Prog_Reg,LBIST Program"
hexmask.long.byte 0x00 0.--7. 1. "LBIST_shift_count,LBIST Shift Count"
tree.end
tree.end
tree "SELFTEST_GPR_TOP"
base ad:0x400B4FE0
group.long 0x00++0x03
line.long 0x00 "Reset_Domain_Selftest_Enable_Register,Reset Domain n Self-Test Enable"
bitfld.long 0x00 1. "RESET_DOMAIN_1_SELFTEST_ENABLE,Reset Domain n Self-Test Enable" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 0. "RESET_DOMAIN_0_SELFTEST_ENABLE,Reset Domain n Self-Test Enable" "0: DISABLED,1: ENABLED"
group.long 0x04++0x03
line.long 0x00 "Reset_Domain_Selftest_Enable_Status_Register,Reset Domain n Self-Test Enable Status"
eventfld.long 0x00 17. "RESET_DOMAIN_1_SELFTEST_ENABLE_LAST_RUN_STATUS,Reset Domain n Self-Test Enable Last Run Status" "0: DISABLED,1: ENABLED"
newline
eventfld.long 0x00 16. "RESET_DOMAIN_0_SELFTEST_ENABLE_LAST_RUN_STATUS,Reset Domain n Self-Test Enable Last Run Status" "0: DISABLED,1: ENABLED"
newline
rbitfld.long 0x00 1. "RESET_DOMAIN_1_SELFTEST_ENABLE_STATUS,Reset Domain n Self-Test Enable Status" "0: DISABLED,1: ENABLED"
newline
rbitfld.long 0x00 0. "RESET_DOMAIN_0_SELFTEST_ENABLE_STATUS,Reset Domain n Self-Test Enable Status" "0: DISABLED,1: ENABLED"
tree.end
tree "SEMA42"
repeat 2. (list 0. 1.) (list ad:0x4044C000 ad:0x44010000)
tree "SEMA42_$1"
base $2
repeat 16. (strings "3" "2" "1" "0" "7" "6" "5" "4" "11" "10" "9" "8" "15" "14" "13" "12" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x00)++0x00
line.byte 0x00 "GATE$1,Gate"
bitfld.byte 0x00 0.--3. "GTFSM,Gate Finite State Machine" "0: The gate is unlocked (free),1: Domain 0 locked the gate,2: Domain 1 locked the gate,3: Domain 2 locked the gate,4: Domain 3 locked the gate,5: Domain 4 locked the gate,6: Domain 5 locked the gate,7: Domain 6 locked the gate,8: Domain 7 locked the gate,9: Domain 8 locked the gate,10: Domain 9 locked the gate,11: Domain 10 locked the gate,12: Domain 11 locked the gate,13: Domain 12 locked the gate,14: Domain 13 locked the gate,15: Domain 14 locked the gate"
repeat.end
rgroup.word 0x42++0x01
line.word 0x00 "RSTGT_R,Reset Gate"
bitfld.word 0x00 12.--13. "RSTGSM,Reset Gate Finite State Machine" "0: Idle waiting for the first data pattern,1: Waiting for the second data pattern,2: The 2-write sequence has completed,?..."
bitfld.word 0x00 8.--11. "RSTGMS,Reset Gate Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.word.byte 0x00 0.--7. 1. "RSTGTN,Reset Gate Number"
wgroup.word 0x42++0x01
line.word 0x00 "RSTGT_W,Reset Gate"
hexmask.word.byte 0x00 8.--15. 1. "RSTGDP,Reset Gate Data Pattern"
hexmask.word.byte 0x00 0.--7. 1. "RSTGTN,Reset Gate Number"
tree.end
repeat.end
tree.end
tree "SIUL2"
base ad:0x40100000
rgroup.long 0x04++0x03
line.long 0x00 "MIDR1,SIUL2 MCU ID 1"
bitfld.long 0x00 26.--31. "PRODUCT_LINE_LETTER,Product Line Letter" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,18: PRODUCT_LINE_LETTER_18,?..."
hexmask.long.word 0x00 16.--25. 1. "FAMILY_NO,Family Number"
newline
bitfld.long 0x00 4.--7. "MAJOR_MASK,Major Mask Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "MINOR_MASK,Minor Mask Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x08++0x03
line.long 0x00 "MIDR2,SIUL2 MCU ID 2"
bitfld.long 0x00 29.--31. "TECHNOLOGY,Technology" "?,?,2: TECHNOLOGY_2,?..."
bitfld.long 0x00 26.--28. "TEMPERATURE,Temperature" "0: TEMPERATURE_0,?..."
newline
bitfld.long 0x00 20.--25. "PACKAGE,Package" "0: PACKAGE_0,?..."
bitfld.long 0x00 18. "BBE,BBE" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 17. "CANFD,CANFD" "0: Disabled,1: CANFD_1"
bitfld.long 0x00 14. "MIPI,MIPI" "0: One instance of MIPICSI2,1: Two instances of MIPICSI2"
newline
hexmask.long.byte 0x00 7.--13. 1. "PERFORMANCE_LETTER,Performance letter"
hexmask.long.byte 0x00 0.--6. 1. "CONFIG_LETTER,Configuration letter"
group.long 0x10++0x03
line.long 0x00 "DISR0,SIUL2 DMA/Interrupt Status Flag 0"
eventfld.long 0x00 31. "EIF31,External Interrupt Status Flag 31" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER31 and.."
eventfld.long 0x00 30. "EIF30,External Interrupt Status Flag 30" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER30 and.."
newline
eventfld.long 0x00 29. "EIF29,External Interrupt Status Flag 29" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER29 and.."
eventfld.long 0x00 28. "EIF28,External Interrupt Status Flag 28" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER28 and.."
newline
eventfld.long 0x00 27. "EIF27,External Interrupt Status Flag 27" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER27 and.."
eventfld.long 0x00 26. "EIF26,External Interrupt Status Flag 26" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER26 and.."
newline
eventfld.long 0x00 25. "EIF25,External Interrupt Status Flag 25" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER25 and.."
eventfld.long 0x00 24. "EIF24,External Interrupt Status Flag 24" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER24 and.."
newline
eventfld.long 0x00 23. "EIF23,External Interrupt Status Flag 23" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER23 and.."
eventfld.long 0x00 22. "EIF22,External Interrupt Status Flag 22" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER22 and.."
newline
eventfld.long 0x00 21. "EIF21,External Interrupt Status Flag 21" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER21 and.."
eventfld.long 0x00 20. "EIF20,External Interrupt Status Flag 20" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER20 and.."
newline
eventfld.long 0x00 19. "EIF19,External Interrupt Status Flag 19" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER19 and.."
eventfld.long 0x00 18. "EIF18,External Interrupt Status Flag 18" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER18 and.."
newline
eventfld.long 0x00 17. "EIF17,External Interrupt Status Flag 17" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER17 and.."
eventfld.long 0x00 16. "EIF16,External Interrupt Status Flag 16" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER16 and.."
newline
eventfld.long 0x00 15. "EIF15,External Interrupt Status Flag 15" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER15 and.."
eventfld.long 0x00 14. "EIF14,External Interrupt Status Flag 14" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER14 and.."
newline
eventfld.long 0x00 13. "EIF13,External Interrupt Status Flag 13" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER13 and.."
eventfld.long 0x00 12. "EIF12,External Interrupt Status Flag 12" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER12 and.."
newline
eventfld.long 0x00 11. "EIF11,External Interrupt Status Flag 11" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER11 and.."
eventfld.long 0x00 10. "EIF10,External Interrupt Status Flag 10" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER10 and.."
newline
eventfld.long 0x00 9. "EIF9,External Interrupt Status Flag 9" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER9 and.."
eventfld.long 0x00 8. "EIF8,External Interrupt Status Flag 8" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER8 and.."
newline
eventfld.long 0x00 7. "EIF7,External Interrupt Status Flag 7" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER7 and.."
eventfld.long 0x00 6. "EIF6,External Interrupt Status Flag 6" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER6 and.."
newline
eventfld.long 0x00 5. "EIF5,External Interrupt Status Flag 5" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER5 and.."
eventfld.long 0x00 4. "EIF4,External Interrupt Status Flag 4" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER4 and.."
newline
eventfld.long 0x00 3. "EIF3,External Interrupt Status Flag 3" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER3 and.."
eventfld.long 0x00 2. "EIF2,External Interrupt Status Flag 2" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER2 and.."
newline
eventfld.long 0x00 1. "EIF1,External Interrupt Status Flag 1" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER1 and.."
eventfld.long 0x00 0. "EIF0,External Interrupt Status Flag 0" "0: No interrupt event has occurred on the pad,1: An interrupt event as defined by IREER0 and.."
group.long 0x18++0x03
line.long 0x00 "DIRER0,SIUL2 DMA/Interrupt Request Enable 0"
bitfld.long 0x00 31. "EIRE31,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 30. "EIRE30,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 29. "EIRE29,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 28. "EIRE28,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 27. "EIRE27,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 26. "EIRE26,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 25. "EIRE25,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 24. "EIRE24,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 23. "EIRE23,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 22. "EIRE22,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 21. "EIRE21,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 20. "EIRE20,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 19. "EIRE19,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 18. "EIRE18,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 17. "EIRE17,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 16. "EIRE16,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 15. "EIRE15,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 14. "EIRE14,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 13. "EIRE13,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 12. "EIRE12,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 11. "EIRE11,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 10. "EIRE10,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 9. "EIRE9,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 8. "EIRE8,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 7. "EIRE7,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 6. "EIRE6,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 5. "EIRE5,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 4. "EIRE4,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 3. "EIRE3,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 2. "EIRE2,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
newline
bitfld.long 0x00 1. "EIRE1,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
bitfld.long 0x00 0. "EIRE0,External Interrupt Request Enable" "0: EIRE_DISABLED,1: EIRE_ENABLED"
group.long 0x20++0x03
line.long 0x00 "DIRSR0,SIUL2 DMA/Interrupt Request Select 0"
bitfld.long 0x00 31. "DIRSR31,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 30. "DIRSR30,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 29. "DIRSR29,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 28. "DIRSR28,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 27. "DIRSR27,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 26. "DIRSR26,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 25. "DIRSR25,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 24. "DIRSR24,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 23. "DIRSR23,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 22. "DIRSR22,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 21. "DIRSR21,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 20. "DIRSR20,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 19. "DIRSR19,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 18. "DIRSR18,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 17. "DIRSR17,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 16. "DIRSR16,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 15. "DIRSR15,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 14. "DIRSR14,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 13. "DIRSR13,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 12. "DIRSR12,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 11. "DIRSR11,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 10. "DIRSR10,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 9. "DIRSR9,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 8. "DIRSR8,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 7. "DIRSR7,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 6. "DIRSR6,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 5. "DIRSR5,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 4. "DIRSR4,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 3. "DIRSR3,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 2. "DIRSR2,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
newline
bitfld.long 0x00 1. "DIRSR1,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
bitfld.long 0x00 0. "DIRSR0,DMA/Interrupt Request Select Register" "0: Interrupt request,1: DMA request"
group.long 0x28++0x03
line.long 0x00 "IREER0,SIUL2 Interrupt Rising-Edge Event Enable 0"
bitfld.long 0x00 31. "IREE31,Enables rising-edge events to set DISR0[EIF31]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 30. "IREE30,Enables rising-edge events to set DISR0[EIF30]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 29. "IREE29,Enables rising-edge events to set DISR0[EIF29]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 28. "IREE28,Enables rising-edge events to set DISR0[EIF28]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 27. "IREE27,Enables rising-edge events to set DISR0[EIF27]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 26. "IREE26,Enables rising-edge events to set DISR0[EIF26]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 25. "IREE25,Enables rising-edge events to set DISR0[EIF25]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 24. "IREE24,Enables rising-edge events to set DISR0[EIF24]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 23. "IREE23,Enables rising-edge events to set DISR0[EIF23]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 22. "IREE22,Enables rising-edge events to set DISR0[EIF22]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 21. "IREE21,Enables rising-edge events to set DISR0[EIF21]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 20. "IREE20,Enables rising-edge events to set DISR0[EIF20]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 19. "IREE19,Enables rising-edge events to set DISR0[EIF19]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 18. "IREE18,Enables rising-edge events to set DISR0[EIF18]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 17. "IREE17,Enables rising-edge events to set DISR0[EIF17]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 16. "IREE16,Enables rising-edge events to set DISR0[EIF16]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 15. "IREE15,Enables rising-edge events to set DISR0[EIF15]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 14. "IREE14,Enables rising-edge events to set DISR0[EIF14]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 13. "IREE13,Enables rising-edge events to set DISR0[EIF13]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 12. "IREE12,Enables rising-edge events to set DISR0[EIF12]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 11. "IREE11,Enables rising-edge events to set DISR0[EIF11]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 10. "IREE10,Enables rising-edge events to set DISR0[EIF10]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 9. "IREE9,Enables rising-edge events to set DISR0[EIF9]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 8. "IREE8,Enables rising-edge events to set DISR0[EIF8]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 7. "IREE7,Enables rising-edge events to set DISR0[EIF7]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 6. "IREE6,Enables rising-edge events to set DISR0[EIF6]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 5. "IREE5,Enables rising-edge events to set DISR0[EIF5]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 4. "IREE4,Enables rising-edge events to set DISR0[EIF4]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 3. "IREE3,Enables rising-edge events to set DISR0[EIF3]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 2. "IREE2,Enables rising-edge events to set DISR0[EIF2]" "0: IREE_DISABLED,1: IREE_ENABLED"
newline
bitfld.long 0x00 1. "IREE1,Enables rising-edge events to set DISR0[EIF1]" "0: IREE_DISABLED,1: IREE_ENABLED"
bitfld.long 0x00 0. "IREE0,Enables rising-edge events to set DISR0[EIF0]" "0: IREE_DISABLED,1: IREE_ENABLED"
group.long 0x30++0x03
line.long 0x00 "IFEER0,SIUL2 Interrupt Falling-Edge Event Enable 0"
bitfld.long 0x00 31. "IFEE31,Enables falling-edge events to set DISR0[EIF31]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 30. "IFEE30,Enables falling-edge events to set DISR0[EIF30]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 29. "IFEE29,Enables falling-edge events to set DISR0[EIF29]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 28. "IFEE28,Enables falling-edge events to set DISR0[EIF28]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 27. "IFEE27,Enables falling-edge events to set DISR0[EIF27]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 26. "IFEE26,Enables falling-edge events to set DISR0[EIF26]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 25. "IFEE25,Enables falling-edge events to set DISR0[EIF25]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 24. "IFEE24,Enables falling-edge events to set DISR0[EIF24]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 23. "IFEE23,Enables falling-edge events to set DISR0[EIF23]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 22. "IFEE22,Enables falling-edge events to set DISR0[EIF22]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 21. "IFEE21,Enables falling-edge events to set DISR0[EIF21]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 20. "IFEE20,Enables falling-edge events to set DISR0[EIF20]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 19. "IFEE19,Enables falling-edge events to set DISR0[EIF19]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 18. "IFEE18,Enables falling-edge events to set DISR0[EIF18]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 17. "IFEE17,Enables falling-edge events to set DISR0[EIF17]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 16. "IFEE16,Enables falling-edge events to set DISR0[EIF16]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 15. "IFEE15,Enables falling-edge events to set DISR0[EIF15]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 14. "IFEE14,Enables falling-edge events to set DISR0[EIF14]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 13. "IFEE13,Enables falling-edge events to set DISR0[EIF13]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 12. "IFEE12,Enables falling-edge events to set DISR0[EIF12]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 11. "IFEE11,Enables falling-edge events to set DISR0[EIF11]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 10. "IFEE10,Enables falling-edge events to set DISR0[EIF10]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 9. "IFEE9,Enables falling-edge events to set DISR0[EIF9]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 8. "IFEE8,Enables falling-edge events to set DISR0[EIF8]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 7. "IFEE7,Enables falling-edge events to set DISR0[EIF7]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 6. "IFEE6,Enables falling-edge events to set DISR0[EIF6]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 5. "IFEE5,Enables falling-edge events to set DISR0[EIF5]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 4. "IFEE4,Enables falling-edge events to set DISR0[EIF4]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 3. "IFEE3,Enables falling-edge events to set DISR0[EIF3]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 2. "IFEE2,Enables falling-edge events to set DISR0[EIF2]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
newline
bitfld.long 0x00 1. "IFEE1,Enables falling-edge events to set DISR0[EIF1]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
bitfld.long 0x00 0. "IFEE0,Enables falling-edge events to set DISR0[EIF0]" "0: IFEE_DISABLED,1: IFEE_ENABLED"
group.long 0x38++0x03
line.long 0x00 "IFER0,SIUL2 Interrupt Filter Enable 0"
bitfld.long 0x00 31. "IFE31,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 30. "IFE30,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 29. "IFE29,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 28. "IFE28,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 27. "IFE27,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 26. "IFE26,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 25. "IFE25,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 24. "IFE24,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 23. "IFE23,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 22. "IFE22,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 21. "IFE21,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 20. "IFE20,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 19. "IFE19,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 18. "IFE18,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 17. "IFE17,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 16. "IFE16,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 15. "IFE15,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 14. "IFE14,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 13. "IFE13,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 12. "IFE12,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 11. "IFE11,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 10. "IFE10,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 9. "IFE9,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 8. "IFE8,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 7. "IFE7,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 6. "IFE6,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 5. "IFE5,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 4. "IFE4,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 3. "IFE3,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 2. "IFE2,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
newline
bitfld.long 0x00 1. "IFE1,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
bitfld.long 0x00 0. "IFE0,Enables digital glitch filter on the interrupt pad input" "0: IFE_DISABLED,1: IFE_ENABLED"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x40)++0x03
line.long 0x00 "IFMCR$1,SIUL2 Interrupt Filter Maximum Counter"
bitfld.long 0x00 0.--3. "MAXCNT,Maximum Interrupt Filter Counter setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x80)++0x03
line.long 0x00 "IFMCR$1,SIUL2 Interrupt Filter Maximum Counter"
bitfld.long 0x00 0.--3. "MAXCNT,Maximum Interrupt Filter Counter setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
group.long 0xC0++0x03
line.long 0x00 "IFCPR,SIUL2 Interrupt Filter Clock Prescaler"
bitfld.long 0x00 0.--3. "IFCP,Interrupt Filter Clock Prescaler setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x200++0x03
line.long 0x00 "MIDR3,SIUL2 MCU ID 3"
bitfld.long 0x00 26.--31. "PROD_FAM_LET,Product Family Letter" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,19: PROD_FAM_LET_19,?..."
hexmask.long.word 0x00 16.--25. 1. "PROD_FAM_NO,Product Family Number"
newline
bitfld.long 0x00 10.--15. "PART_NO_SUF,Part Number Suffix" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,18: PART_NO_SUF_18,?..."
rgroup.long 0x204++0x03
line.long 0x00 "MIDR4,SIUL2 MCU ID 4"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x240)++0x03
line.long 0x00 "MSCR$1,SIUL2 Multiplexed Signal Configuration"
bitfld.long 0x00 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled"
bitfld.long 0x00 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1"
newline
bitfld.long 0x00 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "PUE,Pull Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 12. "PUS,Pull Select" "0: Pull down,1: Pull up"
newline
bitfld.long 0x00 10. "RCVR,Receiver Select" "0: Enables the differential VREF based receiver,1: Enables the single ended CMOS receiver"
bitfld.long 0x00 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable"
newline
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "MSCR$1,SIUL2 Multiplexed Signal Configuration"
bitfld.long 0x00 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled"
bitfld.long 0x00 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1"
newline
bitfld.long 0x00 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "PUE,Pull Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 12. "PUS,Pull Select" "0: Pull down,1: Pull up"
newline
bitfld.long 0x00 10. "RCVR,Receiver Select" "0: Enables the differential VREF based receiver,1: Enables the single ended CMOS receiver"
bitfld.long 0x00 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable"
newline
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x2C0)++0x03
line.long 0x00 "MSCR$1,SIUL2 Multiplexed Signal Configuration"
bitfld.long 0x00 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled"
bitfld.long 0x00 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1"
newline
bitfld.long 0x00 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "PUE,Pull Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 12. "PUS,Pull Select" "0: Pull down,1: Pull up"
newline
bitfld.long 0x00 10. "RCVR,Receiver Select" "0: Enables the differential VREF based receiver,1: Enables the single ended CMOS receiver"
bitfld.long 0x00 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable"
newline
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x300)++0x03
line.long 0x00 "MSCR$1,SIUL2 Multiplexed Signal Configuration"
bitfld.long 0x00 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled"
bitfld.long 0x00 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1"
newline
bitfld.long 0x00 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "PUE,Pull Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 12. "PUS,Pull Select" "0: Pull down,1: Pull up"
newline
bitfld.long 0x00 10. "RCVR,Receiver Select" "0: Enables the differential VREF based receiver,1: Enables the single ended CMOS receiver"
bitfld.long 0x00 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable"
newline
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x340)++0x03
line.long 0x00 "MSCR$1,SIUL2 Multiplexed Signal Configuration"
bitfld.long 0x00 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled"
bitfld.long 0x00 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1"
newline
bitfld.long 0x00 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "PUE,Pull Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 12. "PUS,Pull Select" "0: Pull down,1: Pull up"
newline
bitfld.long 0x00 10. "RCVR,Receiver Select" "0: Enables the differential VREF based receiver,1: Enables the single ended CMOS receiver"
bitfld.long 0x00 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable"
newline
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" "90" "91" "92" "93" "94" "95" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x380)++0x03
line.long 0x00 "MSCR$1,SIUL2 Multiplexed Signal Configuration"
bitfld.long 0x00 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled"
bitfld.long 0x00 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1"
newline
bitfld.long 0x00 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "PUE,Pull Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 12. "PUS,Pull Select" "0: Pull down,1: Pull up"
newline
bitfld.long 0x00 10. "RCVR,Receiver Select" "0: Enables the differential VREF based receiver,1: Enables the single ended CMOS receiver"
bitfld.long 0x00 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable"
newline
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 11. (strings "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" "106" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 )
group.long ($2+0x3C0)++0x03
line.long 0x00 "MSCR$1,SIUL2 Multiplexed Signal Configuration"
bitfld.long 0x00 21. "OBE,GPIO Output Buffer Enable" "0: Output driver disabled,1: Output driver enabled"
bitfld.long 0x00 20. "ODE,Open Drain Enable" "0: Open drain function disabled,1: Open drain function enabled when OBE is also 1"
newline
bitfld.long 0x00 19. "IBE,Input Buffer Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 14.--16. "SRE,Slew Rate Control" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 13. "PUE,Pull Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 12. "PUS,Pull Select" "0: Pull down,1: Pull up"
newline
bitfld.long 0x00 10. "RCVR,Receiver Select" "0: Enables the differential VREF based receiver,1: Enables the single ended CMOS receiver"
bitfld.long 0x00 5. "SMC,Safe Mode Control" "0: Disable (The output buffer returns to its..,1: Don't disable"
newline
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xA40)++0x03
line.long 0x00 "IMCR$1,SIUL2 Input Multiplexed Signal Configuration"
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xA80)++0x03
line.long 0x00 "IMCR$1,SIUL2 Input Multiplexed Signal Configuration"
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "54" "55" "56" "57" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x58 0x5C 0x60 0x64 )
group.long ($2+0xAC0)++0x03
line.long 0x00 "IMCR$1,SIUL2 Input Multiplexed Signal Configuration"
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "58" "59" "60" "61" "62" "63" "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xB28)++0x03
line.long 0x00 "IMCR$1,SIUL2 Input Multiplexed Signal Configuration"
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "74" "75" "76" "77" "78" "79" "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xB68)++0x03
line.long 0x00 "IMCR$1,SIUL2 Input Multiplexed Signal Configuration"
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "90" "91" "92" "93" "94" "95" "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xBA8)++0x03
line.long 0x00 "IMCR$1,SIUL2 Input Multiplexed Signal Configuration"
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 2. (strings "106" "107" )(list 0x00 0x04 )
group.long ($2+0xBE8)++0x03
line.long 0x00 "IMCR$1,SIUL2 Input Multiplexed Signal Configuration"
bitfld.long 0x00 0.--2. "SSS,Source Signal Select" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (strings "3" "2" "1" "0" "7" "6" "5" "4" "11" "10" "9" "8" "15" "14" "13" "12" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
group.byte ($2+0x1300)++0x00
line.byte 0x00 "GPDO$1,SIUL2 GPIO Pad Data Output"
bitfld.byte 0x00 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High"
repeat.end
repeat 16. (strings "19" "18" "17" "16" "23" "22" "21" "20" "27" "26" "25" "24" "31" "30" "29" "28" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
group.byte ($2+0x1310)++0x00
line.byte 0x00 "GPDO$1,SIUL2 GPIO Pad Data Output"
bitfld.byte 0x00 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High"
repeat.end
repeat 16. (strings "35" "34" "33" "32" "39" "38" "37" "36" "43" "42" "41" "40" "47" "46" "45" "44" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
group.byte ($2+0x1320)++0x00
line.byte 0x00 "GPDO$1,SIUL2 GPIO Pad Data Output"
bitfld.byte 0x00 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High"
repeat.end
repeat 16. (strings "51" "50" "49" "48" "55" "54" "53" "52" "59" "58" "57" "56" "63" "62" "61" "60" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
group.byte ($2+0x1330)++0x00
line.byte 0x00 "GPDO$1,SIUL2 GPIO Pad Data Output"
bitfld.byte 0x00 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High"
repeat.end
repeat 16. (strings "67" "66" "65" "64" "71" "70" "69" "68" "75" "74" "73" "72" "79" "78" "77" "76" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
group.byte ($2+0x1340)++0x00
line.byte 0x00 "GPDO$1,SIUL2 GPIO Pad Data Output"
bitfld.byte 0x00 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High"
repeat.end
repeat 12. (strings "83" "82" "81" "80" "87" "86" "85" "84" "91" "90" "89" "88" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B )
group.byte ($2+0x1350)++0x00
line.byte 0x00 "GPDO$1,SIUL2 GPIO Pad Data Output"
bitfld.byte 0x00 0. "PDO_n,Pad Data Out" "0: Pad Data Out Low,1: Pad Data Out High"
repeat.end
repeat 16. (strings "3" "2" "1" "0" "7" "6" "5" "4" "11" "10" "9" "8" "15" "14" "13" "12" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
rgroup.byte ($2+0x1500)++0x00
line.byte 0x00 "GPDI$1,SIUL2 GPIO Pad Data Input"
bitfld.byte 0x00 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High"
repeat.end
repeat 16. (strings "19" "18" "17" "16" "23" "22" "21" "20" "27" "26" "25" "24" "31" "30" "29" "28" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
rgroup.byte ($2+0x1510)++0x00
line.byte 0x00 "GPDI$1,SIUL2 GPIO Pad Data Input"
bitfld.byte 0x00 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High"
repeat.end
repeat 16. (strings "35" "34" "33" "32" "39" "38" "37" "36" "43" "42" "41" "40" "47" "46" "45" "44" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
rgroup.byte ($2+0x1520)++0x00
line.byte 0x00 "GPDI$1,SIUL2 GPIO Pad Data Input"
bitfld.byte 0x00 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High"
repeat.end
repeat 16. (strings "51" "50" "49" "48" "55" "54" "53" "52" "59" "58" "57" "56" "63" "62" "61" "60" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
rgroup.byte ($2+0x1530)++0x00
line.byte 0x00 "GPDI$1,SIUL2 GPIO Pad Data Input"
bitfld.byte 0x00 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High"
repeat.end
repeat 16. (strings "67" "66" "65" "64" "71" "70" "69" "68" "75" "74" "73" "72" "79" "78" "77" "76" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
rgroup.byte ($2+0x1540)++0x00
line.byte 0x00 "GPDI$1,SIUL2 GPIO Pad Data Input"
bitfld.byte 0x00 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High"
repeat.end
repeat 12. (strings "83" "82" "81" "80" "87" "86" "85" "84" "91" "90" "89" "88" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B )
rgroup.byte ($2+0x1550)++0x00
line.byte 0x00 "GPDI$1,SIUL2 GPIO Pad Data Input"
bitfld.byte 0x00 0. "PDI_n,Pad Data In" "0: Pad Data In Low,1: Pad Data In High"
repeat.end
repeat 4. (strings "1" "0" "3" "2" )(list 0x00 0x02 0x04 0x06 )
group.word ($2+0x1700)++0x01
line.word 0x00 "PGPDO$1,SIUL2 Parallel GPIO Pad Data Out"
bitfld.word 0x00 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high"
bitfld.word 0x00 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high"
bitfld.word 0x00 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high"
bitfld.word 0x00 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high"
bitfld.word 0x00 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high"
bitfld.word 0x00 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high"
bitfld.word 0x00 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high"
bitfld.word 0x00 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high"
bitfld.word 0x00 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high"
repeat.end
group.word 0x1708++0x01
line.word 0x00 "PGPDO5,SIUL2 Parallel GPIO Pad Data Out"
bitfld.word 0x00 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high"
bitfld.word 0x00 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high"
bitfld.word 0x00 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high"
bitfld.word 0x00 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high"
bitfld.word 0x00 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high"
bitfld.word 0x00 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high"
bitfld.word 0x00 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high"
group.word 0x170A++0x01
line.word 0x00 "PGPDO4,SIUL2 Parallel GPIO Pad Data Out"
bitfld.word 0x00 15. "PPDO15,Parallel Pad Data Out 15" "0: Logic low,1: Logic high"
bitfld.word 0x00 14. "PPDO14,Parallel Pad Data Out 14" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 13. "PPDO13,Parallel Pad Data Out 13" "0: Logic low,1: Logic high"
bitfld.word 0x00 12. "PPDO12,Parallel Pad Data Out 12" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 11. "PPDO11,Parallel Pad Data Out 11" "0: Logic low,1: Logic high"
bitfld.word 0x00 10. "PPDO10,Parallel Pad Data Out 10" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 9. "PPDO9,Parallel Pad Data Out 9" "0: Logic low,1: Logic high"
bitfld.word 0x00 8. "PPDO8,Parallel Pad Data Out 8" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 7. "PPDO7,Parallel Pad Data Out 7" "0: Logic low,1: Logic high"
bitfld.word 0x00 6. "PPDO6,Parallel Pad Data Out 6" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 5. "PPDO5,Parallel Pad Data Out 5" "0: Logic low,1: Logic high"
bitfld.word 0x00 4. "PPDO4,Parallel Pad Data Out 4" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 3. "PPDO3,Parallel Pad Data Out 3" "0: Logic low,1: Logic high"
bitfld.word 0x00 2. "PPDO2,Parallel Pad Data Out 2" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 1. "PPDO1,Parallel Pad Data Out 1" "0: Logic low,1: Logic high"
bitfld.word 0x00 0. "PPDO0,Parallel Pad Data Out 0" "0: Logic low,1: Logic high"
repeat 4. (strings "1" "0" "3" "2" )(list 0x00 0x02 0x04 0x06 )
rgroup.word ($2+0x1740)++0x01
line.word 0x00 "PGPDI$1,SIUL2 Parallel GPIO Pad Data In"
bitfld.word 0x00 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high"
bitfld.word 0x00 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high"
bitfld.word 0x00 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high"
bitfld.word 0x00 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high"
bitfld.word 0x00 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high"
bitfld.word 0x00 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high"
bitfld.word 0x00 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high"
bitfld.word 0x00 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high"
bitfld.word 0x00 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high"
repeat.end
rgroup.word 0x1748++0x01
line.word 0x00 "PGPDI5,SIUL2 Parallel GPIO Pad Data In"
bitfld.word 0x00 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high"
bitfld.word 0x00 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high"
bitfld.word 0x00 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high"
bitfld.word 0x00 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high"
bitfld.word 0x00 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high"
bitfld.word 0x00 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high"
bitfld.word 0x00 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high"
rgroup.word 0x174A++0x01
line.word 0x00 "PGPDI4,SIUL2 Parallel GPIO Pad Data In"
bitfld.word 0x00 15. "PPDI15,Parallel Pad Data In 15" "0: Logic low,1: Logic high"
bitfld.word 0x00 14. "PPDI14,Parallel Pad Data In 14" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 13. "PPDI13,Parallel Pad Data In 13" "0: Logic low,1: Logic high"
bitfld.word 0x00 12. "PPDI12,Parallel Pad Data In 12" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 11. "PPDI11,Parallel Pad Data In 11" "0: Logic low,1: Logic high"
bitfld.word 0x00 10. "PPDI10,Parallel Pad Data In 10" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 9. "PPDI9,Parallel Pad Data In 9" "0: Logic low,1: Logic high"
bitfld.word 0x00 8. "PPDI8,Parallel Pad Data In 8" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 7. "PPDI7,Parallel Pad Data In 7" "0: Logic low,1: Logic high"
bitfld.word 0x00 6. "PPDI6,Parallel Pad Data In 6" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 5. "PPDI5,Parallel Pad Data In 5" "0: Logic low,1: Logic high"
bitfld.word 0x00 4. "PPDI4,Parallel Pad Data In 4" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 3. "PPDI3,Parallel Pad Data In 3" "0: Logic low,1: Logic high"
bitfld.word 0x00 2. "PPDI2,Parallel Pad Data In 2" "0: Logic low,1: Logic high"
newline
bitfld.word 0x00 1. "PPDI1,Parallel Pad Data In 1" "0: Logic low,1: Logic high"
bitfld.word 0x00 0. "PPDI0,Parallel Pad Data In 0" "0: Logic low,1: Logic high"
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x1780)++0x03
line.long 0x00 "MPGPDO$1,SIUL2 Masked Parallel GPIO Pad Data Out"
bitfld.long 0x00 31. "MASK15,Mask Field 15" "0: MPPDO15 is ignored,1: MPPDO15 is written"
bitfld.long 0x00 30. "MASK14,Mask Field 14" "0: MPPDO14 is ignored,1: MPPDO14 is written"
newline
bitfld.long 0x00 29. "MASK13,Mask Field 13" "0: MPPDO13 is ignored,1: MPPDO13 is written"
bitfld.long 0x00 28. "MASK12,Mask Field 12" "0: MPPDO12 is ignored,1: MPPDO12 is written"
newline
bitfld.long 0x00 27. "MASK11,Mask Field 11" "0: MPPDO11 is ignored,1: MPPDO11 is written"
bitfld.long 0x00 26. "MASK10,Mask Field 10" "0: MPPDO10 is ignored,1: MPPDO10 is written"
newline
bitfld.long 0x00 25. "MASK9,Mask Field 9" "0: MPPDO9 is ignored,1: MPPDO9 is written"
bitfld.long 0x00 24. "MASK8,Mask Field 8" "0: MPPDO8 is ignored,1: MPPDO8 is written"
newline
bitfld.long 0x00 23. "MASK7,Mask Field 7" "0: MPPDO7 is ignored,1: MPPDO7 is written"
bitfld.long 0x00 22. "MASK6,Mask Field 6" "0: MPPDO6 is ignored,1: MPPDO6 is written"
newline
bitfld.long 0x00 21. "MASK5,Mask Field 5" "0: MPPDO5 is ignored,1: MPPDO5 is written"
bitfld.long 0x00 20. "MASK4,Mask Field 4" "0: MPPDO4 is ignored,1: MPPDO4 is written"
newline
bitfld.long 0x00 19. "MASK3,Mask Field 3" "0: MPPDO3 is ignored,1: MPPDO3 is written"
bitfld.long 0x00 18. "MASK2,Mask Field 2" "0: MPPDO2 is ignored,1: MPPDO2 is written"
newline
bitfld.long 0x00 17. "MASK1,Mask Field 1" "0: MPPDO1 is ignored,1: MPPDO1 is written"
bitfld.long 0x00 16. "MASK0,Mask Field 0" "0: MPPDO0 is ignored,1: MPPDO0 is written"
newline
bitfld.long 0x00 15. "MPPDO15,Masked Parallel Pad Data Out 15" "0,1"
bitfld.long 0x00 14. "MPPDO14,Masked Parallel Pad Data Out 14" "0,1"
newline
bitfld.long 0x00 13. "MPPDO13,Masked Parallel Pad Data Out 13" "0,1"
bitfld.long 0x00 12. "MPPDO12,Masked Parallel Pad Data Out 12" "0,1"
newline
bitfld.long 0x00 11. "MPPDO11,Masked Parallel Pad Data Out 11" "0,1"
bitfld.long 0x00 10. "MPPDO10,Masked Parallel Pad Data Out 10" "0,1"
newline
bitfld.long 0x00 9. "MPPDO9,Masked Parallel Pad Data Out 9" "0,1"
bitfld.long 0x00 8. "MPPDO8,Masked Parallel Pad Data Out 8" "0,1"
newline
bitfld.long 0x00 7. "MPPDO7,Masked Parallel Pad Data Out 7" "0,1"
bitfld.long 0x00 6. "MPPDO6,Masked Parallel Pad Data Out 6" "0,1"
newline
bitfld.long 0x00 5. "MPPDO5,Masked Parallel Pad Data Out 5" "0,1"
bitfld.long 0x00 4. "MPPDO4,Masked Parallel Pad Data Out 4" "0,1"
newline
bitfld.long 0x00 3. "MPPDO3,Masked Parallel Pad Data Out 3" "0,1"
bitfld.long 0x00 2. "MPPDO2,Masked Parallel Pad Data Out 2" "0,1"
newline
bitfld.long 0x00 1. "MPPDO1,Masked Parallel Pad Data Out 1" "0,1"
bitfld.long 0x00 0. "MPPDO0,Masked Parallel Pad Data Out 0" "0,1"
repeat.end
tree.end
tree "SPI"
repeat 4. (list 0. 1. 2. 3.) (list ad:0x40290000 ad:0x40294000 ad:0x40490000 ad:0x404A0000)
tree "SPI_$1"
base $2
group.long 0x00++0x03
line.long 0x00 "MCR,Module Configuration Register"
bitfld.long 0x00 31. "MSTR,Master/Slave Mode Select" "0: Enables Slave mode,1: Enables Master mode"
bitfld.long 0x00 30. "CONT_SCKE,Continuous SCK Enable" "0: Continuous SCK disabled,1: Continuous SCK enabled"
newline
rbitfld.long 0x00 28.--29. "DCONF,SPI Configuration" "0: SPI,?..."
bitfld.long 0x00 27. "FRZ,Freeze" "0: Do not halt serial transfers in Debug mode,1: Halt serial transfers in Debug mode"
newline
bitfld.long 0x00 26. "MTFE,Modified Transfer Format Enable" "0: Modified SPI transfer format disabled,1: Modified SPI transfer format enabled"
bitfld.long 0x00 24. "ROOE,Receive FIFO Overflow Overwrite Enable" "0: Incoming data is ignored,1: Incoming data is shifted to the Shift register"
newline
bitfld.long 0x00 16.--19. "PCSIS,Peripheral Chip Select x Inactive State" "0: The inactive state of PCSx is low,1: The inactive state of PCS0 is high and for..,?..."
bitfld.long 0x00 14. "MDIS,Module Disable" "0: Enables the module clocks,1: Allows external logic to disable the module.."
newline
bitfld.long 0x00 13. "DIS_TXF,Disable Transmit FIFO" "0: TX FIFO is enabled,1: TX FIFO is disabled"
bitfld.long 0x00 12. "DIS_RXF,Disable Receive FIFO" "0: RX FIFO is enabled,1: RX FIFO is disabled"
newline
bitfld.long 0x00 11. "CLR_TXF,Clear TX FIFO" "0: Do not clear the TX FIFO counter,1: Clear the TX FIFO counter"
bitfld.long 0x00 10. "CLR_RXF,Clear RX FIFO" "0: Do not clear the RX FIFO counter,1: Clear the RX FIFO counter"
newline
bitfld.long 0x00 8.--9. "SMPL_PT,Sample Point" "0: Zero protocol clock cycles between SCK edge..,1: One protocol clock cycle between SCK edge and..,2: Two protocol clock cycles between SCK edge..,?..."
bitfld.long 0x00 3. "XSPI,Extended SPI Mode" "0: Normal SPI mode,1: Extended SPI mode"
newline
bitfld.long 0x00 2. "FCPCS,Fast Continuous PCS Mode" "0: Normal or slow continuous PCS mode,1: Fast continuous PCS mode"
bitfld.long 0x00 1. "PES,Parity Error Stop" "0: SPI frame transmission continues,1: SPI frame transmission stops"
newline
bitfld.long 0x00 0. "HALT,Halt" "0: Starts transfers,1: Stops transfers"
group.long 0x08++0x03
line.long 0x00 "TCR,Transfer Count Register"
hexmask.long.word 0x00 16.--31. 1. "SPI_TCNT,SPI Transfer Counter"
group.long 0x0C++0x03
line.long 0x00 "CTAR0,Clock and Transfer Attributes Register (in Master mode)"
bitfld.long 0x00 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a..,1: The baud rate is doubled with the duty cycle.."
bitfld.long 0x00 27.--30. "FMSZ,Frame Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
bitfld.long 0x00 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
newline
bitfld.long 0x00 24. "LSBFE,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
bitfld.long 0x00 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1,1: PCS to SCK Prescaler value is 3,2: PCS to SCK Prescaler value is 5,3: PCS to SCK Prescaler value is 7"
newline
bitfld.long 0x00 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1,1: Delay after Transfer Prescaler value is 3,2: Delay after Transfer Prescaler value is 5,3: Delay after Transfer Prescaler value is 7"
bitfld.long 0x00 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1,1: Delay after Transfer Prescaler value is 3,2: Delay after Transfer Prescaler value is 5,3: Delay after Transfer Prescaler value is 7"
newline
bitfld.long 0x00 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7"
bitfld.long 0x00 12.--15. "CSSCK,PCS to SCK Delay Scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "ASC,After SCK Delay Scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DT,Delay After Transfer Scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "BR,Baud Rate Scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "CTAR0_SLAVE,Clock and Transfer Attributes Register (in Slave mode)"
bitfld.long 0x00 27.--31. "FMSZ,Frame Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
newline
bitfld.long 0x00 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
bitfld.long 0x00 24. "PE,Parity Enable" "0: No parity bit included/checked,1: Parity bit is transmitted instead of last.."
newline
bitfld.long 0x00 23. "PP,Parity Polarity" "0: Even Parity,1: Odd Parity"
repeat 5. (strings "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 )
group.long ($2+0x10)++0x03
line.long 0x00 "CTAR$1,Clock and Transfer Attributes Register (in Master mode)"
bitfld.long 0x00 31. "DBR,Double Baud Rate" "0: The baud rate is computed normally with a..,1: The baud rate is doubled with the duty cycle.."
bitfld.long 0x00 27.--30. "FMSZ,Frame Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 26. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
bitfld.long 0x00 25. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
newline
bitfld.long 0x00 24. "LSBFE,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
bitfld.long 0x00 22.--23. "PCSSCK,PCS to SCK Delay Prescaler" "0: PCS to SCK Prescaler value is 1,1: PCS to SCK Prescaler value is 3,2: PCS to SCK Prescaler value is 5,3: PCS to SCK Prescaler value is 7"
newline
bitfld.long 0x00 20.--21. "PASC,After SCK Delay Prescaler" "0: Delay after Transfer Prescaler value is 1,1: Delay after Transfer Prescaler value is 3,2: Delay after Transfer Prescaler value is 5,3: Delay after Transfer Prescaler value is 7"
bitfld.long 0x00 18.--19. "PDT,Delay after Transfer Prescaler" "0: Delay after Transfer Prescaler value is 1,1: Delay after Transfer Prescaler value is 3,2: Delay after Transfer Prescaler value is 5,3: Delay after Transfer Prescaler value is 7"
newline
bitfld.long 0x00 16.--17. "PBR,Baud Rate Prescaler" "0: Baud Rate Prescaler value is 2,1: Baud Rate Prescaler value is 3,2: Baud Rate Prescaler value is 5,3: Baud Rate Prescaler value is 7"
bitfld.long 0x00 12.--15. "CSSCK,PCS to SCK Delay Scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "ASC,After SCK Delay Scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DT,Delay After Transfer Scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "BR,Baud Rate Scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
group.long 0x2C++0x03
line.long 0x00 "SR,Status Register"
eventfld.long 0x00 31. "TCF,Transfer Complete Flag" "0: Transfer is incomplete,1: Transfer is complete"
rbitfld.long 0x00 30. "TXRXS,TX and RX Status" "0: Transmit and receive operations are disabled..,1: Transmit and receive operations are enabled.."
newline
eventfld.long 0x00 28. "EOQF,End of Queue Flag" "0: EOQ is not set in the executing command,1: EOQ is set in the executing SPI command"
eventfld.long 0x00 27. "TFUF,Transmit FIFO Underflow Flag" "0: No TX FIFO underflow occurred,1: TX FIFO underflow occurred"
newline
eventfld.long 0x00 25. "TFFF,Transmit FIFO Fill Flag" "0: TX FIFO is full,1: TX FIFO is not full"
rbitfld.long 0x00 24. "BSYF,Busy Flag" "0: No cyclic command transfer is in progress,1: Cyclic command transfer is in progress"
newline
eventfld.long 0x00 23. "CMDTCF,Command Transfer Complete Flag" "0: Data transfer by current command is incomplete,1: Data transfer by current command is complete"
eventfld.long 0x00 21. "SPEF,SPI Parity Error Flag" "0: No parity error,1: Parity error has occurred"
newline
eventfld.long 0x00 19. "RFOF,Receive FIFO Overflow Flag" "0: No RX FIFO overflow occurred,1: RX FIFO overflow has occurred"
eventfld.long 0x00 18. "TFIWF,Transmit FIFO Invalid Write Flag" "0: No invalid data is present in TX FIFO,1: Invalid data is present in TX FIFO because.."
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eventfld.long 0x00 17. "RFDF,Receive FIFO Drain Flag" "0: RX FIFO is empty,1: RX FIFO is not empty"
eventfld.long 0x00 16. "CMDFFF,Command FIFO Fill Flag" "0: CMD FIFO is full,1: CMD FIFO is not full"
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rbitfld.long 0x00 12.--15. "TXCTR,TX FIFO Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 8.--11. "TXNXTPTR,Transmit Next Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 4.--7. "RXCTR,RX FIFO Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--3. "POPNXTPTR,Pop Next Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "RSER,DMA/Interrupt Request Select and Enable Register"
bitfld.long 0x00 31. "TCF_RE,Transmission Complete Request Enable" "0: TCF interrupt requests are disabled,1: TCF interrupt requests are enabled"
bitfld.long 0x00 30. "CMDFFF_RE,Command FIFO Fill Flag Request Enable" "0: CMDFFF interrupts or DMA requests are disabled,1: CMDFFF interrupts or DMA requests are enabled"
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bitfld.long 0x00 28. "EOQF_RE,Finished Request Enable" "0: EOQF interrupt requests are disabled,1: EOQF interrupt requests are enabled"
bitfld.long 0x00 27. "TFUF_RE,Transmit FIFO Underflow Request Enable" "0: TFUF interrupt requests are disabled,1: TFUF interrupt requests are enabled"
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bitfld.long 0x00 25. "TFFF_RE,Transmit FIFO Fill Request Enable" "0: TFFF interrupts or DMA requests are disabled,1: TFFF interrupts or DMA requests are enabled"
bitfld.long 0x00 24. "TFFF_DIRS,Transmit FIFO Fill DMA or Interrupt Request Select" "0: TFFF flag generates interrupt requests,1: TFFF flag generates DMA requests"
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bitfld.long 0x00 23. "CMDTCF_RE,Command Transmission Complete Request Enable" "0: CMDTCF interrupt requests are disabled,1: CMDTCF interrupt requests are enabled"
bitfld.long 0x00 21. "SPEF_RE,SPI Parity Error Request Enable" "0: SPEF interrupt requests are disabled,1: SPEF interrupt requests are enabled"
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bitfld.long 0x00 19. "RFOF_RE,Receive FIFO Overflow Request Enable" "0: RFOF interrupt requests are disabled,1: RFOF interrupt requests are enabled"
bitfld.long 0x00 18. "TFIWF_RE,Transmit FIFO Invalid Write Request Enable" "0: TFIWF interrupt requests are disabled,1: TFIWF interrupt requests are enabled"
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bitfld.long 0x00 17. "RFDF_RE,Receive FIFO Drain Request Enable" "0: RFDF interrupt or DMA requests are disabled,1: RFDF interrupt or DMA requests are enabled"
bitfld.long 0x00 16. "RFDF_DIRS,Receive FIFO Drain DMA or Interrupt Request Select" "0: Interrupt request,1: DMA_REQUEST"
newline
bitfld.long 0x00 15. "CMDFFF_DIRS,Command FIFO Fill DMA or Interrupt Request Select" "0: CMDFFF flag generates interrupt requests,1: CMDFFF flag generates DMA requests"
group.long 0x34++0x03
line.long 0x00 "PUSHR,PUSH TX FIFO Register In Master Mode"
bitfld.long 0x00 31. "CONT,Continuous Peripheral Chip Select Enable" "0: Return PCSn signals to their inactive state..,1: Keep PCSn signals asserted between transfers"
bitfld.long 0x00 28.--30. "CTAS,Clock and Transfer Attributes Select" "0: CTAR0,1: CTAR1,2: CTAR2,3: CTAR3,4: CTAR4,5: CTAR5,?..."
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bitfld.long 0x00 27. "EOQ,End of Queue" "0: SPI data is not the last data to transfer,1: SPI data is the last data to transfer"
bitfld.long 0x00 26. "CTCNT,Clear Transfer Counter" "0: Do not clear the TCR[TCNT] field,1: Clear the TCR[TCNT] field"
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bitfld.long 0x00 25. "PE_MASC,Parity Enable or Mask TASC Delay in Current Frame" "0: PE - No parity bit is included/checked,1: PE - Parity bit is transmitted instead of the.."
bitfld.long 0x00 24. "PP_MCSC,Parity Polarity or Mask TCSC Delay in Next Frame" "0: PP - Even Parity,1: PP - Odd Parity"
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bitfld.long 0x00 16.--19. "PCS,PCS" "0: Negate the PCS[x] signal,1: Assert the PCS[x] signal,?..."
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit Data"
group.long 0x34++0x03
line.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode"
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit Data"
rgroup.long 0x38++0x03
line.long 0x00 "POPR,POP RX FIFO Register"
hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data"
repeat 5. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x3C)++0x03
line.long 0x00 "TXFR[$1],Transmit FIFO Registers $1"
hexmask.long.word 0x00 16.--31. 1. "TXCMD_TXDATA,Transmit Command or Transmit Data"
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit Data"
repeat.end
repeat 5. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x7C)++0x03
line.long 0x00 "RXFR[$1],Receive FIFO Registers $1"
hexmask.long 0x00 0.--31. 1. "RXDATA,Receive Data"
repeat.end
repeat 6. (increment 0 1) (increment 0 0x04)
group.long ($2+0x11C)++0x03
line.long 0x00 "CTARE[$1],Clock and Transfer Attributes Register Extended $1"
bitfld.long 0x00 16. "FMSZE,Frame Size Extended" "0: Default Mode,1: Up to 32 bit SPI frames can be transferred"
hexmask.long.word 0x00 0.--10. 1. "DTCP,Data Transfer Count Preload"
repeat.end
rgroup.long 0x13C++0x03
line.long 0x00 "SREX,Status Register Extended"
bitfld.long 0x00 14. "TXCTR4,TX FIFO Counter[4]" "0,1"
bitfld.long 0x00 11. "RXCTR4,RX FIFO Counter[4]" "0,1"
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bitfld.long 0x00 4.--8. "CMDCTR,CMD FIFO Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--3. "CMDNXTPTR,Command Next Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
repeat.end
tree.end
tree "SPT"
base ad:0x440A0000
group.long 0x00++0x03
line.long 0x00 "GBL_CTRL,SPT Global Control"
bitfld.long 0x00 31. "ADV_ADAP_SC_CTRL,Advance Adaptive scaling control" "0: Advance adaptive scaling for FFT is..,1: Advance adaptive scaling for FFT is disabled"
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bitfld.long 0x00 30. "CT_IP_EN,Cross Trigger-IN channel enable" "0: Cross Trigger-IN channels are not enabled to..,1: Cross Trigger-IN channels are enabled to.."
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bitfld.long 0x00 29. "CT_OP_EN,Cross Trigger-OUT channel enable" "0: SPT does not assert the Cross Trigger-OUT..,1: SPT asserts the Cross Trigger-OUT channel.."
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bitfld.long 0x00 28. "CTI_DBG_EXIT,Cross Trigger-IN debug exit" "0: Do not force the SPT debug mode exit,1: Force the debug mode exit for SPT"
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bitfld.long 0x00 2. "PG_ST_CTRL,Program Start Control" "0: Program execution does not begin,1: Program execution begins"
group.long 0x04++0x03
line.long 0x00 "CS_PG_ST_ADDR,Program Start Address"
hexmask.long 0x00 0.--31. 1. "PG_ST_ADDR,Program Start Address"
group.long 0x08++0x03
line.long 0x00 "CS_MODE_CTRL,Mode Control"
bitfld.long 0x00 20.--21. "SCS1_DEBUG_MD,SCS1 Debug Mode Control" "0: Halt mode,1: Step Once mode,2: Step To Next Breakpoint mode,3: Command Jamming mode"
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bitfld.long 0x00 18.--19. "SCS0_DEBUG_MD,SCS0 Debug Mode Control" "0: Halt mode,1: Step Once mode,2: Step To Next Breakpoint mode,3: Command Jamming mode"
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bitfld.long 0x00 17. "CFG_HALT_OTHER_THREADS,Command Sequencer Halt In Debug Mode" "0: Active threads continue,1: Active threads halt"
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bitfld.long 0x00 16. "ERROR_EN,Error Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x00 15. "PREFETCH,Early Prefetch Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x00 14. "BKPT3_RE,Breakpoint 3 Remain Enabled" "0: Disabled,1: Enabled"
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bitfld.long 0x00 13. "BKPT3_EN,Breakpoint 3 Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x00 12. "BKPT2_RE,Breakpoint 2 Remain Enabled" "0: Disabled,1: Enabled"
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bitfld.long 0x00 11. "BKPT2_EN,Breakpoint 2 Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x00 10. "BKPT1_RE,Breakpoint 1 Remain Enabled" "0: DISABLE,1: Enabled"
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bitfld.long 0x00 9. "BKPT1_EN,Breakpoint 1 Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x00 8. "BKPT0_RE,Breakpoint 0 Remain Enabled" "0: DISABLE,1: ENABLE"
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bitfld.long 0x00 7. "BKPT0_EN,Breakpoint 0 Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x00 6. "CS_SYS_DEBUG,System Debug Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x00 5. "CS_BKPT_DEBUG,Breakpoint Debug Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x00 4. "CS_IMM_DEBUG,Immediate Debug Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x00 2.--3. "DEBUG_MD,Debug Mode Control" "0: Halt mode,1: Step Once mode,2: Step To Next Breakpoint mode,3: Command Jamming mode"
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bitfld.long 0x00 1. "ASYNCSTOP,Enter Asyncstop State" "0,1"
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bitfld.long 0x00 0. "STOP,Enter Stop State" "0,1"
rgroup.long 0x0C++0x03
line.long 0x00 "CS_WD_STATUS,Watchdog Status"
bitfld.long 0x00 24.--29. "CFG_WD_WAITREG,Reset Event Number For Watchdog" "0: Watchdog is waiting for event CTEn (CTE..,1: Watchdog is waiting for event CTEn (CTE..,2: Watchdog is waiting for event CTEn (CTE..,3: Watchdog is waiting for event CTEn (CTE..,4: Watchdog is waiting for a CTE_RCS event,5: Watchdog is waiting for a CTE_RFS event,6: Watchdog is waiting for an MIPICSI2_1 HSYNCn..,7: Watchdog is waiting for an MIPICSI2_1 HSYNCn..,8: Watchdog is waiting for an MIPICSI2_1 HSYNCn..,9: Watchdog is waiting for an MIPICSI2_1 HSYNCn..,10: Watchdog is waiting for an MIPICSI2_0 HSYNCn..,11: Watchdog is waiting for an MIPICSI2_0 HSYNCn..,12: Watchdog is waiting for an MIPICSI2_0 HSYNCn..,13: Watchdog is waiting for an MIPICSI2_0 HSYNCn..,?,?,?,?,?,?,?,?,22: Watchdog is waiting for an MIPICSI2_1 VSYNCn..,23: Watchdog is waiting for an MIPICSI2_1 VSYNCn..,24: Watchdog is waiting for an MIPICSI2_1 VSYNCn..,25: Watchdog is waiting for an MIPICSI2_1 VSYNCn..,26: Watchdog is waiting for an MIPICSI2_0 VSYNCn..,27: Watchdog is waiting for an MIPICSI2_0 VSYNCn..,28: Watchdog is waiting for an MIPICSI2_0 VSYNCn..,29: Watchdog is waiting for an MIPICSI2_0 VSYNCn..,?..."
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hexmask.long.tbyte 0x00 0.--23. 1. "WD_COUNT,Watchdog Timer Count"
group.long 0x10++0x03
line.long 0x00 "CS_BKPT0_ADDR,Breakpoint 0 Address"
hexmask.long 0x00 0.--31. 1. "BKPT0,Breakpoint 0 Address"
group.long 0x14++0x03
line.long 0x00 "CS_BKPT1_ADDR,Breakpoint 1 Address"
hexmask.long 0x00 0.--31. 1. "BKPT1,Breakpoint 1 Address"
group.long 0x18++0x03
line.long 0x00 "CS_BKPT2_ADDR,Breakpoint 2 Address"
hexmask.long 0x00 0.--31. 1. "BKPT2,Breakpoint 2 Address"
group.long 0x1C++0x03
line.long 0x00 "CS_BKPT3_ADDR,Breakpoint 3 Address"
hexmask.long 0x00 0.--31. 1. "BKPT3,Breakpoint 3 Address"
group.long 0x20++0x03
line.long 0x00 "CS_JAM_INST0,MCS Jamming Command 0"
hexmask.long 0x00 0.--31. 1. "JAM_INST_31_0,MCS Jamming Command Bits 31-0"
group.long 0x24++0x03
line.long 0x00 "CS_JAM_INST1,MCS Jamming Command 1"
hexmask.long 0x00 0.--31. 1. "JAM_INST_63_32,MCS Jamming Command Bits 63-32"
group.long 0x28++0x03
line.long 0x00 "CS_JAM_INST2,MCS Jamming Command 2"
hexmask.long 0x00 0.--31. 1. "JAM_INST_95_64,MCS Jamming Command Bits 95-64"
group.long 0x2C++0x03
line.long 0x00 "CS_JAM_INST3,MCS Jamming Command 3"
hexmask.long 0x00 0.--31. 1. "JAM_INST_127_96,MCS Jamming Command Bits 127-96"
rgroup.long 0x30++0x03
line.long 0x00 "CS_CURR_INST_ADDR,MCS Current Command Address"
hexmask.long 0x00 0.--31. 1. "CURRENT_INST_ADDR,MCS Current Command Pointer"
rgroup.long 0x34++0x03
line.long 0x00 "CS_CURR_INST0,MCS Current Command 0"
hexmask.long 0x00 0.--31. 1. "CURR_INST_31_0,MCS Current Command Bits 31-0"
rgroup.long 0x38++0x03
line.long 0x00 "CS_CURR_INST1,MCS Current Command 1"
hexmask.long 0x00 0.--31. 1. "CURR_INST_63_32,MCS Current Command Bits 63-32"
rgroup.long 0x3C++0x03
line.long 0x00 "CS_CURR_INST2,MCS Current Command 2"
hexmask.long 0x00 0.--31. 1. "CURR_INST_95_64,MCS Current Command Bits 95-64"
rgroup.long 0x40++0x03
line.long 0x00 "CS_CURR_INST3,MCS Current Command 3"
hexmask.long 0x00 0.--31. 1. "CURR_INST_127_96,MCS Current Command Bits 127-96"
rgroup.long 0x44++0x03
line.long 0x00 "CS_LOOPCNTR01,MCS Loop Counters 0 and 1"
hexmask.long.word 0x00 16.--31. 1. "LOOP_CNTR1,MCS Loop Counter 1"
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hexmask.long.word 0x00 0.--15. 1. "LOOP_CNTR0,MCS Loop Counter 0"
rgroup.long 0x48++0x03
line.long 0x00 "CS_LOOPCNTR23,MCS Loop Counters 2 and 3"
hexmask.long.word 0x00 16.--31. 1. "LOOP_CNTR3,MCS Loop Counter 3"
newline
hexmask.long.word 0x00 0.--15. 1. "LOOP_CNTR2,MCS Loop Counter 2"
rgroup.long 0x4C++0x03
line.long 0x00 "CS_ERR_INST_ADDR,MCS Error Command Address"
hexmask.long 0x00 0.--31. 1. "ERROR_INST_ADDR,MCS Error Command Pointer"
rgroup.long 0x50++0x03
line.long 0x00 "CS_ERR_INST0,MCS Error Command 0"
hexmask.long 0x00 0.--31. 1. "ERR_INST_127_96,MCS Error Command Bits 127-96"
rgroup.long 0x54++0x03
line.long 0x00 "CS_ERR_INST1,MCS Error Command 1"
hexmask.long 0x00 0.--31. 1. "ERR_INST_95_64,MCS Error Command Bits 95-64"
rgroup.long 0x58++0x03
line.long 0x00 "CS_ERR_INST2,MCS Error Command 2"
hexmask.long 0x00 0.--31. 1. "ERR_INST_63_32,MCS Error Command Bits 63-32"
rgroup.long 0x5C++0x03
line.long 0x00 "CS_ERR_INST3,MCS Error Command 3"
hexmask.long 0x00 0.--31. 1. "ERR_INST_31_0,MCS Error Command Bits 31-0"
group.long 0x60++0x03
line.long 0x00 "CS_STATUS0,MCS General Status 0"
eventfld.long 0x00 31. "WD_ZERO,Watchdog Timer Reached Zero" "0: Watchdog timer has not reached zero,1: Watchdog timer has reached zero"
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eventfld.long 0x00 16. "BKPT3_OCC,MCS Breakpoint 3 Encountered Indicator" "0: Breakpoint not encountered,1: Breakpoint encountered"
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eventfld.long 0x00 15. "BKPT2_OCC,MCS Breakpoint 2 Encountered Indicator" "0: Breakpoint not encountered,1: Breakpoint encountered"
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eventfld.long 0x00 14. "BKPT1_OCC,MCS Breakpoint 1 Encountered Indicator" "0: Breakpoint not encountered,1: Breakpoint encountered"
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eventfld.long 0x00 13. "BKPT0_OCC,MCS Breakpoint 0 Encountered Indicator" "0: MCS has not encountered enabled breakpoint 0..,1: MCS has encountered enabled breakpoint 0.."
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eventfld.long 0x00 12. "JAM_OVR,MCS Debug State Command Jamming Mode Command Completion Indicator" "0,1"
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eventfld.long 0x00 11. "STEP_JUMP_OVR,MCS Debug state Step To Next Breakpoint mode Break Indicator" "0,1"
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eventfld.long 0x00 10. "STEP_ONCE_OVR,MCS Debug State Step Once Mode Command Completion Indicator" "0,1"
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eventfld.long 0x00 9. "MD_JAM,MCS Debug State Command Jamming Mode Indicator" "0: MCS not in Command Jamming mode in Debug state,1: MCS in Command Jamming mode in Debug state"
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eventfld.long 0x00 8. "MD_STEP_JUMP,MCS Step To Next Breakpoint mode in Debug state Indicator" "0: MCS not in Step To Next Breakpoint mode in..,1: MCS in Step To Next Breakpoint mode in Debug.."
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eventfld.long 0x00 7. "MD_STEP_ONCE,MCS Debug State Step Once Mode Indicator" "0: MCS not in Step Once mode in Debug state,1: MCS in Step Once mode in Debug state"
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eventfld.long 0x00 6. "MD_HALT,MCS Debug State Halt Mode Indicator" "0: MCS not in Halt mode in Debug state,1: MCS in Halt mode in Debug state"
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eventfld.long 0x00 5. "PS_RUN,MCS Run State Indicator" "0: MCS not in Run state,1: MCS in Run state"
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eventfld.long 0x00 4. "PS_ASYNCSTOP,MCS Asyncstop State Indicator" "0: MCS not in Asyncstop state,1: MCS in Asyncstop state"
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eventfld.long 0x00 3. "PS_STOP,MCS Stop State Indicator" "0: MCS not in Stop state,1: MCS in Stop state"
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eventfld.long 0x00 2. "PS_DEBUG,MCS Debug State Indicator" "0: MCS not in Debug state,1: MCS in Debug state"
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eventfld.long 0x00 1. "PS_WAIT,MCS Wait State Indicator" "0: MCS not in Wait state,1: MCS in Wait state"
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eventfld.long 0x00 0. "PS_START,MCS Start State Indicator" "0: MCS not in Start state,1: MCS in Start state"
group.long 0x64++0x03
line.long 0x00 "CS_STATUS1,MCS General Status 1"
eventfld.long 0x00 11. "JAM_ILL_JUMP,MCS Illegal JUMP Command In Debug State Command Jamming Mode Error" "0: No attempted JUMP command execution,1: Attempted JUMP command execution"
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eventfld.long 0x00 10. "JAM_ILL_NEXT,MCS Illegal Next Command In Debug State Command Jamming Mode Error" "0: No attempted Next command execution,1: Attempted Next command execution"
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eventfld.long 0x00 9. "JAM_ILL_LOOP,MCS Illegal Loop Command In Debug State Command Jamming Mode Error" "0: No attempted Loop command execution,1: Attempted Loop command execution"
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eventfld.long 0x00 8. "JAM_ILL_SYNC,MCS Illegal SYNC Command In Debug State Command Jamming Mode Error" "0: No attempted SYNC command execution,1: Attempted SYNC command execution"
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eventfld.long 0x00 7. "JAM_ILL_OPCODE,MCS Illegal Opcode In Debug state Command Jamming Mode Error" "0: No attempted illegal command opcode execution,1: Attempted illegal command opcode execution"
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eventfld.long 0x00 6. "ILL_ADD,MCS Illegal Add Command Error" "0: No attempted execution of an illegal Add Sub..,1: Attempted execution of an illegal Add Sub Cmp.."
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eventfld.long 0x00 5. "ILL_GET,MCS Illegal Get Command Error" "0: No attempted execution of an illegal Get..,1: Attempted execution of an illegal Get command"
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eventfld.long 0x00 4. "ILL_SET,MCS Illegal Set Command Error" "0: No attempted execution of an illegal Set..,1: Attempted execution of an illegal Set command"
newline
eventfld.long 0x00 3. "ILL_NEXT,MCS Illegal Next Command Error" "0: No attempted execution a Next command when no..,1: Attempted execution a Next command when no.."
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eventfld.long 0x00 2. "ILL_0CNTLOOP,MCS Illegal Loop Count Error" "0: No attempted execution of a Loop command with..,1: Attempted execution of a Loop command with.."
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eventfld.long 0x00 1. "ILL_LOOP,MCS Illegal Loop Command Error" "0: No attempt to start a fifth level of nested..,1: Attempt to start a fifth level of nested loops"
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eventfld.long 0x00 0. "ILL_OPCODE,MCS Illegal Opcode Error" "0: Attempted execution of an illegal command..,1: Attempted execution of an illegal command.."
rgroup.long 0x68++0x03
line.long 0x00 "CS_STATUS2,MCS General Status 2"
bitfld.long 0x00 29.--30. "WAITREG_EVT_TYPE,Wait Event Type" "?,1: Wait event is CPU event,2: Wait event is external event,3: Wait event is internal event"
newline
hexmask.long.byte 0x00 16.--22. 1. "WAITREG_EVT_NUMBER,Event Number For Wait Command"
newline
hexmask.long.word 0x00 0.--15. 1. "WAITREG_SW,Wait Status for Software-Triggered Event"
rgroup.long 0x6C++0x03
line.long 0x00 "CS_STATUS3,MCS General Status 3"
bitfld.long 0x00 3.--6. "PROC_STATE,MCS Processing State" "0: MCS in Rst state,1: MCS in Start state,2: MCS in Setup state,3: MCS in Run state,4: MCS in Wait state,5: MCS in Debug state,6: MCS in Stop state,7: MCS in Asyncstop state,?..."
newline
bitfld.long 0x00 0.--2. "LOOP_DEPTH,MCS Loop Depth" "0: No loop being executed,1: Loop has nesting level depth of 1,2: Loop has nesting level depth of 2,3: Loop has nesting level depth of 3,4: Loop has nesting level depth of 4,?..."
group.long 0x70++0x03
line.long 0x00 "CS_EVTREG1,EVT1 Status"
hexmask.long 0x00 0.--31. 1. "EVTREG1,EVT1"
group.long 0x78++0x03
line.long 0x00 "CS_SW_EVTREG,Software Event Trigger"
hexmask.long.word 0x00 0.--15. 1. "SW_EVTREG,Software Event Trigger"
group.long 0x80++0x03
line.long 0x00 "CS_CHRP_CNTR_RST,External Events Chirp FIFO Counter Reset Mapping"
bitfld.long 0x00 28.--31. "RST_CHRP_CNT_EVT_7,Chirp FIFO Counter 7 Reset Event" "0: MIPICSI2 instance 1 Vsync 0 to 3,1: MIPICSI2 instance 1 Vsync 0 to 3,2: MIPICSI2 instance 1 Vsync 0 to 3,3: MIPICSI2 instance 1 Vsync 0 to 3,4: MIPICSI2 instance 0 Vsync 0 to 3,5: MIPICSI2 instance 0 Vsync 0 to 3,6: MIPICSI2 instance 0 Vsync 0 to 3,7: MIPICSI2 instance 0 Vsync 0 to 3,?..."
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bitfld.long 0x00 24.--27. "RST_CHRP_CNT_EVT_6,Chirp FIFO Counter 6 Reset Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "RST_CHRP_CNT_EVT_5,Chirp FIFO Counter 5 Reset Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "RST_CHRP_CNT_EVT_4,Chirp FIFO Counter 4 Reset Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "RST_CHRP_CNT_EVT_3,Chirp FIFO Counter 3 Reset Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "RST_CHRP_CNT_EVT_2,Chirp FIFO Counter 2 Reset Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "RST_CHRP_CNT_EVT_1,Chirp FIFO Counter 1 Reset Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "RST_CHRP_CNT_EVT_0,Chirp FIFO Counter 0 Reset Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x84++0x03
line.long 0x00 "CS_CHRP_CNTR_LD,External Events Chirp FIFO Counter Load Mapping"
bitfld.long 0x00 28.--31. "LOAD_CHRP_CNT_EVT_7,Chirp FIFO Counter 7 Load Event" "0: Line Done signal number,1: Line Done signal number,2: Line Done signal number,3: Line Done signal number,4: Line Done signal number,5: Line Done signal number,6: Line Done signal number,7: Line Done signal number,8: Line Done signal number,9: Line Done signal number,?..."
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bitfld.long 0x00 24.--27. "LOAD_CHRP_CNT_EVT_6,Chirp FIFO Counter 6 Load Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "LOAD_CHRP_CNT_EVT_5,Chirp FIFO Counter 5 Load Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "LOAD_CHRP_CNT_EVT_4,Chirp FIFO Counter 4 Load Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "LOAD_CHRP_CNT_EVT_3,Chirp FIFO Counter 3 Load Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "LOAD_CHRP_CNT_EVT_2,Chirp FIFO Counter 2 Load Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "LOAD_CHRP_CNT_EVT_1,Chirp FIFO Counter 1 Load Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "LOAD_CHRP_CNT_EVT_0,Chirp FIFO Counter 0 Load Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x88++0x03
line.long 0x00 "CS_INTEN0,MCS Interrupt Enable 0"
bitfld.long 0x00 31. "WD_ZERO_INTEN,Watchdog Reached Zero Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 16. "BKPT3_OCC_INTEN,MCS Breakpoint 3 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 15. "BKPT2_OCC_INTEN,MCS Breakpoint 2 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 14. "BKPT1_OCC_INTEN,MCS Breakpoint 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 13. "BKPT0_OCC_INTEN,MCS Breakpoint 0 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 12. "JAM_OVR_INTEN,MCS Debug State Jamming Command Over Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 11. "STEP_JUMP_OVR_INTEN,MCS Breakpoint Encountered in Debug State Step To Next Breakpoint Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 10. "STEP_ONCE_OVR_INTEN,MCS Debug State Step Once Mode Command Over Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 9. "MD_JAM_INTEN,MCS Debug State Command Jamming Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 8. "MD_STEP_JUMP_INTEN,MCS Step To Next Breakpoint mode in Debug state Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 7. "MD_STEP_ONCE_INTEN,MCS Debug State Step Once Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 6. "MD_HALT_INTEN,MCS Debug State Halt Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 5. "PS_RUN_INTEN,MCS Run State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 4. "PS_ASYNCSTOP_INTEN,MCS Asyncstop State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 3. "PS_STOP_INTEN,MCS Stop State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 2. "PS_DEBUG_INTEN,MCS Debug State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 1. "PS_WAIT_INTEN,MCS Wait State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 0. "PS_START_INTEN,MCS Start State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
group.long 0x8C++0x03
line.long 0x00 "CS_INTEN1,MCS Interrupt Enable 1"
bitfld.long 0x00 11. "JAM_ILL_JUMP_INTEN,MCS Illegal JUMP Command In Debug State Command Jamming Mode Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 10. "JAM_ILL_NEXT_INTEN,MCS Illegal Next Command In Debug State Command Jamming Mode Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 9. "JAM_ILL_LOOP_INTEN,MCS Illegal Loop Command In Debug State Command Jamming Mode Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 8. "JAM_ILL_SYNC_INTEN,MCS Illegal SYNC Command In Debug State Command Jamming Mode Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 7. "JAM_ILL_OPCODE_INTEN,MCS Illegal Opcode In Debug State Command Jamming Mode Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 6. "ILL_ADD_INTEN,MCS Illegal Add Command Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 5. "ILL_GET_INTEN,MCS Illegal Get Command Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 4. "ILL_SET_INTEN,MCS Illegal Set Command Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 3. "ILL_NEXT_INTEN,MCS Illegal Next Command Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 2. "ILL_0CNTLOOP_INTEN,MCS Illegal Loop Count Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 1. "ILL_LOOP_INTEN,MCS Illegal Loop Command Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 0. "ILL_OPCODE_INTEN,MCS Illegal Opcode Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
group.long 0x90++0x03
line.long 0x00 "CS_EVT1_INTEN,EVT1 Interrupt Enable"
hexmask.long 0x00 0.--31. 1. "EVT1_INTEN,EVT Interrupt Enable for external output"
group.long 0x94++0x03
line.long 0x00 "DSP_RST_REG,DSP Reset"
bitfld.long 0x00 0. "DSP_RST,DSP Reset" "0,1"
group.long 0x98++0x03
line.long 0x00 "DSP_CONFIG_REG,DSP Configuration"
bitfld.long 0x00 2.--5. "DSP_PROG_COUNT,DSP Program Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 1. "DSP_RUN_STALL,DSP Run/Stall" "0: DSP internal pipeline is stalled,1: DSP internal pipeline stalled"
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bitfld.long 0x00 0. "DSP_BOOT_MODE,DSP Boot Mode" "0,1"
group.long 0x9C++0x03
line.long 0x00 "DSP_ERR_INFO_REG,DSP Error Information"
hexmask.long 0x00 0.--31. 1. "DSP_ERR_INFO,DSP Error Information"
group.long 0xA0++0x03
line.long 0x00 "DSP_ERR_INFO_INT_EN,DSP Error Information Interrupt Enable"
bitfld.long 0x00 0. "DSPERRIE,DSP Error Information Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
rgroup.long 0xA4++0x03
line.long 0x00 "DSP_PFAULT_INFO_REG,DSP PFault Information"
hexmask.long 0x00 0.--31. 1. "DSP_PFAULT_INFO,DSP PFault Information"
rgroup.long 0xA8++0x03
line.long 0x00 "DSP_DEBUG1_REG,DSP Debug 1"
hexmask.long 0x00 0.--31. 1. "DSP_DEBUG1,DSP Debug Information 1"
rgroup.long 0xAC++0x03
line.long 0x00 "DSP_DEBUG2_REG,DSP Debug 2"
hexmask.long 0x00 0.--31. 1. "DSP_DEBUG2,DSP Debug Information 2"
rgroup.long 0xB0++0x03
line.long 0x00 "DSP_DEBUG3_REG,DSP Debug 3"
hexmask.long 0x00 0.--31. 1. "DSP_DEBUG3,DSP Debug Information 3"
rgroup.long 0xB4++0x03
line.long 0x00 "DSP_DEBUG4_REG,DSP Debug 4"
hexmask.long 0x00 0.--31. 1. "DSP_DEBUG4,DSP Debug Information 4"
rgroup.long 0xB8++0x03
line.long 0x00 "DSP_DEBUG5_REG,DSP Debug 5"
hexmask.long 0x00 0.--31. 1. "DSP_DEBUG5,DSP Debug Information 5"
rgroup.long 0xBC++0x03
line.long 0x00 "DSP_DEBUG6_REG,DSP Debug 6"
hexmask.long 0x00 0.--31. 1. "DSP_DEBUG6,DSP Debug Information 6"
group.long 0xC0++0x03
line.long 0x00 "PDMA_LFSR_LOAD_VAL_HIGH,LFSR Load High Value"
hexmask.long 0x00 0.--31. 1. "LFSRVALH,LFSR Value High"
group.long 0xC4++0x03
line.long 0x00 "PDMA_LFSR_LOAD_VAL_LOW,LFSR Low Value"
hexmask.long 0x00 0.--31. 1. "LFSRVALL,LFSR Low Value [31:0] for compression"
group.long 0xC8++0x03
line.long 0x00 "PDMA_CONTROL,PDMA Control"
bitfld.long 0x00 0. "PDMA_LFSR_LOAD_EN,LFSR Load Enable" "0: LFSR not loaded,1: LFSR loaded"
rgroup.long 0xCC++0x03
line.long 0x00 "PDMA_TRANSFER_COUNT_STATUS,MCS PDMA Transfer Count Status"
hexmask.long.word 0x00 16.--31. 1. "AGGR_DATA_COUNT,MCS Aggregation Data Count"
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hexmask.long.word 0x00 0.--15. 1. "TRANSFER_COUNT,MCS Number of Words Transferred via PDMA"
rgroup.long 0xD0++0x03
line.long 0x00 "PDMA_FMTB_EXP_ADDR_STATUS,MCS PDMA FormatB Exponent Address Status"
hexmask.long 0x00 3.--31. 1. "EXPN_ADDR,MCS Exponent Address"
group.long 0xE0++0x03
line.long 0x00 "HIST_OVF_STATUS0,HIST Overflow Status 0"
eventfld.long 0x00 31. "B31_OVF,Bin Counter 31 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 30. "B30_OVF,Bin Counter 30 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 29. "B29_OVF,Bin Counter 29 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 28. "B28_OVF,Bin Counter 28 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 27. "B27_OVF,Bin Counter 27 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 26. "B26_OVF,Bin Counter 26 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 25. "B25_OVF,Bin Counter 25 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 24. "B24_OVF,Bin Counter 24 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 23. "B23_OVF,Bin Counter 23 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 22. "B22_OVF,Bin Counter 22 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 21. "B21_OVF,Bin Counter 21 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 20. "B20_OVF,Bin Counter 20 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 19. "B19_OVF,Bin Counter 19 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 18. "B18_OVF,Bin Counter 18 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 17. "B17_OVF,Bin Counter 17 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 16. "B16_OVF,Bin Counter 16 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 15. "B15_OVF,Bin Counter 15 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 14. "B14_OVF,Bin Counter 14 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 13. "B13_OVF,Bin Counter 13 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 12. "B12_OVF,Bin Counter 12 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 11. "B11_OVF,Bin Counter 11 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 10. "B10_OVF,Bin Counter 10 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 9. "B9_OVF,Bin Counter 9 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 8. "B8_OVF,Bin Counter 8 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 7. "B7_OVF,Bin Counter 7 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 6. "B6_OVF,Bin Counter 6 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 5. "B5_OVF,Bin Counter 5 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 4. "B4_OVF,Bin Counter 4 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 3. "B3_OVF,Bin Counter 3 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 2. "B2_OVF,Bin Counter 2 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 1. "B1_OVF,Bin Counter 1 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 0. "B0_OVF,Bin Counter 0 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
group.long 0xE4++0x03
line.long 0x00 "HIST_OVF_STATUS1,HIST Overflow Status 1"
eventfld.long 0x00 31. "B63_OVF,Bin Counter 63 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 30. "B62_OVF,Bin Counter 62 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 29. "B61_OVF,Bin Counter 61 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 28. "B60_OVF,Bin Counter 60 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 27. "B59_OVF,Bin Counter 59 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 26. "B58_OVF,Bin Counter 58 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 25. "B57_OVF,Bin Counter 57 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 24. "B56_OVF,Bin Counter 56 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 23. "B55_OVF,Bin Counter 55 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 22. "B54_OVF,Bin Counter 54 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 21. "B53_OVF,Bin Counter 53 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 20. "B52_OVF,Bin Counter 52 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 19. "B51_OVF,Bin Counter 51 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 18. "B50_OVF,Bin Counter 50 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 17. "B49_OVF,Bin Counter 49 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 16. "B48_OVF,Bin Counter 48 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 15. "B47_OVF,Bin Counter 47 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 14. "B46_OVF,Bin Counter 46 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 13. "B45_OVF,Bin Counter 45 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 12. "B44_OVF,Bin Counter 44 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 11. "B43_OVF,Bin Counter 43 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 10. "B42_OVF,Bin Counter 42 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 9. "B41_OVF,Bin Counter 41 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 8. "B40_OVF,Bin Counter 40 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 7. "B39_OVF,Bin Counter 39 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 6. "B38_OVF,Bin Counter 38 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 5. "B37_OVF,Bin Counter 37 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 4. "B36_OVF,Bin Counter 36 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 3. "B35_OVF,Bin Counter 35 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 2. "B34_OVF,Bin Counter 34 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 1. "B33_OVF,Bin Counter 33 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
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eventfld.long 0x00 0. "B32_OVF,Bin Counter 32 Overflow" "0: No overflow in HIST bin counter n,1: Overflow in HIST bin counter n"
group.long 0xE8++0x03
line.long 0x00 "HIST_OVF_IE,HIST Overflow Interrupt Enable"
bitfld.long 0x00 0. "OVF_IE,HIST Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
group.long 0x100++0x03
line.long 0x00 "MEM_ERR_INJECT_CTRL,Memory Error Injection"
bitfld.long 0x00 4.--7. "TR_PAR_ERR_INJ,Twiddle RAM Parity Error Injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "OR_PAR_ERR_INJ,Operand RAM Parity Error Injection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x104++0x03
line.long 0x00 "MEM_ERR_STATUS,Memory Error Status"
eventfld.long 0x00 28. "OR_PAR_ERR,OPRAM Banks 0-7 Parity Error" "0: NO_OR_NW_PAR_ERR,1: OR_NW_PAR_ERR"
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eventfld.long 0x00 20. "OR_BANK_RD_LOCK_ERR,OPRAM Banks 0-7 Read Lock Error" "0: NO_OR_NW_BANK_RD_LOCK_ERR,1: OR_NW_BANK_RD_LOCK_ERR"
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eventfld.long 0x00 16. "OR_BANK_WR_LOCK_ERR,OPRAM Banks 0-7 Write Lock Error" "0: NO_OR_NW_BANK_WR_LOCK_ERR,1: OR_NW_BANK_WR_LOCK_ERR"
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eventfld.long 0x00 14. "TR_PAR_ERR,TRAM Banks 0-1 Parity Error" "0: NO_TR_W_PAR_ERR,1: TR_W_PAR_ERR"
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eventfld.long 0x00 10. "TR_BANK_RD_LOCK_ERR,TRAM Banks 0-1 Read Lock Error" "0: NO_TR_W_BANK_RD_LOCK_ERR,1: TR_W_BANK_RD_LOCK_ERR"
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eventfld.long 0x00 8. "TR_BANK_WR_LOCK_ERR,TRAM Banks 0-1 Write Lock Error" "0: NO_TR_W_BANK_WR_LOCK_ERR,1: TR_W_BANK_WR_LOCK_ERR"
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eventfld.long 0x00 2. "SPR_LCK_VIOL,SPR Lock Violation Error" "0: No SPR lock violation error,1: SPR lock violation error"
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eventfld.long 0x00 1. "WR_LCK_VIOL,WR Lock Violation Error" "0: No WR lock violation error,1: WR lock violation error has occurred"
group.long 0x108++0x03
line.long 0x00 "MEM_ERR_INT_EN,Memory Interrupt Enable"
bitfld.long 0x00 28. "OR_PAR_ERR_IE,OPRAM Banks 0-7 Parity Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 20. "OR_BANK_RD_LOCK_ERR_IE,OPRAM Banks 0-7 Read Lock Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 16. "OR_BANK_WR_LOCK_ERR_IE,OPRAM Banks 0-7 Write Lock Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 14. "TR_PAR_ERR_IE,TRAM Bank 0-1 Parity Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 10. "TR_BANK_RD_LOCK_ERR_IE,TRAM Banks 0-1 Read Lock Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 8. "TR_BANK_WR_LOCK_ERR_IE,TRAM Banks 0-1 Write Lock Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 2. "SPR_LCK_IE,SPR Lock Violation Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 1. "WR_LCK_IE,WR Lock Violation Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
rgroup.long 0x10C++0x03
line.long 0x00 "OR_WR_LOCK_ERR_THRD_STATUS,OPRAM Write Lock Error Thread Status"
bitfld.long 0x00 0.--1. "OR_BANK_WR_LOCK_ERR_THRD,OPRAM Banks 0-7 Write Lock Error Thread" "0: xyz,1: SCS0,2: SCS1,?..."
rgroup.long 0x110++0x03
line.long 0x00 "OR_RD_LOCK_ERR_THRD_STATUS,OPRAM Read Lock Error Thread Status"
bitfld.long 0x00 0.--1. "OR_BANK_RD_LOCK_ERR_THRD,OPRAM Banks 0-7 Read Lock Error Thread" "0: xyz,1: SCS0,2: SCS1,?..."
rgroup.long 0x114++0x03
line.long 0x00 "TR_WR_LOCK_ERR_THRD_STATUS,TRAM Write Lock Error Thread Status"
bitfld.long 0x00 0.--1. "TR_BANK_WR_LOCK_ERR_THRD,TRAM Banks 0-1 Write Lock Error Thread" "0: xyz,1: SCS0,2: SCS1,?..."
rgroup.long 0x118++0x03
line.long 0x00 "TR_RD_LOCK_ERR_THRD_STATUS,TRAM Read Lock Error Thread Status"
bitfld.long 0x00 0.--1. "TR_BANK_RD_LOCK_ERR_THRD,TRAM Banks 0-1 Read Lock Error Thread" "0: xyz,1: SCS0,2: SCS1,?..."
rgroup.long 0x11C++0x03
line.long 0x00 "OR_WR_LOCK_ERR_ADDR,OPRAM Write Lock Error Address"
hexmask.long.word 0x00 0.--15. 1. "OR_BANK_WR_LOCK_ERR_ADDR,OPRAM Banks 0-7 Write Lock Error Address"
rgroup.long 0x124++0x03
line.long 0x00 "OR_RD_LOCK_ERR_ADDR,OPRAM Read Lock Error Address"
hexmask.long.word 0x00 0.--15. 1. "OR_BANK_RD_LOCK_ERR_ADDR,OPRAM Banks 0-7 Read Lock Error Address"
rgroup.long 0x12C++0x03
line.long 0x00 "TR_WR_LOCK_ERR_ADDR,TRAM Write Lock Error Address"
hexmask.long.word 0x00 0.--15. 1. "TR_BANK_WR_LOCK_ERR_ADDR,TRAM banks 0-1 write Lock Error Address"
rgroup.long 0x130++0x03
line.long 0x00 "TR_RD_LOCK_ERR_ADDR,TRAM Read Lock Error Address"
hexmask.long.word 0x00 0.--15. 1. "TR_BANK_RD_LOCK_ERR_ADDR,TRAM Banks 0-1 Read Lock Error Address"
rgroup.long 0x134++0x03
line.long 0x00 "OR_PAR_ERR_ADDR,OPRAM Parity Error Address"
hexmask.long.word 0x00 0.--15. 1. "OR_PAR_ERR_ADDR,OPRAM Banks 0-7 Parity Error Address"
rgroup.long 0x13C++0x03
line.long 0x00 "TR_PAR_ERR_ADDR,TRAM Parity Error Address"
hexmask.long.word 0x00 0.--15. 1. "TR_PAR_ERR_ADDR,TRAM Banks 0-1 Parity Error Address"
group.long 0x150++0x03
line.long 0x00 "SPT_AXI_QOS_RD,AXI QoS Priority Level for Read Masters"
bitfld.long 0x00 24.--27. "PDMA_AXI_RD_QOS,PDMA AXI Read QoS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "SCS1_AXI_RD_QOS,SCSn AXI Read QoS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "SCS0_AXI_RD_QOS,SCSn AXI Read QoS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "CS_AXI_RD_QOS,MCS AXI Read QoS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x154++0x03
line.long 0x00 "SPT_AXI_QOS_WR,AXI QoS Priority Level for Write Masters"
bitfld.long 0x00 24.--27. "PDMA_AXI_WR_QOS,PDMA AXI Write QoS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x158++0x03
line.long 0x00 "DMA_ERR_STATUS,DMA Error Status"
bitfld.long 0x00 18.--19. "PDMA_AXI_BRESP,PDMA AXI Write Response" "0: No write error,1: No write error,2: AXI write error,3: AXI write error"
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bitfld.long 0x00 16.--17. "PDMA_AXI_RRESP,PDMA AXI Read Response" "0: No read error,1: No read error,2: AXI read error,3: AXI read error"
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bitfld.long 0x00 4.--5. "SCS1_AXI_RRESP,SCS1 AXI Read Response" "0: No read error,1: No read error,2: AXI read error,3: AXI read error"
newline
bitfld.long 0x00 2.--3. "SCS0_AXI_RRESP,SCS0 AXI Read Response" "0: No read error,1: No read error,2: AXI read error,3: AXI read error"
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bitfld.long 0x00 0.--1. "CS_AXI_RRESP,MCS AXI Read Response" "0: No read error,1: No read error,2: AXI read error,3: AXI read error"
group.long 0x15C++0x03
line.long 0x00 "GBL_STATUS,Global Status"
eventfld.long 0x00 17. "PDMA_AXI_WR_ERR,AXI Write Error In PDMA" "0: No write error,1: Write error"
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eventfld.long 0x00 16. "PDMA_AXI_RD_ERR,AXI Read Error In PDMA" "0: No read error,1: Read error"
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eventfld.long 0x00 10. "SCS1_AXI_RD_ERR,AXI Read Error In SCS1" "0: No read error,1: Read error"
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eventfld.long 0x00 9. "SCS0_AXI_RD_ERR,AXI Read Error In SCS0" "0: No read error,1: Read error"
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eventfld.long 0x00 8. "CS_AXI_RD_ERR,AXI Read Error In MCS" "0: No read error,1: Read error"
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eventfld.long 0x00 2. "SCS1_PDMA_TRANS_DONE,SCS1 PDMA Transfer Done" "0: PDMA transfer not complete,1: PDMA transfer complete"
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eventfld.long 0x00 1. "SCS0_PDMA_TRANS_DONE,SCS0 PDMA Transfer Done" "0: PDMA transfer not complete,1: PDMA transfer complete"
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eventfld.long 0x00 0. "MCS_PDMA_TRANS_DONE,MCS PDMA Transfer Done" "0: PDMA transfer not complete,1: PDMA transfer complete"
group.long 0x160++0x03
line.long 0x00 "GBL_STATUS_IE,Global Status Interrupt Enable"
bitfld.long 0x00 17. "PDMA_AXI_WR_ERR_IE,AXI Write Error In PDMA Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 16. "PDMA_AXI_RD_ERR_IE,AXI Read Error In PDMA Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 10. "SCS1_AXI_RD_ERR_IE,AXI Read Error In SCS1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 9. "SCS0_AXI_RD_ERR_IE,AXI Read Error In SCS0 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 8. "CS_AXI_RD_ERR_IE,AXI Read Error In MCS Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 2. "SCS1_PDMA_TRANS_DONE_IE,SCS1 PDMA Transfer Done Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 1. "SCS0_PDMA_TRANS_DONE_IE,SCS0 PDMA Transfer Done Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
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bitfld.long 0x00 0. "MCS_PDMA_TRANS_DONE_IE,MCS PDMA Transfer Done Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
group.long 0x164++0x03
line.long 0x00 "HW_ACC_ERR_STATUS,Hardware Accelerator Error Status"
eventfld.long 0x00 31. "FFT_RDX2_RND_ERR,FFT Radix2 Round Error" "0: No error,1: Error"
newline
eventfld.long 0x00 30. "FFT_OPR_ADDR_ERR,FFT2 Operand Address Error" "0: No error,1: Error"
newline
eventfld.long 0x00 29. "FFT_MULT_COEF2_ERR,FFT MULT Coefficient 2 Error" "0: No error,1: Error"
newline
eventfld.long 0x00 28. "FFT_MULT_COEF1_ERR,FFT MULT Coefficient 1 Error" "0: No error,1: Error"
newline
eventfld.long 0x00 27. "FFT_TW_OVS_ERR,FFT Twiddle Oversampling Error" "0: No error,1: Error"
newline
eventfld.long 0x00 26. "FFT_QE_VL_OVS_ERR,Quadrature Extension Vector Length Oversampling Error" "0: No error,1: Error"
newline
eventfld.long 0x00 25. "FFT_RDX4_RND_ERR,FFT Radix4 Round Error" "0: No error,1: Error"
newline
eventfld.long 0x00 24. "FFT_WIN_RND_ERR,FFT Window Round Error" "0: No error,1: Error"
newline
eventfld.long 0x00 23. "MAXS_IP_CMD_ERR,Maxs Input Command Error" "0: No command error,1: Command error"
newline
eventfld.long 0x00 19. "COPY_IP_CMD_ERR,Copy Input Command Error" "0: No command error,1: Command error"
newline
eventfld.long 0x00 16. "PDMA_CMD_ERR,PDMA Command Error" "0: No error,1: Error"
newline
eventfld.long 0x00 15. "FFT_ILL_SHFTVAL,FFT Illegal Shift Value Error" "0: No error,1: Error"
newline
eventfld.long 0x00 12. "CS_DSP_IF_MISSING_RESP_ERR,DSP Interface Missing Response Error" "0: No error,1: Error"
newline
eventfld.long 0x00 11. "CS_DSP_IF_EXTRA_RESP_ERR,DSP Interface Extra Response Error" "0: No error,1: Error"
newline
eventfld.long 0x00 10. "HST_DESTADDR_UNALIGN_ERR,Destination Address Error" "0: No error,1: Error"
newline
eventfld.long 0x00 9. "HST_SRCADDR_UNALIGN_ERR,Source Address Not A Multiple of 8 Error" "0: No error,1: Error"
newline
eventfld.long 0x00 8. "HST_SRC_NOT_OR_ERR,Source Address Not In Operand RAM Error" "0: No error,1: Error"
newline
eventfld.long 0x00 7. "HST_VECLEN_NOT_MULTOF8_ERR,Vector Length Not Multiple Of 8 Error" "0: No error,1: Error"
newline
eventfld.long 0x00 6. "HST_INVALID_WR_ACCESS_ERR,HIST WR Access Error" "0: No error,1: Error"
newline
eventfld.long 0x00 5. "HST_INVALID_PROG_ERR,HIST Invalid Programming Error" "0: No error,1: Error"
newline
eventfld.long 0x00 3. "VMT_SHFT_OVF_ERR,Vmt Shift Overflow Error" "0: No saturation,1: Saturation"
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eventfld.long 0x00 2. "VMT_INVLD_DATA_ERR,Vmt Invalid Data Type Error" "0: No error,1: Error"
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eventfld.long 0x00 1. "VMT_INVLD_MODE_CFG_ERR,Vmt Invalid Mode Configuration Error" "0: No error,1: Error"
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eventfld.long 0x00 0. "VMT_INVLD_SRC_DEST_ERR,Vmt Invalid Source Destination Address Error" "0: No error,1: Error"
group.long 0x168++0x03
line.long 0x00 "HW_ACC_ERR_IE,Hardware Accelerator Error Interrupt Enable"
bitfld.long 0x00 31. "FFT_RDX2_RND_IE,FFT Radix2 Round Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 30. "FFT_OPR_ADDR_IE,Operand Address Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 29. "FFT_MULT_COEF2_IE,FFT MULT Coefficient 2 Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 28. "FFT_MULT_COEF1_IE,FFT MULT Coefficient 1 Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 27. "FFT_TW_OVS_IE,FFT Twiddle Oversampling Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 26. "FFT_QE_VL_OVS_IE,Quadrature Extension Vector Length Oversampling Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 25. "FFT_RDX4_RND_IE,FFT Radix4 Round Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 24. "FFT_WIN_RND_IE,FFT Window Round Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 23. "MAXS_IP_CMD_IE,Maxs Input Command Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 19. "COPY_IP_CMD_IE,Copy Input Command Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 16. "PDMA_CMD_IE,PDMA Command Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 15. "FFT_ILL_SHFTVAL_IE,FFT Illegal Shift Value Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 12. "CS_DSP_IF_MISSING_RESP_ERR_IE,DSP Interface Missing Response Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 11. "CS_DSP_IF_EXTRA_RESP_ERR_IE,DSP Interface Extra Response Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 10. "HST_DESTADDR_UNALIGN_ERR_IE,Destination Address Not Multiple Of 8 Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 9. "HST_SRCADDR_UNALIGN_ERR_IE,Source Address Not Multiple of 8 Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 8. "HST_SRC_NOT_OR_ERR_IE,Source Not Operand RAM Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 7. "HST_VECLEN_NOT_MULTOF8_ERR_IE,Vector Length Not A Multiple Of 8 Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 6. "HST_INVALID_WR_ACCESS_ERR_IE,HIST WR Access Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 5. "HST_INVALID_PROG_ERR_IE,HIST Invalid Programming Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 3. "VMT_SHFT_OVF_IE,Vmt Shift Overflow Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 2. "VMT_INVLD_DATA_IE,Vmt Invalid Data Type Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 1. "VMT_INVLD_MODE_CFG_IE,Vmt Invalid Mode Configuration Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 0. "VMT_INVLD_SRC_DEST_IE,Vmt Invalid Source Destination Address Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
group.long 0x174++0x03
line.long 0x00 "WR_ACCESS_ERR_REG,Work Register/SPR Access Error Status"
eventfld.long 0x00 26. "DSP_SPR_ACC_ERR2,DSP Attempted To Access An Out-of-Range SPR Address Error (DSP lookup interface 2)" "0: DSP has not attempted to access out-of-range..,1: DSP attempted to access out-of-range SPR.."
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eventfld.long 0x00 25. "DSP_SPR_ACC_ERR1,DSP Attempted To Access An Out-of-Range SPR Address Error (DSP lookup interface 1)" "0: DSP has not attempted to access out-of-range..,1: DSP attempted to access out-of-range SPR.."
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eventfld.long 0x00 24. "DSP_SPR_ACC_ERR0,DSP Attempted To Access An Out-of-Range SPR Address Error (DSP lookup interface 0)" "0: DSP has not attempted to access out-of-range..,1: DSP attempted to access out-of-range SPR.."
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eventfld.long 0x00 18. "DSP_RF_ACC_ERR2,DSP Attempted To Access An Out-of-Range WR Address Error (DSP lookup interface 2)" "0: DSP has not attempted to access out-of-range..,1: DSP attempted to access out-of-range work.."
newline
eventfld.long 0x00 17. "DSP_RF_ACC_ERR1,DSP Attempted To Access An Out-of-Range WR Address Error (DSP lookup interface 1)" "0: DSP has not attempted to access out-of-range..,1: DSP attempted to access out-of-range work.."
newline
eventfld.long 0x00 16. "DSP_RF_ACC_ERR0,DSP Attempted To Access An Out-of-Range WR Address Error (DSP lookup interface 0)" "0: DSP has not attempted to access out-of-range..,1: DSP attempted to access out-of-range work.."
newline
eventfld.long 0x00 10. "SPT_SPR_ACC_ERR2,SCS1 SPR Conflict Error" "0: No SCS1 SPR access conflict error has occurred,1: An SCS1 SPR access conflict error has occurred"
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eventfld.long 0x00 9. "SPT_SPR_ACC_ERR1,SCS0 SPR Conflict Error" "0: No SCS0 SPR access conflict error has occurred,1: An SCS0 SPR access conflict error has occurred"
newline
eventfld.long 0x00 8. "SPT_SPR_ACC_ERR0,MCS SPR Access Conflict Error" "0: No MCS SPR access conflict error occurred,1: An MCS SPR access conflict error occurred"
newline
eventfld.long 0x00 2. "SPT_RF_ACC_ERR2,SCS1 WR Access Conflict Error" "0: No SCS1 WR access conflict error,1: SCS1 WR access conflict error"
newline
eventfld.long 0x00 1. "SPT_RF_ACC_ERR1,SCS0 WR Access Conflict Error" "0: No SCS0 WR access conflict error,1: SCS0 WR access conflict error"
newline
eventfld.long 0x00 0. "SPT_RF_ACC_ERR0,MCS WR Access Conflict Error" "0: No MCS WR access conflict error occurred,1: MCS WR access conflict error occurred"
group.long 0x178++0x03
line.long 0x00 "WR_ACCESS_ERR_INT_EN,WR/SPR Access Error Interrupt Enable"
bitfld.long 0x00 0. "RF_SPR_ACC_IE,WR/SPR Access Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
group.long 0x180++0x03
line.long 0x00 "WR_0_15_CTRL_REG,Access Control For WRs 0-15"
bitfld.long 0x00 31. "WR15_ACC_CTRL,WR 15 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 30. "WR15_LCK,WR 15 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 29. "WR14_ACC_CTRL,WR 14 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 28. "WR14_LCK,WR 14 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
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bitfld.long 0x00 27. "WR13_ACC_CTRL,WR 13 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 26. "WR13_LCK,WR 13 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 25. "WR12_ACC_CTRL,WR 12 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 24. "WR12_LCK,WR 12 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 23. "WR11_ACC_CTRL,WR 11 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 22. "WR11_LCK,WR 11 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 21. "WR10_ACC_CTRL,WR 10 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 20. "WR10_LCK,WR 10 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 19. "WR9_ACC_CTRL,WR 9 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 18. "WR9_LCK,WR 9 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 17. "WR8_ACC_CTRL,WR 8 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 16. "WR8_LCK,WR 8 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 15. "WR7_ACC_CTRL,WR 7 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 14. "WR7_LCK,WR 7 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 13. "WR6_ACC_CTRL,WR 6 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 12. "WR6_LCK,WR 6 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 11. "WR5_ACC_CTRL,WR 5 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 10. "WR5_LCK,WR 5 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 9. "WR4_ACC_CTRL,WR 4 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 8. "WR4_LCK,WR 4 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 7. "WR3_ACC_CTRL,WR 3 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 6. "WR3_LCK,WR 3 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 5. "WR2_ACC_CTRL,WR 2 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 4. "WR2_LCK,WR 2 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 3. "WR1_ACC_CTRL,WR 1 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 2. "WR1_LCK,WR 1 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 1. "WR0_ACC_CTRL,WR 0 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 0. "WR0_LCK,WR 0 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
group.long 0x184++0x03
line.long 0x00 "WR_16_31_CTRL_REG,Access Control for WRs 16-31"
bitfld.long 0x00 31. "WR31_ACC_CTRL,WR 31 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 30. "WR31_LCK,WR 31 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 29. "WR30_ACC_CTRL,WR 30 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 28. "WR30_LCK,WR 30 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 27. "WR29_ACC_CTRL,WR 29 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 26. "WR29_LCK,WR 29 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 25. "WR28_ACC_CTRL,WR 28 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 24. "WR28_LCK,WR 28 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 23. "WR27_ACC_CTRL,WR 27 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 22. "WR27_LCK,WR 27 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 21. "WR26_ACC_CTRL,WR 26 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 20. "WR26_LCK,WR 26 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 19. "WR25_ACC_CTRL,WR 25 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 18. "WR25_LCK,WR 25 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 17. "WR24_ACC_CTRL,WR 24 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 16. "WR24_LCK,WR 24 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 15. "WR23_ACC_CTRL,WR 23 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 14. "WR23_LCK,WR 23 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 13. "WR22_ACC_CTRL,WR 22 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 12. "WR22_LCK,WR 22 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 11. "WR21_ACC_CTRL,WR 21 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 10. "WR21_LCK,WR 21 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 9. "WR20_ACC_CTRL,WR 20 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 8. "WR20_LCK,WR 20 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 7. "WR19_ACC_CTRL,WR 19 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 6. "WR19_LCK,WR 19 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 5. "WR18_ACC_CTRL,WR 18 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 4. "WR18_LCK,WR 18 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 3. "WR17_ACC_CTRL,WR 17 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 2. "WR17_LCK,WR 17 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 1. "WR16_ACC_CTRL,WR 16 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 0. "WR16_LCK,WR 16 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
group.long 0x188++0x03
line.long 0x00 "WR_32_47_CTRL_REG,Access Control for WRs 32-47"
bitfld.long 0x00 31. "WR47_ACC_CTRL,WR 47 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 30. "WR47_LCK,WR 47 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 29. "WR46_ACC_CTRL,WR 46 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 28. "WR46_LCK,WR 46 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 27. "WR45_ACC_CTRL,WR 45 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 26. "WR45_LCK,WR 45 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 25. "WR44_ACC_CTRL,WR 44 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 24. "WR44_LCK,WR 44 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 23. "WR43_ACC_CTRL,WR 43 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 22. "WR43_LCK,WR 43 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 21. "WR42_ACC_CTRL,WR 42 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 20. "WR42_LCK,WR 42 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 19. "WR41_ACC_CTRL,WR 41 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 18. "WR41_LCK,WR 41 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 17. "WR40_ACC_CTRL,WR 40 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 16. "WR40_LCK,WR 40 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 15. "WR39_ACC_CTRL,WR 39 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 14. "WR39_LCK,WR 39 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 13. "WR38_ACC_CTRL,WR 38 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 12. "WR38_LCK,WR 38 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 11. "WR37_ACC_CTRL,WR 37 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 10. "WR37_LCK,WR 37 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 9. "WR36_ACC_CTRL,WR 36 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 8. "WR36_LCK,WR 36 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 7. "WR35_ACC_CTRL,WR 35 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 6. "WR35_LCK,WR 35 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 5. "WR34_ACC_CTRL,WR 34 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 4. "WR34_LCK,WR 34 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 3. "WR33_ACC_CTRL,WR 33 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 2. "WR33_LCK,WR 33 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
newline
bitfld.long 0x00 1. "WR32_ACC_CTRL,WR 32 Access Control" "0: SPT has write access,1: CPU/DSP has write access"
newline
bitfld.long 0x00 0. "WR32_LCK,WR 32 Lock" "0: Both SPT and CPU/DSP have write access,1: Only one of SPT or CPU/DSP (selected via.."
group.long 0x198++0x03
line.long 0x00 "WR_R0_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x19C++0x03
line.long 0x00 "WR_R0_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x1A0++0x03
line.long 0x00 "WR_R1_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x1A4++0x03
line.long 0x00 "WR_R1_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x1A8++0x03
line.long 0x00 "WR_R2_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x1AC++0x03
line.long 0x00 "WR_R2_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x1B0++0x03
line.long 0x00 "WR_R3_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x1B4++0x03
line.long 0x00 "WR_R3_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x1B8++0x03
line.long 0x00 "WR_R4_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x1BC++0x03
line.long 0x00 "WR_R4_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x1C0++0x03
line.long 0x00 "WR_R5_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x1C4++0x03
line.long 0x00 "WR_R5_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x1C8++0x03
line.long 0x00 "WR_R6_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x1CC++0x03
line.long 0x00 "WR_R6_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x1D0++0x03
line.long 0x00 "WR_R7_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x1D4++0x03
line.long 0x00 "WR_R7_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x1D8++0x03
line.long 0x00 "WR_R8_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x1DC++0x03
line.long 0x00 "WR_R8_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x1E0++0x03
line.long 0x00 "WR_R9_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x1E4++0x03
line.long 0x00 "WR_R9_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x1E8++0x03
line.long 0x00 "WR_R10_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x1EC++0x03
line.long 0x00 "WR_R10_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x1F0++0x03
line.long 0x00 "WR_R11_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x1F4++0x03
line.long 0x00 "WR_R11_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x1F8++0x03
line.long 0x00 "WR_R12_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x1FC++0x03
line.long 0x00 "WR_R12_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x200++0x03
line.long 0x00 "WR_R13_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x204++0x03
line.long 0x00 "WR_R13_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x208++0x03
line.long 0x00 "WR_R14_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x20C++0x03
line.long 0x00 "WR_R14_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x210++0x03
line.long 0x00 "WR_R15_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x214++0x03
line.long 0x00 "WR_R15_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x218++0x03
line.long 0x00 "WR_R16_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x21C++0x03
line.long 0x00 "WR_R16_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x220++0x03
line.long 0x00 "WR_R17_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x224++0x03
line.long 0x00 "WR_R17_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x228++0x03
line.long 0x00 "WR_R18_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x22C++0x03
line.long 0x00 "WR_R18_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x230++0x03
line.long 0x00 "WR_R19_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x234++0x03
line.long 0x00 "WR_R19_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x238++0x03
line.long 0x00 "WR_R20_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x23C++0x03
line.long 0x00 "WR_R20_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x240++0x03
line.long 0x00 "WR_R21_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x244++0x03
line.long 0x00 "WR_R21_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x248++0x03
line.long 0x00 "WR_R22_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x24C++0x03
line.long 0x00 "WR_R22_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x250++0x03
line.long 0x00 "WR_R23_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x254++0x03
line.long 0x00 "WR_R23_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x258++0x03
line.long 0x00 "WR_R24_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x25C++0x03
line.long 0x00 "WR_R24_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x260++0x03
line.long 0x00 "WR_R25_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x264++0x03
line.long 0x00 "WR_R25_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x268++0x03
line.long 0x00 "WR_R26_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x26C++0x03
line.long 0x00 "WR_R26_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x270++0x03
line.long 0x00 "WR_R27_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x274++0x03
line.long 0x00 "WR_R27_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x278++0x03
line.long 0x00 "WR_R28_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x27C++0x03
line.long 0x00 "WR_R28_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x280++0x03
line.long 0x00 "WR_R29_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x284++0x03
line.long 0x00 "WR_R29_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x288++0x03
line.long 0x00 "WR_R30_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x28C++0x03
line.long 0x00 "WR_R30_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x290++0x03
line.long 0x00 "WR_R31_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x294++0x03
line.long 0x00 "WR_R31_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x298++0x03
line.long 0x00 "WR_R32_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x29C++0x03
line.long 0x00 "WR_R32_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x2A0++0x03
line.long 0x00 "WR_R33_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x2A4++0x03
line.long 0x00 "WR_R33_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x2A8++0x03
line.long 0x00 "WR_R34_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x2AC++0x03
line.long 0x00 "WR_R34_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x2B0++0x03
line.long 0x00 "WR_R35_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x2B4++0x03
line.long 0x00 "WR_R35_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x2B8++0x03
line.long 0x00 "WR_R36_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x2BC++0x03
line.long 0x00 "WR_R36_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x2C0++0x03
line.long 0x00 "WR_R37_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x2C4++0x03
line.long 0x00 "WR_R37_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x2C8++0x03
line.long 0x00 "WR_R38_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x2CC++0x03
line.long 0x00 "WR_R38_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x2D0++0x03
line.long 0x00 "WR_R39_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x2D4++0x03
line.long 0x00 "WR_R39_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x2D8++0x03
line.long 0x00 "WR_R40_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x2DC++0x03
line.long 0x00 "WR_R40_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x2E0++0x03
line.long 0x00 "WR_R41_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x2E4++0x03
line.long 0x00 "WR_R41_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x2E8++0x03
line.long 0x00 "WR_R42_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x2EC++0x03
line.long 0x00 "WR_R42_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x2F0++0x03
line.long 0x00 "WR_R43_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x2F4++0x03
line.long 0x00 "WR_R43_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x2F8++0x03
line.long 0x00 "WR_R44_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x2FC++0x03
line.long 0x00 "WR_R44_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x300++0x03
line.long 0x00 "WR_R45_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x304++0x03
line.long 0x00 "WR_R45_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x308++0x03
line.long 0x00 "WR_R46_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x30C++0x03
line.long 0x00 "WR_R46_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x310++0x03
line.long 0x00 "WR_R47_RE,WR n Real"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_WR,Real Component of WR n"
group.long 0x314++0x03
line.long 0x00 "WR_R47_IM,WR n Imaginary"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "IM_WR,Imaginary part of WR n"
group.long 0x400++0x03
line.long 0x00 "SCS0_JAM_INST0,SCSn Jamming Command 0"
hexmask.long 0x00 0.--31. 1. "JAM_INST_31_0,SCSn Jamming Command Bits 31-0"
group.long 0x404++0x03
line.long 0x00 "SCS0_JAM_INST1,SCSn Jamming Command 1"
hexmask.long 0x00 0.--31. 1. "JAM_INST_63_32,SCSn Jamming Command Bits 63-32"
group.long 0x408++0x03
line.long 0x00 "SCS0_JAM_INST2,SCSn Jamming Command 2"
hexmask.long 0x00 0.--31. 1. "JAM_INST_95_64,SCSn Jamming Command Bits 95-64"
group.long 0x40C++0x03
line.long 0x00 "SCS0_JAM_INST3,SCSn Jamming Command 3"
hexmask.long 0x00 0.--31. 1. "JAM_INST_127_96,SCSn Jamming Command Bits 127-96"
rgroup.long 0x410++0x03
line.long 0x00 "SCS0_CURR_INST_ADDR,SCSn Current Command Address"
hexmask.long 0x00 0.--31. 1. "CURRENT_INST_ADDR,SCSn Current Command Pointer"
rgroup.long 0x414++0x03
line.long 0x00 "SCS0_CURR_INST0,SCSn Current Command"
hexmask.long 0x00 0.--31. 1. "CURR_INST_31_0,SCSn Current Command Bits 31-0"
rgroup.long 0x418++0x03
line.long 0x00 "SCS0_CURR_INST1,SCSn Current Command"
hexmask.long 0x00 0.--31. 1. "CURR_INST_63_32,SCSn Current Command Bits 63-32"
rgroup.long 0x41C++0x03
line.long 0x00 "SCS0_CURR_INST2,SCSn Current Command"
hexmask.long 0x00 0.--31. 1. "CURR_INST_95_64,SCSn Current Command Bits 95-64"
rgroup.long 0x420++0x03
line.long 0x00 "SCS0_CURR_INST3,SCSn Current Command"
hexmask.long 0x00 0.--31. 1. "CURR_INST_127_96,SCSn Current Command Bits 127-96"
rgroup.long 0x424++0x03
line.long 0x00 "SCS0_LOOPCNTR01,SCSn Loop Counters 0 and 1"
hexmask.long.word 0x00 16.--31. 1. "SCS_LOOP_CNTR1,SCSn Loop Counter 1"
newline
hexmask.long.word 0x00 0.--15. 1. "SCS_LOOP_CNTR0,SCSn Loop Counter 0"
rgroup.long 0x428++0x03
line.long 0x00 "SCS0_LOOPCNTR23,SCSn Loop Counters 2 and 3"
hexmask.long.word 0x00 16.--31. 1. "SCS_LOOP_CNTR3,SCSn Loop Counter 3"
newline
hexmask.long.word 0x00 0.--15. 1. "SCS_LOOP_CNTR2,SCSn Loop Counter 2"
rgroup.long 0x42C++0x03
line.long 0x00 "SCS0_ERR_INST_ADDR,SCSn Error Command Address"
hexmask.long 0x00 0.--31. 1. "SCS_ERROR_INST_ADDR,Error Command Pointer"
rgroup.long 0x430++0x03
line.long 0x00 "SCS0_ERR_INST0,SCSn Error Command 0"
hexmask.long 0x00 0.--31. 1. "SCS_ERR_INST_127_96,SCSn Error Command Bits 127-96"
rgroup.long 0x434++0x03
line.long 0x00 "SCS0_ERR_INST1,SCSn Error Command 1"
hexmask.long 0x00 0.--31. 1. "SCS_ERR_INST_95_64,SCSn Error Command Bits 95-64"
rgroup.long 0x438++0x03
line.long 0x00 "SCS0_ERR_INST2,SCSn Error Command 2"
hexmask.long 0x00 0.--31. 1. "SCS_ERR_INST_63_32,SCSn Error Command Bits 63-32"
rgroup.long 0x43C++0x03
line.long 0x00 "SCS0_ERR_INST3,SCSn Error Command 3"
hexmask.long 0x00 0.--31. 1. "SCS_ERR_INST_31_0,SCSn Error Command Bits 31-0"
group.long 0x440++0x03
line.long 0x00 "SCS0_STATUS0,SCSn General Status 0"
eventfld.long 0x00 16. "BKPT3_OCC,SCSn Breakpoint 3 Encountered Indicator" "0: SCSn has not encountered enabled breakpoint 3..,1: SCSn has encountered enabled breakpoint 3.."
newline
eventfld.long 0x00 15. "BKPT2_OCC,SCSn Breakpoint 2 Encountered Indicator" "0: SCSn has not encountered enabled breakpoint 2..,1: SCSn has encountered enabled breakpoint 2.."
newline
eventfld.long 0x00 14. "BKPT1_OCC,SCSn Breakpoint 1 Encountered Indicator" "0: SCSn has not encountered enabled breakpoint 1..,1: SCSn has encountered enabled breakpoint 1.."
newline
eventfld.long 0x00 13. "BKPT0_OCC,SCSn Breakpoint 0 Encountered Indicator" "0: Breakpoint not encountered,1: Breakpoint encountered"
newline
eventfld.long 0x00 12. "JAM_OVR,SCSn Debug State Command Jamming Mode Command Completion Indicator" "0,1"
newline
eventfld.long 0x00 11. "STEP_JUMP_OVR,SCSn Debug state Step To Next Breakpoint mode Indicator" "0,1"
newline
eventfld.long 0x00 10. "STEP_ONCE_OVR,SCSn Debug State Step Once Mode Command Completion Indicator" "0,1"
newline
eventfld.long 0x00 9. "MD_JAM,SCSn Debug State Command Jamming Mode Indicator" "0: SCSn not in Command Jamming mode in Debug state,1: SCSn in Command Jamming mode in Debug state"
newline
eventfld.long 0x00 8. "MD_STEP_JUMP,SCSn Step To Next Breakpoint mode in Debug state Indicator" "0: SCSn not in Step To Next Breakpoint mode in..,1: SCSn in Step To Next Breakpoint mode in Debug.."
newline
eventfld.long 0x00 7. "MD_STEP_ONCE,SCSn Debug State Step Once Mode Indicator" "0: SCSn not in Step Once mode in Debug state,1: SCSn in Step Once mode in Debug state"
newline
eventfld.long 0x00 6. "MD_HALT,SCSn Debug State Halt Mode Indicator" "0: SCSn not in Halt mode in Debug state,1: SCSn in Halt mode in Debug state"
newline
eventfld.long 0x00 5. "PS_RUN,SCSn Run State Indicator" "0: SCSn not in Run state,1: SCSn in Run state"
newline
eventfld.long 0x00 4. "PS_ASYNCSTOP,SCSn Asyncstop State Indicator" "0: SCSn not in Asyncstop state,1: SCSn in Asyncstop state"
newline
eventfld.long 0x00 3. "PS_STOP,SCSn Stop State Indicator" "0: SCSn not in Stop state,1: SCSn in Stop state"
newline
eventfld.long 0x00 2. "PS_DEBUG,SCSn Debug State Indicator" "0: SCSn not in Debug state,1: SCSn in Debug state"
newline
eventfld.long 0x00 1. "PS_WAIT,SCSn Wait State Indicator" "0: SCSn not in Wait state,1: SCSn in Wait state"
newline
eventfld.long 0x00 0. "PS_START,SCSn Start State Indicator" "0: SCSn not in Start state,1: SCSn in Start state"
group.long 0x444++0x03
line.long 0x00 "SCS0_STATUS1,SCSn General Status 1"
eventfld.long 0x00 11. "JAM_ILL_JUMP,SCSn Illegal JUMP Command in Debug State Command Jamming Mode Error" "0: No attempted execution of a JUMP command,1: Attempted execution of a JUMP command"
newline
eventfld.long 0x00 10. "JAM_ILL_NEXT,SCSn Illegal Next Command in Debug State Command Jamming Mode Error" "0: No attempted execution of a Next command,1: Attempted execution of a Next command"
newline
eventfld.long 0x00 9. "JAM_ILL_LOOP,SCSn Illegal Loop Command in Debug State Command Jamming Mode Error" "0: No attempted execution of a Loop command,1: Attempted execution of a Loop command"
newline
eventfld.long 0x00 8. "JAM_ILL_SYNC,SCSn Illegal SYNC Command in Debug State Command Jamming Mode Error" "0: No attempted execution of a SYNC command,1: Attempted execution of a SYNC command"
newline
eventfld.long 0x00 7. "JAM_ILL_OPCODE,SCSn Illegal Opcode in Debug state Command Jamming Mode Error" "0: No attempted execution of an illegal command..,1: Attempted execution of an illegal command.."
newline
eventfld.long 0x00 6. "ILL_ADD,SCSn Illegal Add Command Error" "0: No attempted execution of an illegal Add Sub..,1: Attempted execution of an illegal Add Sub Cmp.."
newline
eventfld.long 0x00 5. "ILL_GET,SCSn Illegal Get Command Error" "0: No attempted execution of an illegal Get..,1: Attempted execution of an illegal Get command"
newline
eventfld.long 0x00 4. "ILL_SET,SCSn Illegal Set Command Error" "0: No attempted execution of an illegal Set..,1: Attempted execution of an illegal Set command"
newline
eventfld.long 0x00 3. "ILL_NEXT,SCSn Illegal Next Command Error" "0: No attempted execution of a Next command,1: Attempted execution of a Next command"
newline
eventfld.long 0x00 2. "ILL_0CNTLOOP,SCSn Illegal Loop Count Error" "0: No attempted execution of a Loop command with..,1: Attempted execution of a Loop command with.."
newline
eventfld.long 0x00 1. "ILL_LOOP,SCSn Illegal Loop Command Error" "0: No attempted execution of a Loop command,1: Attempted execution of a Loop command"
newline
eventfld.long 0x00 0. "ILL_OPCODE,SCSn Illegal Opcode Error" "0: No attempted execution of an illegal command..,1: Attempted execution of an illegal command.."
rgroup.long 0x448++0x03
line.long 0x00 "SCS0_STATUS2,SCSn General Status 2"
bitfld.long 0x00 29.--30. "WAITREG_EVT_TYPE,WAIT Event Type" "?,1: WAIT event is CPU event,2: WAIT event is external event,3: WAIT event is internal event"
newline
hexmask.long.byte 0x00 16.--22. 1. "WAITREG_EVT_NUMBER,Event Number For WAIT Command"
newline
hexmask.long.word 0x00 0.--15. 1. "WAITREG_SW,Wait Status for Software-Triggered CPU Event"
rgroup.long 0x44C++0x03
line.long 0x00 "SCS0_STATUS3,SCSn General Status 3"
bitfld.long 0x00 3.--6. "PROC_STATE,SCSn Processing State" "0: SCSn in Rst state,1: SCSn in Start state,2: SCSn in Setup state,3: SCSn in Run state,4: SCSn in Wait state,5: SCSn in Debug state,6: SCSn in Stop state,7: SCSn in Asyncstop state,?..."
newline
bitfld.long 0x00 0.--2. "LOOP_DEPTH,SCSn Loop Depth" "0: No loop is being executed,1: Loop has nesting level depth of 1,2: Loop has nesting level depth of 2,3: Loop has nesting level depth of 3,4: Loop has nesting level depth of 4,?..."
group.long 0x450++0x03
line.long 0x00 "SCS0_INTEN0,SCSn Interrupt Enable 0"
bitfld.long 0x00 16. "BKPT3_OCC_INTEN,SCSn Breakpoint 3 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 15. "BKPT2_OCC_INTEN,SCSn Breakpoint 2 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 14. "BKPT1_OCC_INTEN,SCSn Breakpoint 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 13. "BKPT0_OCC_INTEN,SCSn Breakpoint 0 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 12. "JAM_OVR_INTEN,SCSn Debug State Jamming Command Over Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 11. "STEP_JUMP_OVR_INTEN,SCSn Breakpoint Encountered in Debug State Step To Next Breakpoint Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 10. "STEP_ONCE_OVR_INTEN,SCSn Debug State Step Once Mode Command Over Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 9. "MD_JAM_INTEN,SCSn Debug State Command Jamming Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 8. "MD_STEP_JUMP_INTEN,SCSn Debug State Step To Next Breakpoint Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 7. "MD_STEP_ONCE_INTEN,SCSn Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 6. "MD_HALT_INTEN,SCSn Debug State Halt Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 5. "PS_RUN_INTEN,SCSn Run State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 4. "PS_ASYNCSTOP_INTEN,SCSn Asyncstop State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 3. "PS_STOP_INTEN,SCSn Stop State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 2. "PS_DEBUG_INTEN,SCSn Debug State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 1. "PS_WAIT_INTEN,SCSn Wait State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 0. "PS_START_INTEN,SCSn Start State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
group.long 0x454++0x03
line.long 0x00 "SCS0_INTEN1,SCSn Interrupt Enable 1"
bitfld.long 0x00 11. "JAM_ILL_JUMP_INTEN,SCSn Illegal JUMP Command in Debug State Command Jamming Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 10. "JAM_ILL_NEXT_INTEN,SCSn Illegal Next Command in Debug State Command Jamming Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 9. "JAM_ILL_LOOP_INTEN,SCSn Illegal Loop Command in Debug State Command Jamming Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 8. "JAM_ILL_SYNC_INTEN,SCSn Illegal SYNC Command in Debug State Command Jamming Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 7. "JAM_ILL_OPCODE_INTEN,SCSn Illegal Opcode in Debug State Command Jamming Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 6. "ILL_ADD_INTEN,SCSn Illegal Add Command Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 5. "ILL_GET_INTEN,SCSn Illegal Get Command Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 4. "ILL_SET_INTEN,SCSn Illegal Set Command Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 3. "ILL_NEXT_INTEN,SCSn Illegal Next Command Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 2. "ILL_0CNTLOOP_INTEN,SCSn Illegal Loop Count Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 1. "ILL_LOOP_INTEN,SCSn Illegal Loop Command Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 0. "ILL_OPCODE_INTEN,SCSn Illegal Opcode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
rgroup.long 0x458++0x03
line.long 0x00 "SCS0_PDMA_TRANSFER_COUNT_STATUS,SCSn PDMA Transfer Count Status"
hexmask.long.word 0x00 16.--31. 1. "AGGR_DATA_COUNT,Aggregation Data Count"
newline
hexmask.long.word 0x00 0.--15. 1. "TRANSFER_COUNT,Number of Words Transferred via PDMA"
rgroup.long 0x45C++0x03
line.long 0x00 "SCS0_PDMA_FMTB_EXP_ADDR_STATUS,SCSn PDMA FormatB Exponent Address Status"
hexmask.long 0x00 3.--31. 1. "EXPN_ADDR,Exponent Address"
group.long 0x4A0++0x03
line.long 0x00 "SCS1_JAM_INST0,SCSn Jamming Command 0"
hexmask.long 0x00 0.--31. 1. "JAM_INST_31_0,SCSn Jamming Command Bits 31-0"
group.long 0x4A4++0x03
line.long 0x00 "SCS1_JAM_INST1,SCSn Jamming Command 1"
hexmask.long 0x00 0.--31. 1. "JAM_INST_63_32,SCSn Jamming Command Bits 63-32"
group.long 0x4A8++0x03
line.long 0x00 "SCS1_JAM_INST2,SCSn Jamming Command 2"
hexmask.long 0x00 0.--31. 1. "JAM_INST_95_64,SCSn Jamming Command Bits 95-64"
group.long 0x4AC++0x03
line.long 0x00 "SCS1_JAM_INST3,SCSn Jamming Command 3"
hexmask.long 0x00 0.--31. 1. "JAM_INST_127_96,SCSn Jamming Command Bits 127-96"
rgroup.long 0x4B0++0x03
line.long 0x00 "SCS1_CURR_INST_ADDR,SCSn Current Command Address"
hexmask.long 0x00 0.--31. 1. "CURRENT_INST_ADDR,SCSn Current Command Pointer"
rgroup.long 0x4B4++0x03
line.long 0x00 "SCS1_CURR_INST0,SCSn Current Command"
hexmask.long 0x00 0.--31. 1. "CURR_INST_31_0,SCSn Current Command Bits 31-0"
rgroup.long 0x4B8++0x03
line.long 0x00 "SCS1_CURR_INST1,SCSn Current Command"
hexmask.long 0x00 0.--31. 1. "CURR_INST_63_32,SCSn Current Command Bits 63-32"
rgroup.long 0x4BC++0x03
line.long 0x00 "SCS1_CURR_INST2,SCSn Current Command"
hexmask.long 0x00 0.--31. 1. "CURR_INST_95_64,SCSn Current Command Bits 95-64"
rgroup.long 0x4C0++0x03
line.long 0x00 "SCS1_CURR_INST3,SCSn Current Command"
hexmask.long 0x00 0.--31. 1. "CURR_INST_127_96,SCSn Current Command Bits 127-96"
rgroup.long 0x4C4++0x03
line.long 0x00 "SCS1_LOOPCNTR01,SCSn Loop Counters 0 and 1"
hexmask.long.word 0x00 16.--31. 1. "SCS_LOOP_CNTR1,SCSn Loop Counter 1"
newline
hexmask.long.word 0x00 0.--15. 1. "SCS_LOOP_CNTR0,SCSn Loop Counter 0"
rgroup.long 0x4C8++0x03
line.long 0x00 "SCS1_LOOPCNTR23,SCSn Loop Counters 2 and 3"
hexmask.long.word 0x00 16.--31. 1. "SCS_LOOP_CNTR3,SCSn Loop Counter 3"
newline
hexmask.long.word 0x00 0.--15. 1. "SCS_LOOP_CNTR2,SCSn Loop Counter 2"
rgroup.long 0x4CC++0x03
line.long 0x00 "SCS1_ERR_INST_ADDR,SCSn Error Command Address"
hexmask.long 0x00 0.--31. 1. "SCS_ERROR_INST_ADDR,Error Command Pointer"
rgroup.long 0x4D0++0x03
line.long 0x00 "SCS1_ERR_INST0,SCSn Error Command 0"
hexmask.long 0x00 0.--31. 1. "SCS_ERR_INST_127_96,SCSn Error Command Bits 127-96"
rgroup.long 0x4D4++0x03
line.long 0x00 "SCS1_ERR_INST1,SCSn Error Command 1"
hexmask.long 0x00 0.--31. 1. "SCS_ERR_INST_95_64,SCSn Error Command Bits 95-64"
rgroup.long 0x4D8++0x03
line.long 0x00 "SCS1_ERR_INST2,SCSn Error Command 2"
hexmask.long 0x00 0.--31. 1. "SCS_ERR_INST_63_32,SCSn Error Command Bits 63-32"
rgroup.long 0x4DC++0x03
line.long 0x00 "SCS1_ERR_INST3,SCSn Error Command 3"
hexmask.long 0x00 0.--31. 1. "SCS_ERR_INST_31_0,SCSn Error Command Bits 31-0"
group.long 0x4E0++0x03
line.long 0x00 "SCS1_STATUS0,SCSn General Status 0"
eventfld.long 0x00 16. "BKPT3_OCC,SCSn Breakpoint 3 Encountered Indicator" "0: SCSn has not encountered enabled breakpoint 3..,1: SCSn has encountered enabled breakpoint 3.."
newline
eventfld.long 0x00 15. "BKPT2_OCC,SCSn Breakpoint 2 Encountered Indicator" "0: SCSn has not encountered enabled breakpoint 2..,1: SCSn has encountered enabled breakpoint 2.."
newline
eventfld.long 0x00 14. "BKPT1_OCC,SCSn Breakpoint 1 Encountered Indicator" "0: SCSn has not encountered enabled breakpoint 1..,1: SCSn has encountered enabled breakpoint 1.."
newline
eventfld.long 0x00 13. "BKPT0_OCC,SCSn Breakpoint 0 Encountered Indicator" "0: Breakpoint not encountered,1: Breakpoint encountered"
newline
eventfld.long 0x00 12. "JAM_OVR,SCSn Debug State Command Jamming Mode Command Completion Indicator" "0,1"
newline
eventfld.long 0x00 11. "STEP_JUMP_OVR,SCSn Debug state Step To Next Breakpoint mode Indicator" "0,1"
newline
eventfld.long 0x00 10. "STEP_ONCE_OVR,SCSn Debug State Step Once Mode Command Completion Indicator" "0,1"
newline
eventfld.long 0x00 9. "MD_JAM,SCSn Debug State Command Jamming Mode Indicator" "0: SCSn not in Command Jamming mode in Debug state,1: SCSn in Command Jamming mode in Debug state"
newline
eventfld.long 0x00 8. "MD_STEP_JUMP,SCSn Step To Next Breakpoint mode in Debug state Indicator" "0: SCSn not in Step To Next Breakpoint mode in..,1: SCSn in Step To Next Breakpoint mode in Debug.."
newline
eventfld.long 0x00 7. "MD_STEP_ONCE,SCSn Debug State Step Once Mode Indicator" "0: SCSn not in Step Once mode in Debug state,1: SCSn in Step Once mode in Debug state"
newline
eventfld.long 0x00 6. "MD_HALT,SCSn Debug State Halt Mode Indicator" "0: SCSn not in Halt mode in Debug state,1: SCSn in Halt mode in Debug state"
newline
eventfld.long 0x00 5. "PS_RUN,SCSn Run State Indicator" "0: SCSn not in Run state,1: SCSn in Run state"
newline
eventfld.long 0x00 4. "PS_ASYNCSTOP,SCSn Asyncstop State Indicator" "0: SCSn not in Asyncstop state,1: SCSn in Asyncstop state"
newline
eventfld.long 0x00 3. "PS_STOP,SCSn Stop State Indicator" "0: SCSn not in Stop state,1: SCSn in Stop state"
newline
eventfld.long 0x00 2. "PS_DEBUG,SCSn Debug State Indicator" "0: SCSn not in Debug state,1: SCSn in Debug state"
newline
eventfld.long 0x00 1. "PS_WAIT,SCSn Wait State Indicator" "0: SCSn not in Wait state,1: SCSn in Wait state"
newline
eventfld.long 0x00 0. "PS_START,SCSn Start State Indicator" "0: SCSn not in Start state,1: SCSn in Start state"
group.long 0x4E4++0x03
line.long 0x00 "SCS1_STATUS1,SCSn General Status 1"
eventfld.long 0x00 11. "JAM_ILL_JUMP,SCSn Illegal JUMP Command in Debug State Command Jamming Mode Error" "0: No attempted execution of a JUMP command,1: Attempted execution of a JUMP command"
newline
eventfld.long 0x00 10. "JAM_ILL_NEXT,SCSn Illegal Next Command in Debug State Command Jamming Mode Error" "0: No attempted execution of a Next command,1: Attempted execution of a Next command"
newline
eventfld.long 0x00 9. "JAM_ILL_LOOP,SCSn Illegal Loop Command in Debug State Command Jamming Mode Error" "0: No attempted execution of a Loop command,1: Attempted execution of a Loop command"
newline
eventfld.long 0x00 8. "JAM_ILL_SYNC,SCSn Illegal SYNC Command in Debug State Command Jamming Mode Error" "0: No attempted execution of a SYNC command,1: Attempted execution of a SYNC command"
newline
eventfld.long 0x00 7. "JAM_ILL_OPCODE,SCSn Illegal Opcode in Debug state Command Jamming Mode Error" "0: No attempted execution of an illegal command..,1: Attempted execution of an illegal command.."
newline
eventfld.long 0x00 6. "ILL_ADD,SCSn Illegal Add Command Error" "0: No attempted execution of an illegal Add Sub..,1: Attempted execution of an illegal Add Sub Cmp.."
newline
eventfld.long 0x00 5. "ILL_GET,SCSn Illegal Get Command Error" "0: No attempted execution of an illegal Get..,1: Attempted execution of an illegal Get command"
newline
eventfld.long 0x00 4. "ILL_SET,SCSn Illegal Set Command Error" "0: No attempted execution of an illegal Set..,1: Attempted execution of an illegal Set command"
newline
eventfld.long 0x00 3. "ILL_NEXT,SCSn Illegal Next Command Error" "0: No attempted execution of a Next command,1: Attempted execution of a Next command"
newline
eventfld.long 0x00 2. "ILL_0CNTLOOP,SCSn Illegal Loop Count Error" "0: No attempted execution of a Loop command with..,1: Attempted execution of a Loop command with.."
newline
eventfld.long 0x00 1. "ILL_LOOP,SCSn Illegal Loop Command Error" "0: No attempted execution of a Loop command,1: Attempted execution of a Loop command"
newline
eventfld.long 0x00 0. "ILL_OPCODE,SCSn Illegal Opcode Error" "0: No attempted execution of an illegal command..,1: Attempted execution of an illegal command.."
rgroup.long 0x4E8++0x03
line.long 0x00 "SCS1_STATUS2,SCSn General Status 2"
bitfld.long 0x00 29.--30. "WAITREG_EVT_TYPE,WAIT Event Type" "?,1: WAIT event is CPU event,2: WAIT event is external event,3: WAIT event is internal event"
newline
hexmask.long.byte 0x00 16.--22. 1. "WAITREG_EVT_NUMBER,Event Number For WAIT Command"
newline
hexmask.long.word 0x00 0.--15. 1. "WAITREG_SW,Wait Status for Software-Triggered CPU Event"
rgroup.long 0x4EC++0x03
line.long 0x00 "SCS1_STATUS3,SCSn General Status 3"
bitfld.long 0x00 3.--6. "PROC_STATE,SCSn Processing State" "0: SCSn in Rst state,1: SCSn in Start state,2: SCSn in Setup state,3: SCSn in Run state,4: SCSn in Wait state,5: SCSn in Debug state,6: SCSn in Stop state,7: SCSn in Asyncstop state,?..."
newline
bitfld.long 0x00 0.--2. "LOOP_DEPTH,SCSn Loop Depth" "0: No loop is being executed,1: Loop has nesting level depth of 1,2: Loop has nesting level depth of 2,3: Loop has nesting level depth of 3,4: Loop has nesting level depth of 4,?..."
group.long 0x4F0++0x03
line.long 0x00 "SCS1_INTEN0,SCSn Interrupt Enable 0"
bitfld.long 0x00 16. "BKPT3_OCC_INTEN,SCSn Breakpoint 3 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 15. "BKPT2_OCC_INTEN,SCSn Breakpoint 2 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 14. "BKPT1_OCC_INTEN,SCSn Breakpoint 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 13. "BKPT0_OCC_INTEN,SCSn Breakpoint 0 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 12. "JAM_OVR_INTEN,SCSn Debug State Jamming Command Over Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 11. "STEP_JUMP_OVR_INTEN,SCSn Breakpoint Encountered in Debug State Step To Next Breakpoint Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 10. "STEP_ONCE_OVR_INTEN,SCSn Debug State Step Once Mode Command Over Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 9. "MD_JAM_INTEN,SCSn Debug State Command Jamming Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 8. "MD_STEP_JUMP_INTEN,SCSn Debug State Step To Next Breakpoint Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 7. "MD_STEP_ONCE_INTEN,SCSn Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 6. "MD_HALT_INTEN,SCSn Debug State Halt Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 5. "PS_RUN_INTEN,SCSn Run State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 4. "PS_ASYNCSTOP_INTEN,SCSn Asyncstop State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 3. "PS_STOP_INTEN,SCSn Stop State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 2. "PS_DEBUG_INTEN,SCSn Debug State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 1. "PS_WAIT_INTEN,SCSn Wait State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 0. "PS_START_INTEN,SCSn Start State Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
group.long 0x4F4++0x03
line.long 0x00 "SCS1_INTEN1,SCSn Interrupt Enable 1"
bitfld.long 0x00 11. "JAM_ILL_JUMP_INTEN,SCSn Illegal JUMP Command in Debug State Command Jamming Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 10. "JAM_ILL_NEXT_INTEN,SCSn Illegal Next Command in Debug State Command Jamming Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 9. "JAM_ILL_LOOP_INTEN,SCSn Illegal Loop Command in Debug State Command Jamming Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 8. "JAM_ILL_SYNC_INTEN,SCSn Illegal SYNC Command in Debug State Command Jamming Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 7. "JAM_ILL_OPCODE_INTEN,SCSn Illegal Opcode in Debug State Command Jamming Mode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 6. "ILL_ADD_INTEN,SCSn Illegal Add Command Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 5. "ILL_GET_INTEN,SCSn Illegal Get Command Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 4. "ILL_SET_INTEN,SCSn Illegal Set Command Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 3. "ILL_NEXT_INTEN,SCSn Illegal Next Command Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 2. "ILL_0CNTLOOP_INTEN,SCSn Illegal Loop Count Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 1. "ILL_LOOP_INTEN,SCSn Illegal Loop Command Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
bitfld.long 0x00 0. "ILL_OPCODE_INTEN,SCSn Illegal Opcode Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
rgroup.long 0x4F8++0x03
line.long 0x00 "SCS1_PDMA_TRANSFER_COUNT_STATUS,SCSn PDMA Transfer Count Status"
hexmask.long.word 0x00 16.--31. 1. "AGGR_DATA_COUNT,Aggregation Data Count"
newline
hexmask.long.word 0x00 0.--15. 1. "TRANSFER_COUNT,Number of Words Transferred via PDMA"
rgroup.long 0x4FC++0x03
line.long 0x00 "SCS1_PDMA_FMTB_EXP_ADDR_STATUS,SCSn PDMA FormatB Exponent Address Status"
hexmask.long 0x00 3.--31. 1. "EXPN_ADDR,Exponent Address"
group.long 0x800++0x03
line.long 0x00 "SPR_CTRL_REG,Access Control for SPRs"
bitfld.long 0x00 27. "SPR13_ACC_CTRL,SPR 13 Access Control" "0: SPT has write access to SPR_R13_RE and..,1: CPU has write access to SPR_R13_RE and.."
newline
bitfld.long 0x00 26. "SPR13_LCK,SPR 13 Lock" "0: Both SPT and CPU have write access to..,1: Only one of SPT or CPU (selected via.."
newline
bitfld.long 0x00 25. "SPR12_ACC_CTRL,SPR 12 Access Control" "0: SPT has write access to SPR_R12_RE and..,1: CPU has write access to SPR_R12_RE and.."
newline
bitfld.long 0x00 24. "SPR12_LCK,SPR 12 Lock" "0: Both SPT and CPU have write access to..,1: Only one of SPT or CPU (selected via.."
newline
bitfld.long 0x00 19. "SPR9_ACC_CTRL,SPR 9 Access Control" "0: SPT has write access to SPR_R9_RE and SPR_R9_IM,1: CPU has write access to SPR_R9_RE and SPR_R9_IM"
newline
bitfld.long 0x00 18. "SPR9_LCK,SPR 9 Lock" "0: Both SPT and CPU have write access to..,1: Only one of SPT or CPU (selected via.."
newline
bitfld.long 0x00 13. "SPR6_ACC_CTRL,SPR 6 Access Control" "0: SPT has write access to SPR_R6_RE and SPR_R6_IM,1: CPU has write access to SPR_R6_RE and SPR_R6_IM"
newline
bitfld.long 0x00 12. "SPR6_LCK,SPR 6 Lock" "0: Both SPT and CPU have write access to..,1: Only one of SPT or CPU (selected via.."
newline
bitfld.long 0x00 11. "SPR5_ACC_CTRL,SPR 5 Access Control" "0: SPT has write access to SPR_R5_RE and SPR_R5_IM,1: CPU has write access to SPR_R5_RE and SPR_R5_IM"
newline
bitfld.long 0x00 10. "SPR5_LCK,SPR 5 Lock" "0: Both SPT and CPU have write access to..,1: Only one of SPT or CPU (selected via.."
group.long 0x838++0x03
line.long 0x00 "SPR5_RE,SPR 5 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
bitfld.long 0x00 18.--23. "B1_RD,OPRAM Bank 1 Read Access Control" "?,1: MCS has exclusive read access,2: SCS0 has exclusive read access,?,4: SCS1 has exclusive read access,?,?,7: Any sequencer can read the bank,?..."
newline
bitfld.long 0x00 12.--17. "B1_WR,OPRAM Bank 1 Write Access Control" "?,1: MCS has exclusive write access,2: SCS0 has exclusive write access,?,4: SCS1 has exclusive write access,?,?,7: Any sequencer can write the bank,?..."
newline
bitfld.long 0x00 6.--11. "B0_RD,OPRAM Bank 0 Read Access Control" "?,1: MCS has exclusive read access,2: SCS0 has exclusive read access,?,4: SCS1 has exclusive read access,?,?,7: Any sequencer can read the bank,?..."
newline
bitfld.long 0x00 0.--5. "B0_WR,OPRAM Bank 0 Write Access Control" "?,1: MCS has exclusive write access,2: SCS0 has exclusive write access,?,4: SCS1 has exclusive write access,?,?,7: Any sequencer can write the bank,?..."
group.long 0x83C++0x03
line.long 0x00 "SPR5_IM,SPR 5 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
bitfld.long 0x00 18.--23. "B3_RD,OPRAM Bank 3 Read Access Control" "?,1: MCS has exclusive read access,2: SCS0 has exclusive read access,?,4: SCS1 has exclusive read access,?,?,7: Any sequencer can read the bank,?..."
newline
bitfld.long 0x00 12.--17. "B3_WR,OPRAM Bank 3 Write Access Control" "?,1: MCS has exclusive write access,2: SCS0 has exclusive write access,?,4: SCS1 has exclusive write access,?,?,7: Any sequencer can write the bank,?..."
newline
bitfld.long 0x00 6.--11. "B2_RD,OPRAM Bank 2 Read Access Control" "?,1: MCS has exclusive read access,2: SCS0 has exclusive read access,?,4: SCS1 has exclusive read access,?,?,7: Any sequencer can read the bank,?..."
newline
bitfld.long 0x00 0.--5. "B2_WR,OPRAM Bank 2 Write Access Control" "?,1: MCS has exclusive write access,2: SCS0 has exclusive write access,?,4: SCS1 has exclusive write access,?,?,7: Any sequencer can write the bank,?..."
group.long 0x840++0x03
line.long 0x00 "SPR6_RE,SPR 6 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
bitfld.long 0x00 18.--23. "B5_RD,OPRAM Bank 5 Read Access Control" "?,1: MCS has exclusive read access,2: SCS0 has exclusive read access,?,4: SCS1 has exclusive read access,?,?,7: Any sequencer can read the bank,?..."
newline
bitfld.long 0x00 12.--17. "B5_WR,OPRAM Bank 5 Write Access Control" "?,1: MCS has exclusive write access,2: SCS0 has exclusive write access,?,4: SCS1 has exclusive write access,?,?,7: Any sequencer can write the bank,?..."
newline
bitfld.long 0x00 6.--11. "B4_RD,OPRAM Bank 4 Read Access Control" "?,1: MCS has exclusive read access,2: SCS0 has exclusive read access,?,4: SCS1 has exclusive read access,?,?,7: Any sequencer can read the bank,?..."
newline
bitfld.long 0x00 0.--5. "B4_WR,OPRAM Bank 4 Write Access Control" "?,1: MCS has exclusive write access,2: SCS0 has exclusive write access,?,4: SCS1 has exclusive write access,?,?,7: Any sequencer can write the bank,?..."
group.long 0x844++0x03
line.long 0x00 "SPR6_IM,SPR 6 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
bitfld.long 0x00 18.--23. "B7_RD,OPRAM Bank 7 Read Access Control" "?,1: MCS has exclusive read access,2: SCS0 has exclusive read access,?,4: SCS1 has exclusive read access,?,?,7: Any sequencer can read the bank,?..."
newline
bitfld.long 0x00 12.--17. "B7_WR,OPRAM Bank 7 Write Access Control" "?,1: MCS has exclusive write access,2: SCS0 has exclusive write access,?,4: SCS1 has exclusive write access,?,?,7: Any sequencer can write the bank,?..."
newline
bitfld.long 0x00 6.--11. "B6_RD,OPRAM Bank 6 Read Access Control" "?,1: MCS has exclusive read access,2: SCS0 has exclusive read access,?,4: SCS1 has exclusive read access,?,?,7: Any sequencer can read the bank,?..."
newline
bitfld.long 0x00 0.--5. "B6_WR,OPRAM Bank 6 Write Access Control" "?,1: MCS has exclusive write access,2: SCS0 has exclusive write access,?,4: SCS1 has exclusive write access,?,?,7: Any sequencer can write the bank,?..."
group.long 0x858++0x03
line.long 0x00 "SPR9_RE,SPR 9 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
bitfld.long 0x00 18.--23. "B1_RD,TRAM Bank 1 Read Access Control" "?,1: MCS has exclusive read access,2: SCS0 has exclusive read access,?,4: SCS1 has exclusive read access,?,?,7: Any sequencer can read the bank,?..."
newline
bitfld.long 0x00 12.--17. "B1_WR,TRAM Bank 1 Write Access Control" "?,1: MCS has exclusive write access,2: SCS0 has exclusive read access,?,4: SCS1 has exclusive read access,?,?,7: Any sequencer can read the bank,?..."
newline
bitfld.long 0x00 6.--11. "B0_RD,TRAM Bank 0 Read Access Control" "?,1: MCS has exclusive read access,2: SCS0 has exclusive read access,?,4: SCS1 has exclusive read access,?,?,7: Any sequencer can read the bank,?..."
newline
bitfld.long 0x00 0.--5. "B0_WR,TRAM Bank 0 Write Access Control" "?,1: MCS has exclusive write access,2: SCS0 has exclusive read access,?,4: SCS1 has exclusive read access,?,?,7: Any sequencer can read the bank,?..."
group.long 0x85C++0x03
line.long 0x00 "SPR9_IM,SPR 9 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
group.long 0x870++0x03
line.long 0x00 "SPR12_RE,SPR 12 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.word 0x00 0.--11. 1. "PDMA_SRAM_CONTINUOUS,PDMA SRAM continuous address in case of PDMA flex mode compression in terms of 64-bit words"
group.long 0x874++0x03
line.long 0x00 "SPR12_IM,SPR 12 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.word 0x00 0.--15. 1. "PDMA_SRAM_SKIP,PDMA SRAM skip address in case of PDMA flex mode compression in terms of 64-bit words"
group.long 0x878++0x03
line.long 0x00 "SPR13_RE,SPR 13 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.word 0x00 0.--11. 1. "SRAM_CONT_ADDR,SRAM continuous address for PDMA flex mode decompression in terms of 64-bit words"
group.long 0x87C++0x03
line.long 0x00 "SPR13_IM,SPR 13 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--18. 1. "COMP_BUF_LEN,Compressed buffer length in terms of bytes"
rgroup.long 0x890++0x03
line.long 0x00 "HW_SPR0_RE,Hardware SPR 0 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
bitfld.long 0x00 0.--4. "MIN_EXP,Minimum Exponent for PDMA Compression Mode Transfer" "0: Minimum calculated exponent value (For..,1: Minimum calculated exponent value (For..,2: Minimum calculated exponent value (For..,3: Minimum calculated exponent value (For..,4: Minimum calculated exponent value (For..,5: Minimum calculated exponent value (For..,6: Minimum calculated exponent value (For..,7: Minimum calculated exponent value (For..,8: Minimum calculated exponent value (For..,9: Minimum calculated exponent value (For..,10: Minimum calculated exponent value (For PDMA..,11: Minimum calculated exponent value (For PDMA..,12: Minimum calculated exponent value (For PDMA..,13: Minimum calculated exponent value (For PDMA..,14: Minimum calculated exponent value (For PDMA..,15: Minimum calculated exponent value (For PDMA..,16: Minimum calculated exponent value (For PDMA..,17: Minimum calculated exponent value (For PDMA..,18: Minimum calculated exponent value (For PDMA..,19: Minimum calculated exponent value (For PDMA..,20: Minimum calculated exponent value (For PDMA..,21: Minimum calculated exponent value (For PDMA..,22: Minimum calculated exponent value (For PDMA..,23: Minimum calculated exponent value (For PDMA..,?,?,?,?,?,?,?,31: PDMA transfer was done without compression"
rgroup.long 0x894++0x03
line.long 0x00 "HW_SPR0_IM,Hardware SPR 0 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x898++0x03
line.long 0x00 "HW_SPR1_RE,Hardware SPR 1 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "DSP_RESP_23_0,DSP Response Message Bits 23-0"
rgroup.long 0x89C++0x03
line.long 0x00 "HW_SPR1_IM,Hardware SPR 1 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.byte 0x00 0.--7. 1. "DSP_RESP_31_24,DSP Response Message Bits 31-24"
rgroup.long 0x8A0++0x03
line.long 0x00 "HW_SPR2_RE,Hardware SPR 2 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RST_CNT_23_0,Element Reset Count"
rgroup.long 0x8A4++0x03
line.long 0x00 "HW_SPR2_IM,Hardware SPR 2 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x8B0++0x03
line.long 0x00 "HW_SPR4_RE,Hardware SPR 4 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.word 0x00 0.--13. 1. "MAX_CNT,Maxima Count"
rgroup.long 0x8B4++0x03
line.long 0x00 "HW_SPR4_IM,Hardware SPR 4 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.word 0x00 0.--15. 1. "DEST_ADD,Destination Address"
rgroup.long 0x8C0++0x03
line.long 0x00 "EVT_SPR0_RE,External Event Wait SPR 0 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
bitfld.long 0x00 20.--23. "MCS_MIPI_0_VSYNC_3_0,MCS MIPICSI2_0 VSYNC[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 8.--19. 1. "MCS_MIPI_1_LINE_DONE_11_0,MCS MIPICSI2_1 Line_Done[11:0] Event Status"
newline
bitfld.long 0x00 4.--7. "MCS_MIPI_1_HSYNC_3_0,MCS MIPICSI2_1 HSYNC[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "MCS_MIPI_1_VSYNC_3_0,MCS MIPICSI2_1 VSYNC[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x8C4++0x03
line.long 0x00 "EVT_SPR0_IM,External Event Wait SPR 0 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.word 0x00 4.--15. 1. "MCS_MIPI_0_LINE_DONE_11_0,MCS MIPICSI2_0 Line_Done[11:0] Event Status"
newline
bitfld.long 0x00 0.--3. "MCS_MIPI_0_HSYNC_3_0,MCS MIPICSI2_0 HSYNC[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x8C8++0x03
line.long 0x00 "EVT_SPR1_RE,External Event Wait SPR 1 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x8CC++0x03
line.long 0x00 "EVT_SPR1_IM,External Event Wait SPR 1 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
bitfld.long 0x00 22. "PDMA_MCS_DONE,MCS PDMA Transfer Done Event Status" "0,1"
newline
bitfld.long 0x00 21. "MCS_CTE_RFS,MCS CTE RFS Event Status" "0,1"
newline
bitfld.long 0x00 20. "MCS_CTE_RCS,MCS CTE RCS Event Status" "0,1"
newline
bitfld.long 0x00 16.--19. "MCS_CTE_EVT_3_0,MCS CTE[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x8D0++0x03
line.long 0x00 "EVT_SPR2_RE,External Event Wait SPR 2 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
bitfld.long 0x00 20.--23. "SCS0_MIPI_0_VSYNC_3_0,SCS0 MIPICSI2_0 VSYNC[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 8.--19. 1. "SCS0_MIPI_1_LINE_DONE_11_0,SCS0 MIPICSI2_1 Line_Done[11:0] Event Status"
newline
bitfld.long 0x00 4.--7. "SCS0_MIPI_1_HSYNC_3_0,SCS0 MIPICSI2_1 HSYNC[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "SCS0_MIPI_1_VSYNC_3_0,SCS0 MIPICSI2_1 VSYNC[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x8D4++0x03
line.long 0x00 "EVT_SPR2_IM,External Event Wait SPR 2 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.word 0x00 4.--15. 1. "SCS0_MIPI_0_LINE_DONE_11_0,SCS0 MIPICSI2_0 Line_Done[11:0] Event Status"
newline
bitfld.long 0x00 0.--3. "SCS0_MIPI_0_HSYNC_3_0,SCS0 MIPICSI2_0 HSYNC[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x8D8++0x03
line.long 0x00 "EVT_SPR3_RE,External Event Wait SPR 3 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x8DC++0x03
line.long 0x00 "EVT_SPR3_IM,External Event Wait SPR 3 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
bitfld.long 0x00 22. "PDMA_SCS0_DONE,SCS0 PDMA Transfer Done Event Status" "0,1"
newline
bitfld.long 0x00 21. "SCS0_CTE_RFS,SCS0 CTE RFS Event Status" "0,1"
newline
bitfld.long 0x00 20. "SCS0_CTE_RCS,SCS0 CTE RCS Event Status" "0,1"
newline
bitfld.long 0x00 16.--19. "SCS0_CTE_EVT_3_0,SCS0 CTE[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x8E0++0x03
line.long 0x00 "EVT_SPR4_RE,External Event Wait SPR 4 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
bitfld.long 0x00 20.--23. "SCS1_MIPI_0_VSYNC_3_0,SCS1 MIPICSI2_0 VSYNC[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 8.--19. 1. "SCS1_MIPI_1_LINE_DONE_11_0,SCS1 MIPICSI2_1 Line_Done[11:0] Event Status"
newline
bitfld.long 0x00 4.--7. "SCS1_MIPI_1_HSYNC_3_0,SCS1 MIPICSI2_1 HSYNC[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "SCS1_MIPI_1_VSYNC_3_0,SCS1 MIPICSI2_1 VSYNC[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x8E4++0x03
line.long 0x00 "EVT_SPR4_IM,External Event Wait SPR 4 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.word 0x00 4.--15. 1. "SCS1_MIPI_0_LINE_DONE_11_0,SCS1 MIPICSI2_0 Line_Done[11:0] Event Status"
newline
bitfld.long 0x00 0.--3. "SCS1_MIPI_0_HSYNC_3_0,SCS1 MIPICSI2_0 HSYNC[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x8E8++0x03
line.long 0x00 "EVT_SPR5_RE,External Event Wait SPR 5 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x8EC++0x03
line.long 0x00 "EVT_SPR5_IM,External Event Wait SPR 5 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
bitfld.long 0x00 22. "PDMA_SCS1_DONE,SCS1 PDMA Transfer Done Event Status" "0,1"
newline
bitfld.long 0x00 21. "SCS1_CTE_RFS,SCS1 CTE RFS Event Status" "0,1"
newline
bitfld.long 0x00 20. "SCS1_CTE_RCS,SCS1 CTE RCS Event Status" "0,1"
newline
bitfld.long 0x00 16.--19. "SCS1_CTE_EVT_3_0,SCS1 CTE[3:0] Event Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x910++0x03
line.long 0x00 "CHRP_SPR0_RE,Chirp SPR n Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_CHRP_SPR,Chirp Counter n"
rgroup.long 0x914++0x03
line.long 0x00 "CHRP_SPR0_IM,Chirp SPR n High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x918++0x03
line.long 0x00 "CHRP_SPR1_RE,Chirp SPR n Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_CHRP_SPR,Chirp Counter n"
rgroup.long 0x91C++0x03
line.long 0x00 "CHRP_SPR1_IM,Chirp SPR n High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x920++0x03
line.long 0x00 "CHRP_SPR2_RE,Chirp SPR n Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_CHRP_SPR,Chirp Counter n"
rgroup.long 0x924++0x03
line.long 0x00 "CHRP_SPR2_IM,Chirp SPR n High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x928++0x03
line.long 0x00 "CHRP_SPR3_RE,Chirp SPR n Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_CHRP_SPR,Chirp Counter n"
rgroup.long 0x92C++0x03
line.long 0x00 "CHRP_SPR3_IM,Chirp SPR n High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x930++0x03
line.long 0x00 "CHRP_SPR4_RE,Chirp SPR n Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_CHRP_SPR,Chirp Counter n"
rgroup.long 0x934++0x03
line.long 0x00 "CHRP_SPR4_IM,Chirp SPR n High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x938++0x03
line.long 0x00 "CHRP_SPR5_RE,Chirp SPR n Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_CHRP_SPR,Chirp Counter n"
rgroup.long 0x93C++0x03
line.long 0x00 "CHRP_SPR5_IM,Chirp SPR n High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x940++0x03
line.long 0x00 "CHRP_SPR6_RE,Chirp SPR n Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_CHRP_SPR,Chirp Counter n"
rgroup.long 0x944++0x03
line.long 0x00 "CHRP_SPR6_IM,Chirp SPR n High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x948++0x03
line.long 0x00 "CHRP_SPR7_RE,Chirp SPR n Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "RE_CHRP_SPR,Chirp Counter n"
rgroup.long 0x94C++0x03
line.long 0x00 "CHRP_SPR7_IM,Chirp SPR n High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x990++0x03
line.long 0x00 "HW_SPR6_RE,Hardware SPR 6 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
bitfld.long 0x00 0.--4. "MSB_CNT,Leading MSB count value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x994++0x03
line.long 0x00 "HW_SPR6_IM,Hardware SPR 6 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x998++0x03
line.long 0x00 "HW_SPR7_RE,Hardware SPR 7 Low"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
rgroup.long 0x99C++0x03
line.long 0x00 "HW_SPR7_IM,Hardware SPR 7 High"
hexmask.long.byte 0x00 24.--31. 1. "SIGN_EXT,Sign Extension"
newline
hexmask.long.tbyte 0x00 0.--18. 1. "FLEXMODE_BYTE_CNT,For PDMA flex mode compression (OPRAM to SRAM transfer): 18:0"
tree.end
tree "SRAM_CTL"
tree "RETENTION_RAM"
base ad:0x40014000
group.long 0x00++0x03
line.long 0x00 "RAMCR,RAM Control"
bitfld.long 0x00 8. "INIT_SYSA,Initialize With System Address" "0: LOCAL,1: SYSTEM"
bitfld.long 0x00 1.--2. "IWS,Initialization Wait States" "0: ZERO_CYCLES,1: ONE_CYCLE,2: TWO_CYCLES,3: THREE_CYCLES"
newline
bitfld.long 0x00 0. "INIT,Initialization Request" "0: Not requested,1: Requested"
group.long 0x04++0x03
line.long 0x00 "RAMIAS,RAM Initialization Address Start"
hexmask.long 0x00 0.--31. 1. "IAS,Initialization Address Start"
group.long 0x08++0x03
line.long 0x00 "RAMIAE,RAM Initialization Address End"
hexmask.long 0x00 0.--31. 1. "IAE,Initialization Address End"
group.long 0x0C++0x03
line.long 0x00 "RAMSR,RAM Status"
hexmask.long.byte 0x00 16.--23. 1. "EINFO,Event Information"
hexmask.long.byte 0x00 8.--15. 1. "SYND,ECC Syndrome Value"
newline
eventfld.long 0x00 7. "SGLERR,ECC Single-Bit Error" "0: No error occurred,1: An error occurred"
eventfld.long 0x00 6. "MLTERR,ECC Multi-Bit Error" "0: No error occurred,1: An error occurred"
newline
eventfld.long 0x00 5. "AERR,ECC Address Error" "0: No error occurred,1: An error occurred"
eventfld.long 0x00 3. "AVALID,Addresses Valid" "0: Addresses do not correspond to an event,1: Addresses correspond to an event"
newline
rbitfld.long 0x00 2. "IPEND,Initialization Pending" "0: Not in progress,1: In progress"
eventfld.long 0x00 1. "BUSERR,Bus Error" "0: No error occurred since the last time this..,1: An error occurred"
newline
eventfld.long 0x00 0. "IDONE,Initialization Done" "0: An initialization was not requested is in..,1: An initialization completed successfully"
rgroup.long 0x10++0x03
line.long 0x00 "RAMMEMA,RAM ECC Address"
bitfld.long 0x00 20.--24. "BANK,RAM Bank ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.tbyte 0x00 0.--16. 1. "MEMA,RAM Bank Address"
rgroup.long 0x18++0x03
line.long 0x00 "RAMSYSA,RAM System Address"
hexmask.long 0x00 0.--31. 1. "SYSA,System Address"
group.long 0x1C++0x03
line.long 0x00 "RAMECCNT,RAM Correctable Error Count"
hexmask.long.byte 0x00 0.--7. 1. "ECCNT,ECC Correctable Error Count"
group.long 0x20++0x03
line.long 0x00 "RAMEID0,RAM Error Injection Data 0"
hexmask.long 0x00 0.--31. 1. "EID_W0,Error Injection Data Word 0"
group.long 0x24++0x03
line.long 0x00 "RAMEID1,RAM Error Injection Data 1"
hexmask.long 0x00 0.--31. 1. "EID_W1,Error Injection Data Word 1"
group.long 0x28++0x03
line.long 0x00 "RAMEIDC,RAM Error Injection Data Control"
bitfld.long 0x00 31. "EID_EN,Error Injection Data Enable" "0: No injection,1: Local injection"
bitfld.long 0x00 30. "EIA_EN,Error Injection Address Enable" "0: Ignore RAMEIA and RAMEIAM,1: Enable RAMEIA and RAMEIAM"
newline
bitfld.long 0x00 24. "EIP_EN,Error Injection Into Pipeline Enable" "0: No error injected,1: Error injected"
hexmask.long.byte 0x00 0.--7. 1. "EID_CKB,Error Injection Data Checkbits"
group.long 0x30++0x03
line.long 0x00 "RAMEIA,RAM Error Injection Base Address"
hexmask.long 0x00 0.--31. 1. "EIA,Error Injection Base Address"
group.long 0x34++0x03
line.long 0x00 "RAMEIAM,RAM Error Injection Address Mask"
hexmask.long 0x00 0.--31. 1. "EIAM,Error Injection Address Mask"
group.long 0x40++0x03
line.long 0x00 "RAMMAXA,RAM Maximum-Value Address"
hexmask.long 0x00 0.--31. 1. "MAXA,Maximum Address"
group.long 0x80++0x03
line.long 0x00 "RAMCR2,RAM Control 2"
bitfld.long 0x00 1.--2. "WBUF,Write Buffer Control" "0: Disable write buffer for all write transactions,1: Enable write buffer for write transactions..,2: Enable write buffer for write transactions..,?..."
bitfld.long 0x00 0. "PREF,Prefetch for Read Bursts" "0: No prefetch,1: Prefetch is enabled for sequential beats.."
tree.end
repeat 7. (list 1. 2. 3. 4. 5. 6. 7.) (list ad:0x40014100 ad:0x40014200 ad:0x40014300 ad:0x40014400 ad:0x40014500 ad:0x40014600 ad:0x40014700)
tree "SRAM_CTRL_$1"
base $2
group.long 0x00++0x03
line.long 0x00 "RAMCR,RAM Control"
bitfld.long 0x00 8. "INIT_SYSA,Initialize With System Address" "0: LOCAL,1: SYSTEM"
bitfld.long 0x00 1.--2. "IWS,Initialization Wait States" "0: ZERO_CYCLES,1: ONE_CYCLE,2: TWO_CYCLES,3: THREE_CYCLES"
newline
bitfld.long 0x00 0. "INIT,Initialization Request" "0: Not requested,1: Requested"
group.long 0x04++0x03
line.long 0x00 "RAMIAS,RAM Initialization Address Start"
hexmask.long 0x00 0.--31. 1. "IAS,Initialization Address Start"
group.long 0x08++0x03
line.long 0x00 "RAMIAE,RAM Initialization Address End"
hexmask.long 0x00 0.--31. 1. "IAE,Initialization Address End"
group.long 0x0C++0x03
line.long 0x00 "RAMSR,RAM Status"
hexmask.long.byte 0x00 16.--23. 1. "EINFO,Event Information"
hexmask.long.byte 0x00 8.--15. 1. "SYND,ECC Syndrome Value"
newline
eventfld.long 0x00 7. "SGLERR,ECC Single-Bit Error" "0: No error occurred,1: An error occurred"
eventfld.long 0x00 6. "MLTERR,ECC Multi-Bit Error" "0: No error occurred,1: An error occurred"
newline
eventfld.long 0x00 5. "AERR,ECC Address Error" "0: No error occurred,1: An error occurred"
eventfld.long 0x00 3. "AVALID,Addresses Valid" "0: Addresses do not correspond to an event,1: Addresses correspond to an event"
newline
rbitfld.long 0x00 2. "IPEND,Initialization Pending" "0: Not in progress,1: In progress"
eventfld.long 0x00 1. "BUSERR,Bus Error" "0: No error occurred since the last time this..,1: An error occurred"
newline
eventfld.long 0x00 0. "IDONE,Initialization Done" "0: An initialization was not requested is in..,1: An initialization completed successfully"
rgroup.long 0x10++0x03
line.long 0x00 "RAMMEMA,RAM ECC Address"
bitfld.long 0x00 20.--24. "BANK,RAM Bank ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.tbyte 0x00 0.--16. 1. "MEMA,RAM Bank Address"
rgroup.long 0x18++0x03
line.long 0x00 "RAMSYSA,RAM System Address"
hexmask.long 0x00 0.--31. 1. "SYSA,System Address"
group.long 0x1C++0x03
line.long 0x00 "RAMECCNT,RAM Correctable Error Count"
hexmask.long.byte 0x00 0.--7. 1. "ECCNT,ECC Correctable Error Count"
group.long 0x20++0x03
line.long 0x00 "RAMEID0,RAM Error Injection Data 0"
hexmask.long 0x00 0.--31. 1. "EID_W0,Error Injection Data Word 0"
group.long 0x24++0x03
line.long 0x00 "RAMEID1,RAM Error Injection Data 1"
hexmask.long 0x00 0.--31. 1. "EID_W1,Error Injection Data Word 1"
group.long 0x28++0x03
line.long 0x00 "RAMEIDC,RAM Error Injection Data Control"
bitfld.long 0x00 31. "EID_EN,Error Injection Data Enable" "0: No injection,1: Local injection"
bitfld.long 0x00 30. "EIA_EN,Error Injection Address Enable" "0: Ignore RAMEIA and RAMEIAM,1: Enable RAMEIA and RAMEIAM"
newline
bitfld.long 0x00 24. "EIP_EN,Error Injection Into Pipeline Enable" "0: No error injected,1: Error injected"
hexmask.long.byte 0x00 0.--7. 1. "EID_CKB,Error Injection Data Checkbits"
group.long 0x30++0x03
line.long 0x00 "RAMEIA,RAM Error Injection Base Address"
hexmask.long 0x00 0.--31. 1. "EIA,Error Injection Base Address"
group.long 0x34++0x03
line.long 0x00 "RAMEIAM,RAM Error Injection Address Mask"
hexmask.long 0x00 0.--31. 1. "EIAM,Error Injection Address Mask"
group.long 0x40++0x03
line.long 0x00 "RAMMAXA,RAM Maximum-Value Address"
hexmask.long 0x00 0.--31. 1. "MAXA,Maximum Address"
group.long 0x80++0x03
line.long 0x00 "RAMCR2,RAM Control 2"
bitfld.long 0x00 1.--2. "WBUF,Write Buffer Control" "0: Disable write buffer for all write transactions,1: Enable write buffer for write transactions..,2: Enable write buffer for write transactions..,?..."
bitfld.long 0x00 0. "PREF,Prefetch for Read Bursts" "0: No prefetch,1: Prefetch is enabled for sequential beats.."
tree.end
repeat.end
tree "SRAM_CTRL_8"
base ad:0x40014800
group.long 0x00++0x03
line.long 0x00 "RAMCR,RAM Control"
bitfld.long 0x00 8. "INIT_SYSA,Initialize With System Address" "0: LOCAL,1: SYSTEM"
bitfld.long 0x00 1.--2. "IWS,Initialization Wait States" "0: ZERO_CYCLES,1: ONE_CYCLE,2: TWO_CYCLES,3: THREE_CYCLES"
newline
bitfld.long 0x00 0. "INIT,Initialization Request" "0: Not requested,1: Requested"
group.long 0x04++0x03
line.long 0x00 "RAMIAS,RAM Initialization Address Start"
hexmask.long 0x00 0.--31. 1. "IAS,Initialization Address Start"
group.long 0x08++0x03
line.long 0x00 "RAMIAE,RAM Initialization Address End"
hexmask.long 0x00 0.--31. 1. "IAE,Initialization Address End"
group.long 0x0C++0x03
line.long 0x00 "RAMSR,RAM Status"
rbitfld.long 0x00 24. "SEC,Secure" "0: Not in a secure region,1: In a secure region"
hexmask.long.byte 0x00 16.--23. 1. "EINFO,Event Information"
newline
hexmask.long.byte 0x00 8.--15. 1. "SYND,ECC Syndrome Value"
eventfld.long 0x00 7. "SGLERR,ECC Single-Bit Error" "0: No error occurred,1: An error occurred"
newline
eventfld.long 0x00 6. "MLTERR,ECC Multi-Bit Error" "0: No error occurred,1: An error occurred"
eventfld.long 0x00 5. "AERR,ECC Address Error" "0: No error occurred,1: An error occurred"
newline
eventfld.long 0x00 3. "AVALID,Addresses Valid" "0: Addresses do not correspond to an event,1: Addresses correspond to an event"
rbitfld.long 0x00 2. "IPEND,Initialization Pending" "0: Not in progress,1: In progress"
newline
eventfld.long 0x00 1. "BUSERR,Bus Error" "0: No error occurred since the last time this..,1: An error occurred"
eventfld.long 0x00 0. "IDONE,Initialization Done" "0: An initialization was not requested is in..,1: An initialization completed successfully"
rgroup.long 0x10++0x03
line.long 0x00 "RAMMEMA,RAM ECC Address"
bitfld.long 0x00 20.--24. "BANK,RAM Bank ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.tbyte 0x00 0.--16. 1. "MEMA,RAM Bank Address"
rgroup.long 0x18++0x03
line.long 0x00 "RAMSYSA,RAM System Address"
hexmask.long 0x00 0.--31. 1. "SYSA,System Address"
group.long 0x1C++0x03
line.long 0x00 "RAMECCNT,RAM Correctable Error Count"
hexmask.long.byte 0x00 0.--7. 1. "ECCNT,ECC Correctable Error Count"
group.long 0x20++0x03
line.long 0x00 "RAMEID0,RAM Error Injection Data 0"
hexmask.long 0x00 0.--31. 1. "EID_W0,Error Injection Data Word 0"
group.long 0x24++0x03
line.long 0x00 "RAMEID1,RAM Error Injection Data 1"
hexmask.long 0x00 0.--31. 1. "EID_W1,Error Injection Data Word 1"
group.long 0x28++0x03
line.long 0x00 "RAMEIDC,RAM Error Injection Data Control"
bitfld.long 0x00 31. "EID_EN,Error Injection Data Enable" "0: No injection,1: Local injection"
bitfld.long 0x00 30. "EIA_EN,Error Injection Address Enable" "0: Ignore RAMEIA and RAMEIAM,1: Enable RAMEIA and RAMEIAM"
newline
bitfld.long 0x00 24. "EIP_EN,Error Injection Into Pipeline Enable" "0: No error injected,1: Error injected"
hexmask.long.byte 0x00 0.--7. 1. "EID_CKB,Error Injection Data Checkbits"
group.long 0x30++0x03
line.long 0x00 "RAMEIA,RAM Error Injection Base Address"
hexmask.long 0x00 0.--31. 1. "EIA,Error Injection Base Address"
group.long 0x34++0x03
line.long 0x00 "RAMEIAM,RAM Error Injection Address Mask"
hexmask.long 0x00 0.--31. 1. "EIAM,Error Injection Address Mask"
group.long 0x40++0x03
line.long 0x00 "RAMMAXA,RAM Maximum-Value Address"
hexmask.long 0x00 0.--31. 1. "MAXA,Maximum Address"
group.long 0x80++0x03
line.long 0x00 "RAMCR2,RAM Control 2"
bitfld.long 0x00 1.--2. "WBUF,Write Buffer Control" "0: Disable write buffer for all write transactions,1: Enable write buffer for write transactions..,2: Enable write buffer for write transactions..,?..."
bitfld.long 0x00 0. "PREF,Prefetch for Read Bursts" "0: No prefetch,1: Prefetch is enabled for sequential beats.."
tree.end
tree.end
tree "SRAMC"
base ad:0x44008000
group.long 0x00++0x03
line.long 0x00 "PRAMCR,Platform RAM Control Register"
bitfld.long 0x00 1.--2. "IWS,Initialization Wait Cycles" "0: No wait cycles between memory writes,1: One wait cycle between memory writes,2: Two wait cycles between memory writes,3: Three wait cycles between memory writes"
bitfld.long 0x00 0. "INITREQ,Initialization Request" "0: No initialization is requested,1: An initialization is requested"
group.long 0x04++0x03
line.long 0x00 "PRAMIAS,Platform RAM Initialization Address Register Start"
hexmask.long.tbyte 0x00 0.--16. 1. "IAS,Initialization Start Address"
group.long 0x08++0x03
line.long 0x00 "PRAMIAE,Platform RAM Initialization Address Register End"
hexmask.long.tbyte 0x00 0.--16. 1. "IAE,Initialization End Address"
group.long 0x0C++0x03
line.long 0x00 "PRAMSR,Platform RAM Status Register"
hexmask.long.byte 0x00 8.--15. 1. "SYND,ECC Syndrome Value"
eventfld.long 0x00 7. "SGLERR,ECC Single-bit Error" "0: No single-bit error,1: A single-bit error"
newline
eventfld.long 0x00 6. "MLTERR,ECC Multi-bit Error" "0: No multi-bit error,1: A multi-bit error"
eventfld.long 0x00 5. "AERR,ECC Address Error" "0: No address error,1: An address error"
newline
rbitfld.long 0x00 4. "AEXT,Indicates whether address bits used in the ECC HMatrix were from external or local RAM address" "0: Address bits used in the ECC HMatrix were the..,1: Address bits used in the ECC HMatrix were.."
rbitfld.long 0x00 2. "IPEND,Initialization Progress Status" "0: Initialization is not in progress,1: Initialization is in progress"
newline
eventfld.long 0x00 1. "IERR,Initialization Error" "0: No non-ECC error occurred on a previous access,1: A non-ECC error occurred on a previous access"
eventfld.long 0x00 0. "IDONE,Initialization Done" "0: Initialization is not complete,1: Initialization completed successfully"
rgroup.long 0x10++0x03
line.long 0x00 "PRAMECCA,Platform RAM ECC Address"
bitfld.long 0x00 21.--24. "CTRLID,Indicates the controller ID of the reported error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20. "EBNK,Indicates the RAM bank that has the ECC error indicated in the error fields" "0: Bank 0 has the error,1: Bank 1 has the error"
newline
hexmask.long.tbyte 0x00 0.--16. 1. "EADR,The chip writes to report ECC address associated with the error indicated in the error field in PRAMSR"
tree.end
tree "SRC (System Reset Controller)"
base ad:0x400D8300
group.long 0x00++0x03
line.long 0x00 "SW_NCF,Software Triggered Faults"
bitfld.long 0x00 3. "SW_NCF4,Software Triggered Fault 4" "0: Not asserted,1: FCCU_SW4_1"
newline
bitfld.long 0x00 2. "SW_NCF3,Software Triggered Fault 3" "0: Not asserted,1: FCCU_SW3_1"
newline
bitfld.long 0x00 1. "SW_NCF2,Software Triggered Fault 2" "0: Not asserted,1: FCCU_SW2_1"
newline
bitfld.long 0x00 0. "SW_NCF1,Software Triggered Fault 1" "0: Not asserted,1: FCCU_SW1_1"
group.long 0x04++0x03
line.long 0x00 "GMAC_0_CTRL_STS,GMAC_0 Control"
bitfld.long 0x00 3. "FTM0_SEL,Flextimer_0 Select" "0: FTM0_SEL_0,1: FTM0_SEL_1"
newline
bitfld.long 0x00 0.--2. "PHY_INTF_SEL,PHY Interface Select" "0: PHY_INTF_SEL_0,?,?,?,4: PHY_INTF_SEL_1,?..."
group.long 0x08++0x03
line.long 0x00 "GMAC_1_CTRL_REG,GMAC_1 Control"
bitfld.long 0x00 7.--8. "GMAC0_MIPICSI2_ID,GMAC_0 Auxiliary Trigger Input" "0,1,2,3"
newline
bitfld.long 0x00 5.--6. "GMAC1_VC_ID,MIPICSI2 Data HSYNC Mux" "0: MIPICSI2_0.hsync_raw_data[0] and..,1: MIPICSI2_0.hsync_raw_data[1] and..,2: MIPICSI2_0.hsync_raw_data[2] and..,3: MIPICSI2_0.hsync_raw_data[3] and.."
newline
bitfld.long 0x00 3.--4. "GMAC0_VC_ID,MIPICSI2 Data VSYNC Mux" "0: MIPICSI2_0.vsync_raw_data[0] and..,1: MIPICSI2_0.vsync_raw_data[1] and..,2: MIPICSI2_0.vsync_raw_data[2] and..,3: MIPICSI2_0.vsync_raw_data[3] and.."
newline
bitfld.long 0x00 0.--2. "PHY_INTF_SEL,PHY Interface Select" "0: PHY_select,1: PHY_select_a,?,?,4: PHY_select_b,?..."
group.long 0x10++0x03
line.long 0x00 "CTE_CTRL_REG,CTE Control"
bitfld.long 0x00 3.--4. "MIPICSI2_ID,RCS And RFS Inputs" "0: MIPICSI2_1 drives the CTE input signals RCS..,1: MIPICSI2_0 drives the CTE input signals RCS..,?..."
newline
bitfld.long 0x00 1.--2. "VC_ID,Virtual Channel ID" "0: Virtual channel ID 0,1: Virtual channel ID 1,2: Virtual channel ID 2,3: Virtual channel ID 3"
newline
bitfld.long 0x00 0. "IN_CTE,CTE Inputs" "0: Selects RCS and RFS from pads (see the IOMUX..,1: Selects HSYNC and VSYNC from MIPICSI2"
group.long 0x14++0x03
line.long 0x00 "CMU_FLL_STATUS_REG,CMU FLL Status"
eventfld.long 0x00 18. "CMU_CSI_CFG_CLK_FLL_STATUS,CMU CSI_CFG_CLK Status" "0: CMU_CSI_CFG_CLK_FLL_STATUS_0,1: CMU_CSI_CFG_CLK_FLL_STATUS_1"
newline
eventfld.long 0x00 17. "a53_cluster_FLL_STATUS,CMU A53_CORE_CLK Status" "0: CMU_a53_cluster_FLL_STATUS_0,1: CMU_a53_cluster_FLL_STATUS_1"
newline
eventfld.long 0x00 16. "CMU_GMAC1_TS_CLK_FLL_STATUS,CMU GMAC1_TS_CLK Status" "0: GMAC1_TS_CLK_FLL_STATUS_0,1: GMAC1_TS_CLK_FLL_STATUS_1"
newline
eventfld.long 0x00 15. "CMU_GMAC1_TX_CLK_FLL_STATUS,CMU GMAC1_TX_CLK Status" "0: CMU_GMAC1_TX_CLK_FLL_STATUS_0,1: CMU_GMAC1_TX_CLK_FLL_STATUS_1"
newline
eventfld.long 0x00 14. "CMU_GMAC1_RX_CLK_FLL_STATUS,CMU GMAC1_RX_CLK Status" "0: GMAC1_TS_CLK_FLL_STATUS_0,1: GMAC1_TS_CLK_FLL_STATUS_1"
newline
eventfld.long 0x00 13. "CMU_CTE_CLK_FLL_STATUS,CMU CTE_CLK status" "0: CMU_CTE_CLK_FLL_STATUS_0,1: CMU_CTE_CLK_FLL_STATUS_1"
newline
eventfld.long 0x00 12. "CMU_ACCEL_DIV3_CLK_FLL_STATUS,CMU ACCEL_DIV3_CLK Status" "0: CMU_ACCEL_DIV3_CLK_FLL_STATUS_0,1: CMU_ACCEL_DIV3_CLK_FLL_STATUS_1"
newline
eventfld.long 0x00 11. "CMU_22_FLL_STATUS,CMU SPI_CLK Status" "0: CMU_22_FLL_STATUS_0,1: CMU_22_FLL_STATUS_1"
newline
eventfld.long 0x00 10. "CMU_21_FLL_STATUS,CMU GMAC0_RX_CLK Status" "0: CMU_21_FLL_STATUS_0,1: CMU_21_FLL_STATUS_1"
newline
eventfld.long 0x00 9. "CMU_17_FLL_STATUS,CMU QSPI_1X_CLK Status" "0: CMU_17_FLL_STATUS_0,1: CMU_17_FLL_STATUS_1"
newline
eventfld.long 0x00 8. "CMU_16_FLL_STATUS,CMU LINFLEXD_CLK Status" "0: CMU_16_FLL_STATUS_0,1: CMU_16_FLL_STATUS_1"
newline
eventfld.long 0x00 7. "CMU_15_FLL_STATUS,CMU GMAC0_TS_CLK Status" "0: CMU_15_FLL_STATUS_0,1: CMU_15_FLL_STATUS_1"
newline
eventfld.long 0x00 6. "CMU_14_FLL_STATUS,CMU GMAC0_TX_CLK Status" "0: CMU_14_FLL_STATUS_0,1: CMU_14_FLL_STATUS_1"
newline
eventfld.long 0x00 5. "CMU_13_FLL_STATUS,CMU CAN_PE_CLK Status" "0: CMU_13_FLL_STATUS_0,1: CMU_13_FLL_STATUS_1"
newline
eventfld.long 0x00 4. "CMU_12_FLL_STATUS,CMU FCCU_IPS_CLK Status" "0: CMU_12_FLL_STATUS_0,1: CMU_12_FLL_STATUS_1"
newline
eventfld.long 0x00 3. "CMU_11_FLL_STATUS,CMU CLKOUT0 Status" "0: CMU_11_FLL_STATUS_0,1: CMU_11_FLL_STATUS_1"
newline
eventfld.long 0x00 2. "CMU_10_FLL_STATUS,CMU MC_CLK Status" "0: CMU_10_FLL_STATUS_0,1: CMU_10_FLL_STATUS_1"
newline
eventfld.long 0x00 1. "CMU_1_FLL_STATUS,CMU FIRC_CLK Status" "0: CMU_1_FLL_STATUS_0,1: CMU_1_FLL_STATUS_1"
newline
eventfld.long 0x00 0. "CMU_3_FLL_STATUS,CMU FTM_0_EXT_CLK Status" "0: CMU_3_FLL_STATUS_0,1: CMU_3_FLL_STATUS_1"
rgroup.long 0x18++0x03
line.long 0x00 "TRANSACTION_STAT_REG,Transaction Status"
bitfld.long 0x00 19. "s_to_periph_axbs_T_mainNoPendingTrans,Slave AXBS Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 18. "s_sram_3_T_mainNoPendingTrans,Slave SRAM_3 Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 17. "s_sram_2_T_mainNoPendingTrans,Slave SRAM_2 Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 16. "gic500_T_mainNoPendingTrans,GIC500 Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 15. "spt_wr_I_mainNoPendingTrans,SPT WR_I Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 14. "spt_rd_I_mainNoPendingTrans,SPT RO_I Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 13. "spt_bbe32_tcm_T_mainNoPendingTrans,BBE32_DSP TCM Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 12. "spt_bbe32_mainNoPendingTrans,BBE32_DSP Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 11. "s_to_m7_axbs_ram_T_mainNoPendingTrans,Slave CM7 AXBS To SRAM Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 10. "s_AIPS3_T_mainNoPendingTrans,Slave AIPS_3 Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 9. "m_mipi_1_I_mainNoPendingTrans,Master MIPI_0 Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 8. "m_from_m7_axbs_I_mainNoPendingTrans,Master CM7 AXBS Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 7. "BBE32_DSP_PWaitMode,BBE32_DSP PWaitMode Signal" "0: DSP not in Sleep mode,1: DSP in Sleep mode"
newline
bitfld.long 0x00 6. "m_axi_a53_I_mainNoPendingTrans,Master AXI A53 Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 5. "s_service_Debug_mainNoPendingTrans,Slave Service Debug Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 4. "s_service_Debug_T_mainNoPendingTrans,Slave Service Debug_T Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 3. "s_axi_to_STM500_T_mainNoPendingTrans,Master AXI To STM500 Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 2. "m_axi_MIPI_0_WO_I_mainNoPendingTrans,Master AXI MIPICSI2_0_WO Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 1. "m_axi_ENET_A_I_mainNoPendingTrans,Master AXI GMAC_1 Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 0. "m_apb_debug_AP_I_mainNoPendingTrans,Master APB Debug AP_I Transaction Status" "0: Transaction pending,1: Transaction not pending"
rgroup.long 0x1C++0x03
line.long 0x00 "TRANSACTION_STAT_2_REG,Transaction Status 2"
bitfld.long 0x00 6. "m_nsp_from_cc_mipiro_to_cbram_internal_I_mainNoPendingTrans,m_nsp_from_cc_mipiro_to_cbram_internal_I Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 5. "s_service_ss_user_mainNoPendingTrans,Slave Service NOC User Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 4. "s_service_ss_user_T_mainNoPendingTrans,Slave Service_NOC_User_T Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 3. "s_local_sram_1_T_mainNoPendingTrans,Slave Local SRAM_1 Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 2. "s_local_sram_0_T_mainNoPendingTrans,Slave SRAM_0 Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 1. "m_nsp_sf_host_access_I_mainNoPendingTrans,Master NSP Host Access Transaction Status" "0: Transaction pending,1: Transaction not pending"
newline
bitfld.long 0x00 0. "m_debug_I_etr_mainNoPendingTrans,Master debug_etr Transaction Status" "0: Transaction pending,1: Transaction not pending"
group.long 0x20++0x03
line.long 0x00 "FCCU_EOUT_OVERRIDE_CLEAR_REG,FCCU EOUT Override Clear"
bitfld.long 0x00 1. "EOUT_OVERRIDE_DISABLE_DURING_SELFTEST,Disable FCCU EOUT override during main reset domain selftest" "0: Move the FCCU_F0 to LOW and FCCU_F1 to HIGH..,1: Move the FCCU_F0 and FCCU_F1 to HIGH Z during.."
newline
bitfld.long 0x00 0. "EOUT_OVERRIDE_CLEAR,EOUT Override Clear" "0: eout_override_clear_status_0,1: eout_override_clear_status_1"
group.long 0x24++0x03
line.long 0x00 "MIPI_CSI2_REG,MIPI CSI2 Control"
bitfld.long 0x00 11. "MIPI_CSI2_1_VSYNC_sel_1,MIPI_CSI2_0 Vertical Sync Select 1" "0,1"
newline
bitfld.long 0x00 10. "MIPI_CSI2_1_VSYNC_sel_0,MIPI_CSI2_0 Vertical Sync Select 0" "0,1"
newline
bitfld.long 0x00 9. "MIPI_CSI2_1_LINE_DONE_sel_3,MIPI_CSI2_0 Line Done Select 3" "0,1"
newline
bitfld.long 0x00 8. "MIPI_CSI2_1_LINE_DONE_sel_2,MIPI_CSI2_0 Line Done Select 2" "0,1"
newline
bitfld.long 0x00 7. "MIPI_CSI2_1_LINE_DONE_sel_1,MIPI_CSI2_0 Line Done Select 1" "0,1"
newline
bitfld.long 0x00 6. "MIPI_CSI2_1_LINE_DONE_sel_0,MIPI_CSI2_0 Line Done Select 0" "0,1"
newline
bitfld.long 0x00 5. "MIPI_CSI2_0_VSYNC_sel_1,MIPI_CSI2_1 Vertical Sync Select 1" "0,1"
newline
bitfld.long 0x00 4. "MIPI_CSI2_0_VSYNC_sel_0,MIPI_CSI2_1 Vertical Sync Select 0" "0,1"
newline
bitfld.long 0x00 3. "MIPI_CSI2_0_LINE_DONE_sel_3,MIPI_CSI2_1 Line Done Select 3" "0,1"
newline
bitfld.long 0x00 2. "MIPI_CSI2_0_LINE_DONE_sel_2,MIPI_CSI2_1 Line Done Select 2" "0,1"
newline
bitfld.long 0x00 1. "MIPI_CSI2_0_LINE_DONE_sel_1,MIPI_CSI2_1 Line Done Select 1" "0,1"
newline
bitfld.long 0x00 0. "MIPI_CSI2_0_LINE_DONE_sel_0,MIPI_CSI2_1 Line Done Select 0" "0,1"
rgroup.long 0x28++0x03
line.long 0x00 "TIMEOUT_FAULT_STATUS_REG,Timeout Fault Status"
bitfld.long 0x00 10. "spt_wr_I_mainInitiator_Timeout_Fault,Master SPT WR mainInitiator_Timeout_Fault Status" "0: Timeout fault is not reported,1: Timeout fault is reported"
newline
bitfld.long 0x00 9. "spt_rd_I_mainInitiator_Timeout_Fault,Master SPT RD mainInitiator_Timeout_Fault Status" "0: Timeout fault is not reported,1: Timeout fault is reported"
newline
bitfld.long 0x00 8. "spt_bbe32_I_mainInitiator_Timeout_Fault,SPT_BBE32 mainInitiator_Timeout_Fault Status" "0: Timeout fault is not reported,1: Timeout fault is reported"
newline
bitfld.long 0x00 6. "m_mipi_1_I_mainInitiator_Timeout_Fault,Master MIPI_0 mainInitiator_Timeout_Fault Status" "0: Timeout fault is not reported,1: Timeout fault is reported"
newline
bitfld.long 0x00 5. "m_from_m7_axbs_I_mainInitiator_Timeout_Fault,Master CM7 AXBS mainInitiator_Timeout_Fault Status" "0: Timeout fault is not reported,1: Timeout fault is reported"
newline
bitfld.long 0x00 4. "m_debug_etr_I_mainInitiator_Timeout_Fault,Master debug_etr mainInitiator Timeout Fault Status" "0: Timeout fault is not reported,1: Timeout fault is reported"
newline
bitfld.long 0x00 3. "m_axi_enet_I_mainInitiator_Timeout_Fault,Master GMAC_0 AXI mainInitiator Timeout Fault Status" "0: Timeout fault is not reported,1: Timeout fault is reported"
newline
bitfld.long 0x00 2. "m_axi_a53_I_mainInitiator_Timeout_Fault,Master A53 AXI mainInitiator Timeout Fault Status" "0: Timeout fault is not reported,1: Timeout fault is reported"
newline
bitfld.long 0x00 1. "m_axi_MIPI_0_I_mainInitiator_Timeout_Fault,Master MIPI_1 AXI mainInitiator Timeout Fault Status" "0: Timeout fault is not reported,1: Timeout fault is reported"
newline
bitfld.long 0x00 0. "m_apb_debug_AP_I_mainInitiator_Timeout_Fault,Master Debug APB mainInitiator Timeout Fault Status" "0: Timeout fault is not reported,1: Timeout fault is reported"
group.long 0x3C++0x03
line.long 0x00 "PERIPHERAL_REGISTER,Peripheral Control"
bitfld.long 0x00 14. "quadspi_ipg_stop,QUADSPI Stop Mode" "0: No stop mode request,1: Asserted stop mode request"
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bitfld.long 0x00 13. "ocotp_inst1_ipg_stop,OCOTP Stop Mode" "0: No stop mode request,1: Asserted stop mode request"
newline
bitfld.long 0x00 12. "ocotp_inst_ipg_stop,OCOTP_INST Stop Mode" "0: No stop mode request,1: Asserted stop mode request"
newline
bitfld.long 0x00 11. "ctu_ipg_stop,CTU Stop Mode" "0: No stop mode request,1: Asserted stop mode request"
newline
bitfld.long 0x00 8. "linflex_ipg_stop,LINFLEX Stop Mode" "0: No stop mode request,1: Asserted stop mode request"
newline
bitfld.long 0x00 7. "i2c1_ipg_stop,I2C 1 Stop Mode" "0: No stop mode request,1: Asserted stop mode request"
newline
bitfld.long 0x00 6. "i2c0_ipg_stop,I2C 0 Stop Mode" "0: No stop mode request,1: Asserted stop mode request"
newline
bitfld.long 0x00 5. "dspi3_ipg_stop,DSPI 3 Stop Mode" "0: No stop mode request,1: Asserted stop mode request"
newline
bitfld.long 0x00 4. "dspi2_ipg_stop,DSPI 2 Stop Mode" "0: No stop mode request,1: Asserted stop mode request"
newline
bitfld.long 0x00 3. "dspi1_ipg_stop,DSPI 1 Stop Mode" "0: No stop mode request,1: Asserted stop mode request"
newline
bitfld.long 0x00 2. "dspi0_ipg_stop,DSPI 0 Stop Mode" "0: No stop mode request,1: Asserted stop mode request"
newline
bitfld.long 0x00 1. "flexcan1_ipg_stop,CAN 1 Stop Mode" "0: No stop mode request,1: Asserted stop mode request"
newline
bitfld.long 0x00 0. "flexcan0_ipg_stop,CAN 0 Stop Mode" "0: No stop mode request,1: Asserted stop mode request"
rgroup.long 0x40++0x03
line.long 0x00 "PERIPHERAL_ACK_SIGNAL,Peripheral Acknowledge"
bitfld.long 0x00 15. "ctu_ipg_MT_ack,CTU Stop Mode Acknowledgement AT MT_Clk" "0: periph_ack_bit15_value0,1: periph_ack_bit15_value1"
newline
bitfld.long 0x00 14. "quadspi_stop_ack,QUADSPI Stop Mode Acknowledgement" "0: periph_ack_bit14_value0,1: periph_ack_bit14_value1"
newline
bitfld.long 0x00 13. "ocotop_inst1_stop_ack,OCOTP Stop Mode Acknowledgement" "0: periph_ack_bit13_value0,1: periph_ack_bit13_value1"
newline
bitfld.long 0x00 12. "ocotp_inst_stop_ack,OCOTP_INST Stop Mode Acknowledgement" "0: periph_ack_bit12_value0,1: periph_ack_bit12_value1"
newline
bitfld.long 0x00 11. "ctu_stop_ack,CTU Stop Mode Acknowledgement" "0: periph_ack_bit11_value0,1: periph_ack_bit11_value1"
newline
bitfld.long 0x00 8. "linflex_stop_ack,LINFLEX Stop Mode Acknowledgement" "0: periph_ack_bit8_value0,1: periph_ack_bit8_value1"
newline
bitfld.long 0x00 7. "i2c1_stop_ack,I2C 1 Stop Mode Acknowledgement" "0: periph_ack_bit7_value0,1: periph_ack_bit7_value1"
newline
bitfld.long 0x00 6. "i2c0_stop_ack,I2C 0 Stop Mode Acknowledgement" "0: periph_ack_bit6_value0,1: periph_ack_bit6_value1"
newline
bitfld.long 0x00 5. "dspi3_stop_ack,DSPI 3 Stop Mode Acknowledgement" "0: periph_ack_bit5_value0,1: periph_ack_bit5_value1"
newline
bitfld.long 0x00 4. "dspi2_stop_ack,DSPI 2 Stop Mode Acknowledgement" "0: periph_ack_bit4_value0,1: periph_ack_bit4_value1"
newline
bitfld.long 0x00 3. "dspi1_stop_ack,DSPI 1 Stop Mode Acknowledgement" "0: periph_ack_bit3_value0,1: periph_ack_bit3_value1"
newline
bitfld.long 0x00 2. "dspi0_stop_ack,DSPI 0 Stop Mode Acknowledgement" "0: periph_ack_bit2_value0,1: periph_ack_bit2_value1"
newline
bitfld.long 0x00 1. "flexcan1_stop_ack,CAN 1 Stop Mode Acknowledgement" "0: periph_ack_bit1_value0,1: periph_ack_bit1_value1"
newline
bitfld.long 0x00 0. "flexcan0_stop_ack,CAN 0 Stop Mode Acknowledgement" "0: periph_ack_bit0_value0,1: periph_ack_bit0_value1"
group.long 0x44++0x03
line.long 0x00 "ENET_RT_AHB_GASKET,GMAC_0 AHB Gasket"
bitfld.long 0x00 0. "enet_rt_ahb_gasket_disable_opt_wr,ENET Gasket 2 Disable Write Optimization" "0: GMAC0_AHB_Gasket_Enabled_0,1: GMAC0_AHB_Gasket_Disabled_1"
group.long 0x48++0x03
line.long 0x00 "PFAULT_READ_NCF_FAULT_MASKING,PFAULT Read NCF Fault Masking"
bitfld.long 0x00 0. "src_pfault_speculative_read_ncf_masking,PFAULT Trigger Mask" "0: FCCU fault masked,1: FCCU fault not masked"
group.long 0x4C++0x03
line.long 0x00 "CMU_FHH_STATUS_REG,CMU_FHH Status"
eventfld.long 0x00 18. "a53_cluster_FHH_STATUS,CMU A53_CORE_CLK Status" "0: a53_cluster_FHH_STATUS_0,1: a53_cluster_FHH_STATUS_1"
newline
eventfld.long 0x00 17. "CMU_GMAC1_TS_CLK_FHH_STATUS,CMU GMAC1_TS_CLK Status" "0: CMU_GMAC1_TS_CLK_FHH_STATUS_0,1: CMU_GMAC1_TS_CLK_FHH_STATUS_1"
newline
eventfld.long 0x00 16. "CMU_GMAC1_TX_CLK_FHH_STATUS,CMU GMAC1_TX_CLK Status" "0: CMU_GMAC1_TX_CLK_FHH_STATUS_0,1: CMU_GMAC1_TX_CLK_FHH_STATUS_1"
newline
eventfld.long 0x00 15. "CMU_GMAC1_RX_CLK_FHH_STATUS,CMU GMAC1_RX_CLK Status" "0: CMU_GMAC1_RX_CLK_FHH_STATUS_0,1: CMU_GMAC1_RX_CLK_FHH_STATUS_1"
newline
eventfld.long 0x00 14. "CMU_CTE_CLK_FHH_STATUS,CMU CTE_CLK Status" "0: CMU_CTE_CLK_FHH_STATUS_0,1: CMU_CTE_CLK_FHH_STATUS_1"
newline
eventfld.long 0x00 13. "CMU_CSI_CFG_CLK_FHH_STATUS,CMU CSI_CFG_CLK Status" "0: CMU_CSI_CFG_CLK_FHH_STATUS_0,1: CMU_CSI_CFG_CLK_FHH_STATUS_1"
newline
eventfld.long 0x00 12. "CMU_ACCEL_DIV3_CLK_FHH_STATUS,CMU ACCEL_DIV3_CLK Status" "0: CMU_ACCEL_DIV3_CLK_FHH_STATUS_0,1: CMU_ACCEL_DIV3_CLK_FHH_STATUS_1"
newline
eventfld.long 0x00 11. "CMU_22_FHH_STATUS,CMU SPI_CLK Status" "0: CMU_22_FHH_STATUS_0,1: CMU_22_FHH_STATUS_1"
newline
eventfld.long 0x00 10. "CMU_21_FHH_STATUS,CMU GMAC0_RX_CLK Status" "0: CMU_21_FHH_STATUS_0,1: CMU_21_FHH_STATUS_1"
newline
eventfld.long 0x00 9. "CMU_17_FHH_STATUS,CMU QSPI_1X_CLK Status" "0: CMU_17_FHH_STATUS_0,1: CMU_17_FHH_STATUS_1"
newline
eventfld.long 0x00 8. "CMU_16_FHH_STATUS,CMU LINFLEXD_CLK Status" "0: CMU_16_FHH_STATUS_0,1: CMU_16_FHH_STATUS_1"
newline
eventfld.long 0x00 7. "CMU_15_FHH_STATUS,CMU GMAC0_TS_CLK Status" "0: CMU_15_FHH_STATUS_0,1: CMU_15_FHH_STATUS_1"
newline
eventfld.long 0x00 6. "CMU_14_FHH_STATUS,CMU GMAC0_TX_CLK Status" "0: CMU_14_FHH_STATUS_0,1: CMU_14_FHH_STATUS_1"
newline
eventfld.long 0x00 5. "CMU_13_FHH_STATUS,CMU CAN_PE_CLK Status" "0: CMU_13_FHH_STATUS_0,1: CMU_13_FHH_STATUS_1"
newline
eventfld.long 0x00 4. "CMU_12_FHH_STATUS,CMU FCCU_IPS_CLK Status" "0: CMU_12_FHH_STATUS_0,1: CMU_12_FHH_STATUS_1"
newline
eventfld.long 0x00 3. "CMU_11_FHH_STATUS,CMU CLKOUT0 Status" "0: CMU_11_FHH_STATUS_0,1: CMU_11_FHH_STATUS_1"
newline
eventfld.long 0x00 2. "CMU_10_FHH_STATUS,CMU MC_CLK Status" "0: CMU_10_FHH_STATUS_0,1: CMU_10_FHH_STATUS_1"
newline
eventfld.long 0x00 1. "CMU_1_FHH_STATUS,CMU FIRC_CLK Status" "0: CMU_1_FHH_STATUS_0,1: CMU_1_FHH_STATUS_1"
newline
eventfld.long 0x00 0. "CMU_3_FHH_STATUS,CMU FTM_0_EXT_CLK Status" "0: CMU_3_FHH_STATUS_0,1: CMU_3_FHH_STATUS_1"
group.long 0x50++0x03
line.long 0x00 "GMAC_2_CTRL_REG,GMAC_2 Control"
bitfld.long 0x00 4.--5. "GMAC_1_VC_ID,MIPI Data HSYNC Mux" "0: MIPICSI2_0.hsync_raw_data[0] and..,1: MIPICSI2_0.hsync_raw_data[1] and..,2: MIPICSI2_0.hsync_raw_data[2] and..,3: MIPICSI2_0.hsync_raw_data[3] and.."
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bitfld.long 0x00 2.--3. "GMAC_0_VC_ID,MIPI Data VSYNC Mux" "0: MIPICSI2_0.vsync_raw_data[0] and..,1: MIPICSI2_0.vsync_raw_data[1] and..,2: MIPICSI2_0.vsync_raw_data[2] and..,3: MIPICSI2_0.vsync_raw_data[3] and.."
newline
bitfld.long 0x00 0.--1. "GMAC0_MIPICSI2_ID,GMAC_1 Auxiliary Trigger Input" "0,1,2,3"
group.long 0x54++0x03
line.long 0x00 "DSP_PFAULT_SEL,DSP PFAULT Select"
bitfld.long 0x00 0. "dsp_pfault_sel,DSP PFAULT Select" "0: PFaultInfo[63:32],1: DSP_PFAULT_SEL_1"
group.long 0x58++0x03
line.long 0x00 "PRAM_AHB_ALARM,PRAM AHB Alarm"
eventfld.long 0x00 8. "pram8_fccu_ahb_alarm,PRAM8 Pipeline Error" "0: pram8_ahb_alarm_0,1: pram8_ahb_alarm_1"
newline
eventfld.long 0x00 7. "pram7_fccu_ahb_alarm,PRAM7 Pipeline Error" "0: pram7_ahb_alarm_0,1: pram7_ahb_alarm_1"
newline
eventfld.long 0x00 6. "pram6_fccu_ahb_alarm,PRAM6 Pipeline Error" "0: pram6_ahb_alarm_0,1: pram6_ahb_alarm_1"
newline
eventfld.long 0x00 5. "pram5_fccu_ahb_alarm,PRAM5 Pipeline Error" "0: pram5_ahb_alarm_0,1: pram5_ahb_alarm_1"
newline
eventfld.long 0x00 4. "pram4_fccu_ahb_alarm,PRAM4 Pipeline Error" "0: pram4_ahb_alarm_0,1: pram4_ahb_alarm_1"
newline
eventfld.long 0x00 3. "pram3_fccu_ahb_alarm,PRAM3 Pipeline Error" "0: pram3_ahb_alarm_0,1: pram3_ahb_alarm_1"
newline
eventfld.long 0x00 2. "pram2_fccu_ahb_alarm,PRAM2 Pipeline Error" "0: pram2_ahb_alarm_0,1: pram2_ahb_alarm_1"
newline
eventfld.long 0x00 1. "pram1_fccu_ahb_alarm,PRAM1 Pipeline Error" "0: pram1_ahb_alarm_0,1: pram1_ahb_alarm_1"
newline
eventfld.long 0x00 0. "pram0_fccu_ahb_alarm,PRAM0 Pipeline Error" "0: pram0_ahb_alarm_0,1: pram0_ahb_alarm_1"
group.long 0x5C++0x03
line.long 0x00 "EDC_ERR_OUT,EDC Error Out"
eventfld.long 0x00 12. "rd_app_pram_edc_err_out,RD_APP_PARAM_EDC_ERR_OUT Error" "0: edc_error_out_bit12_0,1: edc_error_out_bit12_1"
newline
eventfld.long 0x00 11. "rd_app_periph_edc_err_out,RD_APP_PERIPH_EDC_ERR_OUT Error" "0: edc_error_out_bit11_0,1: edc_error_out_bit11_1"
newline
eventfld.long 0x00 10. "rd_tcm_edc_err_out,RD_TCM_EDC_ERR_OUT Error" "0: edc_error_out_bit10_0,1: edc_error_out_bit10_1"
newline
eventfld.long 0x00 8. "rd_hse_edc_err_out,RD_HSE_EDC_ERR_OUT Error" "0: edc_error_out_bit8_0,1: edc_error_out_bit8_1"
newline
eventfld.long 0x00 7. "rd_enet_edc_err_out,RD_ENET_EDC_ERR_OUT Error" "0: edc_error_out_bit7_0,1: edc_error_out_bit7_1"
newline
eventfld.long 0x00 6. "rd_edma_edc_err_out,RD_EDMA_EDC_ERR_OUT Error" "0: edc_error_out_bit6_0,1: edc_error_out_bit6_1"
newline
eventfld.long 0x00 5. "rd_dbg_edc_err_out,RD_DBG_EDC_ERR_OUT Error" "0: edc_error_out_bit5_0,1: edc_error_out_bit5_1"
newline
eventfld.long 0x00 4. "rd_cm7_1_ahbp_edc_err_out,CM7_1_AHBP_EDC_ERR_OUT Error" "0: edc_error_out_bit4_0,1: edc_error_out_bit4_1"
newline
eventfld.long 0x00 3. "rd_cm7_1_ahbm_edc_err_out,CM7_1_AHBM_EDC_ERR_OUT Error" "0: edc_error_out_bit3_0,1: edc_error_out_bit3_1"
newline
eventfld.long 0x00 2. "rd_cm7_0_ahbp_edc_err_out,CM7_0_AHBP_EDC_ERR_OUT Error" "0: edc_error_out_bit2_0,1: edc_error_out_bit2_1"
newline
eventfld.long 0x00 1. "rd_cm7_0_ahbm_edc_err_out,CM7_0_AHBM_RDC_ERR_OUT Error" "0: edc_error_out_bit1_0,1: edc_error_out_bit1_1"
newline
eventfld.long 0x00 0. "rd_app_edc_err_out,RD_APP_EDC_ERR_OUT Error" "0: edc_error_out_bit0_0,1: edc_error_out_bit0_1"
group.long 0x60++0x03
line.long 0x00 "FCCU_ALARM,FCCU Alarm 1"
eventfld.long 0x00 9. "enet_mon_error,mon_error From enet_ahb_gasket" "0: value_19,1: value_20"
newline
eventfld.long 0x00 8. "rccu_dma_1_alarm,RCCU_DMA Alarm" "0: value_17,1: value_18"
newline
eventfld.long 0x00 7. "cm7_1_lockstep_debug_masked_fault,CM7_1_LOCKSTEP_DEBUG_MASKED Fault" "0: value_15,1: value_16"
newline
eventfld.long 0x00 6. "cm7_0_lockstep_debug_masked_fault,CM7_0_LOCKSTEP_DEBUG_MASKED Fault" "0: value_13,1: value_14"
newline
eventfld.long 0x00 5. "tcm_axbs_fccu_error,XBIC_3 integrity error" "0: value_11,1: value_12"
newline
eventfld.long 0x00 4. "pram_splt_fccu_error,XBIC_5 integrity error" "0: Inactive,1: value_10"
newline
eventfld.long 0x00 3. "pram_axbs_fccu_error,XBIC_4 integrity error" "0: Inactive,1: value_8"
newline
eventfld.long 0x00 2. "periph_axbs_fccu_alarm,XBIC_1 integrity error" "0: Inactive,1: value_6"
newline
eventfld.long 0x00 1. "dma_axbs_fccu_error,XBIC_2 integrity error" "0: Inactive,1: value_4"
newline
eventfld.long 0x00 0. "axbs_fccu_alarm,XBIC_0 integrity error" "0: Inactive,1: value_2"
group.long 0x64++0x03
line.long 0x00 "FCCU_ALARM_REG,FCCU Alarm 2"
eventfld.long 0x00 19. "cm7_1_ahbp_gskt_fccu_alarm,AXBS_1 M3 Gasket FCCU Alarm" "0: value_61,1: value_62"
newline
eventfld.long 0x00 18. "cm7_0_ahbp_gskt_fccu_alarm,AXBS_1 M0 Gasket FCCU Alarm" "0: value_59,1: value_60"
newline
eventfld.long 0x00 17. "tcm_gskt_fccu_alarm,AXBS_0 S4 Gasket FCCU Alarm" "0: value_57,1: value_58"
newline
eventfld.long 0x00 15. "s_to_periph_gskt_mon_alarm,AXBS_0 S5 Gasket FCCU Alarm" "0: value_53,1: value_54"
newline
eventfld.long 0x00 14. "s0_to_main_gskt_mon_alarm,AXBS_1 S5 Gasket FCCU Alarm" "0: value_50,1: value_51"
newline
eventfld.long 0x00 13. "qspi_gskt_mon_alarm,AXBS_1 S3 Gasket FCCU Alarm" "0: value_47,1: value_48"
newline
eventfld.long 0x00 12. "pram_p3_gskt_fccu_alarm,AXBS_0 S3 Gasket FCCU Alarm" "0: value_45,1: value_46"
newline
eventfld.long 0x00 11. "pram_p2_gskt_fccu_alarm,AXBS_0 S2 Gasket FCCU Alarm" "0: value_43,1: value_44"
newline
eventfld.long 0x00 10. "pram_p1_gskt_fccu_alarm,AXBS_0 S1 Gasket FCCU Alarm" "0: value_41,1: value_42"
newline
eventfld.long 0x00 9. "pram_p0_gskt_fccu_alarm,AXBS_0 S0 Gasket FCCU Alarm" "0: value_39,1: value_40"
newline
eventfld.long 0x00 8. "hse_gskt_mon_alarm,AXBS_0 M6 Gasket FCCU Alarm" "0: value_37,1: value_38"
newline
eventfld.long 0x00 7. "enet_gskt_fccu_alarm,AXBS_0 M7 Gasket FCCU Alarm" "0: value_35,1: value_36"
newline
eventfld.long 0x00 6. "dma_axbs_s1_gskt_mon_alarm,AXBS_2 S1 Gasket FCCU Alarm" "0: value_33,1: value_34"
newline
eventfld.long 0x00 5. "dma_axbs_s0_gskt_mon_alarm,AXBS_2 S0 Gasket FCCU Alarm" "0: value_31,1: value_32"
newline
eventfld.long 0x00 4. "dbg_slv_gskt_fccu_alarm,AXBS_1 S4 Gasket FCCU Alarm" "0: value_29,1: value_30"
newline
eventfld.long 0x00 3. "dbg_gskt_mon_alarm,AXBS_1 M6 Gasket FCCU Alarm" "0: value_27,1: value_28"
newline
eventfld.long 0x00 2. "aips2_gskt_mon_alarm,AXBS_1 S2 Gasket FCCU Alarm" "0: value_25,1: value_26"
newline
eventfld.long 0x00 1. "aips1_gskt_mon_alarm,AXBS_1 S1 Gasket FCCU Alarm" "0: value_23,1: value_24"
newline
eventfld.long 0x00 0. "aips0_gskt_mon_alarm,AXBS_1 S0 Gasket FCCU Alarm" "0: value_21,1: value_22"
group.long 0x68++0x03
line.long 0x00 "MAIN_MISSION_INT_REG,Main Mission Interrupt Status"
eventfld.long 0x00 2. "SW_RESET_DOMAIN_mainMissionInt,Software Reset Domain Main Mission Interrupt" "0: Not active,1: ACTIVE_YES"
newline
eventfld.long 0x00 1. "PBridge_RESET_DOMAIN_mainMissionInt,PBRIDGE Reset Domain Main Mission Interrupt" "0: Not active,1: ACTIVE_YES"
newline
eventfld.long 0x00 0. "MAIN_RESET_DOMAIN_mainMissionInt,Main Reset Domain Main Mission Interrupt" "0: Not active,1: ACTIVE_YES"
group.long 0x70++0x03
line.long 0x00 "BUS_DISABLE_OVERRIDE,Bus Disable Override"
bitfld.long 0x00 0. "bus_disable_override,Bus Disable Override" "0: bus_1,1: Proceed"
group.long 0x74++0x03
line.long 0x00 "RESET_REQUEST_REG,Reset Request"
bitfld.long 0x00 0. "hse_disrgmrst,HSE Disable RGM Reset" "0: Immediate reset executed,1: Interrupt generated"
group.long 0x78++0x03
line.long 0x00 "PIPE_PARITY_MODE_DATA_CTRL1_REG,Pipe Parity Control 1"
hexmask.long.word 0x00 0.--14. 1. "PARITY_SEL,Radar Subsystem Pipe Parity Mode"
group.long 0x80++0x03
line.long 0x00 "DSP_IP_REGISTER,DSP IP Status"
eventfld.long 0x00 0. "DSP_IP_bit,Exception Capture" "0: dsp_ip_bit_status_0,1: dsp_ip_bit_status_1"
group.long 0x84++0x03
line.long 0x00 "ATP_REG,ATP Status"
eventfld.long 0x00 0. "ATP_ipp_pad,ATP Pad Clock Fault" "0: atp_pad_clk_fault_0,1: atp_pad_clk_fault_1"
group.long 0xBC++0x03
line.long 0x00 "DEBUG_CONTROL,Debug Control"
bitfld.long 0x00 7. "DBG_RST_MSK_1a,Debug Reset Mask 1A" "0: Not masked,1: bit_15"
newline
bitfld.long 0x00 6. "READY_FOR_DEBUG,Handshake With Debugger" "0: Cannot be started,1: Can be started"
newline
bitfld.long 0x00 5. "DBG_RST_MSK_0a,Debug Reset Mask 0A" "0: Not masked,1: bit_11"
newline
bitfld.long 0x00 4. "CA53_0_L2RSTDISABLE,CA53_0 L2 Reset Disable" "0: Enable,1: Disable"
newline
rbitfld.long 0x00 3. "JTAG_ACTIVE,JTAG Active Status" "0: Not asserted,1: Asserted"
newline
rbitfld.long 0x00 2. "DBG_SETUP_DONE,Status of Debug Setup By Debugger" "0: Not done by debugger,1: Done by debugger"
newline
bitfld.long 0x00 1. "CA53_0_DBGL1RSTDISABLE,CA53_0 Debug L1 Reset Disable" "0: Enable,1: Disable"
group.long 0xE0++0x03
line.long 0x00 "TIMESTAMP_CONTROL_REGISTER,Timestamp Control"
bitfld.long 0x00 2. "TS_ENABLE,CAN Timestamp Module Enable" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 0.--1. "CAN_TS_CNT_SEL,CAN Timestamp Counter Select" "0: CAN_TS_CNT_SEL_0,1: CAN_TS_CNT_SEL_1,2: CAN_TS_CNT_SEL_2,?..."
tree.end
tree "SRC_GPR_TOP"
base ad:0x400D8000
group.long 0x10++0x03
line.long 0x00 "RETRAM_WR_CTL,Retention RAM Write Control"
bitfld.long 0x00 0. "RETRAM_DIS,Retention RAM Write Disable" "0: Read/Write are possible in Retention RAM,1: It will terminate all in progress.."
group.long 0x14++0x03
line.long 0x00 "RETENTION_CTRL_REG,Retention RAM Control"
bitfld.long 0x00 1. "ETF_MEM_RETENTION,ETF Memory Retention Status" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
newline
bitfld.long 0x00 0. "RET_MEM_RETENTION,Retention RAM Memory Retention Status" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
group.long 0x18++0x03
line.long 0x00 "RETENTION_SRAM_CTRL1_REG,Retention RAM Control 1"
bitfld.long 0x00 11. "SRAM_REAL_MEM_PRAM_8,This bit is used to put Real time SRAM Controlled by SRAMC_8 into retention state except for address range: 0x00_343E_0000 - 0x00_343F_FFFF as it constitutes for secure RAM" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
newline
bitfld.long 0x00 10. "SRAM_REAL_MEM_PRAM_7,This bit is used to put Real time SRAM Controlled by SRAMC_7 into retention state" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
newline
bitfld.long 0x00 9. "SRAM_REAL_MEM_PRAM_6,This bit is used to put Real time SRAM Controlled by SRAMC_6 into retention state" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
newline
bitfld.long 0x00 8. "SRAM_REAL_MEM_PRAM_5,This bit is used to put Real time SRAM Controlled by SRAMC_5 into retention state" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
newline
bitfld.long 0x00 7. "SRAM_REAL_MEM_PRAM_4,This bit is used to put Real time SRAM Controlled by SRAMC_4 into retention state" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
newline
bitfld.long 0x00 6. "SRAM_REAL_MEM_PRAM_3,This bit is used to put Real time SRAM Controlled by SRAMC_3 into retention state" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
newline
bitfld.long 0x00 5. "SRAM_REAL_MEM_PRAM_2,This bit is used to put Real time SRAM Controlled by SRAMC_2 into retention state" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
newline
bitfld.long 0x00 4. "SRAM_REAL_MEM_PRAM_1,This bit is used to put Real time SRAM Controlled by SRAMC_1 into retention state" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
newline
bitfld.long 0x00 3. "SRAM_APPL_MEM_0,This bit put Application SRAM (00_33C0_0000h - 00_33CF-FFFF) into retention state" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
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bitfld.long 0x00 2. "SRAM_APPL_MEM_1,This bit put Application SRAM (00_33D0_0000h - 00_33DF_FFFFh) into retention state" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
newline
bitfld.long 0x00 1. "SRAM_APPL_MEM_2,This bit put Application SRAM (00_33E0_0000h - 00_33EF_FFFF) into retention state" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
newline
bitfld.long 0x00 0. "SRAM_APPL_MEM_3,This bit put Application SRAM (00_33F0_0000h - 00_33FF_FFFFh) into retention state" "0: Memory is in Retention State,1: Read or Write is enabled on memory"
group.long 0x20++0x03
line.long 0x00 "SELFTEST_CTRL_REG,GPR08 Register"
bitfld.long 0x00 0. "POR_GEN_ON_DEST_RST_DURING_SELFTEST,POR generation on dest_reset during selftest" "0: POR reset will not get triggered on a..,1: POR reset will get triggered on a destructive.."
group.long 0x24++0x03
line.long 0x00 "CMU_REG,Clock Monitoring Unit Status"
eventfld.long 0x00 9. "CMU_CM7_1_FLL_STATUS,CMU_CM7_1 FLL Status" "0: No FLL event occurred,1: FLL event occurred"
newline
eventfld.long 0x00 8. "CMU_CM7_1_FHH_STATUS,CMU_CM7_1 FHH Status" "0: No FHH event occurred,1: FHH event occurred"
newline
eventfld.long 0x00 7. "CMU_CM7_0_FLL_STATUS,CMU_CM7_0 FLL Status" "0: No FLL event occurred,1: FLL event occurred"
newline
eventfld.long 0x00 6. "CMU_CM7_0_FHH_STATUS,CMU_CM7_0 FHH Status" "0: No FHH event occurred,1: FHH event occurred"
newline
eventfld.long 0x00 5. "CMU_ACCEL_XBAR_DIV4_FLL_STATUS,CMU_FC_29 FLL Status" "0: No FLL event occurred,1: FLL event occurred"
newline
eventfld.long 0x00 4. "CMU_ACCEL_XBAR_DIV4_FHH_STATUS,CMU_FC_29 FHH Status" "0: No FHH event occurred,1: FHH event occurred"
newline
eventfld.long 0x00 3. "CMU_5_FHH_STATUS,CMU_FC_5 FHH Status" "0: No FHH event occurred,1: FHH event occurred"
newline
eventfld.long 0x00 2. "CMU_5_FLL_STATUS,CMU_FC_5 FLL Status" "0: No FLL event occurred,1: FLL event occurred"
newline
eventfld.long 0x00 1. "CMU_0_FHH_STATUS,CMU_FC_0 FHH Status" "0: No FHH event occurred,1: FHH event occurred"
newline
eventfld.long 0x00 0. "CMU_0_FLL_STATUS,CMU_FC_0 FLL Status" "0: No FLL event occurred,1: FLL event occurred"
group.long 0x28++0x03
line.long 0x00 "NOC_PRAM_REGISTER,PRAM AXBS Priority"
bitfld.long 0x00 4. "pram_p3_high_priority,PRAM XBAR Master 3 (AXBS_0 S3) Priority" "0: Normal Priority,1: High Priority"
newline
bitfld.long 0x00 3. "pram_p2_high_priority,PRAM XBAR Master 2 (AXBS_0 S2) Priority" "0: Normal Priority,1: High Priority"
newline
bitfld.long 0x00 2. "pram_p1_high_priority,PRAM XBAR Master 1 (AXBS_0 S1) Priority" "0: Normal Priority,1: High Priority"
newline
bitfld.long 0x00 1. "pram_p0_high_priority,PRAM XBAR Master 0 (AXBS_0 S0) Priority" "0: Normal Priority,1: High Priority"
newline
bitfld.long 0x00 0. "noc_pram_high_priority,PRAM XBAR Master 4 (AHB Channel from application side (NoC slave for realtime SRAM)) Priority" "0: Normal Priority,1: High Priority"
tree.end
tree "STCU2"
base ad:0x400A8000
group.long 0x04++0x03
line.long 0x00 "RUNSW,STCU2 Run Software"
bitfld.long 0x00 11. "MBIE,MBIST Interrupt Enable" "0: Interrupt is not generated at the end of the..,1: At the end of the software MBIST execution.."
bitfld.long 0x00 10. "LBIE,LBIST Interrupt Enable" "0: Interrupt is not generated at the end of the..,1: At the end of the software LBIST execution.."
newline
bitfld.long 0x00 0. "RUNSW,The RUNSW bit is automatically cleared by STCU2 when the online self-testing procedure is complete" "0: Idle,1: Online self-testing procedure is running"
wgroup.long 0x08++0x03
line.long 0x00 "SKC,STCU2 SK Code"
hexmask.long 0x00 0.--31. 1. "SKC,STCU2 SK Code"
group.long 0x0C++0x03
line.long 0x00 "CFG,STCU2 Configuration"
hexmask.long.word 0x00 21.--30. 1. "PTR,First LBIST or MBIST pointer PTR defines the logical pointer to the first LBIST or MBIST to be scheduled when the self-testing procedure is enabled"
hexmask.long.byte 0x00 13.--20. 1. "LB_DELAY,Delay LBIST run LB_DELAY defines the delay between the LBIST starts when more than a single LBIST is selected to be executed concurrently with the purpose of smoothing the power consumption transient"
newline
bitfld.long 0x00 8. "WRP,Write Protection" "0: Specific STCU2 registers can be written through,1: STCU2 registers cannot be written through IPS"
bitfld.long 0x00 0.--2. "CLK_CFG,Logic Memory BIST and STCU2 CORE_CLK configuration CLK_CFG defines the ratio between the sys_clk and the internal clock used to program both the LBIST and the MBIST and the STCU2 CORE_CLK" "0: sys_clk/1,1: sys_clk/2,2: sys_clk/3,3: sys_clk/4,4: sys_clk/5,5: sys_clk/6,6: sys_clk/7,7: sys_clk/8"
group.long 0x14++0x03
line.long 0x00 "WDG,STCU2 Watchdog Granularity"
hexmask.long 0x00 0.--31. 1. "WDGEOC,Watchdog End of Count Timer This value has to be set to define the time budget related to the online self-test execution and check that everything is correctly working within this slot of time"
group.long 0x18++0x03
line.long 0x00 "INT_FLG,STCU2 Interrupt Flag"
eventfld.long 0x00 1. "MBIFLG,MBIST Interrupt Flag" "0: No interrupt is pending,1: An interrupt highlighting that the online.."
eventfld.long 0x00 0. "LBIFLG,LBIST Interrupt Flag" "0: No interrupt is pending,1: An interrupt highlighting that the online.."
group.long 0x24++0x03
line.long 0x00 "ERR_STAT,STCU2 Error"
rbitfld.long 0x00 25. "ABORTHW,Online hardware abort flag You can always read this field" "0: No hardware abort was requested during the..,1: A hardware abort was detected during the.."
rbitfld.long 0x00 19. "WDTOSW,Online watchdog timeout You can always read this field" "0: LBIST and MBIST time slots completed within..,1: LBIST and MBIST time slots not completed.."
newline
rbitfld.long 0x00 17. "ENGESW,Online engine error You can always read this field" "0: Valid engine execution,1: Invalid engine execution"
rbitfld.long 0x00 16. "INVPSW,Online invalid pointer You can always read this field" "0: Valid linked pointer list,1: Invalid linked pointer list"
newline
bitfld.long 0x00 9. "UFSF,Unrecoverable Faults Status Flag This flag reports the global status of the Unrecoverable Faults(UF)" "0: No errors that trigger the UF condition,1: There are errors that trigger the UF condition"
bitfld.long 0x00 8. "RFSF,Recoverable Faults Status Flag This flag reports the global status of the Recoverable Fault (RF)" "0: No errors that trigger the Recoverable Faults..,1: There are errors that trigger the Recoverable.."
group.long 0x28++0x03
line.long 0x00 "ERR_FM,STCU2 Error FM"
bitfld.long 0x00 3. "WDTOUFM,Watchdog Timeout Unrecoverable Fault Mapping" "0: Recoverable Fault Mapping,1: Unrecoverable Fault Mapping"
bitfld.long 0x00 1. "ENGEUFM,Engine Error Unrecoverable Fault Mapping" "0: Recoverable Fault Mapping,1: Unrecoverable Fault Mapping"
newline
bitfld.long 0x00 0. "INVPUFM,Invalid Pointer Unrecoverable Fault Mapping" "0: Recoverable Fault Mapping,1: Unrecoverable Mapping"
rgroup.long 0x4C++0x03
line.long 0x00 "LBSSW0,STCU2 Online LBIST Status"
bitfld.long 0x00 25. "LBSSW25,LBSSW25" "0: Failed LBIST execution,1: Successful LBIST execution"
bitfld.long 0x00 24. "LBSSW24,LBSSW24" "0: Failed LBIST execution,1: Successful LBIST execution"
newline
bitfld.long 0x00 23. "LBSSW23,LBSSW23" "0: Failed LBIST execution,1: Successful LBIST execution"
bitfld.long 0x00 22. "LBSSW22,LBSSW22" "0: Failed LBIST execution,1: Successful LBIST execution"
newline
bitfld.long 0x00 21. "LBSSW21,LBSSW21" "0: Failed LBIST execution,1: Successful LBIST execution"
bitfld.long 0x00 20. "LBSSW20,LBSSW20" "0: Failed LBIST execution,1: Successful LBIST execution"
newline
bitfld.long 0x00 19. "LBSSW19,LBSSW19" "0: Failed LBIST execution,1: Successful LBIST execution"
bitfld.long 0x00 18. "LBSSW18,LBSSW18" "0: Failed LBIST execution,1: Successful LBIST execution"
newline
bitfld.long 0x00 17. "LBSSW17,LBSSW17" "0: Failed LBIST execution,1: Successful LBIST execution"
bitfld.long 0x00 16. "LBSSW16,LBSSW16" "0: Failed LBIST execution,1: Successful LBIST execution"
newline
bitfld.long 0x00 15. "LBSSW15,LBSSW15" "0: Failed LBIST execution,1: Successful LBIST execution"
bitfld.long 0x00 14. "LBSSW14,LBSSW14" "0: Failed LBIST execution,1: Successful LBIST execution"
newline
bitfld.long 0x00 13. "LBSSW13,LBSSW13" "0: Failed LBIST execution,1: Successful LBIST execution"
bitfld.long 0x00 12. "LBSSW12,LBSSW12" "0: Failed LBIST execution,1: Successful LBIST execution"
newline
bitfld.long 0x00 11. "LBSSW11,LBSSW11" "0: Failed LBIST execution,1: Successful LBIST execution"
bitfld.long 0x00 10. "LBSSW10,LBSSW10" "0: Failed LBIST execution,1: Successful LBIST execution"
newline
bitfld.long 0x00 9. "LBSSW9,LBSSW9" "0: Failed LBIST execution,1: Successful LBIST execution"
bitfld.long 0x00 8. "LBSSW8,LBSSW8" "0: Failed LBIST execution,1: Successful LBIST execution"
newline
bitfld.long 0x00 7. "LBSSW7,LBSSW7" "0: Failed LBIST execution,1: Successful LBIST execution"
bitfld.long 0x00 6. "LBSSW6,LBSSW6" "0: Failed LBIST execution,1: Successful LBIST execution"
newline
bitfld.long 0x00 5. "LBSSW5,LBSSW5" "0: Failed LBIST execution,1: Successful LBIST execution"
bitfld.long 0x00 4. "LBSSW4,LBSSW4" "0: Failed LBIST execution,1: Successful LBIST execution"
newline
bitfld.long 0x00 3. "LBSSW3,LBSSW3" "0: Failed LBIST execution,1: Successful LBIST execution"
bitfld.long 0x00 2. "LBSSW2,LBSSW2" "0: Failed LBIST execution,1: Successful LBIST execution"
newline
bitfld.long 0x00 1. "LBSSW1,LBSSW1" "0: Failed LBIST execution,1: Successful LBIST execution"
bitfld.long 0x00 0. "LBSSW0,LBSSW0" "0: Failed LBIST execution,1: Successful LBIST execution"
rgroup.long 0x5C++0x03
line.long 0x00 "LBESW0,STCU2 Online LBIST End Flag"
bitfld.long 0x00 25. "LBESW25,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
bitfld.long 0x00 24. "LBESW24,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
newline
bitfld.long 0x00 23. "LBESW23,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
bitfld.long 0x00 22. "LBESW22,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
newline
bitfld.long 0x00 21. "LBESW21,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
bitfld.long 0x00 20. "LBESW20,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
newline
bitfld.long 0x00 19. "LBESW19,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
bitfld.long 0x00 18. "LBESW18,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
newline
bitfld.long 0x00 17. "LBESW17,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
bitfld.long 0x00 16. "LBESW16,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
newline
bitfld.long 0x00 15. "LBESW15,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
bitfld.long 0x00 14. "LBESW14,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
newline
bitfld.long 0x00 13. "LBESW13,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
bitfld.long 0x00 12. "LBESW12,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
newline
bitfld.long 0x00 11. "LBESW11,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
bitfld.long 0x00 10. "LBESW10,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
newline
bitfld.long 0x00 9. "LBESW9,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
bitfld.long 0x00 8. "LBESW8,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
newline
bitfld.long 0x00 7. "LBESW7,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
bitfld.long 0x00 6. "LBESW6,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
newline
bitfld.long 0x00 5. "LBESW5,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
bitfld.long 0x00 4. "LBESW4,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
newline
bitfld.long 0x00 3. "LBESW3,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
bitfld.long 0x00 2. "LBESW2,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
newline
bitfld.long 0x00 1. "LBESW1,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
bitfld.long 0x00 0. "LBESW0,LBESW" "0: LBIST execution not yet completed,1: LBIST execution finished"
group.long 0x7C++0x03
line.long 0x00 "LBUFM0,STCU2 Online LBIST Unrecoverable FM"
bitfld.long 0x00 25. "LBUFM25,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
bitfld.long 0x00 24. "LBUFM24,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
newline
bitfld.long 0x00 23. "LBUFM23,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
bitfld.long 0x00 22. "LBUFM22,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
newline
bitfld.long 0x00 21. "LBUFM21,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
bitfld.long 0x00 20. "LBUFM20,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
newline
bitfld.long 0x00 19. "LBUFM19,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
bitfld.long 0x00 18. "LBUFM18,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
newline
bitfld.long 0x00 17. "LBUFM17,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
bitfld.long 0x00 16. "LBUFM16,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
newline
bitfld.long 0x00 15. "LBUFM15,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
bitfld.long 0x00 14. "LBUFM14,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
newline
bitfld.long 0x00 13. "LBUFM13,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
bitfld.long 0x00 12. "LBUFM12,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
newline
bitfld.long 0x00 11. "LBUFM11,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
bitfld.long 0x00 10. "LBUFM10,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
newline
bitfld.long 0x00 9. "LBUFM9,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
bitfld.long 0x00 8. "LBUFM8,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
newline
bitfld.long 0x00 7. "LBUFM7,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
bitfld.long 0x00 6. "LBUFM6,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
newline
bitfld.long 0x00 5. "LBUFM5,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
bitfld.long 0x00 4. "LBUFM4,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
newline
bitfld.long 0x00 3. "LBUFM3,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
bitfld.long 0x00 2. "LBUFM2,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
newline
bitfld.long 0x00 1. "LBUFM1,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
bitfld.long 0x00 0. "LBUFM0,LBIST Unrecoverable Fault Mapping" "0: Recoverable Fault mapping,1: Unrecoverable Fault mapping"
rgroup.long 0x10C++0x03
line.long 0x00 "MBSSW0,STCU2 Online MBIST Status"
bitfld.long 0x00 31. "MBSSW31,MBSSW31" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 30. "MBSSW30,MBSSW30" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 29. "MBSSW29,MBSSW29" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 28. "MBSSW28,MBSSW28" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 27. "MBSSW27,MBSSW27" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 26. "MBSSW26,MBSSW26" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 25. "MBSSW25,MBSSW25" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 24. "MBSSW24,MBSSW24" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 23. "MBSSW23,MBSSW23" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 22. "MBSSW22,MBSSW22" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 21. "MBSSW21,MBSSW21" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 20. "MBSSW20,MBSSW20" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 19. "MBSSW19,MBSSW19" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 18. "MBSSW18,MBSSW18" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 17. "MBSSW17,MBSSW17" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 16. "MBSSW16,MBSSW16" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 15. "MBSSW15,MBSSW15" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 14. "MBSSW14,MBSSW14" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 13. "MBSSW13,MBSSW13" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 12. "MBSSW12,MBSSW12" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 11. "MBSSW11,MBSSW11" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 10. "MBSSW10,MBSSW10" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 9. "MBSSW9,MBSSW9" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 8. "MBSSW8,MBSSW8" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 7. "MBSSW7,MBSSW7" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 6. "MBSSW6,MBSSW6" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 5. "MBSSW5,MBSSW5" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 4. "MBSSW4,MBSSW4" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 3. "MBSSW3,MBSSW3" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 2. "MBSSW2,MBSSW2" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 1. "MBSSW1,MBSSW1" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 0. "MBSSW0,MBSSW0" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
rgroup.long 0x110++0x03
line.long 0x00 "MBSSW1,STCU2 Online MBIST Status"
bitfld.long 0x00 31. "MBSSW63,MBSSW63" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 30. "MBSSW62,MBSSW62" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 29. "MBSSW61,MBSSW61" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 28. "MBSSW60,MBSSW60" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 27. "MBSSW59,MBSSW59" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 26. "MBSSW58,MBSSW58" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 25. "MBSSW57,MBSSW57" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 24. "MBSSW56,MBSSW56" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 23. "MBSSW55,MBSSW55" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 22. "MBSSW54,MBSSW54" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 21. "MBSSW53,MBSSW53" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 20. "MBSSW52,MBSSW52" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 19. "MBSSW51,MBSSW51" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 18. "MBSSW50,MBSSW50" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 17. "MBSSW49,MBSSW49" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 16. "MBSSW48,MBSSW48" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 15. "MBSSW47,MBSSW47" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 14. "MBSSW46,MBSSW46" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 13. "MBSSW45,MBSSW45" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 12. "MBSSW44,MBSSW44" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 11. "MBSSW43,MBSSW43" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 10. "MBSSW42,MBSSW42" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 9. "MBSSW41,MBSSW41" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 8. "MBSSW40,MBSSW40" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 7. "MBSSW39,MBSSW39" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 6. "MBSSW38,MBSSW38" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 5. "MBSSW37,MBSSW37" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 4. "MBSSW36,MBSSW36" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 3. "MBSSW35,MBSSW35" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 2. "MBSSW34,MBSSW34" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 1. "MBSSW33,MBSSW33" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 0. "MBSSW32,MBSSW32" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
rgroup.long 0x114++0x03
line.long 0x00 "MBSSW2,STCU2 Online MBIST Status"
bitfld.long 0x00 31. "MBSSW95,MBSSW95" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 30. "MBSSW94,MBSSW94" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 29. "MBSSW93,MBSSW93" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 28. "MBSSW92,MBSSW92" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 27. "MBSSW91,MBSSW91" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 26. "MBSSW90,MBSSW90" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 25. "MBSSW89,MBSSW89" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 24. "MBSSW88,MBSSW88" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 23. "MBSSW87,MBSSW87" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 22. "MBSSW86,MBSSW86" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 21. "MBSSW85,MBSSW85" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 20. "MBSSW84,MBSSW84" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 19. "MBSSW83,MBSSW83" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 18. "MBSSW82,MBSSW82" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 17. "MBSSW81,MBSSW81" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 16. "MBSSW80,MBSSW80" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 15. "MBSSW79,MBSSW79" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 14. "MBSSW78,MBSSW78" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 13. "MBSSW77,MBSSW77" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 12. "MBSSW76,MBSSW76" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 11. "MBSSW75,MBSSW75" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 10. "MBSSW74,MBSSW74" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 9. "MBSSW73,MBSSW73" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 8. "MBSSW72,MBSSW72" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 7. "MBSSW71,MBSSW71" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 6. "MBSSW70,MBSSW70" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 5. "MBSSW69,MBSSW69" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 4. "MBSSW68,MBSSW68" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 3. "MBSSW67,MBSSW67" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 2. "MBSSW66,MBSSW66" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 1. "MBSSW65,MBSSW65" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 0. "MBSSW64,MBSSW64" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
rgroup.long 0x118++0x03
line.long 0x00 "MBSSW3,STCU2 Online MBIST Status"
bitfld.long 0x00 13. "MBSSW109,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 12. "MBSSW108,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 11. "MBSSW107,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 10. "MBSSW106,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 9. "MBSSW105,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 8. "MBSSW104,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 7. "MBSSW103,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 6. "MBSSW102,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 5. "MBSSW101,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 4. "MBSSW100,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 3. "MBSSW99,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 2. "MBSSW98,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
newline
bitfld.long 0x00 1. "MBSSW97,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
bitfld.long 0x00 0. "MBSSW96,MBSSW" "0: Failed MBIST execution,1: No fault detected during the MBIST execution"
rgroup.long 0x14C++0x03
line.long 0x00 "MBESW0,STCU2 Online MBIST End Flag"
bitfld.long 0x00 31. "MBESW31,Online end status of MBISTn (where n = 62:31)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 30. "MBESW30,Online end status of MBISTn (where n = 61:30)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 29. "MBESW29,Online end status of MBISTn (where n = 60:29)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 28. "MBESW28,Online end status of MBISTn (where n = 59:28)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 27. "MBESW27,Online end status of MBISTn (where n = 58:27)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 26. "MBESW26,Online end status of MBISTn (where n = 57:26)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 25. "MBESW25,Online end status of MBISTn (where n = 56:25)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 24. "MBESW24,Online end status of MBISTn (where n = 55:24)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 23. "MBESW23,Online end status of MBISTn (where n = 54:23)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 22. "MBESW22,Online end status of MBISTn (where n = 53:22)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 21. "MBESW21,Online end status of MBISTn (where n = 52:21)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 20. "MBESW20,Online end status of MBISTn (where n = 51:20)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 19. "MBESW19,Online end status of MBISTn (where n = 50:19)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 18. "MBESW18,Online end status of MBISTn (where n = 49:18)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 17. "MBESW17,Online end status of MBISTn (where n = 48:17)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 16. "MBESW16,Online end status of MBISTn (where n = 47:16)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 15. "MBESW15,Online end status of MBISTn (where n = 46:15)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 14. "MBESW14,Online end status of MBISTn (where n = 45:14)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 13. "MBESW13,Online end status of MBISTn (where n = 44:13)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 12. "MBESW12,Online end status of MBISTn (where n = 43:12)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 11. "MBESW11,Online end status of MBISTn (where n = 42:11)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 10. "MBESW10,Online end status of MBISTn (where n = 41:10)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 9. "MBESW9,Online end status of MBISTn (where n = 40:9)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 8. "MBESW8,Online end status of MBISTn (where n = 39:8)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 7. "MBESW7,Online end status of MBISTn (where n = 38:7)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 6. "MBESW6,Online end status of MBISTn (where n = 37:6)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 5. "MBESW5,Online end status of MBISTn (where n = 36:5)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 4. "MBESW4,Online end status of MBISTn (where n = 35:4)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 3. "MBESW3,Online end status of MBISTn (where n = 34:3)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 2. "MBESW2,Online end status of MBISTn (where n = 33:2)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 1. "MBESW1,Online end status of MBISTn (where n = 32:1)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 0. "MBESW0,Online end status of MBISTn (where n = 31:0)" "0: MBIST execution still ongoing,1: MBIST execution finished"
rgroup.long 0x150++0x03
line.long 0x00 "MBESW1,STCU2 Online MBIST End Flag"
bitfld.long 0x00 31. "MBESW63,Online end status of MBISTn (where n = 94:63)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 30. "MBESW62,Online end status of MBISTn (where n = 93:62)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 29. "MBESW61,Online end status of MBISTn (where n = 92:61)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 28. "MBESW60,Online end status of MBISTn (where n = 91:60)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 27. "MBESW59,Online end status of MBISTn (where n = 90:59)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 26. "MBESW58,Online end status of MBISTn (where n = 89:58)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 25. "MBESW57,Online end status of MBISTn (where n = 88:57)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 24. "MBESW56,Online end status of MBISTn (where n = 87:56)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 23. "MBESW55,Online end status of MBISTn (where n = 86:55)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 22. "MBESW54,Online end status of MBISTn (where n = 85:54)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 21. "MBESW53,Online end status of MBISTn (where n = 84:53)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 20. "MBESW52,Online end status of MBISTn (where n = 83:52)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 19. "MBESW51,Online end status of MBISTn (where n = 82:51)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 18. "MBESW50,Online end status of MBISTn (where n = 81:50)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 17. "MBESW49,Online end status of MBISTn (where n = 80:49)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 16. "MBESW48,Online end status of MBISTn (where n = 79:48)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 15. "MBESW47,Online end status of MBISTn (where n = 78:47)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 14. "MBESW46,Online end status of MBISTn (where n = 77:46)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 13. "MBESW45,Online end status of MBISTn (where n = 76:45)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 12. "MBESW44,Online end status of MBISTn (where n = 75:44)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 11. "MBESW43,Online end status of MBISTn (where n = 74:43)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 10. "MBESW42,Online end status of MBISTn (where n = 73:42)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 9. "MBESW41,Online end status of MBISTn (where n = 72:41)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 8. "MBESW40,Online end status of MBISTn (where n = 71:40)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 7. "MBESW39,Online end status of MBISTn (where n = 70:39)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 6. "MBESW38,Online end status of MBISTn (where n = 69:38)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 5. "MBESW37,Online end status of MBISTn (where n = 68:37)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 4. "MBESW36,Online end status of MBISTn (where n = 67:36)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 3. "MBESW35,Online end status of MBISTn (where n = 66:35)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 2. "MBESW34,Online end status of MBISTn (where n = 65:34)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 1. "MBESW33,Online end status of MBISTn (where n = 64:33)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 0. "MBESW32,Online end status of MBISTn (where n = 63:32)" "0: MBIST execution still ongoing,1: MBIST execution finished"
rgroup.long 0x154++0x03
line.long 0x00 "MBESW2,STCU2 Online MBIST End Flag"
bitfld.long 0x00 31. "MBESW95,Online end status of MBISTn (where n = 126:95)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 30. "MBESW94,Online end status of MBISTn (where n = 125:94)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 29. "MBESW93,Online end status of MBISTn (where n = 124:93)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 28. "MBESW92,Online end status of MBISTn (where n = 123:92)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 27. "MBESW91,Online end status of MBISTn (where n = 122:91)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 26. "MBESW90,Online end status of MBISTn (where n = 121:90)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 25. "MBESW89,Online end status of MBISTn (where n = 120:89)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 24. "MBESW88,Online end status of MBISTn (where n = 119:88)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 23. "MBESW87,Online end status of MBISTn (where n = 118:87)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 22. "MBESW86,Online end status of MBISTn (where n = 117:86)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 21. "MBESW85,Online end status of MBISTn (where n = 116:85)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 20. "MBESW84,Online end status of MBISTn (where n = 115:84)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 19. "MBESW83,Online end status of MBISTn (where n = 114:83)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 18. "MBESW82,Online end status of MBISTn (where n = 113:82)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 17. "MBESW81,Online end status of MBISTn (where n = 112:81)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 16. "MBESW80,Online end status of MBISTn (where n = 111:80)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 15. "MBESW79,Online end status of MBISTn (where n = 110:79)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 14. "MBESW78,Online end status of MBISTn (where n = 109:78)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 13. "MBESW77,Online end status of MBISTn (where n = 108:77)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 12. "MBESW76,Online end status of MBISTn (where n = 107:76)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 11. "MBESW75,Online end status of MBISTn (where n = 106:75)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 10. "MBESW74,Online end status of MBISTn (where n = 105:74)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 9. "MBESW73,Online end status of MBISTn (where n = 104:73)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 8. "MBESW72,Online end status of MBISTn (where n = 103:72)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 7. "MBESW71,Online end status of MBISTn (where n = 102:71)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 6. "MBESW70,Online end status of MBISTn (where n = 101:70)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 5. "MBESW69,Online end status of MBISTn (where n = 100:69)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 4. "MBESW68,Online end status of MBISTn (where n = 99:68)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 3. "MBESW67,Online end status of MBISTn (where n = 98:67)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 2. "MBESW66,Online end status of MBISTn (where n = 97:66)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 1. "MBESW65,Online end status of MBISTn (where n = 96:65)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 0. "MBESW64,Online end status of MBISTn (where n = 95:64)" "0: MBIST execution still ongoing,1: MBIST execution finished"
rgroup.long 0x158++0x03
line.long 0x00 "MBESW3,STCU2 Online MBIST End Flag"
bitfld.long 0x00 13. "MBESW109,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 12. "MBESW108,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 11. "MBESW107,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 10. "MBESW106,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 9. "MBESW105,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 8. "MBESW104,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 7. "MBESW103,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 6. "MBESW102,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 5. "MBESW101,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 4. "MBESW100,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 3. "MBESW99,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 2. "MBESW98,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
newline
bitfld.long 0x00 1. "MBESW97,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
bitfld.long 0x00 0. "MBESW96,Online end status of MBISTn (where n = 109:96)" "0: MBIST execution still ongoing,1: MBIST execution finished"
group.long 0x18C++0x03
line.long 0x00 "MBUFM0,STCU2 MBIST Unrecoverable FM"
bitfld.long 0x00 31. "MBUFM31,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 30. "MBUFM30,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 29. "MBUFM29,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 28. "MBUFM28,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 27. "MBUFM27,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 26. "MBUFM26,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 25. "MBUFM25,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 24. "MBUFM24,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 23. "MBUFM23,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 22. "MBUFM22,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 21. "MBUFM21,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 20. "MBUFM20,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 19. "MBUFM19,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 18. "MBUFM18,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 17. "MBUFM17,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 16. "MBUFM16,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 15. "MBUFM15,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 14. "MBUFM14,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 13. "MBUFM13,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 12. "MBUFM12,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 11. "MBUFM11,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 10. "MBUFM10,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 9. "MBUFM9,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 8. "MBUFM8,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 7. "MBUFM7,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 6. "MBUFM6,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 5. "MBUFM5,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 4. "MBUFM4,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 3. "MBUFM3,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 2. "MBUFM2,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 1. "MBUFM1,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 0. "MBUFM0,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
group.long 0x190++0x03
line.long 0x00 "MBUFM1,STCU2 MBIST Unrecoverable FM"
bitfld.long 0x00 31. "MBUFM63,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 30. "MBUFM62,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 29. "MBUFM61,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 28. "MBUFM60,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 27. "MBUFM59,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 26. "MBUFM58,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 25. "MBUFM57,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 24. "MBUFM56,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 23. "MBUFM55,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 22. "MBUFM54,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 21. "MBUFM53,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 20. "MBUFM52,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 19. "MBUFM51,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 18. "MBUFM50,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 17. "MBUFM49,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 16. "MBUFM48,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 15. "MBUFM47,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 14. "MBUFM46,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 13. "MBUFM45,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 12. "MBUFM44,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 11. "MBUFM43,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 10. "MBUFM42,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 9. "MBUFM41,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 8. "MBUFM40,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 7. "MBUFM39,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 6. "MBUFM38,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 5. "MBUFM37,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 4. "MBUFM36,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 3. "MBUFM35,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 2. "MBUFM34,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 1. "MBUFM33,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 0. "MBUFM32,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
group.long 0x194++0x03
line.long 0x00 "MBUFM2,STCU2 MBIST Unrecoverable FM"
bitfld.long 0x00 31. "MBUFM95,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 30. "MBUFM94,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 29. "MBUFM93,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 28. "MBUFM92,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 27. "MBUFM91,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 26. "MBUFM90,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 25. "MBUFM89,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 24. "MBUFM88,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 23. "MBUFM87,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 22. "MBUFM86,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 21. "MBUFM85,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 20. "MBUFM84,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 19. "MBUFM83,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 18. "MBUFM82,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 17. "MBUFM81,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 16. "MBUFM80,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 15. "MBUFM79,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 14. "MBUFM78,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 13. "MBUFM77,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 12. "MBUFM76,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 11. "MBUFM75,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 10. "MBUFM74,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 9. "MBUFM73,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 8. "MBUFM72,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 7. "MBUFM71,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 6. "MBUFM70,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 5. "MBUFM69,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 4. "MBUFM68,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 3. "MBUFM67,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 2. "MBUFM66,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 1. "MBUFM65,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 0. "MBUFM64,MBUFMn" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
group.long 0x198++0x03
line.long 0x00 "MBUFM3,STCU2 MBIST Unrecoverable FM"
bitfld.long 0x00 13. "MBUFM109,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 12. "MBUFM108,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 11. "MBUFM107,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 10. "MBUFM106,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 9. "MBUFM105,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 8. "MBUFM104,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 7. "MBUFM103,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 6. "MBUFM102,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 5. "MBUFM101,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 4. "MBUFM100,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 3. "MBUFM99,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 2. "MBUFM98,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
newline
bitfld.long 0x00 1. "MBUFM97,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
bitfld.long 0x00 0. "MBUFM96,MBESW" "0: Recoverable fault mapping,1: Unrecoverable fault mapping"
group.long 0x200++0x03
line.long 0x00 "LB_CTRL0,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x204++0x03
line.long 0x00 "LB_PCS0,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x220++0x03
line.long 0x00 "LB_MISRELSW0,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x224++0x03
line.long 0x00 "LB_MISREHSW0,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x228++0x03
line.long 0x00 "LB_MISRRLSW0,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x22C++0x03
line.long 0x00 "LB_MISRRHSW0,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x240++0x03
line.long 0x00 "LB_CTRL1,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x244++0x03
line.long 0x00 "LB_PCS1,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x260++0x03
line.long 0x00 "LB_MISRELSW1,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x264++0x03
line.long 0x00 "LB_MISREHSW1,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x268++0x03
line.long 0x00 "LB_MISRRLSW1,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x26C++0x03
line.long 0x00 "LB_MISRRHSW1,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x280++0x03
line.long 0x00 "LB_CTRL2,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x284++0x03
line.long 0x00 "LB_PCS2,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x2A0++0x03
line.long 0x00 "LB_MISRELSW2,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x2A4++0x03
line.long 0x00 "LB_MISREHSW2,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x2A8++0x03
line.long 0x00 "LB_MISRRLSW2,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x2AC++0x03
line.long 0x00 "LB_MISRRHSW2,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x2C0++0x03
line.long 0x00 "LB_CTRL3,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x2C4++0x03
line.long 0x00 "LB_PCS3,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x2E0++0x03
line.long 0x00 "LB_MISRELSW3,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x2E4++0x03
line.long 0x00 "LB_MISREHSW3,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x2E8++0x03
line.long 0x00 "LB_MISRRLSW3,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x2EC++0x03
line.long 0x00 "LB_MISRRHSW3,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x300++0x03
line.long 0x00 "LB_CTRL4,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x304++0x03
line.long 0x00 "LB_PCS4,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x320++0x03
line.long 0x00 "LB_MISRELSW4,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x324++0x03
line.long 0x00 "LB_MISREHSW4,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x328++0x03
line.long 0x00 "LB_MISRRLSW4,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x32C++0x03
line.long 0x00 "LB_MISRRHSW4,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x340++0x03
line.long 0x00 "LB_CTRL5,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x344++0x03
line.long 0x00 "LB_PCS5,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x360++0x03
line.long 0x00 "LB_MISRELSW5,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x364++0x03
line.long 0x00 "LB_MISREHSW5,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x368++0x03
line.long 0x00 "LB_MISRRLSW5,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x36C++0x03
line.long 0x00 "LB_MISRRHSW5,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x380++0x03
line.long 0x00 "LB_CTRL6,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x384++0x03
line.long 0x00 "LB_PCS6,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x3A0++0x03
line.long 0x00 "LB_MISRELSW6,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x3A4++0x03
line.long 0x00 "LB_MISREHSW6,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x3A8++0x03
line.long 0x00 "LB_MISRRLSW6,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x3AC++0x03
line.long 0x00 "LB_MISRRHSW6,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x3C0++0x03
line.long 0x00 "LB_CTRL7,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x3C4++0x03
line.long 0x00 "LB_PCS7,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x3E0++0x03
line.long 0x00 "LB_MISRELSW7,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x3E4++0x03
line.long 0x00 "LB_MISREHSW7,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x3E8++0x03
line.long 0x00 "LB_MISRRLSW7,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x3EC++0x03
line.long 0x00 "LB_MISRRHSW7,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x400++0x03
line.long 0x00 "LB_CTRL8,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x404++0x03
line.long 0x00 "LB_PCS8,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x420++0x03
line.long 0x00 "LB_MISRELSW8,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x424++0x03
line.long 0x00 "LB_MISREHSW8,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x428++0x03
line.long 0x00 "LB_MISRRLSW8,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x42C++0x03
line.long 0x00 "LB_MISRRHSW8,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x440++0x03
line.long 0x00 "LB_CTRL9,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x444++0x03
line.long 0x00 "LB_PCS9,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x460++0x03
line.long 0x00 "LB_MISRELSW9,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x464++0x03
line.long 0x00 "LB_MISREHSW9,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x468++0x03
line.long 0x00 "LB_MISRRLSW9,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x46C++0x03
line.long 0x00 "LB_MISRRHSW9,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x480++0x03
line.long 0x00 "LB_CTRL10,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x484++0x03
line.long 0x00 "LB_PCS10,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x4A0++0x03
line.long 0x00 "LB_MISRELSW10,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x4A4++0x03
line.long 0x00 "LB_MISREHSW10,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x4A8++0x03
line.long 0x00 "LB_MISRRLSW10,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x4AC++0x03
line.long 0x00 "LB_MISRRHSW10,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x4C0++0x03
line.long 0x00 "LB_CTRL11,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x4C4++0x03
line.long 0x00 "LB_PCS11,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x4E0++0x03
line.long 0x00 "LB_MISRELSW11,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x4E4++0x03
line.long 0x00 "LB_MISREHSW11,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x4E8++0x03
line.long 0x00 "LB_MISRRLSW11,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x4EC++0x03
line.long 0x00 "LB_MISRRHSW11,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x500++0x03
line.long 0x00 "LB_CTRL12,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x504++0x03
line.long 0x00 "LB_PCS12,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x520++0x03
line.long 0x00 "LB_MISRELSW12,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x524++0x03
line.long 0x00 "LB_MISREHSW12,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x528++0x03
line.long 0x00 "LB_MISRRLSW12,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x52C++0x03
line.long 0x00 "LB_MISRRHSW12,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x540++0x03
line.long 0x00 "LB_CTRL13,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x544++0x03
line.long 0x00 "LB_PCS13,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x560++0x03
line.long 0x00 "LB_MISRELSW13,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x564++0x03
line.long 0x00 "LB_MISREHSW13,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x568++0x03
line.long 0x00 "LB_MISRRLSW13,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x56C++0x03
line.long 0x00 "LB_MISRRHSW13,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x580++0x03
line.long 0x00 "LB_CTRL14,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x584++0x03
line.long 0x00 "LB_PCS14,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x5A0++0x03
line.long 0x00 "LB_MISRELSW14,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x5A4++0x03
line.long 0x00 "LB_MISREHSW14,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x5A8++0x03
line.long 0x00 "LB_MISRRLSW14,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x5AC++0x03
line.long 0x00 "LB_MISRRHSW14,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x5C0++0x03
line.long 0x00 "LB_CTRL15,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x5C4++0x03
line.long 0x00 "LB_PCS15,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x5E0++0x03
line.long 0x00 "LB_MISRELSW15,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x5E4++0x03
line.long 0x00 "LB_MISREHSW15,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x5E8++0x03
line.long 0x00 "LB_MISRRLSW15,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x5EC++0x03
line.long 0x00 "LB_MISRRHSW15,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x600++0x03
line.long 0x00 "LB_CTRL16,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x604++0x03
line.long 0x00 "LB_PCS16,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x620++0x03
line.long 0x00 "LB_MISRELSW16,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x624++0x03
line.long 0x00 "LB_MISREHSW16,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x628++0x03
line.long 0x00 "LB_MISRRLSW16,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x62C++0x03
line.long 0x00 "LB_MISRRHSW16,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x640++0x03
line.long 0x00 "LB_CTRL17,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x644++0x03
line.long 0x00 "LB_PCS17,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x660++0x03
line.long 0x00 "LB_MISRELSW17,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x664++0x03
line.long 0x00 "LB_MISREHSW17,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x668++0x03
line.long 0x00 "LB_MISRRLSW17,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x66C++0x03
line.long 0x00 "LB_MISRRHSW17,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x680++0x03
line.long 0x00 "LB_CTRL18,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x684++0x03
line.long 0x00 "LB_PCS18,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x6A0++0x03
line.long 0x00 "LB_MISRELSW18,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x6A4++0x03
line.long 0x00 "LB_MISREHSW18,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x6A8++0x03
line.long 0x00 "LB_MISRRLSW18,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x6AC++0x03
line.long 0x00 "LB_MISRRHSW18,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x6C0++0x03
line.long 0x00 "LB_CTRL19,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x6C4++0x03
line.long 0x00 "LB_PCS19,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x6E0++0x03
line.long 0x00 "LB_MISRELSW19,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x6E4++0x03
line.long 0x00 "LB_MISREHSW19,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x6E8++0x03
line.long 0x00 "LB_MISRRLSW19,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x6EC++0x03
line.long 0x00 "LB_MISRRHSW19,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x700++0x03
line.long 0x00 "LB_CTRL20,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x704++0x03
line.long 0x00 "LB_PCS20,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x720++0x03
line.long 0x00 "LB_MISRELSW20,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x724++0x03
line.long 0x00 "LB_MISREHSW20,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x728++0x03
line.long 0x00 "LB_MISRRLSW20,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x72C++0x03
line.long 0x00 "LB_MISRRHSW20,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x740++0x03
line.long 0x00 "LB_CTRL21,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x744++0x03
line.long 0x00 "LB_PCS21,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x760++0x03
line.long 0x00 "LB_MISRELSW21,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x764++0x03
line.long 0x00 "LB_MISREHSW21,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x768++0x03
line.long 0x00 "LB_MISRRLSW21,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x76C++0x03
line.long 0x00 "LB_MISRRHSW21,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x780++0x03
line.long 0x00 "LB_CTRL22,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x784++0x03
line.long 0x00 "LB_PCS22,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x7A0++0x03
line.long 0x00 "LB_MISRELSW22,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x7A4++0x03
line.long 0x00 "LB_MISREHSW22,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x7A8++0x03
line.long 0x00 "LB_MISRRLSW22,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x7AC++0x03
line.long 0x00 "LB_MISRRHSW22,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x7C0++0x03
line.long 0x00 "LB_CTRL23,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x7C4++0x03
line.long 0x00 "LB_PCS23,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x7E0++0x03
line.long 0x00 "LB_MISRELSW23,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x7E4++0x03
line.long 0x00 "LB_MISREHSW23,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x7E8++0x03
line.long 0x00 "LB_MISRRLSW23,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x7EC++0x03
line.long 0x00 "LB_MISRRHSW23,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x800++0x03
line.long 0x00 "LB_CTRL24,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x804++0x03
line.long 0x00 "LB_PCS24,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x820++0x03
line.long 0x00 "LB_MISRELSW24,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x824++0x03
line.long 0x00 "LB_MISREHSW24,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x828++0x03
line.long 0x00 "LB_MISRRLSW24,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x82C++0x03
line.long 0x00 "LB_MISRRHSW24,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x840++0x03
line.long 0x00 "LB_CTRL25,STCU2 LBIST Control"
bitfld.long 0x00 31. "CSM,Concurrent/sequential mode The next LBIST is scheduled concurrently to the current one if the CSM bit is set to 1 otherwise it is scheduled sequentially to the completion of the current LBIST execution" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,Next LBIST or MBIST pointer PTR defines the logical pointer to the next LBIST or MBIST to be scheduled"
newline
bitfld.long 0x00 16.--18. "SHS,Shift speed SHS defines the shift speed" "0: Shift at full rate (BIST clock),1: Shift at 1/2 rate (BIST clock),2: Shift at 1/3 rate (BIST clock),3: Shift at 1/4 rate (BIST clock),4: Shift at 1/5 rate (BIST clock),5: Shift at 1/6 rate (BIST clock),6: Shift at 1/7 rate (BIST clock),7: Shift at 1/8 rate (BIST clock)"
bitfld.long 0x00 12.--15. "SCEN_OFF,Scan enable OFF SCEN_OFF information is used to configure the lbist controller hardware to generate off_cycles delay cycles during the scan enable off transition" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
newline
bitfld.long 0x00 8.--11. "SCEN_ON,Scan enable ON SCEN_ON information is used to configure the lbist controller hardware to generate on_cycles delay cycles during the scan enable on transition SCEN_ON delay register value must be programmed to a value >=1" "0: 0 delay cycles,1: 1 delay cycle,2: 2 delay cycles,3: 3 delay cycles,4: 4 delay cycles,5: 5 delay cycles,6: 6 delay cycles,7: 7 delay cycles,8: 8 delay cycles,9: 9 delay cycles,10: 10 delay cycles,11: 11 delay cycles,12: 12 delay cycles,13: 13 delay cycles,14: 14 delay cycles,15: 15 delay cycles"
bitfld.long 0x00 0.--5. "CWS,Capture window size CWS defines the capture window size" "0: ILLGEAL,1: Controller waits 1 shift cycle for capture to..,2: Controller waits 2 shift cycles for capture..,3: Controller waits 3 shift cycles for capture..,4: Controller waits 4 shift cycles for capture..,5: Controller waits 5 shift cycles for capture..,6: Controller waits 6 shift cycles for capture..,7: Controller waits 7 shift cycles for capture..,?..."
group.long 0x844++0x03
line.long 0x00 "LB_PCS25,STCU2 LBIST PC Stop"
hexmask.long 0x00 0.--25. 1. "PCS,PCS"
group.long 0x860++0x03
line.long 0x00 "LB_MISRELSW25,STCU2 Online LBIST MISR Expected Low"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR expected low bits This field defines 32 bits of the expected MISR"
group.long 0x864++0x03
line.long 0x00 "LB_MISREHSW25,STCU2 Online LBIST MISR Expected High"
hexmask.long 0x00 0.--31. 1. "MISRESWx,Online MISR Expected High Bits This field defines the 32 bits of the expected MISR"
rgroup.long 0x868++0x03
line.long 0x00 "LB_MISRRLSW25,STCU2 Online LBIST MISR Read Low"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
rgroup.long 0x86C++0x03
line.long 0x00 "LB_MISRRHSW25,STCU2 Online LBIST MISR Read High"
hexmask.long 0x00 0.--31. 1. "MISRRSWx,MISRRSWx"
group.long 0x2200++0x03
line.long 0x00 "ALGOSEL,STCU2 Algorithm Select"
bitfld.long 0x00 31. "ALGOSEL31,Algorithm Select" "0,1"
bitfld.long 0x00 30. "ALGOSEL30,Algorithm Select" "0,1"
newline
bitfld.long 0x00 29. "ALGOSEL29,Algorithm Select" "0,1"
bitfld.long 0x00 28. "ALGOSEL28,Algorithm Select" "0,1"
newline
bitfld.long 0x00 27. "ALGOSEL27,Algorithm Select" "0,1"
bitfld.long 0x00 26. "ALGOSEL26,Algorithm Select" "0,1"
newline
bitfld.long 0x00 25. "ALGOSEL25,Algorithm Select" "0,1"
bitfld.long 0x00 24. "ALGOSEL24,Algorithm Select" "0,1"
newline
bitfld.long 0x00 23. "ALGOSEL23,Algorithm Select" "0,1"
bitfld.long 0x00 22. "ALGOSEL22,Algorithm Select" "0,1"
newline
bitfld.long 0x00 21. "ALGOSEL21,Algorithm Select" "0,1"
bitfld.long 0x00 20. "ALGOSEL20,Algorithm Select" "0,1"
newline
bitfld.long 0x00 19. "ALGOSEL19,Algorithm Select" "0,1"
bitfld.long 0x00 18. "ALGOSEL18,Algorithm Select" "0,1"
newline
bitfld.long 0x00 17. "ALGOSEL17,Algorithm Select" "0,1"
bitfld.long 0x00 16. "ALGOSEL16,Algorithm Select" "0,1"
newline
bitfld.long 0x00 15. "ALGOSEL15,Algorithm Select" "0,1"
bitfld.long 0x00 14. "ALGOSEL14,Algorithm Select" "0,1"
newline
bitfld.long 0x00 13. "ALGOSEL13,Algorithm Select" "0,1"
bitfld.long 0x00 12. "ALGOSEL12,Algorithm Select" "0,1"
newline
bitfld.long 0x00 11. "ALGOSEL11,Algorithm Select" "0,1"
bitfld.long 0x00 10. "ALGOSEL10,Algorithm Select" "0,1"
newline
bitfld.long 0x00 9. "ALGOSEL9,Algorithm Select" "0,1"
bitfld.long 0x00 8. "ALGOSEL8,Algorithm Select" "0,1"
newline
bitfld.long 0x00 7. "ALGOSEL7,Algorithm Select" "0,1"
bitfld.long 0x00 6. "ALGOSEL6,Algorithm Select" "0,1"
newline
bitfld.long 0x00 5. "ALGOSEL5,Algorithm Select" "0,1"
bitfld.long 0x00 4. "ALGOSEL4,Algorithm Select" "0,1"
newline
bitfld.long 0x00 3. "ALGOSEL3,Algorithm Select" "0,1"
bitfld.long 0x00 2. "ALGOSEL2,Algorithm Select" "0,1"
newline
bitfld.long 0x00 1. "ALGOSEL1,Algorithm Select" "0,1"
bitfld.long 0x00 0. "ALGOSEL0,Algorithm Select" "0,1"
group.long 0x220C++0x03
line.long 0x00 "STGGR,STCU2 MBIST Stagger"
hexmask.long 0x00 0.--31. 1. "STAG,STAG"
group.long 0x2210++0x03
line.long 0x00 "BSTART,STCU2 BIST Start"
bitfld.long 0x00 31. "BSTART31,BIST Start" "0,1"
bitfld.long 0x00 30. "BSTART30,BIST Start" "0,1"
newline
bitfld.long 0x00 29. "BSTART29,BIST Start" "0,1"
bitfld.long 0x00 28. "BSTART28,BIST Start" "0,1"
newline
bitfld.long 0x00 27. "BSTART27,BIST Start" "0,1"
bitfld.long 0x00 26. "BSTART26,BIST Start" "0,1"
newline
bitfld.long 0x00 25. "BSTART25,BIST Start" "0,1"
bitfld.long 0x00 24. "BSTART24,BIST Start" "0,1"
newline
bitfld.long 0x00 23. "BSTART23,BIST Start" "0,1"
bitfld.long 0x00 22. "BSTART22,BIST Start" "0,1"
newline
bitfld.long 0x00 21. "BSTART21,BIST Start" "0,1"
bitfld.long 0x00 20. "BSTART20,BIST Start" "0,1"
newline
bitfld.long 0x00 19. "BSTART19,BIST Start" "0,1"
bitfld.long 0x00 18. "BSTART18,BIST Start" "0,1"
newline
bitfld.long 0x00 17. "BSTART17,BIST Start" "0,1"
bitfld.long 0x00 16. "BSTART16,BIST Start" "0,1"
newline
bitfld.long 0x00 15. "BSTART15,BIST Start" "0,1"
bitfld.long 0x00 14. "BSTART14,BIST Start" "0,1"
newline
bitfld.long 0x00 13. "BSTART13,BIST Start" "0,1"
bitfld.long 0x00 12. "BSTART12,BIST Start" "0,1"
newline
bitfld.long 0x00 11. "BSTART11,BIST Start" "0,1"
bitfld.long 0x00 10. "BSTART10,BIST Start" "0,1"
newline
bitfld.long 0x00 9. "BSTART9,BIST Start" "0,1"
bitfld.long 0x00 8. "BSTART8,BIST Start" "0,1"
newline
bitfld.long 0x00 7. "BSTART7,BIST Start" "0,1"
bitfld.long 0x00 6. "BSTART6,BIST Start" "0,1"
newline
bitfld.long 0x00 5. "BSTART5,BIST Start" "0,1"
bitfld.long 0x00 4. "BSTART4,BIST Start" "0,1"
newline
bitfld.long 0x00 3. "BSTART3,BIST Start" "0,1"
bitfld.long 0x00 2. "BSTART2,BIST Start" "0,1"
newline
bitfld.long 0x00 1. "BSTART1,BIST Start" "0,1"
bitfld.long 0x00 0. "BSTART0,BIST Start" "0,1"
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x2214)++0x03
line.long 0x00 "MB_CTRL$1,STCU2 MBIST Control"
bitfld.long 0x00 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,PTR"
newline
bitfld.long 0x00 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution,1: Selected BIST is selected for execution"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x2254)++0x03
line.long 0x00 "MB_CTRL$1,STCU2 MBIST Control"
bitfld.long 0x00 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,PTR"
newline
bitfld.long 0x00 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution,1: Selected BIST is selected for execution"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x2294)++0x03
line.long 0x00 "MB_CTRL$1,STCU2 MBIST Control"
bitfld.long 0x00 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,PTR"
newline
bitfld.long 0x00 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution,1: Selected BIST is selected for execution"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x22D4)++0x03
line.long 0x00 "MB_CTRL$1,STCU2 MBIST Control"
bitfld.long 0x00 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,PTR"
newline
bitfld.long 0x00 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution,1: Selected BIST is selected for execution"
repeat.end
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x2314)++0x03
line.long 0x00 "MB_CTRL$1,STCU2 MBIST Control"
bitfld.long 0x00 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,PTR"
newline
bitfld.long 0x00 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution,1: Selected BIST is selected for execution"
repeat.end
repeat 16. (strings "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" "90" "91" "92" "93" "94" "95" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x2354)++0x03
line.long 0x00 "MB_CTRL$1,STCU2 MBIST Control"
bitfld.long 0x00 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,PTR"
newline
bitfld.long 0x00 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution,1: Selected BIST is selected for execution"
repeat.end
repeat 14. (strings "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" "106" "107" "108" "109" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 )
group.long ($2+0x2394)++0x03
line.long 0x00 "MB_CTRL$1,STCU2 MBIST Control"
bitfld.long 0x00 31. "CSM,CSM" "0: Sequential mode,1: Concurrent mode"
hexmask.long.word 0x00 21.--30. 1. "PTR,PTR"
newline
bitfld.long 0x00 20. "BSEL,BSEL" "0: Selected BIST is not selected for execution,1: Selected BIST is selected for execution"
repeat.end
tree.end
tree "STM (System Timer)"
repeat 3. (list 0. 1. 2.) (list ad:0x4047C000 ad:0x4027C000 ad:0x44004000)
tree "STM_$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CR,Control"
hexmask.long.byte 0x00 8.--15. 1. "CPS,Counter Prescaler"
bitfld.long 0x00 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode"
bitfld.long 0x00 0. "TEN,Timer Enable" "0: disabled,1: enabled"
group.long 0x04++0x03
line.long 0x00 "CNT,Count"
hexmask.long 0x00 0.--31. 1. "CNT,Timer Count"
repeat 4. (increment 0 1)(increment  0 0x10)
tree "CHANNEL[$1]"
group.long ($2+0x10)++0x03
line.long 0x00 "CCR,Channel Control"
bitfld.long 0x00 0. "CEN,Channel Enable" "0: disabled,1: enabled"
group.long ($2+0x14)++0x03
line.long 0x00 "CIR,Channel Interrupt"
eventfld.long 0x00 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted,1: Read: IRQ is asserted"
group.long ($2+0x18)++0x03
line.long 0x00 "CMP,Channel Compare"
hexmask.long 0x00 0.--31. 1. "CMP,Channel Compare"
tree.end
repeat.end
tree.end
repeat.end
tree.end
tree "SWT"
repeat 4. (list 0. 1. 2. 3.) (list ad:0x40000000 ad:0x40004000 ad:0x44000000 ad:0x440A6000)
tree "SWT_$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CR,Control"
bitfld.long 0x00 31. "MAP0,Master Access Protection 0" "0: Access disabled,1: Access enabled"
bitfld.long 0x00 30. "MAP1,Master Access Protection 1" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 29. "MAP2,Master Access Protection 2" "0: Access disabled,1: Access enabled"
bitfld.long 0x00 28. "MAP3,Master Access Protection 3" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 27. "MAP4,Master Access Protection 4" "0: Access disabled,1: Access enabled"
bitfld.long 0x00 26. "MAP5,Master Access Protection 5" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 25. "MAP6,Master Access Protection 6" "0: Access disabled,1: Access enabled"
bitfld.long 0x00 24. "MAP7,Master Access Protection 7" "0: Access disabled,1: Access enabled"
newline
bitfld.long 0x00 9.--10. "SMD,Service Mode" "0: Fixed Service Sequence,1: Keyed Service Sequence,?..."
bitfld.long 0x00 8. "RIA,Reset on Invalid Access" "0: Generate a bus error,1: Generate a bus error and reset request"
newline
bitfld.long 0x00 7. "WND,Window Mode" "0: Regular mode,1: Window mode"
bitfld.long 0x00 6. "ITR,Interrupt Then Reset Request" "0: Generate a reset request on a timeout,1: Generate an interrupt on an initial timeout.."
newline
bitfld.long 0x00 5. "HLK,Hard Lock" "0: CR TO WN and SK are read/write registers if..,1: CR TO WN and SK are read-only registers"
bitfld.long 0x00 4. "SLK,Soft Lock" "0: CR TO WN and SK are read/write registers if..,1: CR TO WN and SK are read-only registers"
newline
bitfld.long 0x00 2. "STP,Stop Mode Control" "0: Timer continues,1: Timer stops"
bitfld.long 0x00 1. "FRZ,Debug Mode Control" "0: Timer continues,1: Timer stops"
newline
bitfld.long 0x00 0. "WEN,Watchdog Enable" "0: disabled,1: enabled"
group.long 0x04++0x03
line.long 0x00 "IR,Interrupt"
eventfld.long 0x00 0. "TIF,Timeout Interrupt Flag" "0: No interrupt request,1: Interrupt request due to an initial timeout"
group.long 0x08++0x03
line.long 0x00 "TO,Timeout"
hexmask.long 0x00 0.--31. 1. "WTO,Watchdog Timeout"
group.long 0x0C++0x03
line.long 0x00 "WN,Window"
hexmask.long 0x00 0.--31. 1. "WST,Window Start Value"
group.long 0x10++0x03
line.long 0x00 "SR,Service"
hexmask.long.word 0x00 0.--15. 1. "WSC,Watchdog Service Code"
rgroup.long 0x14++0x03
line.long 0x00 "CO,Counter Output"
hexmask.long 0x00 0.--31. 1. "CNT,Watchdog Count"
group.long 0x18++0x03
line.long 0x00 "SK,Service Key"
hexmask.long.word 0x00 0.--15. 1. "SK,Service Key"
group.long 0x1C++0x03
line.long 0x00 "RRR,Event Request"
eventfld.long 0x00 0. "RRF,Reset Request Flag" "0: No reset request,1: Any reset request initiated"
tree.end
repeat.end
tree.end
tree "TMU (Thermal Monitoring Unit)"
base ad:0x4008C000
group.long 0x00++0x03
line.long 0x00 "TMR,Mode"
bitfld.long 0x00 30.--31. "MODE,Mode" "0: Idle low-power mode,?,2: Monitoring of sites as defined by TMSR[SITE],?..."
bitfld.long 0x00 29. "CMD,Central Module Disable" "0: Enabled,1: Disabled"
newline
bitfld.long 0x00 24.--25. "ALPF,Average Low Pass Filter Setting" "0: ALPF_d,1: ALPF_c,2: ALPF_b,3: ALPF_a"
group.long 0x04++0x03
line.long 0x00 "TSR,Status"
rbitfld.long 0x00 31. "TB,TMU Busy" "0: TMU is idle,1: TMU is busy"
eventfld.long 0x00 30. "MIE,Monitoring Interval Exceeded" "0: Monitoring interval not exceeded,1: Monitoring interval exceeded"
newline
eventfld.long 0x00 29. "ORL,Out-of-Range Low Temperature Measurement" "0: No out-of-range low temperature measurement..,1: Out-of-range low temperature measurement.."
eventfld.long 0x00 28. "ORH,Out-of-Range High Temperature Measurement" "0: No out-of-range high temperature measurement..,1: Out-of-range high temperature measurement.."
group.long 0x08++0x03
line.long 0x00 "TMSR,Monitor Site"
bitfld.long 0x00 0.--4. "SITE,Monitoring Site Select 4-0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x0C++0x03
line.long 0x00 "TMTMIR,Monitor Temperature Measurement Interval"
bitfld.long 0x00 0.--3. "TMI,Temperature Monitoring Interval in Seconds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "TIER,Interrupt Enable"
bitfld.long 0x00 31. "IHTTIE,Immediate High Temperature Threshold Interrupt Enable" "0: IHTTIE_b,1: Interrupt enabled generates an interrupt if.."
bitfld.long 0x00 30. "AHTTIE,Average High Temperature Threshold Interrupt Enable" "0: AHTTIE_b,1: Interrupt enabled generates an interrupt if.."
newline
bitfld.long 0x00 29. "AHTCTIE,Average High Temperature Critical Threshold Interrupt Enable" "0: AHTCTIE_b,1: Interrupt enabled generates an interrupt if.."
bitfld.long 0x00 28. "ILTTIE,Immediate Low Temperature Threshold Interrupt Enable" "0: ILTTIE_b,1: Interrupt enabled generates an interrupt if.."
newline
bitfld.long 0x00 27. "ALTTIE,Average Low Temperature Threshold Interrupt Enable" "0: ALTTIE_b,1: Interrupt enabled generates an interrupt if.."
bitfld.long 0x00 26. "ALTCTIE,Average Low Temperature Critical Threshold Interrupt Enable" "0: ALTCTIE_b,1: Interrupt enabled generates an interrupt if.."
newline
bitfld.long 0x00 25. "RTRCTIE,Rising Temperature Rate Critical Threshold Interrupt Enable" "0: RTRCTIE_b,1: Interrupt enabled generates an interrupt if.."
bitfld.long 0x00 24. "FTRCTIE,Falling Temperature Rate Critical Threshold Interrupt Enable" "0: FTRCTIE_b,1: Interrupt enabled generates an interrupt if.."
group.long 0x24++0x03
line.long 0x00 "TIDR,Interrupt Detect"
eventfld.long 0x00 31. "IHTT,Immediate High Temperature Threshold Exceeded" "0: No threshold exceeded,1: One or more monitored sites has exceeded the.."
eventfld.long 0x00 30. "AHTT,Average High Temperature Threshold Exceeded" "0: No threshold exceeded,1: One or more monitored sites exceed the.."
newline
eventfld.long 0x00 29. "AHTCT,Average High Temperature Critical Threshold Exceeded" "0: No threshold exceeded,1: One or more monitored sites exceed the.."
eventfld.long 0x00 28. "ILTT,Immediate Low Temperature Threshold" "0: No threshold exceeded,1: One or more monitored sites has passed the.."
newline
eventfld.long 0x00 27. "ALTT,Average Low Temperature Threshold" "0: No threshold exceeded,1: One or more monitored sites pass the average.."
eventfld.long 0x00 26. "ALTCT,Average Low Temperature Critical Threshold" "0: No threshold exceeded,1: One or more monitored sites pass the average.."
newline
eventfld.long 0x00 25. "RTRCT,Rising Temperature Rate Critical Threshold" "0: No threshold exceeded,1: One or more monitored sites pass the rising.."
eventfld.long 0x00 24. "FTRCT,Falling Temperature Rate Critical Threshold" "0: No threshold exceeded,1: One or more monitored sites exceed the.."
group.long 0x30++0x03
line.long 0x00 "TIISCR,Interrupt Immediate Site Capture"
bitfld.long 0x00 0.--4. "SITE,Temperature Sensor Site" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x34++0x03
line.long 0x00 "TIASCR,Interrupt Average Site Capture"
bitfld.long 0x00 0.--4. "SITE,Temperature Sensor Site" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x38++0x03
line.long 0x00 "TICSCR,Interrupt Critical Site Capture"
bitfld.long 0x00 0.--4. "SITE,Temperature Sensor Site" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x40++0x03
line.long 0x00 "TMHTCR,Monitor High Temperature Capture"
eventfld.long 0x00 31. "V,Valid Reading" "0: Temperature reading is not valid due to no..,1: Temperature reading is valid"
rbitfld.long 0x00 9. "TP5,Highest Temperature Recorded in Kelvin by Any Enabled Monitored Site" "0,1"
newline
hexmask.long.word 0x00 0.--8. 1. "TEMP,Highest Temperature Recorded in Kelvin by Any Enabled Monitored Site"
group.long 0x44++0x03
line.long 0x00 "TMLTCR,Monitor Low Temperature Capture"
eventfld.long 0x00 31. "V,Valid Reading" "0: Temperature reading is not valid because of..,1: Temperature reading is valid"
rbitfld.long 0x00 9. "TP5,Lowest Temperature in Kelvin that Any Enabled Monitored Site Records" "0,1"
newline
hexmask.long.word 0x00 0.--8. 1. "TEMP,Lowest Temperature in Kelvin that Any Enabled Monitored Site Records"
group.long 0x48++0x03
line.long 0x00 "TMRTRCR,Monitor Rising Temperature Rate Capture"
eventfld.long 0x00 31. "V,Valid Reading" "0: Temperature reading is not valid because of..,1: Temperature reading is valid"
hexmask.long.byte 0x00 0.--7. 1. "TEMP,Highest Rising Temperature Rate Change in Kelvin that Any Enabled Monitored Site Records"
group.long 0x4C++0x03
line.long 0x00 "TMFTRCR,Monitor Falling Temperature Rate Capture"
eventfld.long 0x00 31. "V,Valid Reading" "0: Temperature reading is not valid because of..,1: Temperature reading is valid"
hexmask.long.byte 0x00 0.--7. 1. "TEMP,Highest Falling Temperature Rate Change in Kelvin that Any Enabled Monitored Site Records"
group.long 0x50++0x03
line.long 0x00 "TMHTITR,Monitor High Temperature Immediate Threshold"
bitfld.long 0x00 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled"
hexmask.long.word 0x00 0.--8. 1. "TEMP,High Temperature Immediate Threshold Value"
group.long 0x54++0x03
line.long 0x00 "TMHTATR,Monitor High Temperature Average Threshold"
bitfld.long 0x00 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled"
hexmask.long.word 0x00 0.--8. 1. "TEMP,High Temperature Average Threshold Value"
group.long 0x58++0x03
line.long 0x00 "TMHTACTR,Monitor High Temperature Average Critical Threshold"
bitfld.long 0x00 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled"
hexmask.long.word 0x00 0.--8. 1. "TEMP,High Temperature Average Critical Threshold Value"
group.long 0x60++0x03
line.long 0x00 "TMLTITR,Monitor Low Temperature Immediate Threshold"
bitfld.long 0x00 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled"
hexmask.long.word 0x00 0.--8. 1. "TEMP,Low Temperature Immediate Threshold Value"
group.long 0x64++0x03
line.long 0x00 "TMLTATR,Monitor Low Temperature Average Threshold"
bitfld.long 0x00 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled"
hexmask.long.word 0x00 0.--8. 1. "TEMP,Low Temperature Average Threshold Value"
group.long 0x68++0x03
line.long 0x00 "TMLTACTR,Monitor Low Temperature Average Critical Threshold"
bitfld.long 0x00 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled"
hexmask.long.word 0x00 0.--8. 1. "TEMP,Low Temperature Average Critical Threshold Value"
group.long 0x70++0x03
line.long 0x00 "TMRTRCTR,Monitor Rising Temperature Rate Critical Threshold"
bitfld.long 0x00 31. "EN,Enable Threshold" "0: Disabled,1: Threshold enabled"
hexmask.long.byte 0x00 0.--7. 1. "TEMP,Temperature Difference Between Two Measurements From the Same Site"
group.long 0x74++0x03
line.long 0x00 "TMFTRCTR,Monitor Falling Temperature Rate Critical Threshold"
bitfld.long 0x00 31. "EN,Enable threshold" "0: Disabled,1: Threshold Enabled"
hexmask.long.byte 0x00 0.--7. 1. "TEMP,Temperature Difference Between Two Measurements From the Same Site"
group.long 0x80++0x03
line.long 0x00 "TTCFGR,Temperature Configuration"
bitfld.long 0x00 0.--3. "CAL_PT,Calibration Point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x84++0x03
line.long 0x00 "TSCFGR,Sensor Configuration"
hexmask.long.word 0x00 0.--8. 1. "SENSOR,Sensor Value"
group.long 0xF00++0x03
line.long 0x00 "TCMCFG,Central Module Configuration"
bitfld.long 0x00 31. "DPM,Dynamic Power Management" "0,1"
bitfld.long 0x00 30. "OCM,Offset Cancellation Mode" "0,1"
newline
bitfld.long 0x00 29. "OCS,Offset Cancellation Manual Setting" "0,1"
bitfld.long 0x00 28. "DEMA,Dynamic Element Match Averaging Mode" "0,1"
newline
bitfld.long 0x00 24.--26. "RCTC,RC Time Constant Setting" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 16. "SAR_RDY,SAR Ready" "0: SAR not ready to receive command,1: SAR ready to receive command"
newline
bitfld.long 0x00 12.--15. "CLK_DIV,Clock Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "DFD,Digital Filter Depth" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "CMET,Central Module Enable Time" "0,1,2,3"
hexmask.long.byte 0x00 0.--6. 1. "DAC_OFFSET,DAC Offset"
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0xF10)++0x03
line.long 0x00 "TTRCR[$1],Temperature Range Control index $1"
bitfld.long 0x00 31. "V,Calibration Point is Valid" "0: Not valid,1: Valid"
hexmask.long.word 0x00 0.--8. 1. "TEMP,Temperature in Kelvin for the Calibration Point"
repeat.end
repeat 5. (increment 0 1)(increment  0 0x10)
tree "TRITRATSR[$1]"
rgroup.long ($2+0x100)++0x03
line.long 0x00 "TRITSR,Report Immediate Temperature at Site"
bitfld.long 0x00 31. "V,Valid Measured Temperature" "0: Not valid temperature is out of sensor..,1: Valid"
bitfld.long 0x00 9. "TP5,Last Temperature Reading in Kelvin at the Site" "0,1"
hexmask.long.word 0x00 0.--8. 1. "TEMP,Last Temperature Reading in Kelvin at the Site"
rgroup.long ($2+0x104)++0x03
line.long 0x00 "TRATSR,Report Average Temperature at Site"
bitfld.long 0x00 31. "V,Valid Measured Temperature" "0: Not valid temperature is out of sensor range..,1: Valid"
hexmask.long.word 0x00 0.--8. 1. "TEMP,Average Temperature Reading in Kelvin at the Site"
tree.end
repeat.end
tree.end
tree "WKPU"
base ad:0x400EC000
group.long 0x00++0x03
line.long 0x00 "NSR,NMI Status Flag Register"
eventfld.long 0x00 31. "NIF0,NMI Status Flag 0" "0: No event has occurred on the pad,1: An event as defined by NREE0 and NFEE0 has.."
eventfld.long 0x00 30. "NOVF0,NMI Overrun Status Flag 0" "0: No overrun has occurred on NMI input 0,1: An overrun has occurred on NMI input 0"
group.long 0x08++0x03
line.long 0x00 "NCR,NMI Configuration Register"
bitfld.long 0x00 31. "NLOCK0,NMI Configuration Lock Register 0" "0,1"
bitfld.long 0x00 29.--30. "NDSS0,NMI Destination Source Select 0" "0: Non-maskable interrupt,?..."
newline
bitfld.long 0x00 28. "NWRE0,NMI Wakeup Request Enable 0" "0: System wakeup requests from the corresponding..,1: Causes a system wakeup request when NIF0 = 1.."
bitfld.long 0x00 26. "NREE0,NMI Rising-Edge Events Enable 0" "0: Rising-edge event is disabled,1: Rising-edge event is enabled"
newline
bitfld.long 0x00 25. "NFEE0,NMI Falling-edge Events Enable 0" "0,1"
bitfld.long 0x00 24. "NFE0,NMI Filter Enable 0" "0: Filter is disabled,1: Filter is enabled"
tree.end
tree "XBIC"
repeat 6. (list 0. 1. 2. 3. 4. 5.) (list ad:0x40030000 ad:0x40034000 ad:0x40038000 ad:0x4003C000 ad:0x40040000 ad:0x40044000)
tree "XBIC_$1"
base $2
group.long 0x00++0x03
line.long 0x00 "MCR,XBIC Module Control"
bitfld.long 0x00 31. "SE0,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for..,1: Attribute integrity checking enabled for.."
bitfld.long 0x00 30. "SE1,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for..,1: Attribute integrity checking enabled for.."
newline
bitfld.long 0x00 29. "SE2,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for..,1: Attribute integrity checking enabled for.."
bitfld.long 0x00 28. "SE3,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for..,1: Attribute integrity checking enabled for.."
newline
bitfld.long 0x00 27. "SE4,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for..,1: Attribute integrity checking enabled for.."
bitfld.long 0x00 26. "SE5,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for..,1: Attribute integrity checking enabled for.."
newline
bitfld.long 0x00 25. "SE6,Slave port EDC Error Detection Enable" "0: Attribute integrity checking disabled for..,1: Attribute integrity checking enabled for.."
bitfld.long 0x00 24. "SE7,Slave Port EDC Error Detection Enable" "0: Attribute integrity checking disabled for..,1: Attribute integrity checking enabled for.."
newline
bitfld.long 0x00 23. "ME0,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for..,1: Feedback integrity checking enabled for.."
bitfld.long 0x00 22. "ME1,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for..,1: Feedback integrity checking enabled for.."
newline
bitfld.long 0x00 21. "ME2,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for..,1: Feedback integrity checking enabled for.."
bitfld.long 0x00 20. "ME3,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for..,1: Feedback integrity checking enabled for.."
newline
bitfld.long 0x00 19. "ME4,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for..,1: Feedback integrity checking enabled for.."
bitfld.long 0x00 18. "ME5,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for..,1: Feedback integrity checking enabled for.."
newline
bitfld.long 0x00 17. "ME6,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for..,1: Feedback integrity checking enabled for.."
bitfld.long 0x00 16. "ME7,Master Port Enable For Feedback Integrity Check" "0: Feedback integrity checking disabled for..,1: Feedback integrity checking enabled for.."
group.long 0x04++0x03
line.long 0x00 "EIR,XBIC Error Injection"
bitfld.long 0x00 31. "EIE,Error Injection Enable" "0: Error injection disabled,1: Error injection enabled"
bitfld.long 0x00 12.--14. "SLV,Target Slave Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--11. "MST,Target Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "SYN,Syndrome"
rgroup.long 0x08++0x03
line.long 0x00 "ESR,XBIC Error Status"
bitfld.long 0x00 31. "VLD,Error Status Valid" "0: No error detected-other fields of the ESR and..,1: Error detected-all fields of the ESR and EAR.."
bitfld.long 0x00 30. "DPSE0,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave.."
newline
bitfld.long 0x00 29. "DPSE1,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave.."
bitfld.long 0x00 28. "DPSE2,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave.."
newline
bitfld.long 0x00 27. "DPSE3,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave.."
bitfld.long 0x00 26. "DPSE4,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave.."
newline
bitfld.long 0x00 25. "DPSE5,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave.."
bitfld.long 0x00 24. "DPSE6,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave.."
newline
bitfld.long 0x00 23. "DPSE7,Data Phase Slave Port Error" "0: No feedback integrity error detected on slave..,1: Feedback integrity error detected on slave.."
bitfld.long 0x00 22. "DPME0,Data Phase Master Port Error" "0: No feedback integrity error detected on..,1: Feedback integrity error detected on master.."
newline
bitfld.long 0x00 21. "DPME1,Data Phase Master Port Error" "0: No feedback integrity error detected on..,1: Feedback integrity error detected on master.."
bitfld.long 0x00 20. "DPME2,Data Phase Master Port Error" "0: No feedback integrity error detected on..,1: Feedback integrity error detected on master.."
newline
bitfld.long 0x00 19. "DPME3,Data Phase Master Port Error" "0: No feedback integrity error detected on..,1: Feedback integrity error detected on master.."
bitfld.long 0x00 18. "DPME4,Data Phase Master Port Error" "0: No feedback integrity error detected on..,1: Feedback integrity error detected on master.."
newline
bitfld.long 0x00 17. "DPME5,Data Phase Master Port Error" "0: No feedback integrity error detected on..,1: Feedback integrity error detected on master.."
bitfld.long 0x00 16. "DPME6,Data Phase Master Port Error" "0: No feedback integrity error detected on..,1: Feedback integrity error detected on master.."
newline
bitfld.long 0x00 15. "DPME7,Data Phase Master Port Error" "0: No feedback integrity error detected on..,1: Feedback integrity error detected on master.."
bitfld.long 0x00 12.--14. "SLV,Slave Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--11. "MST,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "SYN,Syndrome"
rgroup.long 0x0C++0x03
line.long 0x00 "EAR,XBIC Error Address"
hexmask.long 0x00 0.--31. 1. "ADDR,Error Address"
tree.end
repeat.end
tree.end
tree "XRDC"
tree "XRDC_0"
base ad:0x40018000
group.long 0x00++0x03
line.long 0x00 "CR,Control"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
rbitfld.long 0x00 8. "VAW,Virtualization Aware" "0: Not virtualization-aware,1: Virtualization-aware"
newline
rbitfld.long 0x00 7. "MRF,Memory Region Format" "?,1: SMPU family format"
rbitfld.long 0x00 1.--4. "HRL,Hardware Revision Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "GVLD,Global Valid (XRDC Global Enable/Disable)" "0: Disables,1: Enables"
rgroup.long 0xF0++0x03
line.long 0x00 "HWCFG0,Hardware Configuration 0"
bitfld.long 0x00 28.--31. "MID,Module ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "NPAC,Number Of PACs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "NMRC,Number of MRCs"
hexmask.long.byte 0x00 8.--15. 1. "NMSTR,Number Of Bus Masters"
newline
hexmask.long.byte 0x00 0.--7. 1. "NDID,Number Of DIDs"
rgroup.long 0xF4++0x03
line.long 0x00 "HWCFG1,Hardware Configuration 1"
bitfld.long 0x00 0.--3. "DID,Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xF8++0x03
line.long 0x00 "HWCFG2,Hardware Configuration 2"
bitfld.long 0x00 31. "PIDP31,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 30. "PIDP30,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 29. "PIDP29,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 28. "PIDP28,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 27. "PIDP27,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 26. "PIDP26,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 25. "PIDP25,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 24. "PIDP24,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 23. "PIDP23,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 22. "PIDP22,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 21. "PIDP21,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 20. "PIDP20,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 19. "PIDP19,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 18. "PIDP18,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 17. "PIDP17,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 16. "PIDP16,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 15. "PIDP15,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 14. "PIDP14,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 13. "PIDP13,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 12. "PIDP12,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 11. "PIDP11,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 10. "PIDP10,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 9. "PIDP9,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 8. "PIDP8,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 7. "PIDP7,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 6. "PIDP6,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 5. "PIDP5,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 4. "PIDP4,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 3. "PIDP3,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 2. "PIDP2,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 1. "PIDP1,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 0. "PIDP0,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 )
rgroup.byte ($2+0x100)++0x00
line.byte 0x00 "MDACFG$1,Master Domain Assignment Configuration"
bitfld.byte 0x00 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master"
bitfld.byte 0x00 0.--3. "NMDAR,Number Of Master Domain Assignment Registers" "0: Master does not exist,1: Number of registers,2: Number of registers,3: Number of registers,4: Number of registers,5: Number of registers,6: Number of registers,7: Number of registers,8: Number of registers,?..."
repeat.end
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x01 0x02 0x03 0x04 )
rgroup.byte ($2+0x140)++0x00
line.byte 0x00 "MRCFG$1,Memory Region Configuration"
bitfld.byte 0x00 0.--4. "NMRGD,Number Of Memory Region Descriptors" "0: MRC does not exist,?,?,?,4: FOUR,?,?,?,8: EIGHT,?,?,?,12: TWELVE,?,?,?,16: SIXTEEN,?..."
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x200)++0x03
line.long 0x00 "DERRLOC[$1],Domain Error Location $1"
bitfld.long 0x00 16.--19. "PACINST,PAC Instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "MRCINST,MRC Instance"
repeat.end
rgroup.long 0x400++0x03
line.long 0x00 "DERR_W0_0,Domain Error Word 0"
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
rgroup.long 0x404++0x03
line.long 0x00 "DERR_W1_0,Domain Error Word 1"
bitfld.long 0x00 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected"
bitfld.long 0x00 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "ERW,Error Read Or Write" "0: READ_ACCESS,1: WRITE_ACCESS"
bitfld.long 0x00 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
newline
bitfld.long 0x00 0.--3. "EDID,Error Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40C++0x03
line.long 0x00 "DERR_W3_0,Domain Error Word 3"
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0: NO_EFFECT_0,1: Rearms error capture resets error capture..,2: NO_EFFECT_2,3: NO_EFFECT_3"
rgroup.long 0x410++0x03
line.long 0x00 "DERR_W0_1,Domain Error Word 0"
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
rgroup.long 0x414++0x03
line.long 0x00 "DERR_W1_1,Domain Error Word 1"
bitfld.long 0x00 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected"
bitfld.long 0x00 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "ERW,Error Read Or Write" "0: READ_ACCESS,1: WRITE_ACCESS"
bitfld.long 0x00 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
newline
bitfld.long 0x00 0.--3. "EDID,Error Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x41C++0x03
line.long 0x00 "DERR_W3_1,Domain Error Word 3"
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0: NO_EFFECT_0,1: Rearms error capture resets error capture..,2: NO_EFFECT_2,3: NO_EFFECT_3"
rgroup.long 0x420++0x03
line.long 0x00 "DERR_W0_2,Domain Error Word 0"
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
rgroup.long 0x424++0x03
line.long 0x00 "DERR_W1_2,Domain Error Word 1"
bitfld.long 0x00 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected"
bitfld.long 0x00 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "ERW,Error Read Or Write" "0: READ_ACCESS,1: WRITE_ACCESS"
bitfld.long 0x00 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
newline
bitfld.long 0x00 0.--3. "EDID,Error Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x42C++0x03
line.long 0x00 "DERR_W3_2,Domain Error Word 3"
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0: NO_EFFECT_0,1: Rearms error capture resets error capture..,2: NO_EFFECT_2,3: NO_EFFECT_3"
rgroup.long 0x430++0x03
line.long 0x00 "DERR_W0_3,Domain Error Word 0"
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
rgroup.long 0x434++0x03
line.long 0x00 "DERR_W1_3,Domain Error Word 1"
bitfld.long 0x00 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected"
bitfld.long 0x00 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "ERW,Error Read Or Write" "0: READ_ACCESS,1: WRITE_ACCESS"
bitfld.long 0x00 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
newline
bitfld.long 0x00 0.--3. "EDID,Error Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x43C++0x03
line.long 0x00 "DERR_W3_3,Domain Error Word 3"
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0: NO_EFFECT_0,1: Rearms error capture resets error capture..,2: NO_EFFECT_2,3: NO_EFFECT_3"
rgroup.long 0x440++0x03
line.long 0x00 "DERR_W0_4,Domain Error Word 0"
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
rgroup.long 0x444++0x03
line.long 0x00 "DERR_W1_4,Domain Error Word 1"
bitfld.long 0x00 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected"
bitfld.long 0x00 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "ERW,Error Read Or Write" "0: READ_ACCESS,1: WRITE_ACCESS"
bitfld.long 0x00 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
newline
bitfld.long 0x00 0.--3. "EDID,Error Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x44C++0x03
line.long 0x00 "DERR_W3_4,Domain Error Word 3"
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0: NO_EFFECT_0,1: Rearms error capture resets error capture..,2: NO_EFFECT_2,3: NO_EFFECT_3"
rgroup.long 0x500++0x03
line.long 0x00 "DERR_W0_16,Domain Error Word 0"
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
rgroup.long 0x504++0x03
line.long 0x00 "DERR_W1_16,Domain Error Word 1"
bitfld.long 0x00 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected"
bitfld.long 0x00 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "ERW,Error Read Or Write" "0: READ_ACCESS,1: WRITE_ACCESS"
bitfld.long 0x00 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
newline
bitfld.long 0x00 0.--3. "EDID,Error Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50C++0x03
line.long 0x00 "DERR_W3_16,Domain Error Word 3"
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0: NO_EFFECT_0,1: Rearms error capture resets error capture..,2: NO_EFFECT_2,3: NO_EFFECT_3"
rgroup.long 0x510++0x03
line.long 0x00 "DERR_W0_17,Domain Error Word 0"
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
rgroup.long 0x514++0x03
line.long 0x00 "DERR_W1_17,Domain Error Word 1"
bitfld.long 0x00 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected"
bitfld.long 0x00 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "ERW,Error Read Or Write" "0: READ_ACCESS,1: WRITE_ACCESS"
bitfld.long 0x00 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
newline
bitfld.long 0x00 0.--3. "EDID,Error Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x51C++0x03
line.long 0x00 "DERR_W3_17,Domain Error Word 3"
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0: NO_EFFECT_0,1: Rearms error capture resets error capture..,2: NO_EFFECT_2,3: NO_EFFECT_3"
rgroup.long 0x520++0x03
line.long 0x00 "DERR_W0_18,Domain Error Word 0"
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
rgroup.long 0x524++0x03
line.long 0x00 "DERR_W1_18,Domain Error Word 1"
bitfld.long 0x00 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected"
bitfld.long 0x00 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "ERW,Error Read Or Write" "0: READ_ACCESS,1: WRITE_ACCESS"
bitfld.long 0x00 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
newline
bitfld.long 0x00 0.--3. "EDID,Error Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x52C++0x03
line.long 0x00 "DERR_W3_18,Domain Error Word 3"
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0: NO_EFFECT_0,1: Rearms error capture resets error capture..,2: NO_EFFECT_2,3: NO_EFFECT_3"
repeat 4. (strings "1" "2" "5" "6" )(list 0x00 0x04 0x10 0x14 )
group.long ($2+0x704)++0x03
line.long 0x00 "PID$1,Process Identifier"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Any secure privileged,1: Any secure privileged,2: Secure privileged writes from master only,3: LOCKED"
bitfld.long 0x00 28. "TSM,Three-State Model" "0,1"
newline
bitfld.long 0x00 0.--5. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
group.long 0x800++0x03
line.long 0x00 "MDA_W0_0_DFMT1,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)"
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input"
newline
bitfld.long 0x00 6.--7. "SA,Secure Attribute" "0: Force to secure,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master"
bitfld.long 0x00 4.--5. "PA,Privileged Attribute" "0: Force to user,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master"
newline
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x820++0x03
line.long 0x00 "MDA_W0_1_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x824++0x03
line.long 0x00 "MDA_W1_1_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x828++0x03
line.long 0x00 "MDA_W2_1_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
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bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x82C++0x03
line.long 0x00 "MDA_W3_1_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
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bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x830++0x03
line.long 0x00 "MDA_W4_1_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
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bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x834++0x03
line.long 0x00 "MDA_W5_1_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
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bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x838++0x03
line.long 0x00 "MDA_W6_1_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
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bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x83C++0x03
line.long 0x00 "MDA_W7_1_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
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bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x840++0x03
line.long 0x00 "MDA_W0_2_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x844++0x03
line.long 0x00 "MDA_W1_2_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x848++0x03
line.long 0x00 "MDA_W2_2_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x84C++0x03
line.long 0x00 "MDA_W3_2_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x850++0x03
line.long 0x00 "MDA_W4_2_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x854++0x03
line.long 0x00 "MDA_W5_2_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x858++0x03
line.long 0x00 "MDA_W6_2_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x85C++0x03
line.long 0x00 "MDA_W7_2_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
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bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x860++0x03
line.long 0x00 "MDA_W0_3_DFMT1,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)"
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input"
newline
bitfld.long 0x00 6.--7. "SA,Secure Attribute" "0: Force to secure,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master"
bitfld.long 0x00 4.--5. "PA,Privileged Attribute" "0: Force to user,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master"
newline
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x880++0x03
line.long 0x00 "MDA_W0_4_DFMT1,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)"
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input"
newline
bitfld.long 0x00 6.--7. "SA,Secure Attribute" "0: Force to secure,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master"
bitfld.long 0x00 4.--5. "PA,Privileged Attribute" "0: Force to user,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master"
newline
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8A0++0x03
line.long 0x00 "MDA_W0_5_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
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bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8A4++0x03
line.long 0x00 "MDA_W1_5_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
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bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8A8++0x03
line.long 0x00 "MDA_W2_5_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
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bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8AC++0x03
line.long 0x00 "MDA_W3_5_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
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bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8B0++0x03
line.long 0x00 "MDA_W4_5_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
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bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8B4++0x03
line.long 0x00 "MDA_W5_5_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
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bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8B8++0x03
line.long 0x00 "MDA_W6_5_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8BC++0x03
line.long 0x00 "MDA_W7_5_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8C0++0x03
line.long 0x00 "MDA_W0_6_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8C4++0x03
line.long 0x00 "MDA_W1_6_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8C8++0x03
line.long 0x00 "MDA_W2_6_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8CC++0x03
line.long 0x00 "MDA_W3_6_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8D0++0x03
line.long 0x00 "MDA_W4_6_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8D4++0x03
line.long 0x00 "MDA_W5_6_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8D8++0x03
line.long 0x00 "MDA_W6_6_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8DC++0x03
line.long 0x00 "MDA_W7_6_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8E0++0x03
line.long 0x00 "MDA_W0_7_DFMT1,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)"
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input"
newline
bitfld.long 0x00 6.--7. "SA,Secure Attribute" "0: Force to secure,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master"
bitfld.long 0x00 4.--5. "PA,Privileged Attribute" "0: Force to user,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master"
newline
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x1000++0x03
line.long 0x00 "PDAC_W0_0,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1004++0x03
line.long 0x00 "PDAC_W1_0,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1008++0x03
line.long 0x00 "PDAC_W0_1,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x100C++0x03
line.long 0x00 "PDAC_W1_1,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1020++0x03
line.long 0x00 "PDAC_W0_4,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1024++0x03
line.long 0x00 "PDAC_W1_4,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1028++0x03
line.long 0x00 "PDAC_W0_5,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x102C++0x03
line.long 0x00 "PDAC_W1_5,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1030++0x03
line.long 0x00 "PDAC_W0_6,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1034++0x03
line.long 0x00 "PDAC_W1_6,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1060++0x03
line.long 0x00 "PDAC_W0_12,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1064++0x03
line.long 0x00 "PDAC_W1_12,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1068++0x03
line.long 0x00 "PDAC_W0_13,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x106C++0x03
line.long 0x00 "PDAC_W1_13,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1070++0x03
line.long 0x00 "PDAC_W0_14,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1074++0x03
line.long 0x00 "PDAC_W1_14,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1078++0x03
line.long 0x00 "PDAC_W0_15,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x107C++0x03
line.long 0x00 "PDAC_W1_15,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1080++0x03
line.long 0x00 "PDAC_W0_16,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1084++0x03
line.long 0x00 "PDAC_W1_16,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1088++0x03
line.long 0x00 "PDAC_W0_17,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x108C++0x03
line.long 0x00 "PDAC_W1_17,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1100++0x03
line.long 0x00 "PDAC_W0_32,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1104++0x03
line.long 0x00 "PDAC_W1_32,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1108++0x03
line.long 0x00 "PDAC_W0_33,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x110C++0x03
line.long 0x00 "PDAC_W1_33,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1110++0x03
line.long 0x00 "PDAC_W0_34,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1114++0x03
line.long 0x00 "PDAC_W1_34,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1118++0x03
line.long 0x00 "PDAC_W0_35,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x111C++0x03
line.long 0x00 "PDAC_W1_35,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1120++0x03
line.long 0x00 "PDAC_W0_36,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1124++0x03
line.long 0x00 "PDAC_W1_36,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1128++0x03
line.long 0x00 "PDAC_W0_37,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x112C++0x03
line.long 0x00 "PDAC_W1_37,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1150++0x03
line.long 0x00 "PDAC_W0_42,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1154++0x03
line.long 0x00 "PDAC_W1_42,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1160++0x03
line.long 0x00 "PDAC_W0_44,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1164++0x03
line.long 0x00 "PDAC_W1_44,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1168++0x03
line.long 0x00 "PDAC_W0_45,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x116C++0x03
line.long 0x00 "PDAC_W1_45,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1170++0x03
line.long 0x00 "PDAC_W0_46,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1174++0x03
line.long 0x00 "PDAC_W1_46,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1178++0x03
line.long 0x00 "PDAC_W0_47,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x117C++0x03
line.long 0x00 "PDAC_W1_47,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1180++0x03
line.long 0x00 "PDAC_W0_48,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1184++0x03
line.long 0x00 "PDAC_W1_48,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1188++0x03
line.long 0x00 "PDAC_W0_49,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x118C++0x03
line.long 0x00 "PDAC_W1_49,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1190++0x03
line.long 0x00 "PDAC_W0_50,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1194++0x03
line.long 0x00 "PDAC_W1_50,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1198++0x03
line.long 0x00 "PDAC_W0_51,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x119C++0x03
line.long 0x00 "PDAC_W1_51,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x11A0++0x03
line.long 0x00 "PDAC_W0_52,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x11A4++0x03
line.long 0x00 "PDAC_W1_52,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x11A8++0x03
line.long 0x00 "PDAC_W0_53,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x11AC++0x03
line.long 0x00 "PDAC_W1_53,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x11B0++0x03
line.long 0x00 "PDAC_W0_54,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x11B4++0x03
line.long 0x00 "PDAC_W1_54,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x11C0++0x03
line.long 0x00 "PDAC_W0_56,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x11C4++0x03
line.long 0x00 "PDAC_W1_56,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x11C8++0x03
line.long 0x00 "PDAC_W0_57,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x11CC++0x03
line.long 0x00 "PDAC_W1_57,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x11D8++0x03
line.long 0x00 "PDAC_W0_59,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x11DC++0x03
line.long 0x00 "PDAC_W1_59,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x11E8++0x03
line.long 0x00 "PDAC_W0_61,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x11EC++0x03
line.long 0x00 "PDAC_W1_61,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x11F8++0x03
line.long 0x00 "PDAC_W0_63,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x11FC++0x03
line.long 0x00 "PDAC_W1_63,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1200++0x03
line.long 0x00 "PDAC_W0_64,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1204++0x03
line.long 0x00 "PDAC_W1_64,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1208++0x03
line.long 0x00 "PDAC_W0_65,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x120C++0x03
line.long 0x00 "PDAC_W1_65,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1218++0x03
line.long 0x00 "PDAC_W0_67,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x121C++0x03
line.long 0x00 "PDAC_W1_67,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1228++0x03
line.long 0x00 "PDAC_W0_69,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x122C++0x03
line.long 0x00 "PDAC_W1_69,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1230++0x03
line.long 0x00 "PDAC_W0_70,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1234++0x03
line.long 0x00 "PDAC_W1_70,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1250++0x03
line.long 0x00 "PDAC_W0_74,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1254++0x03
line.long 0x00 "PDAC_W1_74,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1268++0x03
line.long 0x00 "PDAC_W0_77,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x126C++0x03
line.long 0x00 "PDAC_W1_77,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1270++0x03
line.long 0x00 "PDAC_W0_78,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1274++0x03
line.long 0x00 "PDAC_W1_78,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1290++0x03
line.long 0x00 "PDAC_W0_82,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1294++0x03
line.long 0x00 "PDAC_W1_82,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x12A0++0x03
line.long 0x00 "PDAC_W0_84,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x12A4++0x03
line.long 0x00 "PDAC_W1_84,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x12A8++0x03
line.long 0x00 "PDAC_W0_85,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x12AC++0x03
line.long 0x00 "PDAC_W1_85,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1400++0x03
line.long 0x00 "PDAC_W0_128,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1404++0x03
line.long 0x00 "PDAC_W1_128,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1408++0x03
line.long 0x00 "PDAC_W0_129,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x140C++0x03
line.long 0x00 "PDAC_W1_129,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1410++0x03
line.long 0x00 "PDAC_W0_130,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1414++0x03
line.long 0x00 "PDAC_W1_130,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1418++0x03
line.long 0x00 "PDAC_W0_131,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x141C++0x03
line.long 0x00 "PDAC_W1_131,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1420++0x03
line.long 0x00 "PDAC_W0_132,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1424++0x03
line.long 0x00 "PDAC_W1_132,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1428++0x03
line.long 0x00 "PDAC_W0_133,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x142C++0x03
line.long 0x00 "PDAC_W1_133,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1430++0x03
line.long 0x00 "PDAC_W0_134,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1434++0x03
line.long 0x00 "PDAC_W1_134,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1438++0x03
line.long 0x00 "PDAC_W0_135,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x143C++0x03
line.long 0x00 "PDAC_W1_135,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1440++0x03
line.long 0x00 "PDAC_W0_136,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1444++0x03
line.long 0x00 "PDAC_W1_136,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1448++0x03
line.long 0x00 "PDAC_W0_137,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x144C++0x03
line.long 0x00 "PDAC_W1_137,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1450++0x03
line.long 0x00 "PDAC_W0_138,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1454++0x03
line.long 0x00 "PDAC_W1_138,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1458++0x03
line.long 0x00 "PDAC_W0_139,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x145C++0x03
line.long 0x00 "PDAC_W1_139,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1460++0x03
line.long 0x00 "PDAC_W0_140,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1464++0x03
line.long 0x00 "PDAC_W1_140,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1468++0x03
line.long 0x00 "PDAC_W0_141,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x146C++0x03
line.long 0x00 "PDAC_W1_141,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1470++0x03
line.long 0x00 "PDAC_W0_142,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1474++0x03
line.long 0x00 "PDAC_W1_142,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1478++0x03
line.long 0x00 "PDAC_W0_143,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x147C++0x03
line.long 0x00 "PDAC_W1_143,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1480++0x03
line.long 0x00 "PDAC_W0_144,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1484++0x03
line.long 0x00 "PDAC_W1_144,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1488++0x03
line.long 0x00 "PDAC_W0_145,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x148C++0x03
line.long 0x00 "PDAC_W1_145,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x14F8++0x03
line.long 0x00 "PDAC_W0_159,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x14FC++0x03
line.long 0x00 "PDAC_W1_159,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1500++0x03
line.long 0x00 "PDAC_W0_160,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1504++0x03
line.long 0x00 "PDAC_W1_160,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1508++0x03
line.long 0x00 "PDAC_W0_161,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x150C++0x03
line.long 0x00 "PDAC_W1_161,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1510++0x03
line.long 0x00 "PDAC_W0_162,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1514++0x03
line.long 0x00 "PDAC_W1_162,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1520++0x03
line.long 0x00 "PDAC_W0_164,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1524++0x03
line.long 0x00 "PDAC_W1_164,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1528++0x03
line.long 0x00 "PDAC_W0_165,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x152C++0x03
line.long 0x00 "PDAC_W1_165,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1530++0x03
line.long 0x00 "PDAC_W0_166,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1534++0x03
line.long 0x00 "PDAC_W1_166,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1540++0x03
line.long 0x00 "PDAC_W0_168,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1544++0x03
line.long 0x00 "PDAC_W1_168,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1548++0x03
line.long 0x00 "PDAC_W0_169,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x154C++0x03
line.long 0x00 "PDAC_W1_169,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1580++0x03
line.long 0x00 "PDAC_W0_176,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1584++0x03
line.long 0x00 "PDAC_W1_176,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1590++0x03
line.long 0x00 "PDAC_W0_178,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1594++0x03
line.long 0x00 "PDAC_W1_178,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1598++0x03
line.long 0x00 "PDAC_W0_179,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x159C++0x03
line.long 0x00 "PDAC_W1_179,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x15A0++0x03
line.long 0x00 "PDAC_W0_180,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x15A4++0x03
line.long 0x00 "PDAC_W1_180,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1810++0x03
line.long 0x00 "PDAC_W0_258,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1814++0x03
line.long 0x00 "PDAC_W1_258,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1818++0x03
line.long 0x00 "PDAC_W0_259,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x181C++0x03
line.long 0x00 "PDAC_W1_259,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1820++0x03
line.long 0x00 "PDAC_W0_260,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1824++0x03
line.long 0x00 "PDAC_W1_260,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1828++0x03
line.long 0x00 "PDAC_W0_261,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x182C++0x03
line.long 0x00 "PDAC_W1_261,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1830++0x03
line.long 0x00 "PDAC_W0_262,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1834++0x03
line.long 0x00 "PDAC_W1_262,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1838++0x03
line.long 0x00 "PDAC_W0_263,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x183C++0x03
line.long 0x00 "PDAC_W1_263,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1840++0x03
line.long 0x00 "PDAC_W0_264,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1844++0x03
line.long 0x00 "PDAC_W1_264,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1848++0x03
line.long 0x00 "PDAC_W0_265,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x184C++0x03
line.long 0x00 "PDAC_W1_265,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1850++0x03
line.long 0x00 "PDAC_W0_266,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1854++0x03
line.long 0x00 "PDAC_W1_266,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1858++0x03
line.long 0x00 "PDAC_W0_267,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x185C++0x03
line.long 0x00 "PDAC_W1_267,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1860++0x03
line.long 0x00 "PDAC_W0_268,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1864++0x03
line.long 0x00 "PDAC_W1_268,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1868++0x03
line.long 0x00 "PDAC_W0_269,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x186C++0x03
line.long 0x00 "PDAC_W1_269,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1870++0x03
line.long 0x00 "PDAC_W0_270,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1874++0x03
line.long 0x00 "PDAC_W1_270,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1878++0x03
line.long 0x00 "PDAC_W0_271,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x187C++0x03
line.long 0x00 "PDAC_W1_271,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1880++0x03
line.long 0x00 "PDAC_W0_272,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1884++0x03
line.long 0x00 "PDAC_W1_272,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1888++0x03
line.long 0x00 "PDAC_W0_273,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x188C++0x03
line.long 0x00 "PDAC_W1_273,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1898++0x03
line.long 0x00 "PDAC_W0_275,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x189C++0x03
line.long 0x00 "PDAC_W1_275,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x18F8++0x03
line.long 0x00 "PDAC_W0_287,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x18FC++0x03
line.long 0x00 "PDAC_W1_287,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1900++0x03
line.long 0x00 "PDAC_W0_288,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1904++0x03
line.long 0x00 "PDAC_W1_288,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1908++0x03
line.long 0x00 "PDAC_W0_289,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x190C++0x03
line.long 0x00 "PDAC_W1_289,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1910++0x03
line.long 0x00 "PDAC_W0_290,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1914++0x03
line.long 0x00 "PDAC_W1_290,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1918++0x03
line.long 0x00 "PDAC_W0_291,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x191C++0x03
line.long 0x00 "PDAC_W1_291,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1920++0x03
line.long 0x00 "PDAC_W0_292,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1924++0x03
line.long 0x00 "PDAC_W1_292,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1930++0x03
line.long 0x00 "PDAC_W0_294,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1934++0x03
line.long 0x00 "PDAC_W1_294,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1940++0x03
line.long 0x00 "PDAC_W0_296,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1944++0x03
line.long 0x00 "PDAC_W1_296,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1980++0x03
line.long 0x00 "PDAC_W0_304,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1984++0x03
line.long 0x00 "PDAC_W1_304,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x2000++0x03
line.long 0x00 "MRGD_W0_0,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2004++0x03
line.long 0x00 "MRGD_W1_0,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2008++0x03
line.long 0x00 "MRGD_W2_0,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x200C++0x03
line.long 0x00 "MRGD_W3_0,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2020++0x03
line.long 0x00 "MRGD_W0_1,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2024++0x03
line.long 0x00 "MRGD_W1_1,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2028++0x03
line.long 0x00 "MRGD_W2_1,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x202C++0x03
line.long 0x00 "MRGD_W3_1,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2040++0x03
line.long 0x00 "MRGD_W0_2,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2044++0x03
line.long 0x00 "MRGD_W1_2,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2048++0x03
line.long 0x00 "MRGD_W2_2,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x204C++0x03
line.long 0x00 "MRGD_W3_2,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2060++0x03
line.long 0x00 "MRGD_W0_3,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2064++0x03
line.long 0x00 "MRGD_W1_3,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2068++0x03
line.long 0x00 "MRGD_W2_3,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x206C++0x03
line.long 0x00 "MRGD_W3_3,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2080++0x03
line.long 0x00 "MRGD_W0_4,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2084++0x03
line.long 0x00 "MRGD_W1_4,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2088++0x03
line.long 0x00 "MRGD_W2_4,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x208C++0x03
line.long 0x00 "MRGD_W3_4,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x20A0++0x03
line.long 0x00 "MRGD_W0_5,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x20A4++0x03
line.long 0x00 "MRGD_W1_5,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x20A8++0x03
line.long 0x00 "MRGD_W2_5,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x20AC++0x03
line.long 0x00 "MRGD_W3_5,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x20C0++0x03
line.long 0x00 "MRGD_W0_6,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x20C4++0x03
line.long 0x00 "MRGD_W1_6,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x20C8++0x03
line.long 0x00 "MRGD_W2_6,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x20CC++0x03
line.long 0x00 "MRGD_W3_6,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x20E0++0x03
line.long 0x00 "MRGD_W0_7,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x20E4++0x03
line.long 0x00 "MRGD_W1_7,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x20E8++0x03
line.long 0x00 "MRGD_W2_7,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x20EC++0x03
line.long 0x00 "MRGD_W3_7,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2200++0x03
line.long 0x00 "MRGD_W0_16,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2204++0x03
line.long 0x00 "MRGD_W1_16,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2208++0x03
line.long 0x00 "MRGD_W2_16,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x220C++0x03
line.long 0x00 "MRGD_W3_16,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2220++0x03
line.long 0x00 "MRGD_W0_17,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2224++0x03
line.long 0x00 "MRGD_W1_17,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2228++0x03
line.long 0x00 "MRGD_W2_17,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x222C++0x03
line.long 0x00 "MRGD_W3_17,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2240++0x03
line.long 0x00 "MRGD_W0_18,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2244++0x03
line.long 0x00 "MRGD_W1_18,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2248++0x03
line.long 0x00 "MRGD_W2_18,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x224C++0x03
line.long 0x00 "MRGD_W3_18,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2260++0x03
line.long 0x00 "MRGD_W0_19,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2264++0x03
line.long 0x00 "MRGD_W1_19,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2268++0x03
line.long 0x00 "MRGD_W2_19,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x226C++0x03
line.long 0x00 "MRGD_W3_19,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2400++0x03
line.long 0x00 "MRGD_W0_32,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2404++0x03
line.long 0x00 "MRGD_W1_32,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2408++0x03
line.long 0x00 "MRGD_W2_32,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x240C++0x03
line.long 0x00 "MRGD_W3_32,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2420++0x03
line.long 0x00 "MRGD_W0_33,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2424++0x03
line.long 0x00 "MRGD_W1_33,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2428++0x03
line.long 0x00 "MRGD_W2_33,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x242C++0x03
line.long 0x00 "MRGD_W3_33,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2440++0x03
line.long 0x00 "MRGD_W0_34,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2444++0x03
line.long 0x00 "MRGD_W1_34,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2448++0x03
line.long 0x00 "MRGD_W2_34,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x244C++0x03
line.long 0x00 "MRGD_W3_34,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2460++0x03
line.long 0x00 "MRGD_W0_35,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2464++0x03
line.long 0x00 "MRGD_W1_35,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2468++0x03
line.long 0x00 "MRGD_W2_35,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x246C++0x03
line.long 0x00 "MRGD_W3_35,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2480++0x03
line.long 0x00 "MRGD_W0_36,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2484++0x03
line.long 0x00 "MRGD_W1_36,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2488++0x03
line.long 0x00 "MRGD_W2_36,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x248C++0x03
line.long 0x00 "MRGD_W3_36,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x24A0++0x03
line.long 0x00 "MRGD_W0_37,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x24A4++0x03
line.long 0x00 "MRGD_W1_37,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x24A8++0x03
line.long 0x00 "MRGD_W2_37,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x24AC++0x03
line.long 0x00 "MRGD_W3_37,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x24C0++0x03
line.long 0x00 "MRGD_W0_38,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x24C4++0x03
line.long 0x00 "MRGD_W1_38,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x24C8++0x03
line.long 0x00 "MRGD_W2_38,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x24CC++0x03
line.long 0x00 "MRGD_W3_38,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x24E0++0x03
line.long 0x00 "MRGD_W0_39,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x24E4++0x03
line.long 0x00 "MRGD_W1_39,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x24E8++0x03
line.long 0x00 "MRGD_W2_39,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x24EC++0x03
line.long 0x00 "MRGD_W3_39,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2600++0x03
line.long 0x00 "MRGD_W0_48,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2604++0x03
line.long 0x00 "MRGD_W1_48,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2608++0x03
line.long 0x00 "MRGD_W2_48,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x260C++0x03
line.long 0x00 "MRGD_W3_48,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2620++0x03
line.long 0x00 "MRGD_W0_49,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2624++0x03
line.long 0x00 "MRGD_W1_49,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2628++0x03
line.long 0x00 "MRGD_W2_49,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x262C++0x03
line.long 0x00 "MRGD_W3_49,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2640++0x03
line.long 0x00 "MRGD_W0_50,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2644++0x03
line.long 0x00 "MRGD_W1_50,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2648++0x03
line.long 0x00 "MRGD_W2_50,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x264C++0x03
line.long 0x00 "MRGD_W3_50,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2660++0x03
line.long 0x00 "MRGD_W0_51,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2664++0x03
line.long 0x00 "MRGD_W1_51,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2668++0x03
line.long 0x00 "MRGD_W2_51,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x266C++0x03
line.long 0x00 "MRGD_W3_51,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2800++0x03
line.long 0x00 "MRGD_W0_64,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2804++0x03
line.long 0x00 "MRGD_W1_64,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2808++0x03
line.long 0x00 "MRGD_W2_64,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x280C++0x03
line.long 0x00 "MRGD_W3_64,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2820++0x03
line.long 0x00 "MRGD_W0_65,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2824++0x03
line.long 0x00 "MRGD_W1_65,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2828++0x03
line.long 0x00 "MRGD_W2_65,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x282C++0x03
line.long 0x00 "MRGD_W3_65,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2840++0x03
line.long 0x00 "MRGD_W0_66,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2844++0x03
line.long 0x00 "MRGD_W1_66,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2848++0x03
line.long 0x00 "MRGD_W2_66,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x284C++0x03
line.long 0x00 "MRGD_W3_66,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2860++0x03
line.long 0x00 "MRGD_W0_67,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2864++0x03
line.long 0x00 "MRGD_W1_67,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2868++0x03
line.long 0x00 "MRGD_W2_67,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x286C++0x03
line.long 0x00 "MRGD_W3_67,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2880++0x03
line.long 0x00 "MRGD_W0_68,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2884++0x03
line.long 0x00 "MRGD_W1_68,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2888++0x03
line.long 0x00 "MRGD_W2_68,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x288C++0x03
line.long 0x00 "MRGD_W3_68,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x28A0++0x03
line.long 0x00 "MRGD_W0_69,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x28A4++0x03
line.long 0x00 "MRGD_W1_69,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x28A8++0x03
line.long 0x00 "MRGD_W2_69,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x28AC++0x03
line.long 0x00 "MRGD_W3_69,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x28C0++0x03
line.long 0x00 "MRGD_W0_70,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x28C4++0x03
line.long 0x00 "MRGD_W1_70,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x28C8++0x03
line.long 0x00 "MRGD_W2_70,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x28CC++0x03
line.long 0x00 "MRGD_W3_70,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x28E0++0x03
line.long 0x00 "MRGD_W0_71,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x28E4++0x03
line.long 0x00 "MRGD_W1_71,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x28E8++0x03
line.long 0x00 "MRGD_W2_71,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x28EC++0x03
line.long 0x00 "MRGD_W3_71,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
tree.end
tree "XRDC_1"
base ad:0x4400C000
group.long 0x00++0x03
line.long 0x00 "CR,Control"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
rbitfld.long 0x00 8. "VAW,Virtualization Aware" "0: Not virtualization-aware,1: Virtualization-aware"
newline
rbitfld.long 0x00 7. "MRF,Memory Region Format" "?,1: SMPU family format"
rbitfld.long 0x00 1.--4. "HRL,Hardware Revision Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "GVLD,Global Valid (XRDC Global Enable/Disable)" "0: Disables,1: Enables"
rgroup.long 0xF0++0x03
line.long 0x00 "HWCFG0,Hardware Configuration 0"
bitfld.long 0x00 28.--31. "MID,Module ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "NPAC,Number Of PACs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "NMRC,Number of MRCs"
hexmask.long.byte 0x00 8.--15. 1. "NMSTR,Number Of Bus Masters"
newline
hexmask.long.byte 0x00 0.--7. 1. "NDID,Number Of DIDs"
rgroup.long 0xF4++0x03
line.long 0x00 "HWCFG1,Hardware Configuration 1"
bitfld.long 0x00 0.--3. "DID,Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xF8++0x03
line.long 0x00 "HWCFG2,Hardware Configuration 2"
bitfld.long 0x00 31. "PIDP31,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 30. "PIDP30,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 29. "PIDP29,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 28. "PIDP28,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 27. "PIDP27,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 26. "PIDP26,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 25. "PIDP25,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 24. "PIDP24,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 23. "PIDP23,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 22. "PIDP22,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 21. "PIDP21,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 20. "PIDP20,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 19. "PIDP19,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 18. "PIDP18,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 17. "PIDP17,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 16. "PIDP16,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 15. "PIDP15,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 14. "PIDP14,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 13. "PIDP13,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 12. "PIDP12,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 11. "PIDP11,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 10. "PIDP10,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 9. "PIDP9,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 8. "PIDP8,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 7. "PIDP7,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 6. "PIDP6,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 5. "PIDP5,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 4. "PIDP4,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 3. "PIDP3,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 2. "PIDP2,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
newline
bitfld.long 0x00 1. "PIDP1,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
bitfld.long 0x00 0. "PIDP0,Process Identifier Present" "0: Does not have PID register,1: Has PID register"
repeat 7. (strings "0" "1" "2" "3" "4" "5" "6" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 )
rgroup.byte ($2+0x100)++0x00
line.byte 0x00 "MDACFG$1,Master Domain Assignment Configuration"
bitfld.byte 0x00 7. "NCM,Noncore Master" "0: Core master or master does not exist,1: Noncore master"
bitfld.byte 0x00 0.--3. "NMDAR,Number Of Master Domain Assignment Registers" "0: Master does not exist,1: Number of registers,2: Number of registers,3: Number of registers,4: Number of registers,5: Number of registers,6: Number of registers,7: Number of registers,8: Number of registers,?..."
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x01 0x02 0x03 )
rgroup.byte ($2+0x140)++0x00
line.byte 0x00 "MRCFG$1,Memory Region Configuration"
bitfld.byte 0x00 0.--4. "NMRGD,Number Of Memory Region Descriptors" "0: MRC does not exist,?,?,?,4: FOUR,?,?,?,8: EIGHT,?,?,?,12: TWELVE,?,?,?,16: SIXTEEN,?..."
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x200)++0x03
line.long 0x00 "DERRLOC[$1],Domain Error Location $1"
bitfld.long 0x00 16.--19. "PACINST,PAC Instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "MRCINST,MRC Instance"
repeat.end
rgroup.long 0x400++0x03
line.long 0x00 "DERR_W0_0,Domain Error Word 0"
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
rgroup.long 0x404++0x03
line.long 0x00 "DERR_W1_0,Domain Error Word 1"
bitfld.long 0x00 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected"
bitfld.long 0x00 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "ERW,Error Read Or Write" "0: READ_ACCESS,1: WRITE_ACCESS"
bitfld.long 0x00 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
newline
bitfld.long 0x00 0.--3. "EDID,Error Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40C++0x03
line.long 0x00 "DERR_W3_0,Domain Error Word 3"
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0: NO_EFFECT_0,1: Rearms error capture resets error capture..,2: NO_EFFECT_2,3: NO_EFFECT_3"
rgroup.long 0x410++0x03
line.long 0x00 "DERR_W0_1,Domain Error Word 0"
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
rgroup.long 0x414++0x03
line.long 0x00 "DERR_W1_1,Domain Error Word 1"
bitfld.long 0x00 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected"
bitfld.long 0x00 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "ERW,Error Read Or Write" "0: READ_ACCESS,1: WRITE_ACCESS"
bitfld.long 0x00 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
newline
bitfld.long 0x00 0.--3. "EDID,Error Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x41C++0x03
line.long 0x00 "DERR_W3_1,Domain Error Word 3"
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0: NO_EFFECT_0,1: Rearms error capture resets error capture..,2: NO_EFFECT_2,3: NO_EFFECT_3"
rgroup.long 0x420++0x03
line.long 0x00 "DERR_W0_2,Domain Error Word 0"
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
rgroup.long 0x424++0x03
line.long 0x00 "DERR_W1_2,Domain Error Word 1"
bitfld.long 0x00 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected"
bitfld.long 0x00 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "ERW,Error Read Or Write" "0: READ_ACCESS,1: WRITE_ACCESS"
bitfld.long 0x00 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
newline
bitfld.long 0x00 0.--3. "EDID,Error Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x42C++0x03
line.long 0x00 "DERR_W3_2,Domain Error Word 3"
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0: NO_EFFECT_0,1: Rearms error capture resets error capture..,2: NO_EFFECT_2,3: NO_EFFECT_3"
rgroup.long 0x430++0x03
line.long 0x00 "DERR_W0_3,Domain Error Word 0"
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
rgroup.long 0x434++0x03
line.long 0x00 "DERR_W1_3,Domain Error Word 1"
bitfld.long 0x00 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected"
bitfld.long 0x00 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "ERW,Error Read Or Write" "0: READ_ACCESS,1: WRITE_ACCESS"
bitfld.long 0x00 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
newline
bitfld.long 0x00 0.--3. "EDID,Error Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x43C++0x03
line.long 0x00 "DERR_W3_3,Domain Error Word 3"
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0: NO_EFFECT_0,1: Rearms error capture resets error capture..,2: NO_EFFECT_2,3: NO_EFFECT_3"
rgroup.long 0x500++0x03
line.long 0x00 "DERR_W0_16,Domain Error Word 0"
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
rgroup.long 0x504++0x03
line.long 0x00 "DERR_W1_16,Domain Error Word 1"
bitfld.long 0x00 30.--31. "EST,Error State" "0: No access violations detected,1: No access violations detected,2: A single access violation has been detected,3: Multiple access violations have been detected"
bitfld.long 0x00 24.--26. "EPORT,Error Port" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11. "ERW,Error Read Or Write" "0: READ_ACCESS,1: WRITE_ACCESS"
bitfld.long 0x00 8.--10. "EATR,Error Attributes" "0: Secure user mode instruction fetch access,1: Secure user mode data access,2: Secure privileged mode instruction fetch access,3: Secure privileged mode data access,4: Nonsecure user mode instruction fetch access,5: Nonsecure user mode data access,6: Nonsecure privileged mode instruction fetch..,7: Nonsecure privileged mode data access"
newline
bitfld.long 0x00 0.--3. "EDID,Error Domain Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50C++0x03
line.long 0x00 "DERR_W3_16,Domain Error Word 3"
bitfld.long 0x00 30.--31. "RECR,Rearm Error Capture Registers" "0: NO_EFFECT_0,1: Rearms error capture resets error capture..,2: NO_EFFECT_2,3: NO_EFFECT_3"
group.long 0x700++0x03
line.long 0x00 "PID0,Process Identifier"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Any secure privileged,1: Any secure privileged,2: Secure privileged writes from master only,3: LOCKED"
bitfld.long 0x00 28. "TSM,Three-State Model" "0,1"
newline
bitfld.long 0x00 0.--5. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x800++0x03
line.long 0x00 "MDA_W0_0_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x804++0x03
line.long 0x00 "MDA_W1_0_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x808++0x03
line.long 0x00 "MDA_W2_0_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x80C++0x03
line.long 0x00 "MDA_W3_0_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x810++0x03
line.long 0x00 "MDA_W4_0_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x814++0x03
line.long 0x00 "MDA_W5_0_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x818++0x03
line.long 0x00 "MDA_W6_0_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x81C++0x03
line.long 0x00 "MDA_W7_0_DFMT0,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "0: Core bus master domain assignment (DFMT0),?..."
bitfld.long 0x00 16.--21. "PID,Process Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "PIDM,Process Identifier Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 6.--7. "PE,Process Identifier Enable" "0: No PID is included,1: No PID is included,2: Partial domain hit = (PID & ~PIDM) ==..,3: Partial domain hit = ~((PID & ~PIDM) ==.."
newline
bitfld.long 0x00 4.--5. "DIDS,DID Select" "0: Use the DID field of this register,1: Use the input DID,2: Concatenate bits 3-2 of this register with..,?..."
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x820++0x03
line.long 0x00 "MDA_W0_1_DFMT1,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)"
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input"
newline
bitfld.long 0x00 6.--7. "SA,Secure Attribute" "0: Force to secure,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master"
bitfld.long 0x00 4.--5. "PA,Privileged Attribute" "0: Force to user,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master"
newline
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x840++0x03
line.long 0x00 "MDA_W0_2_DFMT1,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)"
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input"
newline
bitfld.long 0x00 6.--7. "SA,Secure Attribute" "0: Force to secure,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master"
bitfld.long 0x00 4.--5. "PA,Privileged Attribute" "0: Force to user,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master"
newline
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x860++0x03
line.long 0x00 "MDA_W0_3_DFMT1,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)"
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input"
newline
bitfld.long 0x00 6.--7. "SA,Secure Attribute" "0: Force to secure,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master"
bitfld.long 0x00 4.--5. "PA,Privileged Attribute" "0: Force to user,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master"
newline
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x880++0x03
line.long 0x00 "MDA_W0_4_DFMT1,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)"
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input"
newline
bitfld.long 0x00 6.--7. "SA,Secure Attribute" "0: Force to secure,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master"
bitfld.long 0x00 4.--5. "PA,Privileged Attribute" "0: Force to user,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master"
newline
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8A0++0x03
line.long 0x00 "MDA_W0_5_DFMT1,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)"
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input"
newline
bitfld.long 0x00 6.--7. "SA,Secure Attribute" "0: Force to secure,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master"
bitfld.long 0x00 4.--5. "PA,Privileged Attribute" "0: Force to user,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master"
newline
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x8C0++0x03
line.long 0x00 "MDA_W0_6_DFMT1,Master Domain Assignment"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 30. "LK1,Lock" "0: UNLOCKED_READ,1: LOCKED"
newline
rbitfld.long 0x00 29. "DFMT,Domain Format" "?,1: Bus master domain assignment (DFMT1)"
bitfld.long 0x00 8. "DIDB,DID Bypass" "0: Bypass DID input,1: Use DID input"
newline
bitfld.long 0x00 6.--7. "SA,Secure Attribute" "0: Force to secure,1: Force to nonsecure,2: Use secure attribute from the master,3: Use secure attribute from the master"
bitfld.long 0x00 4.--5. "PA,Privileged Attribute" "0: Force to user,1: Force to privileged,2: Use privileged attribute from the master,3: Use privileged attribute from the master"
newline
bitfld.long 0x00 0.--2. "DID,Domain Identifier" "0,1,2,3,4,5,6,7"
group.long 0x1000++0x03
line.long 0x00 "PDAC_W0_0,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1004++0x03
line.long 0x00 "PDAC_W1_0,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1008++0x03
line.long 0x00 "PDAC_W0_1,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x100C++0x03
line.long 0x00 "PDAC_W1_1,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1010++0x03
line.long 0x00 "PDAC_W0_2,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1014++0x03
line.long 0x00 "PDAC_W1_2,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1018++0x03
line.long 0x00 "PDAC_W0_3,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x101C++0x03
line.long 0x00 "PDAC_W1_3,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1020++0x03
line.long 0x00 "PDAC_W0_4,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1024++0x03
line.long 0x00 "PDAC_W1_4,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1100++0x03
line.long 0x00 "PDAC_W0_32,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1104++0x03
line.long 0x00 "PDAC_W1_32,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1108++0x03
line.long 0x00 "PDAC_W0_33,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x110C++0x03
line.long 0x00 "PDAC_W1_33,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1120++0x03
line.long 0x00 "PDAC_W0_36,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1124++0x03
line.long 0x00 "PDAC_W1_36,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1128++0x03
line.long 0x00 "PDAC_W0_37,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x112C++0x03
line.long 0x00 "PDAC_W1_37,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1138++0x03
line.long 0x00 "PDAC_W0_39,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x113C++0x03
line.long 0x00 "PDAC_W1_39,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1140++0x03
line.long 0x00 "PDAC_W0_40,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1144++0x03
line.long 0x00 "PDAC_W1_40,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1148++0x03
line.long 0x00 "PDAC_W0_41,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x114C++0x03
line.long 0x00 "PDAC_W1_41,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1158++0x03
line.long 0x00 "PDAC_W0_43,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x115C++0x03
line.long 0x00 "PDAC_W1_43,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1180++0x03
line.long 0x00 "PDAC_W0_48,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1184++0x03
line.long 0x00 "PDAC_W1_48,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1190++0x03
line.long 0x00 "PDAC_W0_50,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x1194++0x03
line.long 0x00 "PDAC_W1_50,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x1198++0x03
line.long 0x00 "PDAC_W0_51,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x119C++0x03
line.long 0x00 "PDAC_W1_51,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x11A0++0x03
line.long 0x00 "PDAC_W0_52,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x11A4++0x03
line.long 0x00 "PDAC_W1_52,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x11A8++0x03
line.long 0x00 "PDAC_W0_53,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x11AC++0x03
line.long 0x00 "PDAC_W1_53,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x11B0++0x03
line.long 0x00 "PDAC_W0_54,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x11B4++0x03
line.long 0x00 "PDAC_W1_54,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x11C8++0x03
line.long 0x00 "PDAC_W0_57,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x11CC++0x03
line.long 0x00 "PDAC_W1_57,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x11D0++0x03
line.long 0x00 "PDAC_W0_58,Peripheral Domain Access Control Word 0"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: Enables"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x11D4++0x03
line.long 0x00 "PDAC_W1_58,Peripheral Domain Access Control Word 1"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: Both words can be written to,1: Both words can be written to,2: Domain d can update only its associated DdACP..,3: Locks (both words are read-only)"
group.long 0x2000++0x03
line.long 0x00 "MRGD_W0_0,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2004++0x03
line.long 0x00 "MRGD_W1_0,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2008++0x03
line.long 0x00 "MRGD_W2_0,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x200C++0x03
line.long 0x00 "MRGD_W3_0,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2020++0x03
line.long 0x00 "MRGD_W0_1,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2024++0x03
line.long 0x00 "MRGD_W1_1,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2028++0x03
line.long 0x00 "MRGD_W2_1,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x202C++0x03
line.long 0x00 "MRGD_W3_1,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2040++0x03
line.long 0x00 "MRGD_W0_2,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2044++0x03
line.long 0x00 "MRGD_W1_2,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2048++0x03
line.long 0x00 "MRGD_W2_2,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x204C++0x03
line.long 0x00 "MRGD_W3_2,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2060++0x03
line.long 0x00 "MRGD_W0_3,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2064++0x03
line.long 0x00 "MRGD_W1_3,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2068++0x03
line.long 0x00 "MRGD_W2_3,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x206C++0x03
line.long 0x00 "MRGD_W3_3,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2080++0x03
line.long 0x00 "MRGD_W0_4,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2084++0x03
line.long 0x00 "MRGD_W1_4,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2088++0x03
line.long 0x00 "MRGD_W2_4,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x208C++0x03
line.long 0x00 "MRGD_W3_4,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x20A0++0x03
line.long 0x00 "MRGD_W0_5,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x20A4++0x03
line.long 0x00 "MRGD_W1_5,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x20A8++0x03
line.long 0x00 "MRGD_W2_5,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x20AC++0x03
line.long 0x00 "MRGD_W3_5,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x20C0++0x03
line.long 0x00 "MRGD_W0_6,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x20C4++0x03
line.long 0x00 "MRGD_W1_6,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x20C8++0x03
line.long 0x00 "MRGD_W2_6,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x20CC++0x03
line.long 0x00 "MRGD_W3_6,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x20E0++0x03
line.long 0x00 "MRGD_W0_7,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x20E4++0x03
line.long 0x00 "MRGD_W1_7,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x20E8++0x03
line.long 0x00 "MRGD_W2_7,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x20EC++0x03
line.long 0x00 "MRGD_W3_7,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2100++0x03
line.long 0x00 "MRGD_W0_8,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2104++0x03
line.long 0x00 "MRGD_W1_8,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2108++0x03
line.long 0x00 "MRGD_W2_8,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x210C++0x03
line.long 0x00 "MRGD_W3_8,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2120++0x03
line.long 0x00 "MRGD_W0_9,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2124++0x03
line.long 0x00 "MRGD_W1_9,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2128++0x03
line.long 0x00 "MRGD_W2_9,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x212C++0x03
line.long 0x00 "MRGD_W3_9,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2140++0x03
line.long 0x00 "MRGD_W0_10,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2144++0x03
line.long 0x00 "MRGD_W1_10,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2148++0x03
line.long 0x00 "MRGD_W2_10,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x214C++0x03
line.long 0x00 "MRGD_W3_10,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2160++0x03
line.long 0x00 "MRGD_W0_11,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2164++0x03
line.long 0x00 "MRGD_W1_11,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2168++0x03
line.long 0x00 "MRGD_W2_11,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x216C++0x03
line.long 0x00 "MRGD_W3_11,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2180++0x03
line.long 0x00 "MRGD_W0_12,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2184++0x03
line.long 0x00 "MRGD_W1_12,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2188++0x03
line.long 0x00 "MRGD_W2_12,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x218C++0x03
line.long 0x00 "MRGD_W3_12,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x21A0++0x03
line.long 0x00 "MRGD_W0_13,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x21A4++0x03
line.long 0x00 "MRGD_W1_13,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x21A8++0x03
line.long 0x00 "MRGD_W2_13,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x21AC++0x03
line.long 0x00 "MRGD_W3_13,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x21C0++0x03
line.long 0x00 "MRGD_W0_14,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x21C4++0x03
line.long 0x00 "MRGD_W1_14,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x21C8++0x03
line.long 0x00 "MRGD_W2_14,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x21CC++0x03
line.long 0x00 "MRGD_W3_14,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x21E0++0x03
line.long 0x00 "MRGD_W0_15,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x21E4++0x03
line.long 0x00 "MRGD_W1_15,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x21E8++0x03
line.long 0x00 "MRGD_W2_15,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x21EC++0x03
line.long 0x00 "MRGD_W3_15,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2200++0x03
line.long 0x00 "MRGD_W0_16,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2204++0x03
line.long 0x00 "MRGD_W1_16,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2208++0x03
line.long 0x00 "MRGD_W2_16,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x220C++0x03
line.long 0x00 "MRGD_W3_16,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2220++0x03
line.long 0x00 "MRGD_W0_17,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2224++0x03
line.long 0x00 "MRGD_W1_17,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2228++0x03
line.long 0x00 "MRGD_W2_17,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x222C++0x03
line.long 0x00 "MRGD_W3_17,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2240++0x03
line.long 0x00 "MRGD_W0_18,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2244++0x03
line.long 0x00 "MRGD_W1_18,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2248++0x03
line.long 0x00 "MRGD_W2_18,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x224C++0x03
line.long 0x00 "MRGD_W3_18,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2260++0x03
line.long 0x00 "MRGD_W0_19,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2264++0x03
line.long 0x00 "MRGD_W1_19,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2268++0x03
line.long 0x00 "MRGD_W2_19,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x226C++0x03
line.long 0x00 "MRGD_W3_19,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2400++0x03
line.long 0x00 "MRGD_W0_32,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2404++0x03
line.long 0x00 "MRGD_W1_32,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2408++0x03
line.long 0x00 "MRGD_W2_32,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x240C++0x03
line.long 0x00 "MRGD_W3_32,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2420++0x03
line.long 0x00 "MRGD_W0_33,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2424++0x03
line.long 0x00 "MRGD_W1_33,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2428++0x03
line.long 0x00 "MRGD_W2_33,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x242C++0x03
line.long 0x00 "MRGD_W3_33,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2440++0x03
line.long 0x00 "MRGD_W0_34,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2444++0x03
line.long 0x00 "MRGD_W1_34,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2448++0x03
line.long 0x00 "MRGD_W2_34,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x244C++0x03
line.long 0x00 "MRGD_W3_34,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2460++0x03
line.long 0x00 "MRGD_W0_35,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2464++0x03
line.long 0x00 "MRGD_W1_35,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2468++0x03
line.long 0x00 "MRGD_W2_35,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x246C++0x03
line.long 0x00 "MRGD_W3_35,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2600++0x03
line.long 0x00 "MRGD_W0_48,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2604++0x03
line.long 0x00 "MRGD_W1_48,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2608++0x03
line.long 0x00 "MRGD_W2_48,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x260C++0x03
line.long 0x00 "MRGD_W3_48,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2620++0x03
line.long 0x00 "MRGD_W0_49,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2624++0x03
line.long 0x00 "MRGD_W1_49,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2628++0x03
line.long 0x00 "MRGD_W2_49,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x262C++0x03
line.long 0x00 "MRGD_W3_49,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2640++0x03
line.long 0x00 "MRGD_W0_50,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2644++0x03
line.long 0x00 "MRGD_W1_50,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2648++0x03
line.long 0x00 "MRGD_W2_50,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x264C++0x03
line.long 0x00 "MRGD_W3_50,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
group.long 0x2660++0x03
line.long 0x00 "MRGD_W0_51,Memory Region Descriptor Word 0"
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
group.long 0x2664++0x03
line.long 0x00 "MRGD_W1_51,Memory Region Descriptor Word 1"
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
group.long 0x2668++0x03
line.long 0x00 "MRGD_W2_51,Memory Region Descriptor Word 2"
bitfld.long 0x00 30. "SE,Semaphore Enable" "0: Disables,1: INCLUDE"
bitfld.long 0x00 24.--27. "SNUM,Semaphore Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 21.--23. "D7ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "D6ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15.--17. "D5ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "D4ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "D3ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "D2ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--5. "D1ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "D0ACP,Domain Access Control Policy" "0,1,2,3,4,5,6,7"
group.long 0x266C++0x03
line.long 0x00 "MRGD_W3_51,Memory Region Descriptor Word 3"
bitfld.long 0x00 31. "VLD,Valid" "0: INVALID,1: VALID"
bitfld.long 0x00 29.--30. "LK2,Lock" "0: All words in the set can be written to,?,2: Domain d can update only its associated DdACP..,3: Locks (all words are read-only)"
tree.end
tree.end
autoindent.off
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